1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(ale, pci, 1, 1, 1); 83 MODULE_DEPEND(ale, ether, 1, 1, 1); 84 MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static const struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99 } ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102 }; 103 104 static int ale_attach(device_t); 105 static int ale_check_boundary(struct ale_softc *); 106 static int ale_detach(device_t); 107 static int ale_dma_alloc(struct ale_softc *); 108 static void ale_dma_free(struct ale_softc *); 109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_init(void *); 113 static void ale_init_locked(struct ale_softc *); 114 static void ale_init_rx_pages(struct ale_softc *); 115 static void ale_init_tx_ring(struct ale_softc *); 116 static void ale_int_task(void *, int); 117 static int ale_intr(void *); 118 static int ale_ioctl(if_t, u_long, caddr_t); 119 static void ale_mac_config(struct ale_softc *); 120 static int ale_miibus_readreg(device_t, int, int); 121 static void ale_miibus_statchg(device_t); 122 static int ale_miibus_writereg(device_t, int, int, int); 123 static int ale_mediachange(if_t); 124 static void ale_mediastatus(if_t, struct ifmediareq *); 125 static void ale_phy_reset(struct ale_softc *); 126 static int ale_probe(device_t); 127 static void ale_reset(struct ale_softc *); 128 static int ale_resume(device_t); 129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132 static int ale_rxeof(struct ale_softc *sc, int); 133 static void ale_rxfilter(struct ale_softc *); 134 static void ale_rxvlan(struct ale_softc *); 135 static void ale_setlinkspeed(struct ale_softc *); 136 static void ale_setwol(struct ale_softc *); 137 static int ale_shutdown(device_t); 138 static void ale_start(if_t); 139 static void ale_start_locked(if_t); 140 static void ale_stats_clear(struct ale_softc *); 141 static void ale_stats_update(struct ale_softc *); 142 static void ale_stop(struct ale_softc *); 143 static void ale_stop_mac(struct ale_softc *); 144 static int ale_suspend(device_t); 145 static void ale_sysctl_node(struct ale_softc *); 146 static void ale_tick(void *); 147 static void ale_txeof(struct ale_softc *); 148 static void ale_watchdog(struct ale_softc *); 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153 static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 DEVMETHOD_END 168 }; 169 170 static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174 }; 175 176 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 177 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 178 nitems(ale_devs)); 179 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 180 181 static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184 }; 185 186 static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static int 202 ale_miibus_readreg(device_t dev, int phy, int reg) 203 { 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225 } 226 227 static int 228 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229 { 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250 } 251 252 static void 253 ale_miibus_statchg(device_t dev) 254 { 255 struct ale_softc *sc; 256 struct mii_data *mii; 257 if_t ifp; 258 uint32_t reg; 259 260 sc = device_get_softc(dev); 261 mii = device_get_softc(sc->ale_miibus); 262 ifp = sc->ale_ifp; 263 if (mii == NULL || ifp == NULL || 264 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ale_flags &= ~ALE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 sc->ale_flags |= ALE_FLAG_LINK; 274 break; 275 case IFM_1000_T: 276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 default: 280 break; 281 } 282 } 283 284 /* Stop Rx/Tx MACs. */ 285 ale_stop_mac(sc); 286 287 /* Program MACs with resolved speed/duplex/flow-control. */ 288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 289 ale_mac_config(sc); 290 /* Reenable Tx/Rx MACs. */ 291 reg = CSR_READ_4(sc, ALE_MAC_CFG); 292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 294 } 295 } 296 297 static void 298 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 299 { 300 struct ale_softc *sc; 301 struct mii_data *mii; 302 303 sc = if_getsoftc(ifp); 304 ALE_LOCK(sc); 305 if ((if_getflags(ifp) & IFF_UP) == 0) { 306 ALE_UNLOCK(sc); 307 return; 308 } 309 mii = device_get_softc(sc->ale_miibus); 310 311 mii_pollstat(mii); 312 ifmr->ifm_status = mii->mii_media_status; 313 ifmr->ifm_active = mii->mii_media_active; 314 ALE_UNLOCK(sc); 315 } 316 317 static int 318 ale_mediachange(if_t ifp) 319 { 320 struct ale_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = if_getsoftc(ifp); 326 ALE_LOCK(sc); 327 mii = device_get_softc(sc->ale_miibus); 328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 329 PHY_RESET(miisc); 330 error = mii_mediachg(mii); 331 ALE_UNLOCK(sc); 332 333 return (error); 334 } 335 336 static int 337 ale_probe(device_t dev) 338 { 339 const struct ale_dev *sp; 340 int i; 341 uint16_t vendor, devid; 342 343 vendor = pci_get_vendor(dev); 344 devid = pci_get_device(dev); 345 sp = ale_devs; 346 for (i = 0; i < nitems(ale_devs); i++) { 347 if (vendor == sp->ale_vendorid && 348 devid == sp->ale_deviceid) { 349 device_set_desc(dev, sp->ale_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 sp++; 353 } 354 355 return (ENXIO); 356 } 357 358 static void 359 ale_get_macaddr(struct ale_softc *sc) 360 { 361 uint32_t ea[2], reg; 362 int i, vpdc; 363 364 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 365 if ((reg & SPI_VPD_ENB) != 0) { 366 reg &= ~SPI_VPD_ENB; 367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 368 } 369 370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 371 /* 372 * PCI VPD capability found, let TWSI reload EEPROM. 373 * This will set ethernet address of controller. 374 */ 375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 376 TWSI_CTRL_SW_LD_START); 377 for (i = 100; i > 0; i--) { 378 DELAY(1000); 379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 380 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 381 break; 382 } 383 if (i == 0) 384 device_printf(sc->ale_dev, 385 "reloading EEPROM timeout!\n"); 386 } else { 387 if (bootverbose) 388 device_printf(sc->ale_dev, 389 "PCI VPD capability not found!\n"); 390 } 391 392 ea[0] = CSR_READ_4(sc, ALE_PAR0); 393 ea[1] = CSR_READ_4(sc, ALE_PAR1); 394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 400 } 401 402 static void 403 ale_phy_reset(struct ale_softc *sc) 404 { 405 406 /* Reset magic from Linux. */ 407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 409 GPHY_CTRL_PHY_PLL_ON); 410 DELAY(1000); 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 416 #define ATPHY_DBG_ADDR 0x1D 417 #define ATPHY_DBG_DATA 0x1E 418 419 /* Enable hibernation mode. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x0B); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_DATA, 0xBC00); 424 /* Set Class A/B for all modes. */ 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_ADDR, 0x00); 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_DATA, 0x02EF); 429 /* Enable 10BT power saving. */ 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x12); 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_DATA, 0x4C04); 434 /* Adjust 1000T power. */ 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x04); 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x8BBB); 439 /* 10BT center tap voltage. */ 440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 441 ATPHY_DBG_ADDR, 0x05); 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x2C46); 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 DELAY(1000); 448 } 449 450 static int 451 ale_attach(device_t dev) 452 { 453 struct ale_softc *sc; 454 if_t ifp; 455 uint16_t burst; 456 int error, i, msic, msixc, pmc; 457 uint32_t rxf_len, txf_len; 458 459 error = 0; 460 sc = device_get_softc(dev); 461 sc->ale_dev = dev; 462 463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 464 MTX_DEF); 465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 466 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 467 468 /* Map the device. */ 469 pci_enable_busmaster(dev); 470 sc->ale_res_spec = ale_res_spec_mem; 471 sc->ale_irq_spec = ale_irq_spec_legacy; 472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 473 if (error != 0) { 474 device_printf(dev, "cannot allocate memory resources.\n"); 475 goto fail; 476 } 477 478 /* Set PHY address. */ 479 sc->ale_phyaddr = ALE_PHY_ADDR; 480 481 /* Reset PHY. */ 482 ale_phy_reset(sc); 483 484 /* Reset the ethernet controller. */ 485 ale_reset(sc); 486 487 /* Get PCI and chip id/revision. */ 488 sc->ale_rev = pci_get_revid(dev); 489 if (sc->ale_rev >= 0xF0) { 490 /* L2E Rev. B. AR8114 */ 491 sc->ale_flags |= ALE_FLAG_FASTETHER; 492 } else { 493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 494 /* L1E AR8121 */ 495 sc->ale_flags |= ALE_FLAG_JUMBO; 496 } else { 497 /* L2E Rev. A. AR8113 */ 498 sc->ale_flags |= ALE_FLAG_FASTETHER; 499 } 500 } 501 /* 502 * All known controllers seems to require 4 bytes alignment 503 * of Tx buffers to make Tx checksum offload with custom 504 * checksum generation method work. 505 */ 506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 507 /* 508 * All known controllers seems to have issues on Rx checksum 509 * offload for fragmented IP datagrams. 510 */ 511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 512 /* 513 * Don't use Tx CMB. It is known to cause RRS update failure 514 * under certain circumstances. Typical phenomenon of the 515 * issue would be unexpected sequence number encountered in 516 * Rx handler. 517 */ 518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 520 MASTER_CHIP_REV_SHIFT; 521 if (bootverbose) { 522 device_printf(dev, "PCI device revision : 0x%04x\n", 523 sc->ale_rev); 524 device_printf(dev, "Chip id/revision : 0x%04x\n", 525 sc->ale_chip_rev); 526 } 527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 529 /* 530 * Uninitialized hardware returns an invalid chip id/revision 531 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 532 */ 533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 534 rxf_len == 0xFFFFFFF) { 535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 537 txf_len, rxf_len); 538 error = ENXIO; 539 goto fail; 540 } 541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 542 543 /* Allocate IRQ resources. */ 544 msixc = pci_msix_count(dev); 545 msic = pci_msi_count(dev); 546 if (bootverbose) { 547 device_printf(dev, "MSIX count : %d\n", msixc); 548 device_printf(dev, "MSI count : %d\n", msic); 549 } 550 551 /* Prefer MSIX over MSI. */ 552 if (msix_disable == 0 || msi_disable == 0) { 553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 554 pci_alloc_msix(dev, &msixc) == 0) { 555 if (msixc == ALE_MSIX_MESSAGES) { 556 device_printf(dev, "Using %d MSIX messages.\n", 557 msixc); 558 sc->ale_flags |= ALE_FLAG_MSIX; 559 sc->ale_irq_spec = ale_irq_spec_msix; 560 } else 561 pci_release_msi(dev); 562 } 563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 564 msic == ALE_MSI_MESSAGES && 565 pci_alloc_msi(dev, &msic) == 0) { 566 if (msic == ALE_MSI_MESSAGES) { 567 device_printf(dev, "Using %d MSI messages.\n", 568 msic); 569 sc->ale_flags |= ALE_FLAG_MSI; 570 sc->ale_irq_spec = ale_irq_spec_msi; 571 } else 572 pci_release_msi(dev); 573 } 574 } 575 576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 577 if (error != 0) { 578 device_printf(dev, "cannot allocate IRQ resources.\n"); 579 goto fail; 580 } 581 582 /* Get DMA parameters from PCIe device control register. */ 583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 584 sc->ale_flags |= ALE_FLAG_PCIE; 585 burst = pci_read_config(dev, i + 0x08, 2); 586 /* Max read request size. */ 587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 588 DMA_CFG_RD_BURST_SHIFT; 589 /* Max payload size. */ 590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 591 DMA_CFG_WR_BURST_SHIFT; 592 if (bootverbose) { 593 device_printf(dev, "Read request size : %d bytes.\n", 594 128 << ((burst >> 12) & 0x07)); 595 device_printf(dev, "TLP payload size : %d bytes.\n", 596 128 << ((burst >> 5) & 0x07)); 597 } 598 } else { 599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 601 } 602 603 /* Create device sysctl node. */ 604 ale_sysctl_node(sc); 605 606 if ((error = ale_dma_alloc(sc)) != 0) 607 goto fail; 608 609 /* Load station address. */ 610 ale_get_macaddr(sc); 611 612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 613 if (ifp == NULL) { 614 device_printf(dev, "cannot allocate ifnet structure.\n"); 615 error = ENXIO; 616 goto fail; 617 } 618 619 if_setsoftc(ifp, sc); 620 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 621 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 622 if_setioctlfn(ifp, ale_ioctl); 623 if_setstartfn(ifp, ale_start); 624 if_setinitfn(ifp, ale_init); 625 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 626 if_setsendqready(ifp); 627 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 628 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 629 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 630 sc->ale_flags |= ALE_FLAG_PMCAP; 631 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 632 } 633 if_setcapenable(ifp, if_getcapabilities(ifp)); 634 635 /* Set up MII bus. */ 636 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 637 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 638 MIIF_DOPAUSE); 639 if (error != 0) { 640 device_printf(dev, "attaching PHYs failed\n"); 641 goto fail; 642 } 643 644 ether_ifattach(ifp, sc->ale_eaddr); 645 646 /* VLAN capability setup. */ 647 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 648 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 649 if_setcapenable(ifp, if_getcapabilities(ifp)); 650 /* 651 * Even though controllers supported by ale(3) have Rx checksum 652 * offload bug the workaround for fragmented frames seemed to 653 * work so far. However it seems Rx checksum offload does not 654 * work under certain conditions. So disable Rx checksum offload 655 * until I find more clue about it but allow users to override it. 656 */ 657 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 658 659 /* Tell the upper layer(s) we support long frames. */ 660 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 661 662 /* Create local taskq. */ 663 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 664 taskqueue_thread_enqueue, &sc->ale_tq); 665 if (sc->ale_tq == NULL) { 666 device_printf(dev, "could not create taskqueue.\n"); 667 ether_ifdetach(ifp); 668 error = ENXIO; 669 goto fail; 670 } 671 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 672 device_get_nameunit(sc->ale_dev)); 673 674 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 675 msic = ALE_MSIX_MESSAGES; 676 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 677 msic = ALE_MSI_MESSAGES; 678 else 679 msic = 1; 680 for (i = 0; i < msic; i++) { 681 error = bus_setup_intr(dev, sc->ale_irq[i], 682 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 683 &sc->ale_intrhand[i]); 684 if (error != 0) 685 break; 686 } 687 if (error != 0) { 688 device_printf(dev, "could not set up interrupt handler.\n"); 689 taskqueue_free(sc->ale_tq); 690 sc->ale_tq = NULL; 691 ether_ifdetach(ifp); 692 goto fail; 693 } 694 695 fail: 696 if (error != 0) 697 ale_detach(dev); 698 699 return (error); 700 } 701 702 static int 703 ale_detach(device_t dev) 704 { 705 struct ale_softc *sc; 706 if_t ifp; 707 int i, msic; 708 709 sc = device_get_softc(dev); 710 711 ifp = sc->ale_ifp; 712 if (device_is_attached(dev)) { 713 ether_ifdetach(ifp); 714 ALE_LOCK(sc); 715 ale_stop(sc); 716 ALE_UNLOCK(sc); 717 callout_drain(&sc->ale_tick_ch); 718 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 719 } 720 721 if (sc->ale_tq != NULL) { 722 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 723 taskqueue_free(sc->ale_tq); 724 sc->ale_tq = NULL; 725 } 726 727 if (sc->ale_miibus != NULL) { 728 device_delete_child(dev, sc->ale_miibus); 729 sc->ale_miibus = NULL; 730 } 731 bus_generic_detach(dev); 732 ale_dma_free(sc); 733 734 if (ifp != NULL) { 735 if_free(ifp); 736 sc->ale_ifp = NULL; 737 } 738 739 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 740 msic = ALE_MSIX_MESSAGES; 741 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 742 msic = ALE_MSI_MESSAGES; 743 else 744 msic = 1; 745 for (i = 0; i < msic; i++) { 746 if (sc->ale_intrhand[i] != NULL) { 747 bus_teardown_intr(dev, sc->ale_irq[i], 748 sc->ale_intrhand[i]); 749 sc->ale_intrhand[i] = NULL; 750 } 751 } 752 753 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 754 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 755 pci_release_msi(dev); 756 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 757 mtx_destroy(&sc->ale_mtx); 758 759 return (0); 760 } 761 762 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 763 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 764 765 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 766 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 767 768 static void 769 ale_sysctl_node(struct ale_softc *sc) 770 { 771 struct sysctl_ctx_list *ctx; 772 struct sysctl_oid_list *child, *parent; 773 struct sysctl_oid *tree; 774 struct ale_hw_stats *stats; 775 int error; 776 777 stats = &sc->ale_stats; 778 ctx = device_get_sysctl_ctx(sc->ale_dev); 779 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 780 781 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 782 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 783 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 784 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 785 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 786 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 787 /* Pull in device tunables. */ 788 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 789 error = resource_int_value(device_get_name(sc->ale_dev), 790 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 791 if (error == 0) { 792 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 793 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 794 device_printf(sc->ale_dev, "int_rx_mod value out of " 795 "range; using default: %d\n", 796 ALE_IM_RX_TIMER_DEFAULT); 797 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 798 } 799 } 800 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 801 error = resource_int_value(device_get_name(sc->ale_dev), 802 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 803 if (error == 0) { 804 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 805 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 806 device_printf(sc->ale_dev, "int_tx_mod value out of " 807 "range; using default: %d\n", 808 ALE_IM_TX_TIMER_DEFAULT); 809 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 810 } 811 } 812 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 813 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 814 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 815 "max number of Rx events to process"); 816 /* Pull in device tunables. */ 817 sc->ale_process_limit = ALE_PROC_DEFAULT; 818 error = resource_int_value(device_get_name(sc->ale_dev), 819 device_get_unit(sc->ale_dev), "process_limit", 820 &sc->ale_process_limit); 821 if (error == 0) { 822 if (sc->ale_process_limit < ALE_PROC_MIN || 823 sc->ale_process_limit > ALE_PROC_MAX) { 824 device_printf(sc->ale_dev, 825 "process_limit value out of range; " 826 "using default: %d\n", ALE_PROC_DEFAULT); 827 sc->ale_process_limit = ALE_PROC_DEFAULT; 828 } 829 } 830 831 /* Misc statistics. */ 832 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 833 &stats->reset_brk_seq, 834 "Controller resets due to broken Rx sequnce number"); 835 836 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 837 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 838 parent = SYSCTL_CHILDREN(tree); 839 840 /* Rx statistics. */ 841 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 842 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 843 child = SYSCTL_CHILDREN(tree); 844 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 845 &stats->rx_frames, "Good frames"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 847 &stats->rx_bcast_frames, "Good broadcast frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 849 &stats->rx_mcast_frames, "Good multicast frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 851 &stats->rx_pause_frames, "Pause control frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 853 &stats->rx_control_frames, "Control frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 855 &stats->rx_crcerrs, "CRC errors"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 857 &stats->rx_lenerrs, "Frames with length mismatched"); 858 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 859 &stats->rx_bytes, "Good octets"); 860 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 861 &stats->rx_bcast_bytes, "Good broadcast octets"); 862 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 863 &stats->rx_mcast_bytes, "Good multicast octets"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 865 &stats->rx_runts, "Too short frames"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 867 &stats->rx_fragments, "Fragmented frames"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 869 &stats->rx_pkts_64, "64 bytes frames"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 871 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 873 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 875 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 877 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 879 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 881 &stats->rx_pkts_1519_max, "1519 to max frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 883 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 885 &stats->rx_fifo_oflows, "FIFO overflows"); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 887 &stats->rx_rrs_errs, "Return status write-back errors"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 889 &stats->rx_alignerrs, "Alignment errors"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 891 &stats->rx_pkts_filtered, 892 "Frames dropped due to address filtering"); 893 894 /* Tx statistics. */ 895 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 896 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 897 child = SYSCTL_CHILDREN(tree); 898 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 899 &stats->tx_frames, "Good frames"); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 901 &stats->tx_bcast_frames, "Good broadcast frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 903 &stats->tx_mcast_frames, "Good multicast frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 905 &stats->tx_pause_frames, "Pause control frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 907 &stats->tx_control_frames, "Control frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 909 &stats->tx_excess_defer, "Frames with excessive derferrals"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 911 &stats->tx_excess_defer, "Frames with derferrals"); 912 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 913 &stats->tx_bytes, "Good octets"); 914 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 915 &stats->tx_bcast_bytes, "Good broadcast octets"); 916 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 917 &stats->tx_mcast_bytes, "Good multicast octets"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 919 &stats->tx_pkts_64, "64 bytes frames"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 921 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 923 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 924 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 925 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 927 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 929 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 930 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 931 &stats->tx_pkts_1519_max, "1519 to max frames"); 932 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 933 &stats->tx_single_colls, "Single collisions"); 934 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 935 &stats->tx_multi_colls, "Multiple collisions"); 936 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 937 &stats->tx_late_colls, "Late collisions"); 938 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 939 &stats->tx_excess_colls, "Excessive collisions"); 940 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 941 &stats->tx_underrun, "FIFO underruns"); 942 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 943 &stats->tx_desc_underrun, "Descriptor write-back errors"); 944 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 945 &stats->tx_lenerrs, "Frames with length mismatched"); 946 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 947 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 948 } 949 950 #undef ALE_SYSCTL_STAT_ADD32 951 #undef ALE_SYSCTL_STAT_ADD64 952 953 struct ale_dmamap_arg { 954 bus_addr_t ale_busaddr; 955 }; 956 957 static void 958 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 959 { 960 struct ale_dmamap_arg *ctx; 961 962 if (error != 0) 963 return; 964 965 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 966 967 ctx = (struct ale_dmamap_arg *)arg; 968 ctx->ale_busaddr = segs[0].ds_addr; 969 } 970 971 /* 972 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 973 * which specifies high address region of DMA blocks. Therefore these 974 * blocks should have the same high address of given 4GB address 975 * space(i.e. crossing 4GB boundary is not allowed). 976 */ 977 static int 978 ale_check_boundary(struct ale_softc *sc) 979 { 980 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 981 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 982 983 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 984 sc->ale_pagesize; 985 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 986 sc->ale_pagesize; 987 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 988 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 989 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 990 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 991 992 if ((ALE_ADDR_HI(tx_ring_end) != 993 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 994 (ALE_ADDR_HI(rx_page_end[0]) != 995 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 996 (ALE_ADDR_HI(rx_page_end[1]) != 997 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 998 (ALE_ADDR_HI(tx_cmb_end) != 999 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1000 (ALE_ADDR_HI(rx_cmb_end[0]) != 1001 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1002 (ALE_ADDR_HI(rx_cmb_end[1]) != 1003 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1004 return (EFBIG); 1005 1006 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1007 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1008 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1009 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1010 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1011 return (EFBIG); 1012 1013 return (0); 1014 } 1015 1016 static int 1017 ale_dma_alloc(struct ale_softc *sc) 1018 { 1019 struct ale_txdesc *txd; 1020 bus_addr_t lowaddr; 1021 struct ale_dmamap_arg ctx; 1022 int error, guard_size, i; 1023 1024 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1025 guard_size = ALE_JUMBO_FRAMELEN; 1026 else 1027 guard_size = ALE_MAX_FRAMELEN; 1028 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1029 ALE_RX_PAGE_ALIGN); 1030 lowaddr = BUS_SPACE_MAXADDR; 1031 again: 1032 /* Create parent DMA tag. */ 1033 error = bus_dma_tag_create( 1034 bus_get_dma_tag(sc->ale_dev), /* parent */ 1035 1, 0, /* alignment, boundary */ 1036 lowaddr, /* lowaddr */ 1037 BUS_SPACE_MAXADDR, /* highaddr */ 1038 NULL, NULL, /* filter, filterarg */ 1039 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1040 0, /* nsegments */ 1041 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1042 0, /* flags */ 1043 NULL, NULL, /* lockfunc, lockarg */ 1044 &sc->ale_cdata.ale_parent_tag); 1045 if (error != 0) { 1046 device_printf(sc->ale_dev, 1047 "could not create parent DMA tag.\n"); 1048 goto fail; 1049 } 1050 1051 /* Create DMA tag for Tx descriptor ring. */ 1052 error = bus_dma_tag_create( 1053 sc->ale_cdata.ale_parent_tag, /* parent */ 1054 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1055 BUS_SPACE_MAXADDR, /* lowaddr */ 1056 BUS_SPACE_MAXADDR, /* highaddr */ 1057 NULL, NULL, /* filter, filterarg */ 1058 ALE_TX_RING_SZ, /* maxsize */ 1059 1, /* nsegments */ 1060 ALE_TX_RING_SZ, /* maxsegsize */ 1061 0, /* flags */ 1062 NULL, NULL, /* lockfunc, lockarg */ 1063 &sc->ale_cdata.ale_tx_ring_tag); 1064 if (error != 0) { 1065 device_printf(sc->ale_dev, 1066 "could not create Tx ring DMA tag.\n"); 1067 goto fail; 1068 } 1069 1070 /* Create DMA tag for Rx pages. */ 1071 for (i = 0; i < ALE_RX_PAGES; i++) { 1072 error = bus_dma_tag_create( 1073 sc->ale_cdata.ale_parent_tag, /* parent */ 1074 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1075 BUS_SPACE_MAXADDR, /* lowaddr */ 1076 BUS_SPACE_MAXADDR, /* highaddr */ 1077 NULL, NULL, /* filter, filterarg */ 1078 sc->ale_pagesize, /* maxsize */ 1079 1, /* nsegments */ 1080 sc->ale_pagesize, /* maxsegsize */ 1081 0, /* flags */ 1082 NULL, NULL, /* lockfunc, lockarg */ 1083 &sc->ale_cdata.ale_rx_page[i].page_tag); 1084 if (error != 0) { 1085 device_printf(sc->ale_dev, 1086 "could not create Rx page %d DMA tag.\n", i); 1087 goto fail; 1088 } 1089 } 1090 1091 /* Create DMA tag for Tx coalescing message block. */ 1092 error = bus_dma_tag_create( 1093 sc->ale_cdata.ale_parent_tag, /* parent */ 1094 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1095 BUS_SPACE_MAXADDR, /* lowaddr */ 1096 BUS_SPACE_MAXADDR, /* highaddr */ 1097 NULL, NULL, /* filter, filterarg */ 1098 ALE_TX_CMB_SZ, /* maxsize */ 1099 1, /* nsegments */ 1100 ALE_TX_CMB_SZ, /* maxsegsize */ 1101 0, /* flags */ 1102 NULL, NULL, /* lockfunc, lockarg */ 1103 &sc->ale_cdata.ale_tx_cmb_tag); 1104 if (error != 0) { 1105 device_printf(sc->ale_dev, 1106 "could not create Tx CMB DMA tag.\n"); 1107 goto fail; 1108 } 1109 1110 /* Create DMA tag for Rx coalescing message block. */ 1111 for (i = 0; i < ALE_RX_PAGES; i++) { 1112 error = bus_dma_tag_create( 1113 sc->ale_cdata.ale_parent_tag, /* parent */ 1114 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1115 BUS_SPACE_MAXADDR, /* lowaddr */ 1116 BUS_SPACE_MAXADDR, /* highaddr */ 1117 NULL, NULL, /* filter, filterarg */ 1118 ALE_RX_CMB_SZ, /* maxsize */ 1119 1, /* nsegments */ 1120 ALE_RX_CMB_SZ, /* maxsegsize */ 1121 0, /* flags */ 1122 NULL, NULL, /* lockfunc, lockarg */ 1123 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1124 if (error != 0) { 1125 device_printf(sc->ale_dev, 1126 "could not create Rx page %d CMB DMA tag.\n", i); 1127 goto fail; 1128 } 1129 } 1130 1131 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1132 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1133 (void **)&sc->ale_cdata.ale_tx_ring, 1134 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1135 &sc->ale_cdata.ale_tx_ring_map); 1136 if (error != 0) { 1137 device_printf(sc->ale_dev, 1138 "could not allocate DMA'able memory for Tx ring.\n"); 1139 goto fail; 1140 } 1141 ctx.ale_busaddr = 0; 1142 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1143 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1144 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1145 if (error != 0 || ctx.ale_busaddr == 0) { 1146 device_printf(sc->ale_dev, 1147 "could not load DMA'able memory for Tx ring.\n"); 1148 goto fail; 1149 } 1150 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1151 1152 /* Rx pages. */ 1153 for (i = 0; i < ALE_RX_PAGES; i++) { 1154 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1155 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1156 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1157 &sc->ale_cdata.ale_rx_page[i].page_map); 1158 if (error != 0) { 1159 device_printf(sc->ale_dev, 1160 "could not allocate DMA'able memory for " 1161 "Rx page %d.\n", i); 1162 goto fail; 1163 } 1164 ctx.ale_busaddr = 0; 1165 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1166 sc->ale_cdata.ale_rx_page[i].page_map, 1167 sc->ale_cdata.ale_rx_page[i].page_addr, 1168 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1169 if (error != 0 || ctx.ale_busaddr == 0) { 1170 device_printf(sc->ale_dev, 1171 "could not load DMA'able memory for " 1172 "Rx page %d.\n", i); 1173 goto fail; 1174 } 1175 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1176 } 1177 1178 /* Tx CMB. */ 1179 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1180 (void **)&sc->ale_cdata.ale_tx_cmb, 1181 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1182 &sc->ale_cdata.ale_tx_cmb_map); 1183 if (error != 0) { 1184 device_printf(sc->ale_dev, 1185 "could not allocate DMA'able memory for Tx CMB.\n"); 1186 goto fail; 1187 } 1188 ctx.ale_busaddr = 0; 1189 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1190 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1191 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1192 if (error != 0 || ctx.ale_busaddr == 0) { 1193 device_printf(sc->ale_dev, 1194 "could not load DMA'able memory for Tx CMB.\n"); 1195 goto fail; 1196 } 1197 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1198 1199 /* Rx CMB. */ 1200 for (i = 0; i < ALE_RX_PAGES; i++) { 1201 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1202 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1203 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1204 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1205 if (error != 0) { 1206 device_printf(sc->ale_dev, "could not allocate " 1207 "DMA'able memory for Rx page %d CMB.\n", i); 1208 goto fail; 1209 } 1210 ctx.ale_busaddr = 0; 1211 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1212 sc->ale_cdata.ale_rx_page[i].cmb_map, 1213 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1214 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1215 if (error != 0 || ctx.ale_busaddr == 0) { 1216 device_printf(sc->ale_dev, "could not load DMA'able " 1217 "memory for Rx page %d CMB.\n", i); 1218 goto fail; 1219 } 1220 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1221 } 1222 1223 /* 1224 * Tx descriptors/RXF0/CMB DMA blocks share the same 1225 * high address region of 64bit DMA address space. 1226 */ 1227 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1228 (error = ale_check_boundary(sc)) != 0) { 1229 device_printf(sc->ale_dev, "4GB boundary crossed, " 1230 "switching to 32bit DMA addressing mode.\n"); 1231 ale_dma_free(sc); 1232 /* 1233 * Limit max allowable DMA address space to 32bit 1234 * and try again. 1235 */ 1236 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1237 goto again; 1238 } 1239 1240 /* 1241 * Create Tx buffer parent tag. 1242 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1243 * needs separate parent DMA tag as parent DMA address space 1244 * could be restricted to be within 32bit address space by 1245 * 4GB boundary crossing. 1246 */ 1247 error = bus_dma_tag_create( 1248 bus_get_dma_tag(sc->ale_dev), /* parent */ 1249 1, 0, /* alignment, boundary */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1254 0, /* nsegments */ 1255 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1256 0, /* flags */ 1257 NULL, NULL, /* lockfunc, lockarg */ 1258 &sc->ale_cdata.ale_buffer_tag); 1259 if (error != 0) { 1260 device_printf(sc->ale_dev, 1261 "could not create parent buffer DMA tag.\n"); 1262 goto fail; 1263 } 1264 1265 /* Create DMA tag for Tx buffers. */ 1266 error = bus_dma_tag_create( 1267 sc->ale_cdata.ale_buffer_tag, /* parent */ 1268 1, 0, /* alignment, boundary */ 1269 BUS_SPACE_MAXADDR, /* lowaddr */ 1270 BUS_SPACE_MAXADDR, /* highaddr */ 1271 NULL, NULL, /* filter, filterarg */ 1272 ALE_TSO_MAXSIZE, /* maxsize */ 1273 ALE_MAXTXSEGS, /* nsegments */ 1274 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1275 0, /* flags */ 1276 NULL, NULL, /* lockfunc, lockarg */ 1277 &sc->ale_cdata.ale_tx_tag); 1278 if (error != 0) { 1279 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1280 goto fail; 1281 } 1282 1283 /* Create DMA maps for Tx buffers. */ 1284 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1285 txd = &sc->ale_cdata.ale_txdesc[i]; 1286 txd->tx_m = NULL; 1287 txd->tx_dmamap = NULL; 1288 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1289 &txd->tx_dmamap); 1290 if (error != 0) { 1291 device_printf(sc->ale_dev, 1292 "could not create Tx dmamap.\n"); 1293 goto fail; 1294 } 1295 } 1296 1297 fail: 1298 return (error); 1299 } 1300 1301 static void 1302 ale_dma_free(struct ale_softc *sc) 1303 { 1304 struct ale_txdesc *txd; 1305 int i; 1306 1307 /* Tx buffers. */ 1308 if (sc->ale_cdata.ale_tx_tag != NULL) { 1309 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1310 txd = &sc->ale_cdata.ale_txdesc[i]; 1311 if (txd->tx_dmamap != NULL) { 1312 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1313 txd->tx_dmamap); 1314 txd->tx_dmamap = NULL; 1315 } 1316 } 1317 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1318 sc->ale_cdata.ale_tx_tag = NULL; 1319 } 1320 /* Tx descriptor ring. */ 1321 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1322 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1323 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1324 sc->ale_cdata.ale_tx_ring_map); 1325 if (sc->ale_cdata.ale_tx_ring != NULL) 1326 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1327 sc->ale_cdata.ale_tx_ring, 1328 sc->ale_cdata.ale_tx_ring_map); 1329 sc->ale_cdata.ale_tx_ring_paddr = 0; 1330 sc->ale_cdata.ale_tx_ring = NULL; 1331 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1332 sc->ale_cdata.ale_tx_ring_tag = NULL; 1333 } 1334 /* Rx page block. */ 1335 for (i = 0; i < ALE_RX_PAGES; i++) { 1336 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1337 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1338 bus_dmamap_unload( 1339 sc->ale_cdata.ale_rx_page[i].page_tag, 1340 sc->ale_cdata.ale_rx_page[i].page_map); 1341 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1342 bus_dmamem_free( 1343 sc->ale_cdata.ale_rx_page[i].page_tag, 1344 sc->ale_cdata.ale_rx_page[i].page_addr, 1345 sc->ale_cdata.ale_rx_page[i].page_map); 1346 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1347 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1348 bus_dma_tag_destroy( 1349 sc->ale_cdata.ale_rx_page[i].page_tag); 1350 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1351 } 1352 } 1353 /* Rx CMB. */ 1354 for (i = 0; i < ALE_RX_PAGES; i++) { 1355 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1356 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1357 bus_dmamap_unload( 1358 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1359 sc->ale_cdata.ale_rx_page[i].cmb_map); 1360 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1361 bus_dmamem_free( 1362 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1363 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1364 sc->ale_cdata.ale_rx_page[i].cmb_map); 1365 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1366 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1367 bus_dma_tag_destroy( 1368 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1369 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1370 } 1371 } 1372 /* Tx CMB. */ 1373 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1374 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1375 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1376 sc->ale_cdata.ale_tx_cmb_map); 1377 if (sc->ale_cdata.ale_tx_cmb != NULL) 1378 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1379 sc->ale_cdata.ale_tx_cmb, 1380 sc->ale_cdata.ale_tx_cmb_map); 1381 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1382 sc->ale_cdata.ale_tx_cmb = NULL; 1383 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1384 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1385 } 1386 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1387 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1388 sc->ale_cdata.ale_buffer_tag = NULL; 1389 } 1390 if (sc->ale_cdata.ale_parent_tag != NULL) { 1391 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1392 sc->ale_cdata.ale_parent_tag = NULL; 1393 } 1394 } 1395 1396 static int 1397 ale_shutdown(device_t dev) 1398 { 1399 1400 return (ale_suspend(dev)); 1401 } 1402 1403 /* 1404 * Note, this driver resets the link speed to 10/100Mbps by 1405 * restarting auto-negotiation in suspend/shutdown phase but we 1406 * don't know whether that auto-negotiation would succeed or not 1407 * as driver has no control after powering off/suspend operation. 1408 * If the renegotiation fail WOL may not work. Running at 1Gbps 1409 * will draw more power than 375mA at 3.3V which is specified in 1410 * PCI specification and that would result in complete 1411 * shutdowning power to ethernet controller. 1412 * 1413 * TODO 1414 * Save current negotiated media speed/duplex/flow-control to 1415 * softc and restore the same link again after resuming. PHY 1416 * handling such as power down/resetting to 100Mbps may be better 1417 * handled in suspend method in phy driver. 1418 */ 1419 static void 1420 ale_setlinkspeed(struct ale_softc *sc) 1421 { 1422 struct mii_data *mii; 1423 int aneg, i; 1424 1425 mii = device_get_softc(sc->ale_miibus); 1426 mii_pollstat(mii); 1427 aneg = 0; 1428 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1429 (IFM_ACTIVE | IFM_AVALID)) { 1430 switch IFM_SUBTYPE(mii->mii_media_active) { 1431 case IFM_10_T: 1432 case IFM_100_TX: 1433 return; 1434 case IFM_1000_T: 1435 aneg++; 1436 break; 1437 default: 1438 break; 1439 } 1440 } 1441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1443 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1445 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1446 DELAY(1000); 1447 if (aneg != 0) { 1448 /* 1449 * Poll link state until ale(4) get a 10/100Mbps link. 1450 */ 1451 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1452 mii_pollstat(mii); 1453 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1454 == (IFM_ACTIVE | IFM_AVALID)) { 1455 switch (IFM_SUBTYPE( 1456 mii->mii_media_active)) { 1457 case IFM_10_T: 1458 case IFM_100_TX: 1459 ale_mac_config(sc); 1460 return; 1461 default: 1462 break; 1463 } 1464 } 1465 ALE_UNLOCK(sc); 1466 pause("alelnk", hz); 1467 ALE_LOCK(sc); 1468 } 1469 if (i == MII_ANEGTICKS_GIGE) 1470 device_printf(sc->ale_dev, 1471 "establishing a link failed, WOL may not work!"); 1472 } 1473 /* 1474 * No link, force MAC to have 100Mbps, full-duplex link. 1475 * This is the last resort and may/may not work. 1476 */ 1477 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1478 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1479 ale_mac_config(sc); 1480 } 1481 1482 static void 1483 ale_setwol(struct ale_softc *sc) 1484 { 1485 if_t ifp; 1486 uint32_t reg, pmcs; 1487 uint16_t pmstat; 1488 int pmc; 1489 1490 ALE_LOCK_ASSERT(sc); 1491 1492 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1493 /* Disable WOL. */ 1494 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1495 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1496 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1497 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1498 /* Force PHY power down. */ 1499 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1500 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1501 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1502 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1503 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1504 return; 1505 } 1506 1507 ifp = sc->ale_ifp; 1508 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1509 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1510 ale_setlinkspeed(sc); 1511 } 1512 1513 pmcs = 0; 1514 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1515 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1516 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1517 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1518 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1519 MAC_CFG_BCAST); 1520 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1521 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1522 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1523 reg |= MAC_CFG_RX_ENB; 1524 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1525 1526 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1527 /* WOL disabled, PHY power down. */ 1528 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1529 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1530 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1531 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1532 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1533 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1534 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1535 GPHY_CTRL_PWDOWN_HW); 1536 } 1537 /* Request PME. */ 1538 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1539 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1540 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1541 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1542 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1543 } 1544 1545 static int 1546 ale_suspend(device_t dev) 1547 { 1548 struct ale_softc *sc; 1549 1550 sc = device_get_softc(dev); 1551 1552 ALE_LOCK(sc); 1553 ale_stop(sc); 1554 ale_setwol(sc); 1555 ALE_UNLOCK(sc); 1556 1557 return (0); 1558 } 1559 1560 static int 1561 ale_resume(device_t dev) 1562 { 1563 struct ale_softc *sc; 1564 if_t ifp; 1565 int pmc; 1566 uint16_t pmstat; 1567 1568 sc = device_get_softc(dev); 1569 1570 ALE_LOCK(sc); 1571 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1572 /* Disable PME and clear PME status. */ 1573 pmstat = pci_read_config(sc->ale_dev, 1574 pmc + PCIR_POWER_STATUS, 2); 1575 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1576 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1577 pci_write_config(sc->ale_dev, 1578 pmc + PCIR_POWER_STATUS, pmstat, 2); 1579 } 1580 } 1581 /* Reset PHY. */ 1582 ale_phy_reset(sc); 1583 ifp = sc->ale_ifp; 1584 if ((if_getflags(ifp) & IFF_UP) != 0) { 1585 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1586 ale_init_locked(sc); 1587 } 1588 ALE_UNLOCK(sc); 1589 1590 return (0); 1591 } 1592 1593 static int 1594 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1595 { 1596 struct ale_txdesc *txd, *txd_last; 1597 struct tx_desc *desc; 1598 struct mbuf *m; 1599 struct ip *ip; 1600 struct tcphdr *tcp; 1601 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1602 bus_dmamap_t map; 1603 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1604 int error, i, nsegs, prod, si; 1605 1606 ALE_LOCK_ASSERT(sc); 1607 1608 M_ASSERTPKTHDR((*m_head)); 1609 1610 m = *m_head; 1611 ip = NULL; 1612 tcp = NULL; 1613 cflags = vtag = 0; 1614 ip_off = poff = 0; 1615 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1616 /* 1617 * AR81xx requires offset of TCP/UDP payload in its Tx 1618 * descriptor to perform hardware Tx checksum offload. 1619 * Additionally, TSO requires IP/TCP header size and 1620 * modification of IP/TCP header in order to make TSO 1621 * engine work. This kind of operation takes many CPU 1622 * cycles on FreeBSD so fast host CPU is required to 1623 * get smooth TSO performance. 1624 */ 1625 struct ether_header *eh; 1626 1627 if (M_WRITABLE(m) == 0) { 1628 /* Get a writable copy. */ 1629 m = m_dup(*m_head, M_NOWAIT); 1630 /* Release original mbufs. */ 1631 m_freem(*m_head); 1632 if (m == NULL) { 1633 *m_head = NULL; 1634 return (ENOBUFS); 1635 } 1636 *m_head = m; 1637 } 1638 1639 /* 1640 * Buggy-controller requires 4 byte aligned Tx buffer 1641 * to make custom checksum offload work. 1642 */ 1643 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1644 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1645 (mtod(m, intptr_t) & 3) != 0) { 1646 m = m_defrag(*m_head, M_NOWAIT); 1647 if (m == NULL) { 1648 m_freem(*m_head); 1649 *m_head = NULL; 1650 return (ENOBUFS); 1651 } 1652 *m_head = m; 1653 } 1654 1655 ip_off = sizeof(struct ether_header); 1656 m = m_pullup(m, ip_off); 1657 if (m == NULL) { 1658 *m_head = NULL; 1659 return (ENOBUFS); 1660 } 1661 eh = mtod(m, struct ether_header *); 1662 /* 1663 * Check if hardware VLAN insertion is off. 1664 * Additional check for LLC/SNAP frame? 1665 */ 1666 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1667 ip_off = sizeof(struct ether_vlan_header); 1668 m = m_pullup(m, ip_off); 1669 if (m == NULL) { 1670 *m_head = NULL; 1671 return (ENOBUFS); 1672 } 1673 } 1674 m = m_pullup(m, ip_off + sizeof(struct ip)); 1675 if (m == NULL) { 1676 *m_head = NULL; 1677 return (ENOBUFS); 1678 } 1679 ip = (struct ip *)(mtod(m, char *) + ip_off); 1680 poff = ip_off + (ip->ip_hl << 2); 1681 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1682 /* 1683 * XXX 1684 * AR81xx requires the first descriptor should 1685 * not include any TCP playload for TSO case. 1686 * (i.e. ethernet header + IP + TCP header only) 1687 * m_pullup(9) above will ensure this too. 1688 * However it's not correct if the first mbuf 1689 * of the chain does not use cluster. 1690 */ 1691 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1692 if (m == NULL) { 1693 *m_head = NULL; 1694 return (ENOBUFS); 1695 } 1696 ip = (struct ip *)(mtod(m, char *) + ip_off); 1697 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1698 m = m_pullup(m, poff + (tcp->th_off << 2)); 1699 if (m == NULL) { 1700 *m_head = NULL; 1701 return (ENOBUFS); 1702 } 1703 /* 1704 * AR81xx requires IP/TCP header size and offset as 1705 * well as TCP pseudo checksum which complicates 1706 * TSO configuration. I guess this comes from the 1707 * adherence to Microsoft NDIS Large Send 1708 * specification which requires insertion of 1709 * pseudo checksum by upper stack. The pseudo 1710 * checksum that NDIS refers to doesn't include 1711 * TCP payload length so ale(4) should recompute 1712 * the pseudo checksum here. Hopefully this wouldn't 1713 * be much burden on modern CPUs. 1714 * Reset IP checksum and recompute TCP pseudo 1715 * checksum as NDIS specification said. 1716 */ 1717 ip->ip_sum = 0; 1718 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1719 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1720 } 1721 *m_head = m; 1722 } 1723 1724 si = prod = sc->ale_cdata.ale_tx_prod; 1725 txd = &sc->ale_cdata.ale_txdesc[prod]; 1726 txd_last = txd; 1727 map = txd->tx_dmamap; 1728 1729 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1730 *m_head, txsegs, &nsegs, 0); 1731 if (error == EFBIG) { 1732 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1733 if (m == NULL) { 1734 m_freem(*m_head); 1735 *m_head = NULL; 1736 return (ENOMEM); 1737 } 1738 *m_head = m; 1739 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1740 *m_head, txsegs, &nsegs, 0); 1741 if (error != 0) { 1742 m_freem(*m_head); 1743 *m_head = NULL; 1744 return (error); 1745 } 1746 } else if (error != 0) 1747 return (error); 1748 if (nsegs == 0) { 1749 m_freem(*m_head); 1750 *m_head = NULL; 1751 return (EIO); 1752 } 1753 1754 /* Check descriptor overrun. */ 1755 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1756 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1757 return (ENOBUFS); 1758 } 1759 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1760 1761 m = *m_head; 1762 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1763 /* Request TSO and set MSS. */ 1764 cflags |= ALE_TD_TSO; 1765 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1766 /* Set IP/TCP header size. */ 1767 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1768 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1769 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1770 /* 1771 * AR81xx supports Tx custom checksum offload feature 1772 * that offloads single 16bit checksum computation. 1773 * So you can choose one among IP, TCP and UDP. 1774 * Normally driver sets checksum start/insertion 1775 * position from the information of TCP/UDP frame as 1776 * TCP/UDP checksum takes more time than that of IP. 1777 * However it seems that custom checksum offload 1778 * requires 4 bytes aligned Tx buffers due to hardware 1779 * bug. 1780 * AR81xx also supports explicit Tx checksum computation 1781 * if it is told that the size of IP header and TCP 1782 * header(for UDP, the header size does not matter 1783 * because it's fixed length). However with this scheme 1784 * TSO does not work so you have to choose one either 1785 * TSO or explicit Tx checksum offload. I chosen TSO 1786 * plus custom checksum offload with work-around which 1787 * will cover most common usage for this consumer 1788 * ethernet controller. The work-around takes a lot of 1789 * CPU cycles if Tx buffer is not aligned on 4 bytes 1790 * boundary, though. 1791 */ 1792 cflags |= ALE_TD_CXSUM; 1793 /* Set checksum start offset. */ 1794 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1795 /* Set checksum insertion position of TCP/UDP. */ 1796 cflags |= ((poff + m->m_pkthdr.csum_data) << 1797 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1798 } 1799 1800 /* Configure VLAN hardware tag insertion. */ 1801 if ((m->m_flags & M_VLANTAG) != 0) { 1802 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1803 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1804 cflags |= ALE_TD_INSERT_VLAN_TAG; 1805 } 1806 1807 i = 0; 1808 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1809 /* 1810 * Make sure the first fragment contains 1811 * only ethernet and IP/TCP header with options. 1812 */ 1813 hdrlen = poff + (tcp->th_off << 2); 1814 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1815 desc->addr = htole64(txsegs[i].ds_addr); 1816 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1817 desc->flags = htole32(cflags); 1818 sc->ale_cdata.ale_tx_cnt++; 1819 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1820 if (m->m_len - hdrlen > 0) { 1821 /* Handle remaining payload of the first fragment. */ 1822 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1823 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1824 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1825 vtag); 1826 desc->flags = htole32(cflags); 1827 sc->ale_cdata.ale_tx_cnt++; 1828 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1829 } 1830 i = 1; 1831 } 1832 for (; i < nsegs; i++) { 1833 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1834 desc->addr = htole64(txsegs[i].ds_addr); 1835 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1836 desc->flags = htole32(cflags); 1837 sc->ale_cdata.ale_tx_cnt++; 1838 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1839 } 1840 /* Update producer index. */ 1841 sc->ale_cdata.ale_tx_prod = prod; 1842 /* Set TSO header on the first descriptor. */ 1843 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1844 desc = &sc->ale_cdata.ale_tx_ring[si]; 1845 desc->flags |= htole32(ALE_TD_TSO_HDR); 1846 } 1847 1848 /* Finally set EOP on the last descriptor. */ 1849 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1850 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1851 desc->flags |= htole32(ALE_TD_EOP); 1852 1853 /* Swap dmamap of the first and the last. */ 1854 txd = &sc->ale_cdata.ale_txdesc[prod]; 1855 map = txd_last->tx_dmamap; 1856 txd_last->tx_dmamap = txd->tx_dmamap; 1857 txd->tx_dmamap = map; 1858 txd->tx_m = m; 1859 1860 /* Sync descriptors. */ 1861 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1862 sc->ale_cdata.ale_tx_ring_map, 1863 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1864 1865 return (0); 1866 } 1867 1868 static void 1869 ale_start(if_t ifp) 1870 { 1871 struct ale_softc *sc; 1872 1873 sc = if_getsoftc(ifp); 1874 ALE_LOCK(sc); 1875 ale_start_locked(ifp); 1876 ALE_UNLOCK(sc); 1877 } 1878 1879 static void 1880 ale_start_locked(if_t ifp) 1881 { 1882 struct ale_softc *sc; 1883 struct mbuf *m_head; 1884 int enq; 1885 1886 sc = if_getsoftc(ifp); 1887 1888 ALE_LOCK_ASSERT(sc); 1889 1890 /* Reclaim transmitted frames. */ 1891 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1892 ale_txeof(sc); 1893 1894 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1895 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1896 return; 1897 1898 for (enq = 0; !if_sendq_empty(ifp); ) { 1899 m_head = if_dequeue(ifp); 1900 if (m_head == NULL) 1901 break; 1902 /* 1903 * Pack the data into the transmit ring. If we 1904 * don't have room, set the OACTIVE flag and wait 1905 * for the NIC to drain the ring. 1906 */ 1907 if (ale_encap(sc, &m_head)) { 1908 if (m_head == NULL) 1909 break; 1910 if_sendq_prepend(ifp, m_head); 1911 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1912 break; 1913 } 1914 1915 enq++; 1916 /* 1917 * If there's a BPF listener, bounce a copy of this frame 1918 * to him. 1919 */ 1920 ETHER_BPF_MTAP(ifp, m_head); 1921 } 1922 1923 if (enq > 0) { 1924 /* Kick. */ 1925 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1926 sc->ale_cdata.ale_tx_prod); 1927 /* Set a timeout in case the chip goes out to lunch. */ 1928 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1929 } 1930 } 1931 1932 static void 1933 ale_watchdog(struct ale_softc *sc) 1934 { 1935 if_t ifp; 1936 1937 ALE_LOCK_ASSERT(sc); 1938 1939 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1940 return; 1941 1942 ifp = sc->ale_ifp; 1943 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1944 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1945 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1946 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1947 ale_init_locked(sc); 1948 return; 1949 } 1950 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1951 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1952 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1953 ale_init_locked(sc); 1954 if (!if_sendq_empty(ifp)) 1955 ale_start_locked(ifp); 1956 } 1957 1958 static int 1959 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1960 { 1961 struct ale_softc *sc; 1962 struct ifreq *ifr; 1963 struct mii_data *mii; 1964 int error, mask; 1965 1966 sc = if_getsoftc(ifp); 1967 ifr = (struct ifreq *)data; 1968 error = 0; 1969 switch (cmd) { 1970 case SIOCSIFMTU: 1971 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1972 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1973 ifr->ifr_mtu > ETHERMTU)) 1974 error = EINVAL; 1975 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1976 ALE_LOCK(sc); 1977 if_setmtu(ifp, ifr->ifr_mtu); 1978 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1979 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1980 ale_init_locked(sc); 1981 } 1982 ALE_UNLOCK(sc); 1983 } 1984 break; 1985 case SIOCSIFFLAGS: 1986 ALE_LOCK(sc); 1987 if ((if_getflags(ifp) & IFF_UP) != 0) { 1988 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1989 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1990 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1991 ale_rxfilter(sc); 1992 } else { 1993 ale_init_locked(sc); 1994 } 1995 } else { 1996 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1997 ale_stop(sc); 1998 } 1999 sc->ale_if_flags = if_getflags(ifp); 2000 ALE_UNLOCK(sc); 2001 break; 2002 case SIOCADDMULTI: 2003 case SIOCDELMULTI: 2004 ALE_LOCK(sc); 2005 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2006 ale_rxfilter(sc); 2007 ALE_UNLOCK(sc); 2008 break; 2009 case SIOCSIFMEDIA: 2010 case SIOCGIFMEDIA: 2011 mii = device_get_softc(sc->ale_miibus); 2012 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2013 break; 2014 case SIOCSIFCAP: 2015 ALE_LOCK(sc); 2016 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2017 if ((mask & IFCAP_TXCSUM) != 0 && 2018 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2019 if_togglecapenable(ifp, IFCAP_TXCSUM); 2020 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2021 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 2022 else 2023 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 2024 } 2025 if ((mask & IFCAP_RXCSUM) != 0 && 2026 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2027 if_togglecapenable(ifp, IFCAP_RXCSUM); 2028 if ((mask & IFCAP_TSO4) != 0 && 2029 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2030 if_togglecapenable(ifp, IFCAP_TSO4); 2031 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2032 if_sethwassistbits(ifp, CSUM_TSO, 0); 2033 else 2034 if_sethwassistbits(ifp, 0, CSUM_TSO); 2035 } 2036 2037 if ((mask & IFCAP_WOL_MCAST) != 0 && 2038 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2039 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2040 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2041 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2042 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2043 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2044 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2045 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2046 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2047 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2048 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2049 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2050 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2051 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2052 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2053 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2054 ale_rxvlan(sc); 2055 } 2056 ALE_UNLOCK(sc); 2057 VLAN_CAPABILITIES(ifp); 2058 break; 2059 default: 2060 error = ether_ioctl(ifp, cmd, data); 2061 break; 2062 } 2063 2064 return (error); 2065 } 2066 2067 static void 2068 ale_mac_config(struct ale_softc *sc) 2069 { 2070 struct mii_data *mii; 2071 uint32_t reg; 2072 2073 ALE_LOCK_ASSERT(sc); 2074 2075 mii = device_get_softc(sc->ale_miibus); 2076 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2077 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2078 MAC_CFG_SPEED_MASK); 2079 /* Reprogram MAC with resolved speed/duplex. */ 2080 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2081 case IFM_10_T: 2082 case IFM_100_TX: 2083 reg |= MAC_CFG_SPEED_10_100; 2084 break; 2085 case IFM_1000_T: 2086 reg |= MAC_CFG_SPEED_1000; 2087 break; 2088 } 2089 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2090 reg |= MAC_CFG_FULL_DUPLEX; 2091 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2092 reg |= MAC_CFG_TX_FC; 2093 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2094 reg |= MAC_CFG_RX_FC; 2095 } 2096 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2097 } 2098 2099 static void 2100 ale_stats_clear(struct ale_softc *sc) 2101 { 2102 struct smb sb; 2103 uint32_t *reg; 2104 int i; 2105 2106 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2107 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2108 i += sizeof(uint32_t); 2109 } 2110 /* Read Tx statistics. */ 2111 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2112 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2113 i += sizeof(uint32_t); 2114 } 2115 } 2116 2117 static void 2118 ale_stats_update(struct ale_softc *sc) 2119 { 2120 struct ale_hw_stats *stat; 2121 struct smb sb, *smb; 2122 if_t ifp; 2123 uint32_t *reg; 2124 int i; 2125 2126 ALE_LOCK_ASSERT(sc); 2127 2128 ifp = sc->ale_ifp; 2129 stat = &sc->ale_stats; 2130 smb = &sb; 2131 2132 /* Read Rx statistics. */ 2133 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2134 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2135 i += sizeof(uint32_t); 2136 } 2137 /* Read Tx statistics. */ 2138 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2139 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2140 i += sizeof(uint32_t); 2141 } 2142 2143 /* Rx stats. */ 2144 stat->rx_frames += smb->rx_frames; 2145 stat->rx_bcast_frames += smb->rx_bcast_frames; 2146 stat->rx_mcast_frames += smb->rx_mcast_frames; 2147 stat->rx_pause_frames += smb->rx_pause_frames; 2148 stat->rx_control_frames += smb->rx_control_frames; 2149 stat->rx_crcerrs += smb->rx_crcerrs; 2150 stat->rx_lenerrs += smb->rx_lenerrs; 2151 stat->rx_bytes += smb->rx_bytes; 2152 stat->rx_runts += smb->rx_runts; 2153 stat->rx_fragments += smb->rx_fragments; 2154 stat->rx_pkts_64 += smb->rx_pkts_64; 2155 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2156 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2157 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2158 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2159 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2160 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2161 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2162 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2163 stat->rx_rrs_errs += smb->rx_rrs_errs; 2164 stat->rx_alignerrs += smb->rx_alignerrs; 2165 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2166 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2167 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2168 2169 /* Tx stats. */ 2170 stat->tx_frames += smb->tx_frames; 2171 stat->tx_bcast_frames += smb->tx_bcast_frames; 2172 stat->tx_mcast_frames += smb->tx_mcast_frames; 2173 stat->tx_pause_frames += smb->tx_pause_frames; 2174 stat->tx_excess_defer += smb->tx_excess_defer; 2175 stat->tx_control_frames += smb->tx_control_frames; 2176 stat->tx_deferred += smb->tx_deferred; 2177 stat->tx_bytes += smb->tx_bytes; 2178 stat->tx_pkts_64 += smb->tx_pkts_64; 2179 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2180 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2181 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2182 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2183 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2184 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2185 stat->tx_single_colls += smb->tx_single_colls; 2186 stat->tx_multi_colls += smb->tx_multi_colls; 2187 stat->tx_late_colls += smb->tx_late_colls; 2188 stat->tx_excess_colls += smb->tx_excess_colls; 2189 stat->tx_underrun += smb->tx_underrun; 2190 stat->tx_desc_underrun += smb->tx_desc_underrun; 2191 stat->tx_lenerrs += smb->tx_lenerrs; 2192 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2193 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2194 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2195 2196 /* Update counters in ifnet. */ 2197 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2198 2199 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2200 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2201 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2202 2203 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2204 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2205 2206 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2207 2208 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2209 smb->rx_crcerrs + smb->rx_lenerrs + 2210 smb->rx_runts + smb->rx_pkts_truncated + 2211 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2212 smb->rx_alignerrs); 2213 } 2214 2215 static int 2216 ale_intr(void *arg) 2217 { 2218 struct ale_softc *sc; 2219 uint32_t status; 2220 2221 sc = (struct ale_softc *)arg; 2222 2223 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2224 if ((status & ALE_INTRS) == 0) 2225 return (FILTER_STRAY); 2226 /* Disable interrupts. */ 2227 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2228 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2229 2230 return (FILTER_HANDLED); 2231 } 2232 2233 static void 2234 ale_int_task(void *arg, int pending) 2235 { 2236 struct ale_softc *sc; 2237 if_t ifp; 2238 uint32_t status; 2239 int more; 2240 2241 sc = (struct ale_softc *)arg; 2242 2243 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2244 ALE_LOCK(sc); 2245 if (sc->ale_morework != 0) 2246 status |= INTR_RX_PKT; 2247 if ((status & ALE_INTRS) == 0) 2248 goto done; 2249 2250 /* Acknowledge interrupts but still disable interrupts. */ 2251 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2252 2253 ifp = sc->ale_ifp; 2254 more = 0; 2255 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2256 more = ale_rxeof(sc, sc->ale_process_limit); 2257 if (more == EAGAIN) 2258 sc->ale_morework = 1; 2259 else if (more == EIO) { 2260 sc->ale_stats.reset_brk_seq++; 2261 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2262 ale_init_locked(sc); 2263 ALE_UNLOCK(sc); 2264 return; 2265 } 2266 2267 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2268 if ((status & INTR_DMA_RD_TO_RST) != 0) 2269 device_printf(sc->ale_dev, 2270 "DMA read error! -- resetting\n"); 2271 if ((status & INTR_DMA_WR_TO_RST) != 0) 2272 device_printf(sc->ale_dev, 2273 "DMA write error! -- resetting\n"); 2274 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2275 ale_init_locked(sc); 2276 ALE_UNLOCK(sc); 2277 return; 2278 } 2279 if (!if_sendq_empty(ifp)) 2280 ale_start_locked(ifp); 2281 } 2282 2283 if (more == EAGAIN || 2284 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2285 ALE_UNLOCK(sc); 2286 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2287 return; 2288 } 2289 2290 done: 2291 ALE_UNLOCK(sc); 2292 2293 /* Re-enable interrupts. */ 2294 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2295 } 2296 2297 static void 2298 ale_txeof(struct ale_softc *sc) 2299 { 2300 if_t ifp; 2301 struct ale_txdesc *txd; 2302 uint32_t cons, prod; 2303 int prog; 2304 2305 ALE_LOCK_ASSERT(sc); 2306 2307 ifp = sc->ale_ifp; 2308 2309 if (sc->ale_cdata.ale_tx_cnt == 0) 2310 return; 2311 2312 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2313 sc->ale_cdata.ale_tx_ring_map, 2314 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2315 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2316 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2317 sc->ale_cdata.ale_tx_cmb_map, 2318 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2319 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2320 } else 2321 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2322 cons = sc->ale_cdata.ale_tx_cons; 2323 /* 2324 * Go through our Tx list and free mbufs for those 2325 * frames which have been transmitted. 2326 */ 2327 for (prog = 0; cons != prod; prog++, 2328 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2329 if (sc->ale_cdata.ale_tx_cnt <= 0) 2330 break; 2331 prog++; 2332 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2333 sc->ale_cdata.ale_tx_cnt--; 2334 txd = &sc->ale_cdata.ale_txdesc[cons]; 2335 if (txd->tx_m != NULL) { 2336 /* Reclaim transmitted mbufs. */ 2337 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2338 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2339 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2340 txd->tx_dmamap); 2341 m_freem(txd->tx_m); 2342 txd->tx_m = NULL; 2343 } 2344 } 2345 2346 if (prog > 0) { 2347 sc->ale_cdata.ale_tx_cons = cons; 2348 /* 2349 * Unarm watchdog timer only when there is no pending 2350 * Tx descriptors in queue. 2351 */ 2352 if (sc->ale_cdata.ale_tx_cnt == 0) 2353 sc->ale_watchdog_timer = 0; 2354 } 2355 } 2356 2357 static void 2358 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2359 uint32_t length, uint32_t *prod) 2360 { 2361 struct ale_rx_page *rx_page; 2362 2363 rx_page = *page; 2364 /* Update consumer position. */ 2365 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2366 ALE_RX_PAGE_ALIGN); 2367 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2368 /* 2369 * End of Rx page reached, let hardware reuse 2370 * this page. 2371 */ 2372 rx_page->cons = 0; 2373 *rx_page->cmb_addr = 0; 2374 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2375 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2376 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2377 RXF_VALID); 2378 /* Switch to alternate Rx page. */ 2379 sc->ale_cdata.ale_rx_curp ^= 1; 2380 rx_page = *page = 2381 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2382 /* Page flipped, sync CMB and Rx page. */ 2383 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2384 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2385 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2387 /* Sync completed, cache updated producer index. */ 2388 *prod = *rx_page->cmb_addr; 2389 } 2390 } 2391 2392 /* 2393 * It seems that AR81xx controller can compute partial checksum. 2394 * The partial checksum value can be used to accelerate checksum 2395 * computation for fragmented TCP/UDP packets. Upper network stack 2396 * already takes advantage of the partial checksum value in IP 2397 * reassembly stage. But I'm not sure the correctness of the 2398 * partial hardware checksum assistance due to lack of data sheet. 2399 * In addition, the Rx feature of controller that requires copying 2400 * for every frames effectively nullifies one of most nice offload 2401 * capability of controller. 2402 */ 2403 static void 2404 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2405 { 2406 if_t ifp; 2407 struct ip *ip; 2408 char *p; 2409 2410 ifp = sc->ale_ifp; 2411 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2412 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2413 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2414 2415 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2416 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2417 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2418 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2419 m->m_pkthdr.csum_flags |= 2420 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2421 m->m_pkthdr.csum_data = 0xffff; 2422 } 2423 } else { 2424 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2425 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2426 p = mtod(m, char *); 2427 p += ETHER_HDR_LEN; 2428 if ((status & ALE_RD_802_3) != 0) 2429 p += LLC_SNAPFRAMELEN; 2430 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2431 (status & ALE_RD_VLAN) != 0) 2432 p += ETHER_VLAN_ENCAP_LEN; 2433 ip = (struct ip *)p; 2434 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2435 return; 2436 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2437 CSUM_PSEUDO_HDR; 2438 m->m_pkthdr.csum_data = 0xffff; 2439 } 2440 } 2441 /* 2442 * Don't mark bad checksum for TCP/UDP frames 2443 * as fragmented frames may always have set 2444 * bad checksummed bit of frame status. 2445 */ 2446 } 2447 2448 /* Process received frames. */ 2449 static int 2450 ale_rxeof(struct ale_softc *sc, int count) 2451 { 2452 struct ale_rx_page *rx_page; 2453 struct rx_rs *rs; 2454 if_t ifp; 2455 struct mbuf *m; 2456 uint32_t length, prod, seqno, status, vtags; 2457 int prog; 2458 2459 ifp = sc->ale_ifp; 2460 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2461 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2462 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2463 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2464 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2465 /* 2466 * Don't directly access producer index as hardware may 2467 * update it while Rx handler is in progress. It would 2468 * be even better if there is a way to let hardware 2469 * know how far driver processed its received frames. 2470 * Alternatively, hardware could provide a way to disable 2471 * CMB updates until driver acknowledges the end of CMB 2472 * access. 2473 */ 2474 prod = *rx_page->cmb_addr; 2475 for (prog = 0; prog < count; prog++) { 2476 if (rx_page->cons >= prod) 2477 break; 2478 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2479 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2480 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2481 /* 2482 * Normally I believe this should not happen unless 2483 * severe driver bug or corrupted memory. However 2484 * it seems to happen under certain conditions which 2485 * is triggered by abrupt Rx events such as initiation 2486 * of bulk transfer of remote host. It's not easy to 2487 * reproduce this and I doubt it could be related 2488 * with FIFO overflow of hardware or activity of Tx 2489 * CMB updates. I also remember similar behaviour 2490 * seen on RealTek 8139 which uses resembling Rx 2491 * scheme. 2492 */ 2493 if (bootverbose) 2494 device_printf(sc->ale_dev, 2495 "garbled seq: %u, expected: %u -- " 2496 "resetting!\n", seqno, 2497 sc->ale_cdata.ale_rx_seqno); 2498 return (EIO); 2499 } 2500 /* Frame received. */ 2501 sc->ale_cdata.ale_rx_seqno++; 2502 length = ALE_RX_BYTES(le32toh(rs->length)); 2503 status = le32toh(rs->flags); 2504 if ((status & ALE_RD_ERROR) != 0) { 2505 /* 2506 * We want to pass the following frames to upper 2507 * layer regardless of error status of Rx return 2508 * status. 2509 * 2510 * o IP/TCP/UDP checksum is bad. 2511 * o frame length and protocol specific length 2512 * does not match. 2513 */ 2514 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2515 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2516 ALE_RD_TRUNC)) != 0) { 2517 ale_rx_update_page(sc, &rx_page, length, &prod); 2518 continue; 2519 } 2520 } 2521 /* 2522 * m_devget(9) is major bottle-neck of ale(4)(It comes 2523 * from hardware limitation). For jumbo frames we could 2524 * get a slightly better performance if driver use 2525 * m_getjcl(9) with proper buffer size argument. However 2526 * that would make code more complicated and I don't 2527 * think users would expect good Rx performance numbers 2528 * on these low-end consumer ethernet controller. 2529 */ 2530 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2531 ETHER_ALIGN, ifp, NULL); 2532 if (m == NULL) { 2533 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2534 ale_rx_update_page(sc, &rx_page, length, &prod); 2535 continue; 2536 } 2537 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2538 (status & ALE_RD_IPV4) != 0) 2539 ale_rxcsum(sc, m, status); 2540 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2541 (status & ALE_RD_VLAN) != 0) { 2542 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2543 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2544 m->m_flags |= M_VLANTAG; 2545 } 2546 2547 /* Pass it to upper layer. */ 2548 ALE_UNLOCK(sc); 2549 if_input(ifp, m); 2550 ALE_LOCK(sc); 2551 2552 ale_rx_update_page(sc, &rx_page, length, &prod); 2553 } 2554 2555 return (count > 0 ? 0 : EAGAIN); 2556 } 2557 2558 static void 2559 ale_tick(void *arg) 2560 { 2561 struct ale_softc *sc; 2562 struct mii_data *mii; 2563 2564 sc = (struct ale_softc *)arg; 2565 2566 ALE_LOCK_ASSERT(sc); 2567 2568 mii = device_get_softc(sc->ale_miibus); 2569 mii_tick(mii); 2570 ale_stats_update(sc); 2571 /* 2572 * Reclaim Tx buffers that have been transferred. It's not 2573 * needed here but it would release allocated mbuf chains 2574 * faster and limit the maximum delay to a hz. 2575 */ 2576 ale_txeof(sc); 2577 ale_watchdog(sc); 2578 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2579 } 2580 2581 static void 2582 ale_reset(struct ale_softc *sc) 2583 { 2584 uint32_t reg; 2585 int i; 2586 2587 /* Initialize PCIe module. From Linux. */ 2588 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2589 2590 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2591 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2592 DELAY(10); 2593 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2594 break; 2595 } 2596 if (i == 0) 2597 device_printf(sc->ale_dev, "master reset timeout!\n"); 2598 2599 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2600 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2601 break; 2602 DELAY(10); 2603 } 2604 2605 if (i == 0) 2606 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2607 } 2608 2609 static void 2610 ale_init(void *xsc) 2611 { 2612 struct ale_softc *sc; 2613 2614 sc = (struct ale_softc *)xsc; 2615 ALE_LOCK(sc); 2616 ale_init_locked(sc); 2617 ALE_UNLOCK(sc); 2618 } 2619 2620 static void 2621 ale_init_locked(struct ale_softc *sc) 2622 { 2623 if_t ifp; 2624 struct mii_data *mii; 2625 uint8_t eaddr[ETHER_ADDR_LEN]; 2626 bus_addr_t paddr; 2627 uint32_t reg, rxf_hi, rxf_lo; 2628 2629 ALE_LOCK_ASSERT(sc); 2630 2631 ifp = sc->ale_ifp; 2632 mii = device_get_softc(sc->ale_miibus); 2633 2634 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2635 return; 2636 /* 2637 * Cancel any pending I/O. 2638 */ 2639 ale_stop(sc); 2640 /* 2641 * Reset the chip to a known state. 2642 */ 2643 ale_reset(sc); 2644 /* Initialize Tx descriptors, DMA memory blocks. */ 2645 ale_init_rx_pages(sc); 2646 ale_init_tx_ring(sc); 2647 2648 /* Reprogram the station address. */ 2649 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2650 CSR_WRITE_4(sc, ALE_PAR0, 2651 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2652 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2653 /* 2654 * Clear WOL status and disable all WOL feature as WOL 2655 * would interfere Rx operation under normal environments. 2656 */ 2657 CSR_READ_4(sc, ALE_WOL_CFG); 2658 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2659 /* 2660 * Set Tx descriptor/RXF0/CMB base addresses. They share 2661 * the same high address part of DMAable region. 2662 */ 2663 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2664 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2665 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2666 CSR_WRITE_4(sc, ALE_TPD_CNT, 2667 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2668 /* Set Rx page base address, note we use single queue. */ 2669 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2670 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2671 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2672 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2673 /* Set Tx/Rx CMB addresses. */ 2674 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2675 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2676 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2677 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2678 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2679 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2680 /* Mark RXF0 is valid. */ 2681 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2682 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2683 /* 2684 * No need to initialize RFX1/RXF2/RXF3. We don't use 2685 * multi-queue yet. 2686 */ 2687 2688 /* Set Rx page size, excluding guard frame size. */ 2689 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2690 /* Tell hardware that we're ready to load DMA blocks. */ 2691 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2692 2693 /* Set Rx/Tx interrupt trigger threshold. */ 2694 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2695 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2696 /* 2697 * XXX 2698 * Set interrupt trigger timer, its purpose and relation 2699 * with interrupt moderation mechanism is not clear yet. 2700 */ 2701 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2702 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2703 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2704 2705 /* Configure interrupt moderation timer. */ 2706 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2707 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2708 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2709 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2710 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2711 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2712 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2713 reg |= MASTER_IM_RX_TIMER_ENB; 2714 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2715 reg |= MASTER_IM_TX_TIMER_ENB; 2716 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2717 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2718 2719 /* Set Maximum frame size of controller. */ 2720 if (if_getmtu(ifp) < ETHERMTU) 2721 sc->ale_max_frame_size = ETHERMTU; 2722 else 2723 sc->ale_max_frame_size = if_getmtu(ifp); 2724 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2725 ETHER_CRC_LEN; 2726 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2727 /* Configure IPG/IFG parameters. */ 2728 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2729 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2730 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2731 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2732 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2733 /* Set parameters for half-duplex media. */ 2734 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2735 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2736 HDPX_CFG_LCOL_MASK) | 2737 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2738 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2739 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2740 HDPX_CFG_ABEBT_MASK) | 2741 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2742 HDPX_CFG_JAMIPG_MASK)); 2743 2744 /* Configure Tx jumbo frame parameters. */ 2745 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2746 if (if_getmtu(ifp) < ETHERMTU) 2747 reg = sc->ale_max_frame_size; 2748 else if (if_getmtu(ifp) < 6 * 1024) 2749 reg = (sc->ale_max_frame_size * 2) / 3; 2750 else 2751 reg = sc->ale_max_frame_size / 2; 2752 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2753 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2754 TX_JUMBO_THRESH_UNIT_SHIFT); 2755 } 2756 /* Configure TxQ. */ 2757 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2758 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2759 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2760 TXQ_CFG_TPD_BURST_MASK; 2761 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2762 2763 /* Configure Rx jumbo frame & flow control parameters. */ 2764 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2765 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2766 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2767 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2768 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2769 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2770 RX_JUMBO_LKAH_MASK)); 2771 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2772 rxf_hi = (reg * 7) / 10; 2773 rxf_lo = (reg * 3)/ 10; 2774 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2775 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2776 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2777 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2778 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2779 } 2780 2781 /* Disable RSS. */ 2782 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2783 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2784 2785 /* Configure RxQ. */ 2786 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2787 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2788 2789 /* Configure DMA parameters. */ 2790 reg = 0; 2791 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2792 reg |= DMA_CFG_TXCMB_ENB; 2793 CSR_WRITE_4(sc, ALE_DMA_CFG, 2794 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2795 sc->ale_dma_rd_burst | reg | 2796 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2797 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2798 DMA_CFG_RD_DELAY_CNT_MASK) | 2799 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2800 DMA_CFG_WR_DELAY_CNT_MASK)); 2801 2802 /* 2803 * Hardware can be configured to issue SMB interrupt based 2804 * on programmed interval. Since there is a callout that is 2805 * invoked for every hz in driver we use that instead of 2806 * relying on periodic SMB interrupt. 2807 */ 2808 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2809 /* Clear MAC statistics. */ 2810 ale_stats_clear(sc); 2811 2812 /* 2813 * Configure Tx/Rx MACs. 2814 * - Auto-padding for short frames. 2815 * - Enable CRC generation. 2816 * Actual reconfiguration of MAC for resolved speed/duplex 2817 * is followed after detection of link establishment. 2818 * AR81xx always does checksum computation regardless of 2819 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2820 * cause Rx handling issue for fragmented IP datagrams due 2821 * to silicon bug. 2822 */ 2823 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2824 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2825 MAC_CFG_PREAMBLE_MASK); 2826 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2827 reg |= MAC_CFG_SPEED_10_100; 2828 else 2829 reg |= MAC_CFG_SPEED_1000; 2830 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2831 2832 /* Set up the receive filter. */ 2833 ale_rxfilter(sc); 2834 ale_rxvlan(sc); 2835 2836 /* Acknowledge all pending interrupts and clear it. */ 2837 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2838 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2839 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2840 2841 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2842 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2843 2844 sc->ale_flags &= ~ALE_FLAG_LINK; 2845 /* Switch to the current media. */ 2846 mii_mediachg(mii); 2847 2848 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2849 } 2850 2851 static void 2852 ale_stop(struct ale_softc *sc) 2853 { 2854 if_t ifp; 2855 struct ale_txdesc *txd; 2856 uint32_t reg; 2857 int i; 2858 2859 ALE_LOCK_ASSERT(sc); 2860 /* 2861 * Mark the interface down and cancel the watchdog timer. 2862 */ 2863 ifp = sc->ale_ifp; 2864 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2865 sc->ale_flags &= ~ALE_FLAG_LINK; 2866 callout_stop(&sc->ale_tick_ch); 2867 sc->ale_watchdog_timer = 0; 2868 ale_stats_update(sc); 2869 /* Disable interrupts. */ 2870 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2871 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2872 /* Disable queue processing and DMA. */ 2873 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2874 reg &= ~TXQ_CFG_ENB; 2875 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2876 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2877 reg &= ~RXQ_CFG_ENB; 2878 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2879 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2880 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2881 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2882 DELAY(1000); 2883 /* Stop Rx/Tx MACs. */ 2884 ale_stop_mac(sc); 2885 /* Disable interrupts which might be touched in taskq handler. */ 2886 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2887 2888 /* 2889 * Free TX mbufs still in the queues. 2890 */ 2891 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2892 txd = &sc->ale_cdata.ale_txdesc[i]; 2893 if (txd->tx_m != NULL) { 2894 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2895 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2896 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2897 txd->tx_dmamap); 2898 m_freem(txd->tx_m); 2899 txd->tx_m = NULL; 2900 } 2901 } 2902 } 2903 2904 static void 2905 ale_stop_mac(struct ale_softc *sc) 2906 { 2907 uint32_t reg; 2908 int i; 2909 2910 ALE_LOCK_ASSERT(sc); 2911 2912 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2913 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2914 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2915 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2916 } 2917 2918 for (i = ALE_TIMEOUT; i > 0; i--) { 2919 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2920 if (reg == 0) 2921 break; 2922 DELAY(10); 2923 } 2924 if (i == 0) 2925 device_printf(sc->ale_dev, 2926 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2927 } 2928 2929 static void 2930 ale_init_tx_ring(struct ale_softc *sc) 2931 { 2932 struct ale_txdesc *txd; 2933 int i; 2934 2935 ALE_LOCK_ASSERT(sc); 2936 2937 sc->ale_cdata.ale_tx_prod = 0; 2938 sc->ale_cdata.ale_tx_cons = 0; 2939 sc->ale_cdata.ale_tx_cnt = 0; 2940 2941 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2942 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2943 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2944 txd = &sc->ale_cdata.ale_txdesc[i]; 2945 txd->tx_m = NULL; 2946 } 2947 *sc->ale_cdata.ale_tx_cmb = 0; 2948 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2949 sc->ale_cdata.ale_tx_cmb_map, 2950 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2951 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2952 sc->ale_cdata.ale_tx_ring_map, 2953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2954 } 2955 2956 static void 2957 ale_init_rx_pages(struct ale_softc *sc) 2958 { 2959 struct ale_rx_page *rx_page; 2960 int i; 2961 2962 ALE_LOCK_ASSERT(sc); 2963 2964 sc->ale_morework = 0; 2965 sc->ale_cdata.ale_rx_seqno = 0; 2966 sc->ale_cdata.ale_rx_curp = 0; 2967 2968 for (i = 0; i < ALE_RX_PAGES; i++) { 2969 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2970 bzero(rx_page->page_addr, sc->ale_pagesize); 2971 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2972 rx_page->cons = 0; 2973 *rx_page->cmb_addr = 0; 2974 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2976 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2977 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2978 } 2979 } 2980 2981 static void 2982 ale_rxvlan(struct ale_softc *sc) 2983 { 2984 if_t ifp; 2985 uint32_t reg; 2986 2987 ALE_LOCK_ASSERT(sc); 2988 2989 ifp = sc->ale_ifp; 2990 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2991 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2992 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2993 reg |= MAC_CFG_VLAN_TAG_STRIP; 2994 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2995 } 2996 2997 static u_int 2998 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2999 { 3000 uint32_t crc, *mchash = arg; 3001 3002 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3003 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3004 3005 return (1); 3006 } 3007 3008 static void 3009 ale_rxfilter(struct ale_softc *sc) 3010 { 3011 if_t ifp; 3012 uint32_t mchash[2]; 3013 uint32_t rxcfg; 3014 3015 ALE_LOCK_ASSERT(sc); 3016 3017 ifp = sc->ale_ifp; 3018 3019 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3020 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3021 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3022 rxcfg |= MAC_CFG_BCAST; 3023 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3024 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3025 rxcfg |= MAC_CFG_PROMISC; 3026 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3027 rxcfg |= MAC_CFG_ALLMULTI; 3028 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3029 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3030 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3031 return; 3032 } 3033 3034 /* Program new filter. */ 3035 bzero(mchash, sizeof(mchash)); 3036 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3037 3038 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3039 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3040 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3041 } 3042 3043 static int 3044 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3045 { 3046 int error, value; 3047 3048 if (arg1 == NULL) 3049 return (EINVAL); 3050 value = *(int *)arg1; 3051 error = sysctl_handle_int(oidp, &value, 0, req); 3052 if (error || req->newptr == NULL) 3053 return (error); 3054 if (value < low || value > high) 3055 return (EINVAL); 3056 *(int *)arg1 = value; 3057 3058 return (0); 3059 } 3060 3061 static int 3062 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3063 { 3064 return (sysctl_int_range(oidp, arg1, arg2, req, 3065 ALE_PROC_MIN, ALE_PROC_MAX)); 3066 } 3067 3068 static int 3069 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3070 { 3071 3072 return (sysctl_int_range(oidp, arg1, arg2, req, 3073 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3074 } 3075