1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_ALCVAR_H 31 #define _IF_ALCVAR_H 32 33 #define ALC_TX_RING_CNT 256 34 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 35 #define ALC_RX_RING_CNT 256 36 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 37 #define ALC_RX_BUF_ALIGN 4 38 #define ALC_RR_RING_CNT ALC_RX_RING_CNT 39 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 40 #define ALC_CMB_ALIGN 8 41 #define ALC_SMB_ALIGN 8 42 43 #define ALC_TSO_MAXSEGSIZE 4096 44 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 45 #define ALC_MAXTXSEGS 35 46 47 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 48 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 49 50 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 51 52 /* Water mark to kick reclaiming Tx buffers. */ 53 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 54 55 /* 56 * AR816x controllers support up to 16 messages but this driver 57 * uses single message. 58 */ 59 #define ALC_MSI_MESSAGES 1 60 #define ALC_MSIX_MESSAGES 1 61 62 #define ALC_TX_RING_SZ \ 63 (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 64 #define ALC_RX_RING_SZ \ 65 (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 66 #define ALC_RR_RING_SZ \ 67 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 68 #define ALC_CMB_SZ (sizeof(struct cmb)) 69 #define ALC_SMB_SZ (sizeof(struct smb)) 70 71 #define ALC_PROC_MIN 16 72 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 73 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 74 75 /* 76 * The number of bits reserved for MSS in AR813x/AR815x controllers 77 * are 13 bits. This limits the maximum interface MTU size in TSO 78 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 79 * stack should not generate TCP segments with MSS greater than the 80 * limit. Also Atheros says that maximum MTU for TSO is 6KB. 81 */ 82 #define ALC_TSO_MTU (6 * 1024) 83 84 struct alc_rxdesc { 85 struct mbuf *rx_m; 86 bus_dmamap_t rx_dmamap; 87 struct rx_desc *rx_desc; 88 }; 89 90 struct alc_txdesc { 91 struct mbuf *tx_m; 92 bus_dmamap_t tx_dmamap; 93 }; 94 95 struct alc_ring_data { 96 struct tx_desc *alc_tx_ring; 97 bus_addr_t alc_tx_ring_paddr; 98 struct rx_desc *alc_rx_ring; 99 bus_addr_t alc_rx_ring_paddr; 100 struct rx_rdesc *alc_rr_ring; 101 bus_addr_t alc_rr_ring_paddr; 102 struct cmb *alc_cmb; 103 bus_addr_t alc_cmb_paddr; 104 struct smb *alc_smb; 105 bus_addr_t alc_smb_paddr; 106 }; 107 108 struct alc_chain_data { 109 bus_dma_tag_t alc_parent_tag; 110 bus_dma_tag_t alc_buffer_tag; 111 bus_dma_tag_t alc_tx_tag; 112 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 113 bus_dma_tag_t alc_rx_tag; 114 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 115 bus_dma_tag_t alc_tx_ring_tag; 116 bus_dmamap_t alc_tx_ring_map; 117 bus_dma_tag_t alc_rx_ring_tag; 118 bus_dmamap_t alc_rx_ring_map; 119 bus_dma_tag_t alc_rr_ring_tag; 120 bus_dmamap_t alc_rr_ring_map; 121 bus_dmamap_t alc_rx_sparemap; 122 bus_dma_tag_t alc_cmb_tag; 123 bus_dmamap_t alc_cmb_map; 124 bus_dma_tag_t alc_smb_tag; 125 bus_dmamap_t alc_smb_map; 126 127 int alc_tx_prod; 128 int alc_tx_cons; 129 int alc_tx_cnt; 130 int alc_rx_cons; 131 int alc_rr_cons; 132 int alc_rxlen; 133 134 struct mbuf *alc_rxhead; 135 struct mbuf *alc_rxtail; 136 struct mbuf *alc_rxprev_tail; 137 }; 138 139 struct alc_hw_stats { 140 /* Rx stats. */ 141 uint32_t rx_frames; 142 uint32_t rx_bcast_frames; 143 uint32_t rx_mcast_frames; 144 uint32_t rx_pause_frames; 145 uint32_t rx_control_frames; 146 uint32_t rx_crcerrs; 147 uint32_t rx_lenerrs; 148 uint64_t rx_bytes; 149 uint32_t rx_runts; 150 uint32_t rx_fragments; 151 uint32_t rx_pkts_64; 152 uint32_t rx_pkts_65_127; 153 uint32_t rx_pkts_128_255; 154 uint32_t rx_pkts_256_511; 155 uint32_t rx_pkts_512_1023; 156 uint32_t rx_pkts_1024_1518; 157 uint32_t rx_pkts_1519_max; 158 uint32_t rx_pkts_truncated; 159 uint32_t rx_fifo_oflows; 160 uint32_t rx_rrs_errs; 161 uint32_t rx_alignerrs; 162 uint64_t rx_bcast_bytes; 163 uint64_t rx_mcast_bytes; 164 uint32_t rx_pkts_filtered; 165 /* Tx stats. */ 166 uint32_t tx_frames; 167 uint32_t tx_bcast_frames; 168 uint32_t tx_mcast_frames; 169 uint32_t tx_pause_frames; 170 uint32_t tx_excess_defer; 171 uint32_t tx_control_frames; 172 uint32_t tx_deferred; 173 uint64_t tx_bytes; 174 uint32_t tx_pkts_64; 175 uint32_t tx_pkts_65_127; 176 uint32_t tx_pkts_128_255; 177 uint32_t tx_pkts_256_511; 178 uint32_t tx_pkts_512_1023; 179 uint32_t tx_pkts_1024_1518; 180 uint32_t tx_pkts_1519_max; 181 uint32_t tx_single_colls; 182 uint32_t tx_multi_colls; 183 uint32_t tx_late_colls; 184 uint32_t tx_excess_colls; 185 uint32_t tx_abort; 186 uint32_t tx_underrun; 187 uint32_t tx_desc_underrun; 188 uint32_t tx_lenerrs; 189 uint32_t tx_pkts_truncated; 190 uint64_t tx_bcast_bytes; 191 uint64_t tx_mcast_bytes; 192 }; 193 194 struct alc_ident { 195 uint16_t vendorid; 196 uint16_t deviceid; 197 uint32_t max_framelen; 198 const char *name; 199 }; 200 201 /* 202 * Software state per device. 203 */ 204 struct alc_softc { 205 struct ifnet *alc_ifp; 206 device_t alc_dev; 207 device_t alc_miibus; 208 struct resource *alc_res[1]; 209 struct resource_spec *alc_res_spec; 210 struct resource *alc_irq[ALC_MSI_MESSAGES]; 211 struct resource_spec *alc_irq_spec; 212 void *alc_intrhand[ALC_MSI_MESSAGES]; 213 struct alc_ident *alc_ident; 214 int alc_rev; 215 int alc_chip_rev; 216 int alc_phyaddr; 217 uint8_t alc_eaddr[ETHER_ADDR_LEN]; 218 uint32_t alc_dma_rd_burst; 219 uint32_t alc_dma_wr_burst; 220 uint32_t alc_rcb; 221 int alc_expcap; 222 int alc_pmcap; 223 int alc_flags; 224 #define ALC_FLAG_PCIE 0x0001 225 #define ALC_FLAG_PCIX 0x0002 226 #define ALC_FLAG_MSI 0x0004 227 #define ALC_FLAG_MSIX 0x0008 228 #define ALC_FLAG_PM 0x0010 229 #define ALC_FLAG_FASTETHER 0x0020 230 #define ALC_FLAG_JUMBO 0x0040 231 #define ALC_FLAG_CMB_BUG 0x0100 232 #define ALC_FLAG_SMB_BUG 0x0200 233 #define ALC_FLAG_L0S 0x0400 234 #define ALC_FLAG_L1S 0x0800 235 #define ALC_FLAG_APS 0x1000 236 #define ALC_FLAG_AR816X_FAMILY 0x2000 237 #define ALC_FLAG_LINK_WAR 0x4000 238 #define ALC_FLAG_E2X00 0x8000 239 #define ALC_FLAG_LINK 0x10000 240 241 struct callout alc_tick_ch; 242 struct alc_hw_stats alc_stats; 243 struct alc_chain_data alc_cdata; 244 struct alc_ring_data alc_rdata; 245 int alc_if_flags; 246 int alc_watchdog_timer; 247 int alc_process_limit; 248 volatile int alc_morework; 249 int alc_int_rx_mod; 250 int alc_int_tx_mod; 251 int alc_buf_size; 252 253 struct task alc_int_task; 254 struct taskqueue *alc_tq; 255 struct mtx alc_mtx; 256 }; 257 258 /* Register access macros. */ 259 #define CSR_WRITE_4(_sc, reg, val) \ 260 bus_write_4((_sc)->alc_res[0], (reg), (val)) 261 #define CSR_WRITE_2(_sc, reg, val) \ 262 bus_write_2((_sc)->alc_res[0], (reg), (val)) 263 #define CSR_WRITE_1(_sc, reg, val) \ 264 bus_write_1((_sc)->alc_res[0], (reg), (val)) 265 #define CSR_READ_2(_sc, reg) \ 266 bus_read_2((_sc)->alc_res[0], (reg)) 267 #define CSR_READ_4(_sc, reg) \ 268 bus_read_4((_sc)->alc_res[0], (reg)) 269 270 #define ALC_RXCHAIN_RESET(_sc) \ 271 do { \ 272 (_sc)->alc_cdata.alc_rxhead = NULL; \ 273 (_sc)->alc_cdata.alc_rxtail = NULL; \ 274 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 275 (_sc)->alc_cdata.alc_rxlen = 0; \ 276 } while (0) 277 278 #define ALC_LOCK(_sc) mtx_lock(&(_sc)->alc_mtx) 279 #define ALC_UNLOCK(_sc) mtx_unlock(&(_sc)->alc_mtx) 280 #define ALC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->alc_mtx, MA_OWNED) 281 282 #define ALC_TX_TIMEOUT 5 283 #define ALC_RESET_TIMEOUT 100 284 #define ALC_TIMEOUT 1000 285 #define ALC_PHY_TIMEOUT 1000 286 287 #endif /* _IF_ALCVAR_H */ 288