1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _IF_ALCREG_H 33 #define _IF_ALCREG_H 34 35 /* 36 * Atheros Communucations, Inc. PCI vendor ID 37 */ 38 #define VENDORID_ATHEROS 0x1969 39 40 /* 41 * Atheros AR813x/AR815x device ID 42 */ 43 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 44 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 45 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 46 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 47 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 48 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 49 #define DEVICEID_ATHEROS_AR8161 0x1091 50 #define DEVICEID_ATHEROS_AR8162 0x1090 51 #define DEVICEID_ATHEROS_AR8171 0x10A1 52 #define DEVICEID_ATHEROS_AR8172 0x10A0 53 #define DEVICEID_ATHEROS_E2200 0xE091 54 #define DEVICEID_ATHEROS_E2400 0xE0A1 55 #define DEVICEID_ATHEROS_E2500 0xE0B1 56 57 #define ATHEROS_AR8152_B_V10 0xC0 58 #define ATHEROS_AR8152_B_V11 0xC1 59 60 /* 61 * Atheros AR816x/AR817x revisions 62 */ 63 #define AR816X_REV_A0 0 64 #define AR816X_REV_A1 1 65 #define AR816X_REV_B0 2 66 #define AR816X_REV_C0 3 67 68 #define AR816X_REV_SHIFT 3 69 #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) 70 71 /* 0x0000 - 0x02FF : PCIe configuration space */ 72 73 #define ALC_PEX_UNC_ERR_SEV 0x10C 74 #define PEX_UNC_ERR_SEV_TRN 0x00000001 75 #define PEX_UNC_ERR_SEV_DLP 0x00000010 76 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 77 #define PEX_UNC_ERR_SEV_FCP 0x00002000 78 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 79 #define PEX_UNC_ERR_SEV_CA 0x00008000 80 #define PEX_UNC_ERR_SEV_UC 0x00010000 81 #define PEX_UNC_ERR_SEV_ROV 0x00020000 82 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 83 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 84 #define PEX_UNC_ERR_SEV_UR 0x00100000 85 86 #define ALC_EEPROM_LD 0x204 /* AR816x */ 87 #define EEPROM_LD_START 0x00000001 88 #define EEPROM_LD_IDLE 0x00000010 89 #define EEPROM_LD_DONE 0x00000000 90 #define EEPROM_LD_PROGRESS 0x00000020 91 #define EEPROM_LD_EXIST 0x00000100 92 #define EEPROM_LD_EEPROM_EXIST 0x00000200 93 #define EEPROM_LD_FLASH_EXIST 0x00000400 94 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 95 #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 96 97 #define ALC_TWSI_CFG 0x218 98 #define TWSI_CFG_SW_LD_START 0x00000800 99 #define TWSI_CFG_HW_LD_START 0x00001000 100 #define TWSI_CFG_LD_EXIST 0x00400000 101 102 #define ALC_SLD 0x218 /* AR816x */ 103 #define SLD_START 0x00000800 104 #define SLD_PROGRESS 0x00001000 105 #define SLD_IDLE 0x00002000 106 #define SLD_SLVADDR_MASK 0x007F0000 107 #define SLD_EXIST 0x00800000 108 #define SLD_FREQ_MASK 0x03000000 109 #define SLD_FREQ_100K 0x00000000 110 #define SLD_FREQ_200K 0x01000000 111 #define SLD_FREQ_300K 0x02000000 112 #define SLD_FREQ_400K 0x03000000 113 114 #define ALC_PCIE_PHYMISC 0x1000 115 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 116 117 #define ALC_PCIE_PHYMISC2 0x1004 118 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 119 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 120 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 121 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 122 123 #define ALC_PDLL_TRNS1 0x1104 124 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 125 126 #define ALC_TWSI_DEBUG 0x1108 127 #define TWSI_DEBUG_DEV_EXIST 0x20000000 128 129 #define ALC_EEPROM_CFG 0x12C0 130 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 131 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 132 #define EEPROM_CFG_ACK 0x40000000 133 #define EEPROM_CFG_RW 0x80000000 134 #define EEPROM_CFG_DATA_HI_SHIFT 0 135 #define EEPROM_CFG_ADDR_SHIFT 16 136 137 #define ALC_EEPROM_DATA_LO 0x12C4 138 139 #define ALC_OPT_CFG 0x12F0 140 #define OPT_CFG_CLK_ENB 0x00000002 141 142 #define ALC_PM_CFG 0x12F8 143 #define PM_CFG_SERDES_ENB 0x00000001 144 #define PM_CFG_RBER_ENB 0x00000002 145 #define PM_CFG_CLK_REQ_ENB 0x00000004 146 #define PM_CFG_ASPM_L1_ENB 0x00000008 147 #define PM_CFG_SERDES_L1_ENB 0x00000010 148 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 149 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 150 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 151 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 152 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800 153 #define PM_CFG_ASPM_L0S_ENB 0x00001000 154 #define PM_CFG_CLK_SWH_L1 0x00002000 155 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 156 #define PM_CFG_PCIE_RECV 0x00008000 157 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 158 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 159 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000 160 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 161 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 162 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 163 #define PM_CFG_SA_DLY_ENB 0x20000000 164 #define PM_CFG_MAC_ASPM_CHK 0x40000000 165 #define PM_CFG_HOTRST 0x80000000 166 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 167 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 168 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 169 #define PM_CFG_LCKDET_TIMER_SHIFT 24 170 171 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 172 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 173 #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 174 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 175 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 176 #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 177 178 #define ALC_LTSSM_ID_CFG 0x12FC 179 #define LTSSM_ID_WRO_ENB 0x00001000 180 181 #define ALC_MASTER_CFG 0x1400 182 #define MASTER_RESET 0x00000001 183 #define MASTER_TEST_MODE_MASK 0x0000000C 184 #define MASTER_BERT_START 0x00000010 185 #define MASTER_WAKEN_25M 0x00000020 186 #define MASTER_OOB_DIS_OFF 0x00000040 187 #define MASTER_SA_TIMER_ENB 0x00000080 188 #define MASTER_MTIMER_ENB 0x00000100 189 #define MASTER_MANUAL_INTR_ENB 0x00000200 190 #define MASTER_IM_TX_TIMER_ENB 0x00000400 191 #define MASTER_IM_RX_TIMER_ENB 0x00000800 192 #define MASTER_CLK_SEL_DIS 0x00001000 193 #define MASTER_CLK_SWH_MODE 0x00002000 194 #define MASTER_INTR_RD_CLR 0x00004000 195 #define MASTER_CHIP_REV_MASK 0x00FF0000 196 #define MASTER_CHIP_ID_MASK 0x7F000000 197 #define MASTER_OTP_SEL 0x80000000 198 #define MASTER_TEST_MODE_SHIFT 2 199 #define MASTER_CHIP_REV_SHIFT 16 200 #define MASTER_CHIP_ID_SHIFT 24 201 202 /* Number of ticks per usec for AR813x/AR815x. */ 203 #define ALC_TICK_USECS 2 204 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 205 206 #define ALC_MANUAL_TIMER 0x1404 207 208 #define ALC_IM_TIMER 0x1408 209 #define IM_TIMER_TX_MASK 0x0000FFFF 210 #define IM_TIMER_RX_MASK 0xFFFF0000 211 #define IM_TIMER_TX_SHIFT 0 212 #define IM_TIMER_RX_SHIFT 16 213 #define ALC_IM_TIMER_MIN 0 214 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 215 /* 216 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 217 * interrupts in a second. 218 */ 219 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 220 /* 221 * alc(4) does not rely on Tx completion interrupts, so set it 222 * somewhat large value to reduce Tx completion interrupts. 223 */ 224 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 225 226 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ 227 #define GPHY_CFG_EXT_RESET 0x0001 228 #define GPHY_CFG_RTL_MODE 0x0002 229 #define GPHY_CFG_LED_MODE 0x0004 230 #define GPHY_CFG_ANEG_NOW 0x0008 231 #define GPHY_CFG_RECV_ANEG 0x0010 232 #define GPHY_CFG_GATE_25M_ENB 0x0020 233 #define GPHY_CFG_LPW_EXIT 0x0040 234 #define GPHY_CFG_PHY_IDDQ 0x0080 235 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 236 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 237 #define GPHY_CFG_HIB_EN 0x0400 238 #define GPHY_CFG_HIB_PULSE 0x0800 239 #define GPHY_CFG_SEL_ANA_RESET 0x1000 240 #define GPHY_CFG_PHY_PLL_ON 0x2000 241 #define GPHY_CFG_PWDOWN_HW 0x4000 242 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 243 #define GPHY_CFG_100AB_ENB 0x00020000 244 245 #define ALC_IDLE_STATUS 0x1410 246 #define IDLE_STATUS_RXMAC 0x00000001 247 #define IDLE_STATUS_TXMAC 0x00000002 248 #define IDLE_STATUS_RXQ 0x00000004 249 #define IDLE_STATUS_TXQ 0x00000008 250 #define IDLE_STATUS_DMARD 0x00000010 251 #define IDLE_STATUS_DMAWR 0x00000020 252 #define IDLE_STATUS_SMB 0x00000040 253 #define IDLE_STATUS_CMB 0x00000080 254 255 #define ALC_MDIO 0x1414 256 #define MDIO_DATA_MASK 0x0000FFFF 257 #define MDIO_REG_ADDR_MASK 0x001F0000 258 #define MDIO_OP_READ 0x00200000 259 #define MDIO_OP_WRITE 0x00000000 260 #define MDIO_SUP_PREAMBLE 0x00400000 261 #define MDIO_OP_EXECUTE 0x00800000 262 #define MDIO_CLK_25_4 0x00000000 263 #define MDIO_CLK_25_6 0x02000000 264 #define MDIO_CLK_25_8 0x03000000 265 #define MDIO_CLK_25_10 0x04000000 266 #define MDIO_CLK_25_14 0x05000000 267 #define MDIO_CLK_25_20 0x06000000 268 #define MDIO_CLK_25_128 0x07000000 269 #define MDIO_OP_BUSY 0x08000000 270 #define MDIO_AP_ENB 0x10000000 271 #define MDIO_MODE_EXT 0x40000000 272 #define MDIO_DATA_SHIFT 0 273 #define MDIO_REG_ADDR_SHIFT 16 274 275 #define MDIO_REG_ADDR(x) \ 276 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 277 /* Default PHY address. */ 278 #define ALC_PHY_ADDR 0 279 280 #define ALC_PHY_STATUS 0x1418 281 #define PHY_STATUS_RECV_ENB 0x00000001 282 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 283 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 284 #define PHY_STATUS_LPW_STATE 0x80000000 285 #define PHY_STATIS_OE_PWSP_SHIFT 16 286 287 /* Packet memory BIST. */ 288 #define ALC_BIST0 0x141C 289 #define BIST0_ENB 0x00000001 290 #define BIST0_SRAM_FAIL 0x00000002 291 #define BIST0_FUSE_FLAG 0x00000004 292 293 /* PCIe retry buffer BIST. */ 294 #define ALC_BIST1 0x1420 295 #define BIST1_ENB 0x00000001 296 #define BIST1_SRAM_FAIL 0x00000002 297 #define BIST1_FUSE_FLAG 0x00000004 298 299 #define ALC_SERDES_LOCK 0x1424 300 #define SERDES_LOCK_DET 0x00000001 301 #define SERDES_LOCK_DET_ENB 0x00000002 302 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 303 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 304 305 #define ALC_LPI_CTL 0x1440 306 #define LPI_CTL_ENB 0x00000001 307 308 #define ALC_EXT_MDIO 0x1448 309 #define EXT_MDIO_REG_MASK 0x0000FFFF 310 #define EXT_MDIO_DEVADDR_MASK 0x001F0000 311 #define EXT_MDIO_REG_SHIFT 0 312 #define EXT_MDIO_DEVADDR_SHIFT 16 313 314 #define EXT_MDIO_REG(x) \ 315 (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) 316 #define EXT_MDIO_DEVADDR(x) \ 317 (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) 318 319 #define ALC_IDLE_DECISN_TIMER 0x1474 320 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 321 322 #define ALC_MAC_CFG 0x1480 323 #define MAC_CFG_TX_ENB 0x00000001 324 #define MAC_CFG_RX_ENB 0x00000002 325 #define MAC_CFG_TX_FC 0x00000004 326 #define MAC_CFG_RX_FC 0x00000008 327 #define MAC_CFG_LOOP 0x00000010 328 #define MAC_CFG_FULL_DUPLEX 0x00000020 329 #define MAC_CFG_TX_CRC_ENB 0x00000040 330 #define MAC_CFG_TX_AUTO_PAD 0x00000080 331 #define MAC_CFG_TX_LENCHK 0x00000100 332 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 333 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 334 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 335 #define MAC_CFG_PROMISC 0x00008000 336 #define MAC_CFG_TX_PAUSE 0x00010000 337 #define MAC_CFG_SCNT 0x00020000 338 #define MAC_CFG_SYNC_RST_TX 0x00040000 339 #define MAC_CFG_SIM_RST_TX 0x00080000 340 #define MAC_CFG_SPEED_MASK 0x00300000 341 #define MAC_CFG_SPEED_10_100 0x00100000 342 #define MAC_CFG_SPEED_1000 0x00200000 343 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 344 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 345 #define MAC_CFG_RXCSUM_ENB 0x01000000 346 #define MAC_CFG_ALLMULTI 0x02000000 347 #define MAC_CFG_BCAST 0x04000000 348 #define MAC_CFG_DBG 0x08000000 349 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 350 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 351 #define MAC_CFG_SPEED_MODE_SW 0x40000000 352 #define MAC_CFG_FAST_PAUSE 0x80000000 353 #define MAC_CFG_PREAMBLE_SHIFT 10 354 #define MAC_CFG_PREAMBLE_DEFAULT 7 355 356 #define ALC_IPG_IFG_CFG 0x1484 357 #define IPG_IFG_IPGT_MASK 0x0000007F 358 #define IPG_IFG_MIFG_MASK 0x0000FF00 359 #define IPG_IFG_IPG1_MASK 0x007F0000 360 #define IPG_IFG_IPG2_MASK 0x7F000000 361 #define IPG_IFG_IPGT_SHIFT 0 362 #define IPG_IFG_IPGT_DEFAULT 0x60 363 #define IPG_IFG_MIFG_SHIFT 8 364 #define IPG_IFG_MIFG_DEFAULT 0x50 365 #define IPG_IFG_IPG1_SHIFT 16 366 #define IPG_IFG_IPG1_DEFAULT 0x40 367 #define IPG_IFG_IPG2_SHIFT 24 368 #define IPG_IFG_IPG2_DEFAULT 0x60 369 370 /* Station address. */ 371 #define ALC_PAR0 0x1488 372 #define ALC_PAR1 0x148C 373 374 /* 64bit multicast hash register. */ 375 #define ALC_MAR0 0x1490 376 #define ALC_MAR1 0x1494 377 378 /* half-duplex parameter configuration. */ 379 #define ALC_HDPX_CFG 0x1498 380 #define HDPX_CFG_LCOL_MASK 0x000003FF 381 #define HDPX_CFG_RETRY_MASK 0x0000F000 382 #define HDPX_CFG_EXC_DEF_EN 0x00010000 383 #define HDPX_CFG_NO_BACK_C 0x00020000 384 #define HDPX_CFG_NO_BACK_P 0x00040000 385 #define HDPX_CFG_ABEBE 0x00080000 386 #define HDPX_CFG_ABEBT_MASK 0x00F00000 387 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 388 #define HDPX_CFG_LCOL_SHIFT 0 389 #define HDPX_CFG_LCOL_DEFAULT 0x37 390 #define HDPX_CFG_RETRY_SHIFT 12 391 #define HDPX_CFG_RETRY_DEFAULT 0x0F 392 #define HDPX_CFG_ABEBT_SHIFT 20 393 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 394 #define HDPX_CFG_JAMIPG_SHIFT 24 395 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 396 397 #define ALC_FRAME_SIZE 0x149C 398 399 #define ALC_WOL_CFG 0x14A0 400 #define WOL_CFG_PATTERN 0x00000001 401 #define WOL_CFG_PATTERN_ENB 0x00000002 402 #define WOL_CFG_MAGIC 0x00000004 403 #define WOL_CFG_MAGIC_ENB 0x00000008 404 #define WOL_CFG_LINK_CHG 0x00000010 405 #define WOL_CFG_LINK_CHG_ENB 0x00000020 406 #define WOL_CFG_PATTERN_DET 0x00000100 407 #define WOL_CFG_MAGIC_DET 0x00000200 408 #define WOL_CFG_LINK_CHG_DET 0x00000400 409 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 410 #define WOL_CFG_PATTERN0 0x00010000 411 #define WOL_CFG_PATTERN1 0x00020000 412 #define WOL_CFG_PATTERN2 0x00040000 413 #define WOL_CFG_PATTERN3 0x00080000 414 #define WOL_CFG_PATTERN4 0x00100000 415 #define WOL_CFG_PATTERN5 0x00200000 416 #define WOL_CFG_PATTERN6 0x00400000 417 418 /* WOL pattern length. */ 419 #define ALC_PATTERN_CFG0 0x14A4 420 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 421 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 422 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 423 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 424 425 #define ALC_PATTERN_CFG1 0x14A8 426 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 427 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 428 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 429 430 /* RSS */ 431 #define ALC_RSS_KEY0 0x14B0 432 433 #define ALC_RSS_KEY1 0x14B4 434 435 #define ALC_RSS_KEY2 0x14B8 436 437 #define ALC_RSS_KEY3 0x14BC 438 439 #define ALC_RSS_KEY4 0x14C0 440 441 #define ALC_RSS_KEY5 0x14C4 442 443 #define ALC_RSS_KEY6 0x14C8 444 445 #define ALC_RSS_KEY7 0x14CC 446 447 #define ALC_RSS_KEY8 0x14D0 448 449 #define ALC_RSS_KEY9 0x14D4 450 451 #define ALC_RSS_IDT_TABLE0 0x14E0 452 453 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ 454 455 #define ALC_RSS_IDT_TABLE1 0x14E4 456 457 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ 458 459 #define ALC_RSS_IDT_TABLE2 0x14E8 460 461 #define ALC_RSS_IDT_TABLE3 0x14EC 462 463 #define ALC_RSS_IDT_TABLE4 0x14F0 464 465 #define ALC_RSS_IDT_TABLE5 0x14F4 466 467 #define ALC_RSS_IDT_TABLE6 0x14F8 468 469 #define ALC_RSS_IDT_TABLE7 0x14FC 470 471 #define ALC_SRAM_RD0_ADDR 0x1500 472 473 #define ALC_SRAM_RD1_ADDR 0x1504 474 475 #define ALC_SRAM_RD2_ADDR 0x1508 476 477 #define ALC_SRAM_RD3_ADDR 0x150C 478 479 #define RD_HEAD_ADDR_MASK 0x000003FF 480 #define RD_TAIL_ADDR_MASK 0x03FF0000 481 #define RD_HEAD_ADDR_SHIFT 0 482 #define RD_TAIL_ADDR_SHIFT 16 483 484 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 485 #define RD_NIC_LEN_MASK 0x000003FF 486 487 #define ALC_RD_NIC_LEN1 0x1514 488 489 #define ALC_SRAM_TD_ADDR 0x1518 490 #define TD_HEAD_ADDR_MASK 0x000003FF 491 #define TD_TAIL_ADDR_MASK 0x03FF0000 492 #define TD_HEAD_ADDR_SHIFT 0 493 #define TD_TAIL_ADDR_SHIFT 16 494 495 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 496 #define SRAM_TD_LEN_MASK 0x000003FF 497 498 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 499 500 #define ALC_SRAM_RX_FIFO_LEN 0x1524 501 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF 502 #define SRAM_RX_FIFO_LEN_SHIFT 0 503 504 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 505 506 #define ALC_SRAM_TX_FIFO_LEN 0x152C 507 508 #define ALC_SRAM_TCPH_ADDR 0x1530 509 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 510 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 511 #define SRAM_TCPH_ADDR_SHIFT 0 512 #define SRAM_PKTH_ADDR_SHIFT 16 513 514 #define ALC_DMA_BLOCK 0x1534 515 #define DMA_BLOCK_LOAD 0x00000001 516 517 #define ALC_RX_BASE_ADDR_HI 0x1540 518 519 #define ALC_TX_BASE_ADDR_HI 0x1544 520 521 #define ALC_SMB_BASE_ADDR_HI 0x1548 522 523 #define ALC_SMB_BASE_ADDR_LO 0x154C 524 525 #define ALC_RD0_HEAD_ADDR_LO 0x1550 526 527 #define ALC_RD1_HEAD_ADDR_LO 0x1554 528 529 #define ALC_RD2_HEAD_ADDR_LO 0x1558 530 531 #define ALC_RD3_HEAD_ADDR_LO 0x155C 532 533 #define ALC_RD_RING_CNT 0x1560 534 #define RD_RING_CNT_MASK 0x00000FFF 535 #define RD_RING_CNT_SHIFT 0 536 537 #define ALC_RX_BUF_SIZE 0x1564 538 #define RX_BUF_SIZE_MASK 0x0000FFFF 539 /* 540 * If larger buffer size than 1536 is specified the controller 541 * will be locked up. This is hardware limitation. 542 */ 543 #define RX_BUF_SIZE_MAX 1536 544 545 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 546 547 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 548 549 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 550 551 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 552 553 #define ALC_RRD_RING_CNT 0x1578 554 #define RRD_RING_CNT_MASK 0x00000FFF 555 #define RRD_RING_CNT_SHIFT 0 556 557 #define ALC_TDH_HEAD_ADDR_LO 0x157C 558 559 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ 560 561 #define ALC_TDL_HEAD_ADDR_LO 0x1580 562 563 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ 564 565 #define ALC_TD_RING_CNT 0x1584 566 #define TD_RING_CNT_MASK 0x0000FFFF 567 #define TD_RING_CNT_SHIFT 0 568 569 #define ALC_CMB_BASE_ADDR_LO 0x1588 570 571 #define ALC_TXQ_CFG 0x1590 572 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 573 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 574 #define TXQ_CFG_ENB 0x00000020 575 #define TXQ_CFG_ENHANCED_MODE 0x00000040 576 #define TXQ_CFG_8023_ENB 0x00000080 577 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 578 #define TXQ_CFG_TD_BURST_SHIFT 0 579 #define TXQ_CFG_TD_BURST_DEFAULT 5 580 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 581 582 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 583 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 584 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 585 #define TSO_OFFLOAD_THRESH_SHIFT 0 586 #define TSO_OFFLOAD_THRESH_UNIT 8 587 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 588 589 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 590 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 591 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 592 #define TXF_WATER_MARK_BURST_ENB 0x80000000 593 #define TXF_WATER_MARK_LO_SHIFT 0 594 #define TXF_WATER_MARK_HI_SHIFT 16 595 596 #define ALC_THROUGHPUT_MON 0x159C 597 #define THROUGHPUT_MON_RATE_MASK 0x00000003 598 #define THROUGHPUT_MON_ENB 0x00000080 599 #define THROUGHPUT_MON_RATE_SHIFT 0 600 601 #define ALC_RXQ_CFG 0x15A0 602 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 603 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 604 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 605 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 606 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 607 #define RXQ_CFG_QUEUE1_ENB 0x00000010 608 #define RXQ_CFG_QUEUE2_ENB 0x00000020 609 #define RXQ_CFG_QUEUE3_ENB 0x00000040 610 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 611 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 612 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 613 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 614 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 615 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 616 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 617 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 618 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 619 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 620 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 621 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 622 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 623 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 624 #define RXQ_CFG_QUEUE0_ENB 0x80000000 625 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 626 #define RXQ_CFG_RD_BURST_DEFAULT 8 627 #define RXQ_CFG_RD_BURST_SHIFT 20 628 #define RXQ_CFG_ENB \ 629 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 630 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 631 632 /* AR816x specific bits */ 633 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 634 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 635 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 636 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 637 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C 638 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 639 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 640 #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 641 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 642 643 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 644 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 645 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 646 #define RX_RD_FREE_THRESH_HI_SHIFT 0 647 #define RX_RD_FREE_THRESH_LO_SHIFT 6 648 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 649 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 650 651 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 652 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 653 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 654 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 655 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 656 /* 657 * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 658 * rx-packet(1522) + delay-of-link(64) 659 * = 3212. 660 */ 661 #define RX_FIFO_PAUSE_816X_RSVD 3212 662 663 #define ALC_RD_DMA_CFG 0x15AC 664 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 665 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 666 #define RD_DMA_CFG_THRESH_SHIFT 0 667 #define RD_DMA_CFG_TIMER_SHIFT 16 668 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 669 #define RD_DMA_CFG_TIMER_DEFAULT 0 670 #define RD_DMA_CFG_TICK_USECS 8 671 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 672 673 #define ALC_RSS_HASH_VALUE 0x15B0 674 675 #define ALC_RSS_HASH_FLAG 0x15B4 676 677 #define ALC_RSS_CPU 0x15B8 678 679 #define ALC_DMA_CFG 0x15C0 680 #define DMA_CFG_IN_ORDER 0x00000001 681 #define DMA_CFG_ENH_ORDER 0x00000002 682 #define DMA_CFG_OUT_ORDER 0x00000004 683 #define DMA_CFG_RCB_64 0x00000000 684 #define DMA_CFG_RCB_128 0x00000008 685 #define DMA_CFG_PEND_AUTO_RST 0x00000008 686 #define DMA_CFG_RD_BURST_128 0x00000000 687 #define DMA_CFG_RD_BURST_256 0x00000010 688 #define DMA_CFG_RD_BURST_512 0x00000020 689 #define DMA_CFG_RD_BURST_1024 0x00000030 690 #define DMA_CFG_RD_BURST_2048 0x00000040 691 #define DMA_CFG_RD_BURST_4096 0x00000050 692 #define DMA_CFG_WR_BURST_128 0x00000000 693 #define DMA_CFG_WR_BURST_256 0x00000080 694 #define DMA_CFG_WR_BURST_512 0x00000100 695 #define DMA_CFG_WR_BURST_1024 0x00000180 696 #define DMA_CFG_WR_BURST_2048 0x00000200 697 #define DMA_CFG_WR_BURST_4096 0x00000280 698 #define DMA_CFG_RD_REQ_PRI 0x00000400 699 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 700 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 701 #define DMA_CFG_CMB_ENB 0x00100000 702 #define DMA_CFG_SMB_ENB 0x00200000 703 #define DMA_CFG_CMB_NOW 0x00400000 704 #define DMA_CFG_SMB_DIS 0x01000000 705 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 706 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000 707 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000 708 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000 709 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 710 #define DMA_CFG_WSRAM_RDCTL 0x10000000 711 #define DMA_CFG_RD_PEND_CLR 0x20000000 712 #define DMA_CFG_WR_PEND_CLR 0x40000000 713 #define DMA_CFG_SMB_NOW 0x80000000 714 #define DMA_CFG_RD_BURST_MASK 0x07 715 #define DMA_CFG_RD_BURST_SHIFT 4 716 #define DMA_CFG_WR_BURST_MASK 0x07 717 #define DMA_CFG_WR_BURST_SHIFT 7 718 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 719 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 720 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 721 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 722 723 #define ALC_SMB_STAT_TIMER 0x15C4 724 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 725 #define SMB_STAT_TIMER_SHIFT 0 726 727 #define ALC_CMB_TD_THRESH 0x15C8 728 #define CMB_TD_THRESH_MASK 0x0000FFFF 729 #define CMB_TD_THRESH_SHIFT 0 730 731 #define ALC_CMB_TX_TIMER 0x15CC 732 #define CMB_TX_TIMER_MASK 0x0000FFFF 733 #define CMB_TX_TIMER_SHIFT 0 734 735 #define ALC_MSI_MAP_TBL1 0x15D0 736 737 #define ALC_MSI_ID_MAP 0x15D4 738 739 #define ALC_MSI_MAP_TBL2 0x15D8 740 741 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 742 743 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 744 745 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 746 747 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 748 749 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 750 #define MBOX_RD_PROD_SHIFT 0 751 752 #define ALC_MBOX_TD_PROD_IDX 0x15F0 753 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 754 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 755 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 756 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 757 758 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ 759 760 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ 761 762 #define ALC_MBOX_TD_CONS_IDX 0x15F4 763 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 764 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 765 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 766 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 767 768 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ 769 770 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ 771 772 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 773 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 774 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 775 #define MBOX_RD0_CONS_IDX_SHIFT 0 776 #define MBOX_RD1_CONS_IDX_SHIFT 16 777 778 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 779 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 780 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 781 #define MBOX_RD2_CONS_IDX_SHIFT 0 782 #define MBOX_RD3_CONS_IDX_SHIFT 16 783 784 #define ALC_INTR_STATUS 0x1600 785 #define INTR_SMB 0x00000001 786 #define INTR_TIMER 0x00000002 787 #define INTR_MANUAL_TIMER 0x00000004 788 #define INTR_RX_FIFO_OFLOW 0x00000008 789 #define INTR_RD0_UNDERRUN 0x00000010 790 #define INTR_RD1_UNDERRUN 0x00000020 791 #define INTR_RD2_UNDERRUN 0x00000040 792 #define INTR_RD3_UNDERRUN 0x00000080 793 #define INTR_TX_FIFO_UNDERRUN 0x00000100 794 #define INTR_DMA_RD_TO_RST 0x00000200 795 #define INTR_DMA_WR_TO_RST 0x00000400 796 #define INTR_TX_CREDIT 0x00000800 797 #define INTR_GPHY 0x00001000 798 #define INTR_GPHY_LOW_PW 0x00002000 799 #define INTR_TXQ_TO_RST 0x00004000 800 #define INTR_TX_PKT0 0x00008000 801 #define INTR_RX_PKT0 0x00010000 802 #define INTR_RX_PKT1 0x00020000 803 #define INTR_RX_PKT2 0x00040000 804 #define INTR_RX_PKT3 0x00080000 805 #define INTR_MAC_RX 0x00100000 806 #define INTR_MAC_TX 0x00200000 807 #define INTR_UNDERRUN 0x00400000 808 #define INTR_FRAME_ERROR 0x00800000 809 #define INTR_FRAME_OK 0x01000000 810 #define INTR_CSUM_ERROR 0x02000000 811 #define INTR_PHY_LINK_DOWN 0x04000000 812 #define INTR_DIS_INT 0x80000000 813 814 /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ 815 #define INTR_TX_PKT1 0x00000020 816 #define INTR_TX_PKT2 0x00000040 817 #define INTR_TX_PKT3 0x00000080 818 #define INTR_RX_PKT4 0x08000000 819 #define INTR_RX_PKT5 0x10000000 820 #define INTR_RX_PKT6 0x20000000 821 #define INTR_RX_PKT7 0x40000000 822 823 /* Interrupt Mask Register */ 824 #define ALC_INTR_MASK 0x1604 825 826 #ifdef notyet 827 #define INTR_RX_PKT \ 828 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 829 INTR_RX_PKT3) 830 #define INTR_RD_UNDERRUN \ 831 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 832 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 833 #else 834 #define INTR_TX_PKT INTR_TX_PKT0 835 #define INTR_RX_PKT INTR_RX_PKT0 836 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 837 #endif 838 839 #define ALC_INTRS \ 840 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 841 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 842 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 843 INTR_TX_FIFO_UNDERRUN) 844 845 #define ALC_INTR_RETRIG_TIMER 0x1608 846 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 847 #define INTR_RETRIG_TIMER_SHIFT 0 848 849 #define ALC_HDS_CFG 0x160C 850 #define HDS_CFG_ENB 0x00000001 851 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 852 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 853 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 854 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 855 856 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ 857 858 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ 859 860 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ 861 862 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ 863 864 /* AR813x/AR815x registers for MAC statistics */ 865 #define ALC_RX_MIB_BASE 0x1700 866 867 #define ALC_TX_MIB_BASE 0x1760 868 869 #define ALC_DRV 0x1804 /* AR816x */ 870 #define DRV_ASPM_SPD10LMT_1M 0x00000000 871 #define DRV_ASPM_SPD10LMT_10M 0x00000001 872 #define DRV_ASPM_SPD10LMT_100M 0x00000002 873 #define DRV_ASPM_SPD10LMT_NO 0x00000003 874 #define DRV_ASPM_SPD10LMT_MASK 0x00000003 875 #define DRV_ASPM_SPD100LMT_1M 0x00000000 876 #define DRV_ASPM_SPD100LMT_10M 0x00000004 877 #define DRV_ASPM_SPD100LMT_100M 0x00000008 878 #define DRV_ASPM_SPD100LMT_NO 0x0000000C 879 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C 880 #define DRV_ASPM_SPD1000LMT_100M 0x00000000 881 #define DRV_ASPM_SPD1000LMT_NO 0x00000010 882 #define DRV_ASPM_SPD1000LMT_1M 0x00000020 883 #define DRV_ASPM_SPD1000LMT_10M 0x00000030 884 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000 885 #define DRV_WOLCAP_BIOS_EN 0x00000100 886 #define DRV_WOLMAGIC_EN 0x00000200 887 #define DRV_WOLLINKUP_EN 0x00000400 888 #define DRV_WOLPATTERN_EN 0x00000800 889 #define DRV_AZ_EN 0x00001000 890 #define DRV_WOLS5_BIOS_EN 0x00010000 891 #define DRV_WOLS5_EN 0x00020000 892 #define DRV_DISABLE 0x00040000 893 #define DRV_PHY_MASK 0x1FE00000 894 #define DRV_PHY_EEE 0x00200000 895 #define DRV_PHY_APAUSE 0x00400000 896 #define DRV_PHY_PAUSE 0x00800000 897 #define DRV_PHY_DUPLEX 0x01000000 898 #define DRV_PHY_10 0x02000000 899 #define DRV_PHY_100 0x04000000 900 #define DRV_PHY_1000 0x08000000 901 #define DRV_PHY_AUTO 0x10000000 902 #define DRV_PHY_SHIFT 21 903 904 #define ALC_CLK_GATING_CFG 0x1814 905 #define CLK_GATING_DMAW_ENB 0x0001 906 #define CLK_GATING_DMAR_ENB 0x0002 907 #define CLK_GATING_TXQ_ENB 0x0004 908 #define CLK_GATING_RXQ_ENB 0x0008 909 #define CLK_GATING_TXMAC_ENB 0x0010 910 #define CLK_GATING_RXMAC_ENB 0x0020 911 912 #define ALC_DEBUG_DATA0 0x1900 913 914 #define ALC_DEBUG_DATA1 0x1904 915 916 #define ALC_MSI_RETRANS_TIMER 0x1920 917 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF 918 #define MSI_RETRANS_MASK_SEL_STD 0x00000000 919 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000 920 #define MSI_RETRANS_TIMER_SHIFT 0 921 922 #define ALC_WRR 0x1938 923 #define WRR_PRI0_MASK 0x0000001F 924 #define WRR_PRI1_MASK 0x00001F00 925 #define WRR_PRI2_MASK 0x001F0000 926 #define WRR_PRI3_MASK 0x1F000000 927 #define WRR_PRI_RESTRICT_MASK 0x60000000 928 #define WRR_PRI_RESTRICT_ALL 0x00000000 929 #define WRR_PRI_RESTRICT_HI 0x20000000 930 #define WRR_PRI_RESTRICT_HI2 0x40000000 931 #define WRR_PRI_RESTRICT_NONE 0x60000000 932 #define WRR_PRI0_SHIFT 0 933 #define WRR_PRI1_SHIFT 8 934 #define WRR_PRI2_SHIFT 16 935 #define WRR_PRI3_SHIFT 24 936 #define WRR_PRI_DEFAULT 4 937 #define WRR_PRI_RESTRICT_SHIFT 29 938 939 #define ALC_HQTD_CFG 0x193C 940 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F 941 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0 942 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00 943 #define HQTD_CFG_BURST_ENB 0x80000000 944 #define HQTD_CFG_Q1_BURST_SHIFT 0 945 #define HQTD_CFG_Q2_BURST_SHIFT 4 946 #define HQTD_CFG_Q3_BURST_SHIFT 8 947 948 #define ALC_MISC 0x19C0 949 #define MISC_INTNLOSC_OPEN 0x00000008 950 #define MISC_ISO_ENB 0x00001000 951 #define MISC_PSW_OCP_MASK 0x00E00000 952 #define MISC_PSW_OCP_SHIFT 21 953 #define MISC_PSW_OCP_DEFAULT 7 954 955 #define ALC_MISC2 0x19C8 956 #define MISC2_CALB_START 0x00000001 957 958 #define ALC_MISC3 0x19CC 959 #define MISC3_25M_NOTO_INTNL 0x00000001 960 #define MISC3_25M_BY_SW 0x00000002 961 962 #define ALC_MII_DBG_ADDR 0x1D 963 #define ALC_MII_DBG_DATA 0x1E 964 965 #define MII_ANA_CFG0 0x00 966 #define ANA_RESTART_CAL 0x0001 967 #define ANA_MANUL_SWICH_ON_MASK 0x001E 968 #define ANA_MAN_ENABLE 0x0020 969 #define ANA_SEL_HSP 0x0040 970 #define ANA_EN_HB 0x0080 971 #define ANA_EN_HBIAS 0x0100 972 #define ANA_OEN_125M 0x0200 973 #define ANA_EN_LCKDT 0x0400 974 #define ANA_LCKDT_PHY 0x0800 975 #define ANA_AFE_MODE 0x1000 976 #define ANA_VCO_SLOW 0x2000 977 #define ANA_VCO_FAST 0x4000 978 #define ANA_SEL_CLK125M_DSP 0x8000 979 #define ANA_MANUL_SWICH_ON_SHIFT 1 980 981 #define MII_DBG_ANACTL 0x00 982 #define DBG_ANACTL_DEFAULT 0x02EF 983 984 #define MII_ANA_CFG4 0x04 985 #define ANA_IECHO_ADJ_MASK 0x0F 986 #define ANA_IECHO_ADJ_3_MASK 0x000F 987 #define ANA_IECHO_ADJ_2_MASK 0x00F0 988 #define ANA_IECHO_ADJ_1_MASK 0x0F00 989 #define ANA_IECHO_ADJ_0_MASK 0xF000 990 #define ANA_IECHO_ADJ_3_SHIFT 0 991 #define ANA_IECHO_ADJ_2_SHIFT 4 992 #define ANA_IECHO_ADJ_1_SHIFT 8 993 #define ANA_IECHO_ADJ_0_SHIFT 12 994 995 #define MII_DBG_SYSMODCTL 0x04 996 #define DBG_SYSMODCTL_DEFAULT 0xBB8B 997 998 #define MII_ANA_CFG5 0x05 999 #define ANA_SERDES_CDR_BW_MASK 0x0003 1000 #define ANA_MS_PAD_DBG 0x0004 1001 #define ANA_SPEEDUP_DBG 0x0008 1002 #define ANA_SERDES_TH_LOS_MASK 0x0030 1003 #define ANA_SERDES_EN_DEEM 0x0040 1004 #define ANA_SERDES_TXELECIDLE 0x0080 1005 #define ANA_SERDES_BEACON 0x0100 1006 #define ANA_SERDES_HALFTXDR 0x0200 1007 #define ANA_SERDES_SEL_HSP 0x0400 1008 #define ANA_SERDES_EN_PLL 0x0800 1009 #define ANA_SERDES_EN 0x1000 1010 #define ANA_SERDES_EN_LCKDT 0x2000 1011 #define ANA_SERDES_CDR_BW_SHIFT 0 1012 #define ANA_SERDES_TH_LOS_SHIFT 4 1013 1014 #define MII_DBG_SRDSYSMOD 0x05 1015 #define DBG_SRDSYSMOD_DEFAULT 0x2C46 1016 1017 #define MII_ANA_CFG11 0x0B 1018 #define ANA_PS_HIB_EN 0x8000 1019 1020 #define MII_DBG_HIBNEG 0x0B 1021 #define DBG_HIBNEG_HIB_PULSE 0x1000 1022 #define DBG_HIBNEG_PSHIB_EN 0x8000 1023 #define DBG_HIBNEG_DEFAULT 0xBC40 1024 1025 #define MII_ANA_CFG18 0x12 1026 #define ANA_TEST_MODE_10BT_01MASK 0x0003 1027 #define ANA_LOOP_SEL_10BT 0x0004 1028 #define ANA_RGMII_MODE_SW 0x0008 1029 #define ANA_EN_LONGECABLE 0x0010 1030 #define ANA_TEST_MODE_10BT_2 0x0020 1031 #define ANA_EN_10BT_IDLE 0x0400 1032 #define ANA_EN_MASK_TB 0x0800 1033 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 1034 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 1035 #define ANA_TEST_MODE_10BT_01SHIFT 0 1036 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 1037 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 1038 1039 #define MII_DBG_TST10BTCFG 0x12 1040 #define DBG_TST10BTCFG_DEFAULT 0x4C04 1041 1042 #define MII_DBG_AZ_ANADECT 0x15 1043 #define DBG_AZ_ANADECT_DEFAULT 0x3220 1044 #define DBG_AZ_ANADECT_LONG 0x3210 1045 1046 #define MII_DBG_MSE16DB 0x18 1047 #define DBG_MSE16DB_UP 0x05EA 1048 #define DBG_MSE16DB_DOWN 0x02EA 1049 1050 #define MII_DBG_MSE20DB 0x1C 1051 #define DBG_MSE20DB_TH_MASK 0x01FC 1052 #define DBG_MSE20DB_TH_DEFAULT 0x2E 1053 #define DBG_MSE20DB_TH_HI 0x54 1054 #define DBG_MSE20DB_TH_SHIFT 2 1055 1056 #define MII_DBG_AGC 0x23 1057 #define DBG_AGC_2_VGA_MASK 0x3F00 1058 #define DBG_AGC_2_VGA_SHIFT 8 1059 #define DBG_AGC_LONG1G_LIMT 40 1060 #define DBG_AGC_LONG100M_LIMT 44 1061 1062 #define MII_ANA_CFG41 0x29 1063 #define ANA_TOP_PS_EN 0x8000 1064 1065 #define MII_DBG_LEGCYPS 0x29 1066 #define DBG_LEGCYPS_ENB 0x8000 1067 #define DBG_LEGCYPS_DEFAULT 0x129D 1068 1069 #define MII_ANA_CFG54 0x36 1070 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 1071 #define ANA_DESERVED 0x0040 1072 #define ANA_EN_LIT_CH 0x0080 1073 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 1074 #define ANA_BP_BAD_LINK_ACCUM 0x4000 1075 #define ANA_BP_SMALL_BW 0x8000 1076 #define ANA_LONG_CABLE_TH_100_SHIFT 0 1077 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 1078 1079 #define MII_DBG_TST100BTCFG 0x36 1080 #define DBG_TST100BTCFG_DEFAULT 0xE12C 1081 1082 #define MII_DBG_GREENCFG 0x3B 1083 #define DBG_GREENCFG_DEFAULT 0x7078 1084 1085 #define MII_DBG_GREENCFG2 0x3D 1086 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 1087 #define DBG_GREENCFG2_BP_GREEN 0x8000 1088 1089 /* Device addr 3 */ 1090 #define MII_EXT_PCS 3 1091 1092 #define MII_EXT_CLDCTL3 0x8003 1093 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 1094 1095 #define MII_EXT_CLDCTL5 0x8005 1096 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 1097 1098 #define MII_EXT_CLDCTL6 0x8006 1099 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF 1100 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0 1101 #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 1102 #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 1103 1104 #define MII_EXT_VDRVBIAS 0x8062 1105 #define EXT_VDRVBIAS_DEFAULT 3 1106 1107 /* Device addr 7 */ 1108 #define MII_EXT_ANEG 7 1109 1110 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C 1111 #define ANEG_LOCA_EEEADV_100BT 0x0002 1112 #define ANEG_LOCA_EEEADV_1000BT 0x0004 1113 1114 #define MII_EXT_ANEG_AFE 0x801A 1115 #define ANEG_AFEE_10BT_100M_TH 0x0040 1116 1117 #define MII_EXT_ANEG_S3DIG10 0x8023 1118 #define ANEG_S3DIG10_SL 0x0001 1119 #define ANEG_S3DIG10_DEFAULT 0 1120 1121 #define MII_EXT_ANEG_NLP78 0x8027 1122 #define ANEG_NLP78_120M_DEFAULT 0x8A05 1123 1124 /* Statistics counters collected by the MAC. */ 1125 struct smb { 1126 /* Rx stats. */ 1127 uint32_t rx_frames; 1128 uint32_t rx_bcast_frames; 1129 uint32_t rx_mcast_frames; 1130 uint32_t rx_pause_frames; 1131 uint32_t rx_control_frames; 1132 uint32_t rx_crcerrs; 1133 uint32_t rx_lenerrs; 1134 uint32_t rx_bytes; 1135 uint32_t rx_runts; 1136 uint32_t rx_fragments; 1137 uint32_t rx_pkts_64; 1138 uint32_t rx_pkts_65_127; 1139 uint32_t rx_pkts_128_255; 1140 uint32_t rx_pkts_256_511; 1141 uint32_t rx_pkts_512_1023; 1142 uint32_t rx_pkts_1024_1518; 1143 uint32_t rx_pkts_1519_max; 1144 uint32_t rx_pkts_truncated; 1145 uint32_t rx_fifo_oflows; 1146 uint32_t rx_rrs_errs; 1147 uint32_t rx_alignerrs; 1148 uint32_t rx_bcast_bytes; 1149 uint32_t rx_mcast_bytes; 1150 uint32_t rx_pkts_filtered; 1151 /* Tx stats. */ 1152 uint32_t tx_frames; 1153 uint32_t tx_bcast_frames; 1154 uint32_t tx_mcast_frames; 1155 uint32_t tx_pause_frames; 1156 uint32_t tx_excess_defer; 1157 uint32_t tx_control_frames; 1158 uint32_t tx_deferred; 1159 uint32_t tx_bytes; 1160 uint32_t tx_pkts_64; 1161 uint32_t tx_pkts_65_127; 1162 uint32_t tx_pkts_128_255; 1163 uint32_t tx_pkts_256_511; 1164 uint32_t tx_pkts_512_1023; 1165 uint32_t tx_pkts_1024_1518; 1166 uint32_t tx_pkts_1519_max; 1167 uint32_t tx_single_colls; 1168 uint32_t tx_multi_colls; 1169 uint32_t tx_late_colls; 1170 uint32_t tx_excess_colls; 1171 uint32_t tx_underrun; 1172 uint32_t tx_desc_underrun; 1173 uint32_t tx_lenerrs; 1174 uint32_t tx_pkts_truncated; 1175 uint32_t tx_bcast_bytes; 1176 uint32_t tx_mcast_bytes; 1177 uint32_t updated; 1178 }; 1179 1180 /* CMB(Coalesing message block) */ 1181 struct cmb { 1182 uint32_t cons; 1183 }; 1184 1185 /* Rx free descriptor */ 1186 struct rx_desc { 1187 uint64_t addr; 1188 }; 1189 1190 /* Rx return descriptor */ 1191 struct rx_rdesc { 1192 uint32_t rdinfo; 1193 #define RRD_CSUM_MASK 0x0000FFFF 1194 #define RRD_RD_CNT_MASK 0x000F0000 1195 #define RRD_RD_IDX_MASK 0xFFF00000 1196 #define RRD_CSUM_SHIFT 0 1197 #define RRD_RD_CNT_SHIFT 16 1198 #define RRD_RD_IDX_SHIFT 20 1199 #define RRD_CSUM(x) \ 1200 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 1201 #define RRD_RD_CNT(x) \ 1202 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 1203 #define RRD_RD_IDX(x) \ 1204 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 1205 uint32_t rss; 1206 uint32_t vtag; 1207 #define RRD_VLAN_MASK 0x0000FFFF 1208 #define RRD_HEAD_LEN_MASK 0x00FF0000 1209 #define RRD_HDS_MASK 0x03000000 1210 #define RRD_HDS_NONE 0x00000000 1211 #define RRD_HDS_HEAD 0x01000000 1212 #define RRD_HDS_DATA 0x02000000 1213 #define RRD_CPU_MASK 0x0C000000 1214 #define RRD_HASH_FLAG_MASK 0xF0000000 1215 #define RRD_VLAN_SHIFT 0 1216 #define RRD_HEAD_LEN_SHIFT 16 1217 #define RRD_HDS_SHIFT 24 1218 #define RRD_CPU_SHIFT 26 1219 #define RRD_HASH_FLAG_SHIFT 28 1220 #define RRD_VLAN(x) \ 1221 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 1222 #define RRD_HEAD_LEN(x) \ 1223 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 1224 #define RRD_CPU(x) \ 1225 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 1226 uint32_t status; 1227 #define RRD_LEN_MASK 0x00003FFF 1228 #define RRD_LEN_SHIFT 0 1229 #define RRD_TCP_UDPCSUM_NOK 0x00004000 1230 #define RRD_IPCSUM_NOK 0x00008000 1231 #define RRD_VLAN_TAG 0x00010000 1232 #define RRD_PROTO_MASK 0x000E0000 1233 #define RRD_PROTO_IPV4 0x00020000 1234 #define RRD_PROTO_IPV6 0x000C0000 1235 #define RRD_ERR_SUM 0x00100000 1236 #define RRD_ERR_CRC 0x00200000 1237 #define RRD_ERR_ALIGN 0x00400000 1238 #define RRD_ERR_TRUNC 0x00800000 1239 #define RRD_ERR_RUNT 0x01000000 1240 #define RRD_ERR_ICMP 0x02000000 1241 #define RRD_BCAST 0x04000000 1242 #define RRD_MCAST 0x08000000 1243 #define RRD_SNAP_LLC 0x10000000 1244 #define RRD_ETHER 0x00000000 1245 #define RRD_FIFO_FULL 0x20000000 1246 #define RRD_ERR_LENGTH 0x40000000 1247 #define RRD_VALID 0x80000000 1248 #define RRD_BYTES(x) \ 1249 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 1250 #define RRD_IPV4(x) \ 1251 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 1252 }; 1253 1254 /* Tx descriptor */ 1255 struct tx_desc { 1256 uint32_t len; 1257 #define TD_BUFLEN_MASK 0x00003FFF 1258 #define TD_VLAN_MASK 0xFFFF0000 1259 #define TD_BUFLEN_SHIFT 0 1260 #define TX_BYTES(x) \ 1261 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 1262 #define TD_VLAN_SHIFT 16 1263 uint32_t flags; 1264 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 1265 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 1266 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 1267 #define TD_CUSTOM_CSUM 0x00000100 1268 #define TD_IPCSUM 0x00000200 1269 #define TD_TCPCSUM 0x00000400 1270 #define TD_UDPCSUM 0x00000800 1271 #define TD_TSO 0x00001000 1272 #define TD_TSO_DESCV1 0x00000000 1273 #define TD_TSO_DESCV2 0x00002000 1274 #define TD_CON_VLAN_TAG 0x00004000 1275 #define TD_INS_VLAN_TAG 0x00008000 1276 #define TD_IPV4_DESCV2 0x00010000 1277 #define TD_LLC_SNAP 0x00020000 1278 #define TD_ETHERNET 0x00000000 1279 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 1280 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 1281 #define TD_MSS_MASK 0x7FFC0000 1282 #define TD_EOP 0x80000000 1283 #define TD_L4HDR_OFFSET_SHIFT 0 1284 #define TD_TCPHDR_OFFSET_SHIFT 0 1285 #define TD_PLOAD_OFFSET_SHIFT 0 1286 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 1287 #define TD_MSS_SHIFT 18 1288 uint64_t addr; 1289 }; 1290 1291 #endif /* _IF_ALCREG_H */ 1292