1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMATE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR8131/AR8132 device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43 44 /* 0x0000 - 0x02FF : PCIe configuration space */ 45 46 #define ALC_PEX_UNC_ERR_SEV 0x10C 47 #define PEX_UNC_ERR_SEV_TRN 0x00000001 48 #define PEX_UNC_ERR_SEV_DLP 0x00000010 49 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 50 #define PEX_UNC_ERR_SEV_FCP 0x00002000 51 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 52 #define PEX_UNC_ERR_SEV_CA 0x00008000 53 #define PEX_UNC_ERR_SEV_UC 0x00010000 54 #define PEX_UNC_ERR_SEV_ROV 0x00020000 55 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 56 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 57 #define PEX_UNC_ERR_SEV_UR 0x00100000 58 59 #define ALC_TWSI_CFG 0x218 60 #define TWSI_CFG_SW_LD_START 0x00000800 61 #define TWSI_CFG_HW_LD_START 0x00001000 62 #define TWSI_CFG_LD_EXIST 0x00400000 63 64 #define ALC_PCIE_PHYMISC 0x1000 65 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 66 67 #define ALC_TWSI_DEBUG 0x1108 68 #define TWSI_DEBUG_DEV_EXIST 0x20000000 69 70 #define ALC_EEPROM_CFG 0x12C0 71 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 72 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 73 #define EEPROM_CFG_ACK 0x40000000 74 #define EEPROM_CFG_RW 0x80000000 75 #define EEPROM_CFG_DATA_HI_SHIFT 0 76 #define EEPROM_CFG_ADDR_SHIFT 16 77 78 #define ALC_EEPROM_DATA_LO 0x12C4 79 80 #define ALC_OPT_CFG 0x12F0 81 #define OPT_CFG_CLK_ENB 0x00000002 82 83 #define ALC_PM_CFG 0x12F8 84 #define PM_CFG_SERDES_ENB 0x00000001 85 #define PM_CFG_RBER_ENB 0x00000002 86 #define PM_CFG_CLK_REQ_ENB 0x00000004 87 #define PM_CFG_ASPM_L1_ENB 0x00000008 88 #define PM_CFG_SERDES_L1_ENB 0x00000010 89 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 90 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 91 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 92 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 93 #define PM_CFG_ASPM_L0S_ENB 0x00001000 94 #define PM_CFG_CLK_SWH_L1 0x00002000 95 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 96 #define PM_CFG_PCIE_RECV 0x00008000 97 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 98 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 99 #define PM_CFG_LCKDET_TIMER_MASK 0x3F000000 100 #define PM_CFG_MAC_ASPM_CHK 0x40000000 101 #define PM_CFG_HOTRST 0x80000000 102 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 103 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 104 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 105 #define PM_CFG_LCKDET_TIMER_SHIFT 24 106 107 #define ALC_MASTER_CFG 0x1400 108 #define MASTER_RESET 0x00000001 109 #define MASTER_BERT_START 0x00000010 110 #define MASTER_TEST_MODE_MASK 0x000000C0 111 #define MASTER_MTIMER_ENB 0x00000100 112 #define MASTER_MANUAL_INTR_ENB 0x00000200 113 #define MASTER_IM_TX_TIMER_ENB 0x00000400 114 #define MASTER_IM_RX_TIMER_ENB 0x00000800 115 #define MASTER_CLK_SEL_DIS 0x00001000 116 #define MASTER_CLK_SWH_MODE 0x00002000 117 #define MASTER_INTR_RD_CLR 0x00004000 118 #define MASTER_CHIP_REV_MASK 0x00FF0000 119 #define MASTER_CHIP_ID_MASK 0x7F000000 120 #define MASTER_OTP_SEL 0x80000000 121 #define MASTER_TEST_MODE_SHIFT 2 122 #define MASTER_CHIP_REV_SHIFT 16 123 #define MASTER_CHIP_ID_SHIFT 24 124 125 /* Number of ticks per usec for AR8131/AR8132. */ 126 #define ALC_TICK_USECS 2 127 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 128 129 #define ALC_MANUAL_TIMER 0x1404 130 131 #define ALC_IM_TIMER 0x1408 132 #define IM_TIMER_TX_MASK 0x0000FFFF 133 #define IM_TIMER_RX_MASK 0xFFFF0000 134 #define IM_TIMER_TX_SHIFT 0 135 #define IM_TIMER_RX_SHIFT 16 136 #define ALC_IM_TIMER_MIN 0 137 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 138 /* 139 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 140 * interrupts in a second. 141 */ 142 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 143 /* 144 * alc(4) does not rely on Tx completion interrupts, so set it 145 * somewhat large value to reduce Tx completion interrupts. 146 */ 147 #define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */ 148 149 #define ALC_GPHY_CFG 0x140C /* 16bits */ 150 #define GPHY_CFG_EXT_RESET 0x0001 151 #define GPHY_CFG_RTL_MODE 0x0002 152 #define GPHY_CFG_LED_MODE 0x0004 153 #define GPHY_CFG_ANEG_NOW 0x0008 154 #define GPHY_CFG_RECV_ANEG 0x0010 155 #define GPHY_CFG_GATE_25M_ENB 0x0020 156 #define GPHY_CFG_LPW_EXIT 0x0040 157 #define GPHY_CFG_PHY_IDDQ 0x0080 158 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 159 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 160 #define GPHY_CFG_HIB_EN 0x0400 161 #define GPHY_CFG_HIB_PULSE 0x0800 162 #define GPHY_CFG_SEL_ANA_RESET 0x1000 163 #define GPHY_CFG_PHY_PLL_ON 0x2000 164 #define GPHY_CFG_PWDOWN_HW 0x4000 165 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 166 167 #define ALC_IDLE_STATUS 0x1410 168 #define IDLE_STATUS_RXMAC 0x00000001 169 #define IDLE_STATUS_TXMAC 0x00000002 170 #define IDLE_STATUS_RXQ 0x00000004 171 #define IDLE_STATUS_TXQ 0x00000008 172 #define IDLE_STATUS_DMARD 0x00000010 173 #define IDLE_STATUS_DMAWR 0x00000020 174 #define IDLE_STATUS_SMB 0x00000040 175 #define IDLE_STATUS_CMB 0x00000080 176 177 #define ALC_MDIO 0x1414 178 #define MDIO_DATA_MASK 0x0000FFFF 179 #define MDIO_REG_ADDR_MASK 0x001F0000 180 #define MDIO_OP_READ 0x00200000 181 #define MDIO_OP_WRITE 0x00000000 182 #define MDIO_SUP_PREAMBLE 0x00400000 183 #define MDIO_OP_EXECUTE 0x00800000 184 #define MDIO_CLK_25_4 0x00000000 185 #define MDIO_CLK_25_6 0x02000000 186 #define MDIO_CLK_25_8 0x03000000 187 #define MDIO_CLK_25_10 0x04000000 188 #define MDIO_CLK_25_14 0x05000000 189 #define MDIO_CLK_25_20 0x06000000 190 #define MDIO_CLK_25_28 0x07000000 191 #define MDIO_OP_BUSY 0x08000000 192 #define MDIO_AP_ENB 0x10000000 193 #define MDIO_DATA_SHIFT 0 194 #define MDIO_REG_ADDR_SHIFT 16 195 196 #define MDIO_REG_ADDR(x) \ 197 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 198 /* Default PHY address. */ 199 #define ALC_PHY_ADDR 0 200 201 #define ALC_PHY_STATUS 0x1418 202 #define PHY_STATUS_RECV_ENB 0x00000001 203 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 204 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 205 #define PHY_STATUS_LPW_STATE 0x80000000 206 #define PHY_STATIS_OE_PWSP_SHIFT 16 207 208 /* Packet memory BIST. */ 209 #define ALC_BIST0 0x141C 210 #define BIST0_ENB 0x00000001 211 #define BIST0_SRAM_FAIL 0x00000002 212 #define BIST0_FUSE_FLAG 0x00000004 213 214 /* PCIe retry buffer BIST. */ 215 #define ALC_BIST1 0x1420 216 #define BIST1_ENB 0x00000001 217 #define BIST1_SRAM_FAIL 0x00000002 218 #define BIST1_FUSE_FLAG 0x00000004 219 220 #define ALC_SERDES_LOCK 0x1424 221 #define SERDES_LOCK_DET 0x00000001 222 #define SERDES_LOCK_DET_ENB 0x00000002 223 224 #define ALC_MAC_CFG 0x1480 225 #define MAC_CFG_TX_ENB 0x00000001 226 #define MAC_CFG_RX_ENB 0x00000002 227 #define MAC_CFG_TX_FC 0x00000004 228 #define MAC_CFG_RX_FC 0x00000008 229 #define MAC_CFG_LOOP 0x00000010 230 #define MAC_CFG_FULL_DUPLEX 0x00000020 231 #define MAC_CFG_TX_CRC_ENB 0x00000040 232 #define MAC_CFG_TX_AUTO_PAD 0x00000080 233 #define MAC_CFG_TX_LENCHK 0x00000100 234 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 235 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 236 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 237 #define MAC_CFG_PROMISC 0x00008000 238 #define MAC_CFG_TX_PAUSE 0x00010000 239 #define MAC_CFG_SCNT 0x00020000 240 #define MAC_CFG_SYNC_RST_TX 0x00040000 241 #define MAC_CFG_SIM_RST_TX 0x00080000 242 #define MAC_CFG_SPEED_MASK 0x00300000 243 #define MAC_CFG_SPEED_10_100 0x00100000 244 #define MAC_CFG_SPEED_1000 0x00200000 245 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 246 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 247 #define MAC_CFG_RXCSUM_ENB 0x01000000 248 #define MAC_CFG_ALLMULTI 0x02000000 249 #define MAC_CFG_BCAST 0x04000000 250 #define MAC_CFG_DBG 0x08000000 251 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 252 #define MAC_CFG_PREAMBLE_SHIFT 10 253 #define MAC_CFG_PREAMBLE_DEFAULT 7 254 255 #define ALC_IPG_IFG_CFG 0x1484 256 #define IPG_IFG_IPGT_MASK 0x0000007F 257 #define IPG_IFG_MIFG_MASK 0x0000FF00 258 #define IPG_IFG_IPG1_MASK 0x007F0000 259 #define IPG_IFG_IPG2_MASK 0x7F000000 260 #define IPG_IFG_IPGT_SHIFT 0 261 #define IPG_IFG_IPGT_DEFAULT 0x60 262 #define IPG_IFG_MIFG_SHIFT 8 263 #define IPG_IFG_MIFG_DEFAULT 0x50 264 #define IPG_IFG_IPG1_SHIFT 16 265 #define IPG_IFG_IPG1_DEFAULT 0x40 266 #define IPG_IFG_IPG2_SHIFT 24 267 #define IPG_IFG_IPG2_DEFAULT 0x60 268 269 /* Station address. */ 270 #define ALC_PAR0 0x1488 271 #define ALC_PAR1 0x148C 272 273 /* 64bit multicast hash register. */ 274 #define ALC_MAR0 0x1490 275 #define ALC_MAR1 0x1494 276 277 /* half-duplex parameter configuration. */ 278 #define ALC_HDPX_CFG 0x1498 279 #define HDPX_CFG_LCOL_MASK 0x000003FF 280 #define HDPX_CFG_RETRY_MASK 0x0000F000 281 #define HDPX_CFG_EXC_DEF_EN 0x00010000 282 #define HDPX_CFG_NO_BACK_C 0x00020000 283 #define HDPX_CFG_NO_BACK_P 0x00040000 284 #define HDPX_CFG_ABEBE 0x00080000 285 #define HDPX_CFG_ABEBT_MASK 0x00F00000 286 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 287 #define HDPX_CFG_LCOL_SHIFT 0 288 #define HDPX_CFG_LCOL_DEFAULT 0x37 289 #define HDPX_CFG_RETRY_SHIFT 12 290 #define HDPX_CFG_RETRY_DEFAULT 0x0F 291 #define HDPX_CFG_ABEBT_SHIFT 20 292 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 293 #define HDPX_CFG_JAMIPG_SHIFT 24 294 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 295 296 #define ALC_FRAME_SIZE 0x149C 297 298 #define ALC_WOL_CFG 0x14A0 299 #define WOL_CFG_PATTERN 0x00000001 300 #define WOL_CFG_PATTERN_ENB 0x00000002 301 #define WOL_CFG_MAGIC 0x00000004 302 #define WOL_CFG_MAGIC_ENB 0x00000008 303 #define WOL_CFG_LINK_CHG 0x00000010 304 #define WOL_CFG_LINK_CHG_ENB 0x00000020 305 #define WOL_CFG_PATTERN_DET 0x00000100 306 #define WOL_CFG_MAGIC_DET 0x00000200 307 #define WOL_CFG_LINK_CHG_DET 0x00000400 308 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 309 #define WOL_CFG_PATTERN0 0x00010000 310 #define WOL_CFG_PATTERN1 0x00020000 311 #define WOL_CFG_PATTERN2 0x00040000 312 #define WOL_CFG_PATTERN3 0x00080000 313 #define WOL_CFG_PATTERN4 0x00100000 314 #define WOL_CFG_PATTERN5 0x00200000 315 #define WOL_CFG_PATTERN6 0x00400000 316 317 /* WOL pattern length. */ 318 #define ALC_PATTERN_CFG0 0x14A4 319 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 320 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 321 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 322 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 323 324 #define ALC_PATTERN_CFG1 0x14A8 325 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 326 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 327 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 328 329 /* RSS */ 330 #define ALC_RSS_KEY0 0x14B0 331 332 #define ALC_RSS_KEY1 0x14B4 333 334 #define ALC_RSS_KEY2 0x14B8 335 336 #define ALC_RSS_KEY3 0x14BC 337 338 #define ALC_RSS_KEY4 0x14C0 339 340 #define ALC_RSS_KEY5 0x14C4 341 342 #define ALC_RSS_KEY6 0x14C8 343 344 #define ALC_RSS_KEY7 0x14CC 345 346 #define ALC_RSS_KEY8 0x14D0 347 348 #define ALC_RSS_KEY9 0x14D4 349 350 #define ALC_RSS_IDT_TABLE0 0x14E0 351 352 #define ALC_RSS_IDT_TABLE1 0x14E4 353 354 #define ALC_RSS_IDT_TABLE2 0x14E8 355 356 #define ALC_RSS_IDT_TABLE3 0x14EC 357 358 #define ALC_RSS_IDT_TABLE4 0x14F0 359 360 #define ALC_RSS_IDT_TABLE5 0x14F4 361 362 #define ALC_RSS_IDT_TABLE6 0x14F8 363 364 #define ALC_RSS_IDT_TABLE7 0x14FC 365 366 #define ALC_SRAM_RD0_ADDR 0x1500 367 368 #define ALC_SRAM_RD1_ADDR 0x1504 369 370 #define ALC_SRAM_RD2_ADDR 0x1508 371 372 #define ALC_SRAM_RD3_ADDR 0x150C 373 374 #define RD_HEAD_ADDR_MASK 0x000003FF 375 #define RD_TAIL_ADDR_MASK 0x03FF0000 376 #define RD_HEAD_ADDR_SHIFT 0 377 #define RD_TAIL_ADDR_SHIFT 16 378 379 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 380 #define RD_NIC_LEN_MASK 0x000003FF 381 382 #define ALC_RD_NIC_LEN1 0x1514 383 384 #define ALC_SRAM_TD_ADDR 0x1518 385 #define TD_HEAD_ADDR_MASK 0x000003FF 386 #define TD_TAIL_ADDR_MASK 0x03FF0000 387 #define TD_HEAD_ADDR_SHIFT 0 388 #define TD_TAIL_ADDR_SHIFT 16 389 390 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 391 #define SRAM_TD_LEN_MASK 0x000003FF 392 393 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 394 395 #define ALC_SRAM_RX_FIFO_LEN 0x1524 396 397 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 398 399 #define ALC_SRAM_TX_FIFO_LEN 0x152C 400 401 #define ALC_SRAM_TCPH_ADDR 0x1530 402 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 403 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 404 #define SRAM_TCPH_ADDR_SHIFT 0 405 #define SRAM_PKTH_ADDR_SHIFT 16 406 407 #define ALC_DMA_BLOCK 0x1534 408 #define DMA_BLOCK_LOAD 0x00000001 409 410 #define ALC_RX_BASE_ADDR_HI 0x1540 411 412 #define ALC_TX_BASE_ADDR_HI 0x1544 413 414 #define ALC_SMB_BASE_ADDR_HI 0x1548 415 416 #define ALC_SMB_BASE_ADDR_LO 0x154C 417 418 #define ALC_RD0_HEAD_ADDR_LO 0x1550 419 420 #define ALC_RD1_HEAD_ADDR_LO 0x1554 421 422 #define ALC_RD2_HEAD_ADDR_LO 0x1558 423 424 #define ALC_RD3_HEAD_ADDR_LO 0x155C 425 426 #define ALC_RD_RING_CNT 0x1560 427 #define RD_RING_CNT_MASK 0x00000FFF 428 #define RD_RING_CNT_SHIFT 0 429 430 #define ALC_RX_BUF_SIZE 0x1564 431 #define RX_BUF_SIZE_MASK 0x0000FFFF 432 /* 433 * If larger buffer size than 1536 is specified the controller 434 * will be locked up. This is hardware limitation. 435 */ 436 #define RX_BUF_SIZE_MAX 1536 437 438 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 439 440 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 441 442 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 443 444 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 445 446 #define ALC_RRD_RING_CNT 0x1578 447 #define RRD_RING_CNT_MASK 0x00000FFF 448 #define RRD_RING_CNT_SHIFT 0 449 450 #define ALC_TDH_HEAD_ADDR_LO 0x157C 451 452 #define ALC_TDL_HEAD_ADDR_LO 0x1580 453 454 #define ALC_TD_RING_CNT 0x1584 455 #define TD_RING_CNT_MASK 0x0000FFFF 456 #define TD_RING_CNT_SHIFT 0 457 458 #define ALC_CMB_BASE_ADDR_LO 0x1588 459 460 #define ALC_TXQ_CFG 0x1590 461 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 462 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 463 #define TXQ_CFG_ENB 0x00000020 464 #define TXQ_CFG_ENHANCED_MODE 0x00000040 465 #define TXQ_CFG_8023_ENB 0x00000080 466 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 467 #define TXQ_CFG_TD_BURST_SHIFT 0 468 #define TXQ_CFG_TD_BURST_DEFAULT 5 469 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 470 471 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 472 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 473 #define TSO_OFFLOAD_THRESH_SHIFT 0 474 #define TSO_OFFLOAD_THRESH_UNIT 8 475 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 476 477 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 478 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 479 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 480 #define TXF_WATER_MARK_BURST_ENB 0x80000000 481 #define TXF_WATER_MARK_LO_SHIFT 0 482 #define TXF_WATER_MARK_HI_SHIFT 16 483 484 #define ALC_THROUGHPUT_MON 0x159C 485 #define THROUGHPUT_MON_RATE_MASK 0x00000003 486 #define THROUGHPUT_MON_ENB 0x00000080 487 #define THROUGHPUT_MON_RATE_SHIFT 0 488 489 #define ALC_RXQ_CFG 0x15A0 490 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 491 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 492 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 493 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 494 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 495 #define RXQ_CFG_QUEUE1_ENB 0x00000010 496 #define RXQ_CFG_QUEUE2_ENB 0x00000020 497 #define RXQ_CFG_QUEUE3_ENB 0x00000040 498 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 499 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 500 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 501 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 502 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 503 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 504 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 505 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 506 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 507 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 508 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 509 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 510 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 511 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 512 #define RXQ_CFG_QUEUE0_ENB 0x80000000 513 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 514 #define RXQ_CFG_RD_BURST_DEFAULT 8 515 #define RXQ_CFG_RD_BURST_SHIFT 20 516 #define RXQ_CFG_ENB \ 517 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 518 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 519 520 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 521 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 522 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 523 #define RX_RD_FREE_THRESH_HI_SHIFT 0 524 #define RX_RD_FREE_THRESH_LO_SHIFT 6 525 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 526 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 527 528 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 529 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 530 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 531 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 532 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 533 534 #define ALC_RD_DMA_CFG 0x15AC 535 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 536 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 537 #define RD_DMA_CFG_THRESH_SHIFT 0 538 #define RD_DMA_CFG_TIMER_SHIFT 16 539 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 540 #define RD_DMA_CFG_TIMER_DEFAULT 0 541 #define RD_DMA_CFG_TICK_USECS 8 542 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 543 544 #define ALC_RSS_HASH_VALUE 0x15B0 545 546 #define ALC_RSS_HASH_FLAG 0x15B4 547 548 #define ALC_RSS_CPU 0x15B8 549 550 #define ALC_DMA_CFG 0x15C0 551 #define DMA_CFG_IN_ORDER 0x00000001 552 #define DMA_CFG_ENH_ORDER 0x00000002 553 #define DMA_CFG_OUT_ORDER 0x00000004 554 #define DMA_CFG_RCB_64 0x00000000 555 #define DMA_CFG_RCB_128 0x00000008 556 #define DMA_CFG_RD_BURST_128 0x00000000 557 #define DMA_CFG_RD_BURST_256 0x00000010 558 #define DMA_CFG_RD_BURST_512 0x00000020 559 #define DMA_CFG_RD_BURST_1024 0x00000030 560 #define DMA_CFG_RD_BURST_2048 0x00000040 561 #define DMA_CFG_RD_BURST_4096 0x00000050 562 #define DMA_CFG_WR_BURST_128 0x00000000 563 #define DMA_CFG_WR_BURST_256 0x00000080 564 #define DMA_CFG_WR_BURST_512 0x00000100 565 #define DMA_CFG_WR_BURST_1024 0x00000180 566 #define DMA_CFG_WR_BURST_2048 0x00000200 567 #define DMA_CFG_WR_BURST_4096 0x00000280 568 #define DMA_CFG_RD_REQ_PRI 0x00000400 569 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 570 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 571 #define DMA_CFG_CMB_ENB 0x00100000 572 #define DMA_CFG_SMB_ENB 0x00200000 573 #define DMA_CFG_CMB_NOW 0x00400000 574 #define DMA_CFG_SMB_DIS 0x01000000 575 #define DMA_CFG_SMB_NOW 0x80000000 576 #define DMA_CFG_RD_BURST_MASK 0x07 577 #define DMA_CFG_RD_BURST_SHIFT 4 578 #define DMA_CFG_WR_BURST_MASK 0x07 579 #define DMA_CFG_WR_BURST_SHIFT 7 580 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 581 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 582 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 583 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 584 585 #define ALC_SMB_STAT_TIMER 0x15C4 586 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 587 #define SMB_STAT_TIMER_SHIFT 0 588 589 #define ALC_CMB_TD_THRESH 0x15C8 590 #define CMB_TD_THRESH_MASK 0x0000FFFF 591 #define CMB_TD_THRESH_SHIFT 0 592 593 #define ALC_CMB_TX_TIMER 0x15CC 594 #define CMB_TX_TIMER_MASK 0x0000FFFF 595 #define CMB_TX_TIMER_SHIFT 0 596 597 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 598 599 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 600 601 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 602 603 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 604 605 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 606 #define MBOX_RD_PROD_SHIFT 0 607 608 #define ALC_MBOX_TD_PROD_IDX 0x15F0 609 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 610 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 611 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 612 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 613 614 #define ALC_MBOX_TD_CONS_IDX 0x15F4 615 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 616 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 617 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 618 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 619 620 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 621 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 622 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 623 #define MBOX_RD0_CONS_IDX_SHIFT 0 624 #define MBOX_RD1_CONS_IDX_SHIFT 16 625 626 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 627 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 628 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 629 #define MBOX_RD2_CONS_IDX_SHIFT 0 630 #define MBOX_RD3_CONS_IDX_SHIFT 16 631 632 #define ALC_INTR_STATUS 0x1600 633 #define INTR_SMB 0x00000001 634 #define INTR_TIMER 0x00000002 635 #define INTR_MANUAL_TIMER 0x00000004 636 #define INTR_RX_FIFO_OFLOW 0x00000008 637 #define INTR_RD0_UNDERRUN 0x00000010 638 #define INTR_RD1_UNDERRUN 0x00000020 639 #define INTR_RD2_UNDERRUN 0x00000040 640 #define INTR_RD3_UNDERRUN 0x00000080 641 #define INTR_TX_FIFO_UNDERRUN 0x00000100 642 #define INTR_DMA_RD_TO_RST 0x00000200 643 #define INTR_DMA_WR_TO_RST 0x00000400 644 #define INTR_TX_CREDIT 0x00000800 645 #define INTR_GPHY 0x00001000 646 #define INTR_GPHY_LOW_PW 0x00002000 647 #define INTR_TXQ_TO_RST 0x00004000 648 #define INTR_TX_PKT 0x00008000 649 #define INTR_RX_PKT0 0x00010000 650 #define INTR_RX_PKT1 0x00020000 651 #define INTR_RX_PKT2 0x00040000 652 #define INTR_RX_PKT3 0x00080000 653 #define INTR_MAC_RX 0x00100000 654 #define INTR_MAC_TX 0x00200000 655 #define INTR_UNDERRUN 0x00400000 656 #define INTR_FRAME_ERROR 0x00800000 657 #define INTR_FRAME_OK 0x01000000 658 #define INTR_CSUM_ERROR 0x02000000 659 #define INTR_PHY_LINK_DOWN 0x04000000 660 #define INTR_DIS_INT 0x80000000 661 662 /* Interrupt Mask Register */ 663 #define ALC_INTR_MASK 0x1604 664 665 #ifdef notyet 666 #define INTR_RX_PKT \ 667 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 668 INTR_RX_PKT3) 669 #define INTR_RD_UNDERRUN \ 670 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 671 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 672 #else 673 #define INTR_RX_PKT INTR_RX_PKT0 674 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 675 #endif 676 677 #define ALC_INTRS \ 678 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 679 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 680 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 681 INTR_TX_FIFO_UNDERRUN) 682 683 #define ALC_INTR_RETRIG_TIMER 0x1608 684 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 685 #define INTR_RETRIG_TIMER_SHIFT 0 686 687 #define ALC_HDS_CFG 0x160C 688 #define HDS_CFG_ENB 0x00000001 689 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 690 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 691 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 692 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 693 694 /* AR8131/AR8132 registers for MAC statistics */ 695 #define ALC_RX_MIB_BASE 0x1700 696 697 #define ALC_TX_MIB_BASE 0x1760 698 699 #define ALC_DEBUG_DATA0 0x1900 700 701 #define ALC_DEBUG_DATA1 0x1904 702 703 #define ALC_MII_DBG_ADDR 0x1D 704 #define ALC_MII_DBG_DATA 0x1E 705 706 #define MII_ANA_CFG0 0x00 707 #define ANA_RESTART_CAL 0x0001 708 #define ANA_MANUL_SWICH_ON_MASK 0x001E 709 #define ANA_MAN_ENABLE 0x0020 710 #define ANA_SEL_HSP 0x0040 711 #define ANA_EN_HB 0x0080 712 #define ANA_EN_HBIAS 0x0100 713 #define ANA_OEN_125M 0x0200 714 #define ANA_EN_LCKDT 0x0400 715 #define ANA_LCKDT_PHY 0x0800 716 #define ANA_AFE_MODE 0x1000 717 #define ANA_VCO_SLOW 0x2000 718 #define ANA_VCO_FAST 0x4000 719 #define ANA_SEL_CLK125M_DSP 0x8000 720 #define ANA_MANUL_SWICH_ON_SHIFT 1 721 722 #define MII_ANA_CFG4 0x04 723 #define ANA_IECHO_ADJ_MASK 0x0F 724 #define ANA_IECHO_ADJ_3_MASK 0x000F 725 #define ANA_IECHO_ADJ_2_MASK 0x00F0 726 #define ANA_IECHO_ADJ_1_MASK 0x0F00 727 #define ANA_IECHO_ADJ_0_MASK 0xF000 728 #define ANA_IECHO_ADJ_3_SHIFT 0 729 #define ANA_IECHO_ADJ_2_SHIFT 4 730 #define ANA_IECHO_ADJ_1_SHIFT 8 731 #define ANA_IECHO_ADJ_0_SHIFT 12 732 733 #define MII_ANA_CFG5 0x05 734 #define ANA_SERDES_CDR_BW_MASK 0x0003 735 #define ANA_MS_PAD_DBG 0x0004 736 #define ANA_SPEEDUP_DBG 0x0008 737 #define ANA_SERDES_TH_LOS_MASK 0x0030 738 #define ANA_SERDES_EN_DEEM 0x0040 739 #define ANA_SERDES_TXELECIDLE 0x0080 740 #define ANA_SERDES_BEACON 0x0100 741 #define ANA_SERDES_HALFTXDR 0x0200 742 #define ANA_SERDES_SEL_HSP 0x0400 743 #define ANA_SERDES_EN_PLL 0x0800 744 #define ANA_SERDES_EN 0x1000 745 #define ANA_SERDES_EN_LCKDT 0x2000 746 #define ANA_SERDES_CDR_BW_SHIFT 0 747 #define ANA_SERDES_TH_LOS_SHIFT 4 748 749 #define MII_ANA_CFG11 0x0B 750 #define ANA_PS_HIB_EN 0x8000 751 752 #define MII_ANA_CFG18 0x12 753 #define ANA_TEST_MODE_10BT_01MASK 0x0003 754 #define ANA_LOOP_SEL_10BT 0x0004 755 #define ANA_RGMII_MODE_SW 0x0008 756 #define ANA_EN_LONGECABLE 0x0010 757 #define ANA_TEST_MODE_10BT_2 0x0020 758 #define ANA_EN_10BT_IDLE 0x0400 759 #define ANA_EN_MASK_TB 0x0800 760 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 761 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 762 #define ANA_TEST_MODE_10BT_01SHIFT 0 763 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 764 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 765 766 #define MII_ANA_CFG41 0x29 767 #define ANA_TOP_PS_EN 0x8000 768 769 #define MII_ANA_CFG54 0x36 770 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 771 #define ANA_DESERVED 0x0040 772 #define ANA_EN_LIT_CH 0x0080 773 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 774 #define ANA_BP_BAD_LINK_ACCUM 0x4000 775 #define ANA_BP_SMALL_BW 0x8000 776 #define ANA_LONG_CABLE_TH_100_SHIFT 0 777 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 778 779 /* Statistics counters collected by the MAC. */ 780 struct smb { 781 /* Rx stats. */ 782 uint32_t rx_frames; 783 uint32_t rx_bcast_frames; 784 uint32_t rx_mcast_frames; 785 uint32_t rx_pause_frames; 786 uint32_t rx_control_frames; 787 uint32_t rx_crcerrs; 788 uint32_t rx_lenerrs; 789 uint32_t rx_bytes; 790 uint32_t rx_runts; 791 uint32_t rx_fragments; 792 uint32_t rx_pkts_64; 793 uint32_t rx_pkts_65_127; 794 uint32_t rx_pkts_128_255; 795 uint32_t rx_pkts_256_511; 796 uint32_t rx_pkts_512_1023; 797 uint32_t rx_pkts_1024_1518; 798 uint32_t rx_pkts_1519_max; 799 uint32_t rx_pkts_truncated; 800 uint32_t rx_fifo_oflows; 801 uint32_t rx_rrs_errs; 802 uint32_t rx_alignerrs; 803 uint32_t rx_bcast_bytes; 804 uint32_t rx_mcast_bytes; 805 uint32_t rx_pkts_filtered; 806 /* Tx stats. */ 807 uint32_t tx_frames; 808 uint32_t tx_bcast_frames; 809 uint32_t tx_mcast_frames; 810 uint32_t tx_pause_frames; 811 uint32_t tx_excess_defer; 812 uint32_t tx_control_frames; 813 uint32_t tx_deferred; 814 uint32_t tx_bytes; 815 uint32_t tx_pkts_64; 816 uint32_t tx_pkts_65_127; 817 uint32_t tx_pkts_128_255; 818 uint32_t tx_pkts_256_511; 819 uint32_t tx_pkts_512_1023; 820 uint32_t tx_pkts_1024_1518; 821 uint32_t tx_pkts_1519_max; 822 uint32_t tx_single_colls; 823 uint32_t tx_multi_colls; 824 uint32_t tx_late_colls; 825 uint32_t tx_excess_colls; 826 uint32_t tx_abort; 827 uint32_t tx_underrun; 828 uint32_t tx_desc_underrun; 829 uint32_t tx_lenerrs; 830 uint32_t tx_pkts_truncated; 831 uint32_t tx_bcast_bytes; 832 uint32_t tx_mcast_bytes; 833 uint32_t updated; 834 }; 835 836 /* CMB(Coalesing message block) */ 837 struct cmb { 838 uint32_t cons; 839 }; 840 841 /* Rx free descriptor */ 842 struct rx_desc { 843 uint64_t addr; 844 }; 845 846 /* Rx return descriptor */ 847 struct rx_rdesc { 848 uint32_t rdinfo; 849 #define RRD_CSUM_MASK 0x0000FFFF 850 #define RRD_RD_CNT_MASK 0x000F0000 851 #define RRD_RD_IDX_MASK 0xFFF00000 852 #define RRD_CSUM_SHIFT 0 853 #define RRD_RD_CNT_SHIFT 16 854 #define RRD_RD_IDX_SHIFT 20 855 #define RRD_CSUM(x) \ 856 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 857 #define RRD_RD_CNT(x) \ 858 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 859 #define RRD_RD_IDX(x) \ 860 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 861 uint32_t rss; 862 uint32_t vtag; 863 #define RRD_VLAN_MASK 0x0000FFFF 864 #define RRD_HEAD_LEN_MASK 0x00FF0000 865 #define RRD_HDS_MASK 0x03000000 866 #define RRD_HDS_NONE 0x00000000 867 #define RRD_HDS_HEAD 0x01000000 868 #define RRD_HDS_DATA 0x02000000 869 #define RRD_CPU_MASK 0x0C000000 870 #define RRD_HASH_FLAG_MASK 0xF0000000 871 #define RRD_VLAN_SHIFT 0 872 #define RRD_HEAD_LEN_SHIFT 16 873 #define RRD_HDS_SHIFT 24 874 #define RRD_CPU_SHIFT 26 875 #define RRD_HASH_FLAG_SHIFT 28 876 #define RRD_VLAN(x) \ 877 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 878 #define RRD_HEAD_LEN(x) \ 879 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 880 #define RRD_CPU(x) \ 881 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 882 uint32_t status; 883 #define RRD_LEN_MASK 0x00003FFF 884 #define RRD_LEN_SHIFT 0 885 #define RRD_TCP_UDPCSUM_NOK 0x00004000 886 #define RRD_IPCSUM_NOK 0x00008000 887 #define RRD_VLAN_TAG 0x00010000 888 #define RRD_PROTO_MASK 0x000E0000 889 #define RRD_PROTO_IPV4 0x00020000 890 #define RRD_PROTO_IPV6 0x000C0000 891 #define RRD_ERR_SUM 0x00100000 892 #define RRD_ERR_CRC 0x00200000 893 #define RRD_ERR_ALIGN 0x00400000 894 #define RRD_ERR_TRUNC 0x00800000 895 #define RRD_ERR_RUNT 0x01000000 896 #define RRD_ERR_ICMP 0x02000000 897 #define RRD_BCAST 0x04000000 898 #define RRD_MCAST 0x08000000 899 #define RRD_SNAP_LLC 0x10000000 900 #define RRD_ETHER 0x00000000 901 #define RRD_FIFO_FULL 0x20000000 902 #define RRD_ERR_LENGTH 0x40000000 903 #define RRD_VALID 0x80000000 904 #define RRD_BYTES(x) \ 905 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 906 #define RRD_IPV4(x) \ 907 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 908 }; 909 910 /* Tx descriptor */ 911 struct tx_desc { 912 uint32_t len; 913 #define TD_BUFLEN_MASK 0x00003FFF 914 #define TD_VLAN_MASK 0xFFFF0000 915 #define TD_BUFLEN_SHIFT 0 916 #define TX_BYTES(x) \ 917 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 918 #define TD_VLAN_SHIFT 16 919 uint32_t flags; 920 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 921 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 922 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 923 #define TD_CUSTOM_CSUM 0x00000100 924 #define TD_IPCSUM 0x00000200 925 #define TD_TCPCSUM 0x00000400 926 #define TD_UDPCSUM 0x00000800 927 #define TD_TSO 0x00001000 928 #define TD_TSO_DESCV1 0x00000000 929 #define TD_TSO_DESCV2 0x00002000 930 #define TD_CON_VLAN_TAG 0x00004000 931 #define TD_INS_VLAN_TAG 0x00008000 932 #define TD_IPV4_DESCV2 0x00010000 933 #define TD_LLC_SNAP 0x00020000 934 #define TD_ETHERNET 0x00000000 935 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 936 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 937 #define TD_MSS_MASK 0x7FFC0000 938 #define TD_EOP 0x80000000 939 #define TD_L4HDR_OFFSET_SHIFT 0 940 #define TD_TCPHDR_OFFSET_SHIFT 0 941 #define TD_PLOAD_OFFSET_SHIFT 0 942 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 943 #define TD_MSS_SHIFT 18 944 uint64_t addr; 945 }; 946 947 #endif /* _IF_ALCREG_H */ 948