1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/debugnet.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 96 /* 97 * The default value of msix_disable is 2, which means to decide whether to 98 * enable MSI-X in alc_attach() depending on the card type. The operator can 99 * set this to 0 or 1 to override the default. 100 */ 101 static int msix_disable = 2; 102 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 103 104 /* 105 * Devices supported by this driver. 106 */ 107 static struct alc_ident alc_ident_table[] = { 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 109 "Atheros AR8131 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 111 "Atheros AR8132 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 117 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 121 "Atheros AR8161 PCIe Gigabit Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 123 "Atheros AR8162 PCIe Fast Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 125 "Atheros AR8171 PCIe Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 127 "Atheros AR8172 PCIe Fast Ethernet" }, 128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 129 "Killer E2200 Gigabit Ethernet" }, 130 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 131 "Killer E2400 Gigabit Ethernet" }, 132 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 133 "Killer E2500 Gigabit Ethernet" }, 134 { 0, 0, 0, NULL} 135 }; 136 137 static void alc_aspm(struct alc_softc *, int, int); 138 static void alc_aspm_813x(struct alc_softc *, int); 139 static void alc_aspm_816x(struct alc_softc *, int); 140 static int alc_attach(device_t); 141 static int alc_check_boundary(struct alc_softc *); 142 static void alc_config_msi(struct alc_softc *); 143 static int alc_detach(device_t); 144 static void alc_disable_l0s_l1(struct alc_softc *); 145 static int alc_dma_alloc(struct alc_softc *); 146 static void alc_dma_free(struct alc_softc *); 147 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 148 static void alc_dsp_fixup(struct alc_softc *, int); 149 static int alc_encap(struct alc_softc *, struct mbuf **); 150 static struct alc_ident * 151 alc_find_ident(device_t); 152 #ifndef __NO_STRICT_ALIGNMENT 153 static struct mbuf * 154 alc_fixup_rx(if_t, struct mbuf *); 155 #endif 156 static void alc_get_macaddr(struct alc_softc *); 157 static void alc_get_macaddr_813x(struct alc_softc *); 158 static void alc_get_macaddr_816x(struct alc_softc *); 159 static void alc_get_macaddr_par(struct alc_softc *); 160 static void alc_init(void *); 161 static void alc_init_cmb(struct alc_softc *); 162 static void alc_init_locked(struct alc_softc *); 163 static void alc_init_rr_ring(struct alc_softc *); 164 static int alc_init_rx_ring(struct alc_softc *); 165 static void alc_init_smb(struct alc_softc *); 166 static void alc_init_tx_ring(struct alc_softc *); 167 static void alc_int_task(void *, int); 168 static int alc_intr(void *); 169 static int alc_ioctl(if_t, u_long, caddr_t); 170 static void alc_mac_config(struct alc_softc *); 171 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 172 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 173 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 174 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 175 static int alc_miibus_readreg(device_t, int, int); 176 static void alc_miibus_statchg(device_t); 177 static int alc_miibus_writereg(device_t, int, int, int); 178 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 179 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 180 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 181 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 182 static int alc_mediachange(if_t); 183 static int alc_mediachange_locked(struct alc_softc *); 184 static void alc_mediastatus(if_t, struct ifmediareq *); 185 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 186 static void alc_osc_reset(struct alc_softc *); 187 static void alc_phy_down(struct alc_softc *); 188 static void alc_phy_reset(struct alc_softc *); 189 static void alc_phy_reset_813x(struct alc_softc *); 190 static void alc_phy_reset_816x(struct alc_softc *); 191 static int alc_probe(device_t); 192 static void alc_reset(struct alc_softc *); 193 static int alc_resume(device_t); 194 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 195 static int alc_rxintr(struct alc_softc *, int); 196 static void alc_rxfilter(struct alc_softc *); 197 static void alc_rxvlan(struct alc_softc *); 198 static void alc_setlinkspeed(struct alc_softc *); 199 static void alc_setwol(struct alc_softc *); 200 static void alc_setwol_813x(struct alc_softc *); 201 static void alc_setwol_816x(struct alc_softc *); 202 static int alc_shutdown(device_t); 203 static void alc_start(if_t); 204 static void alc_start_locked(if_t); 205 static void alc_start_queue(struct alc_softc *); 206 static void alc_start_tx(struct alc_softc *); 207 static void alc_stats_clear(struct alc_softc *); 208 static void alc_stats_update(struct alc_softc *); 209 static void alc_stop(struct alc_softc *); 210 static void alc_stop_mac(struct alc_softc *); 211 static void alc_stop_queue(struct alc_softc *); 212 static int alc_suspend(device_t); 213 static void alc_sysctl_node(struct alc_softc *); 214 static void alc_tick(void *); 215 static void alc_txeof(struct alc_softc *); 216 static void alc_watchdog(struct alc_softc *); 217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 218 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 219 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 220 221 DEBUGNET_DEFINE(alc); 222 223 static device_method_t alc_methods[] = { 224 /* Device interface. */ 225 DEVMETHOD(device_probe, alc_probe), 226 DEVMETHOD(device_attach, alc_attach), 227 DEVMETHOD(device_detach, alc_detach), 228 DEVMETHOD(device_shutdown, alc_shutdown), 229 DEVMETHOD(device_suspend, alc_suspend), 230 DEVMETHOD(device_resume, alc_resume), 231 232 /* MII interface. */ 233 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 234 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 235 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 236 237 DEVMETHOD_END 238 }; 239 240 static driver_t alc_driver = { 241 "alc", 242 alc_methods, 243 sizeof(struct alc_softc) 244 }; 245 246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 247 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 248 nitems(alc_ident_table) - 1); 249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 250 251 static struct resource_spec alc_res_spec_mem[] = { 252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 253 { -1, 0, 0 } 254 }; 255 256 static struct resource_spec alc_irq_spec_legacy[] = { 257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 258 { -1, 0, 0 } 259 }; 260 261 static struct resource_spec alc_irq_spec_msi[] = { 262 { SYS_RES_IRQ, 1, RF_ACTIVE }, 263 { -1, 0, 0 } 264 }; 265 266 static struct resource_spec alc_irq_spec_msix[] = { 267 { SYS_RES_IRQ, 1, RF_ACTIVE }, 268 { -1, 0, 0 } 269 }; 270 271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 272 273 static int 274 alc_miibus_readreg(device_t dev, int phy, int reg) 275 { 276 struct alc_softc *sc; 277 int v; 278 279 sc = device_get_softc(dev); 280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 281 v = alc_mii_readreg_816x(sc, phy, reg); 282 else 283 v = alc_mii_readreg_813x(sc, phy, reg); 284 return (v); 285 } 286 287 static uint32_t 288 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 289 { 290 uint32_t v; 291 int i; 292 293 /* 294 * For AR8132 fast ethernet controller, do not report 1000baseT 295 * capability to mii(4). Even though AR8132 uses the same 296 * model/revision number of F1 gigabit PHY, the PHY has no 297 * ability to establish 1000baseT link. 298 */ 299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 300 reg == MII_EXTSR) 301 return (0); 302 303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 304 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 306 DELAY(5); 307 v = CSR_READ_4(sc, ALC_MDIO); 308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 309 break; 310 } 311 312 if (i == 0) { 313 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 314 return (0); 315 } 316 317 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 318 } 319 320 static uint32_t 321 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 322 { 323 uint32_t clk, v; 324 int i; 325 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 327 clk = MDIO_CLK_25_128; 328 else 329 clk = MDIO_CLK_25_4; 330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 331 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 333 DELAY(5); 334 v = CSR_READ_4(sc, ALC_MDIO); 335 if ((v & MDIO_OP_BUSY) == 0) 336 break; 337 } 338 339 if (i == 0) { 340 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 341 return (0); 342 } 343 344 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 345 } 346 347 static int 348 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 349 { 350 struct alc_softc *sc; 351 int v; 352 353 sc = device_get_softc(dev); 354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 355 v = alc_mii_writereg_816x(sc, phy, reg, val); 356 else 357 v = alc_mii_writereg_813x(sc, phy, reg, val); 358 return (v); 359 } 360 361 static uint32_t 362 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 363 { 364 uint32_t v; 365 int i; 366 367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 368 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 369 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 v = CSR_READ_4(sc, ALC_MDIO); 373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 374 break; 375 } 376 377 if (i == 0) 378 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 379 380 return (0); 381 } 382 383 static uint32_t 384 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 385 { 386 uint32_t clk, v; 387 int i; 388 389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 390 clk = MDIO_CLK_25_128; 391 else 392 clk = MDIO_CLK_25_4; 393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 394 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 395 MDIO_SUP_PREAMBLE | clk); 396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 397 DELAY(5); 398 v = CSR_READ_4(sc, ALC_MDIO); 399 if ((v & MDIO_OP_BUSY) == 0) 400 break; 401 } 402 403 if (i == 0) 404 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 405 406 return (0); 407 } 408 409 static void 410 alc_miibus_statchg(device_t dev) 411 { 412 struct alc_softc *sc; 413 struct mii_data *mii; 414 if_t ifp; 415 uint32_t reg; 416 417 sc = device_get_softc(dev); 418 419 mii = device_get_softc(sc->alc_miibus); 420 ifp = sc->alc_ifp; 421 if (mii == NULL || ifp == NULL || 422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 423 return; 424 425 sc->alc_flags &= ~ALC_FLAG_LINK; 426 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 427 (IFM_ACTIVE | IFM_AVALID)) { 428 switch (IFM_SUBTYPE(mii->mii_media_active)) { 429 case IFM_10_T: 430 case IFM_100_TX: 431 sc->alc_flags |= ALC_FLAG_LINK; 432 break; 433 case IFM_1000_T: 434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 435 sc->alc_flags |= ALC_FLAG_LINK; 436 break; 437 default: 438 break; 439 } 440 } 441 /* Stop Rx/Tx MACs. */ 442 alc_stop_mac(sc); 443 444 /* Program MACs with resolved speed/duplex/flow-control. */ 445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 446 alc_start_queue(sc); 447 alc_mac_config(sc); 448 /* Re-enable Tx/Rx MACs. */ 449 reg = CSR_READ_4(sc, ALC_MAC_CFG); 450 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 452 } 453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 454 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 455 } 456 457 static uint32_t 458 alc_miidbg_readreg(struct alc_softc *sc, int reg) 459 { 460 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 462 reg); 463 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA)); 465 } 466 467 static uint32_t 468 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 469 { 470 471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 472 reg); 473 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 474 ALC_MII_DBG_DATA, val)); 475 } 476 477 static uint32_t 478 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 479 { 480 uint32_t clk, v; 481 int i; 482 483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 484 EXT_MDIO_DEVADDR(devaddr)); 485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 486 clk = MDIO_CLK_25_128; 487 else 488 clk = MDIO_CLK_25_4; 489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 490 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 492 DELAY(5); 493 v = CSR_READ_4(sc, ALC_MDIO); 494 if ((v & MDIO_OP_BUSY) == 0) 495 break; 496 } 497 498 if (i == 0) { 499 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 500 devaddr, reg); 501 return (0); 502 } 503 504 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 505 } 506 507 static uint32_t 508 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 509 { 510 uint32_t clk, v; 511 int i; 512 513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 514 EXT_MDIO_DEVADDR(devaddr)); 515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 516 clk = MDIO_CLK_25_128; 517 else 518 clk = MDIO_CLK_25_4; 519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 520 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 521 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 523 DELAY(5); 524 v = CSR_READ_4(sc, ALC_MDIO); 525 if ((v & MDIO_OP_BUSY) == 0) 526 break; 527 } 528 529 if (i == 0) 530 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 531 devaddr, reg); 532 533 return (0); 534 } 535 536 static void 537 alc_dsp_fixup(struct alc_softc *sc, int media) 538 { 539 uint16_t agc, len, val; 540 541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 542 return; 543 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 544 return; 545 546 /* 547 * Vendor PHY magic. 548 * 1000BT/AZ, wrong cable length 549 */ 550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 551 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 552 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 553 EXT_CLDCTL6_CAB_LEN_MASK; 554 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 555 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 556 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 557 agc > DBG_AGC_LONG1G_LIMT) || 558 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 559 agc > DBG_AGC_LONG1G_LIMT)) { 560 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 561 DBG_AZ_ANADECT_LONG); 562 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 563 MII_EXT_ANEG_AFE); 564 val |= ANEG_AFEE_10BT_100M_TH; 565 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 566 val); 567 } else { 568 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 569 DBG_AZ_ANADECT_DEFAULT); 570 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 571 MII_EXT_ANEG_AFE); 572 val &= ~ANEG_AFEE_10BT_100M_TH; 573 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 574 val); 575 } 576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 577 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 578 if (media == IFM_1000_T) { 579 /* 580 * Giga link threshold, raise the tolerance of 581 * noise 50%. 582 */ 583 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 584 val &= ~DBG_MSE20DB_TH_MASK; 585 val |= (DBG_MSE20DB_TH_HI << 586 DBG_MSE20DB_TH_SHIFT); 587 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 588 } else if (media == IFM_100_TX) 589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 590 DBG_MSE16DB_UP); 591 } 592 } else { 593 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 594 val &= ~ANEG_AFEE_10BT_100M_TH; 595 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 597 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 598 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 599 DBG_MSE16DB_DOWN); 600 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 601 val &= ~DBG_MSE20DB_TH_MASK; 602 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 603 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 604 } 605 } 606 } 607 608 static void 609 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 610 { 611 struct alc_softc *sc; 612 struct mii_data *mii; 613 614 sc = if_getsoftc(ifp); 615 ALC_LOCK(sc); 616 if ((if_getflags(ifp) & IFF_UP) == 0) { 617 ALC_UNLOCK(sc); 618 return; 619 } 620 mii = device_get_softc(sc->alc_miibus); 621 622 mii_pollstat(mii); 623 ifmr->ifm_status = mii->mii_media_status; 624 ifmr->ifm_active = mii->mii_media_active; 625 ALC_UNLOCK(sc); 626 } 627 628 static int 629 alc_mediachange(if_t ifp) 630 { 631 struct alc_softc *sc; 632 int error; 633 634 sc = if_getsoftc(ifp); 635 ALC_LOCK(sc); 636 error = alc_mediachange_locked(sc); 637 ALC_UNLOCK(sc); 638 639 return (error); 640 } 641 642 static int 643 alc_mediachange_locked(struct alc_softc *sc) 644 { 645 struct mii_data *mii; 646 struct mii_softc *miisc; 647 int error; 648 649 ALC_LOCK_ASSERT(sc); 650 651 mii = device_get_softc(sc->alc_miibus); 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 PHY_RESET(miisc); 654 error = mii_mediachg(mii); 655 656 return (error); 657 } 658 659 static struct alc_ident * 660 alc_find_ident(device_t dev) 661 { 662 struct alc_ident *ident; 663 uint16_t vendor, devid; 664 665 vendor = pci_get_vendor(dev); 666 devid = pci_get_device(dev); 667 for (ident = alc_ident_table; ident->name != NULL; ident++) { 668 if (vendor == ident->vendorid && devid == ident->deviceid) 669 return (ident); 670 } 671 672 return (NULL); 673 } 674 675 static int 676 alc_probe(device_t dev) 677 { 678 struct alc_ident *ident; 679 680 ident = alc_find_ident(dev); 681 if (ident != NULL) { 682 device_set_desc(dev, ident->name); 683 return (BUS_PROBE_DEFAULT); 684 } 685 686 return (ENXIO); 687 } 688 689 static void 690 alc_get_macaddr(struct alc_softc *sc) 691 { 692 693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 694 alc_get_macaddr_816x(sc); 695 else 696 alc_get_macaddr_813x(sc); 697 } 698 699 static void 700 alc_get_macaddr_813x(struct alc_softc *sc) 701 { 702 uint32_t opt; 703 uint16_t val; 704 int eeprom, i; 705 706 eeprom = 0; 707 opt = CSR_READ_4(sc, ALC_OPT_CFG); 708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 710 /* 711 * EEPROM found, let TWSI reload EEPROM configuration. 712 * This will set ethernet address of controller. 713 */ 714 eeprom++; 715 switch (sc->alc_ident->deviceid) { 716 case DEVICEID_ATHEROS_AR8131: 717 case DEVICEID_ATHEROS_AR8132: 718 if ((opt & OPT_CFG_CLK_ENB) == 0) { 719 opt |= OPT_CFG_CLK_ENB; 720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 721 CSR_READ_4(sc, ALC_OPT_CFG); 722 DELAY(1000); 723 } 724 break; 725 case DEVICEID_ATHEROS_AR8151: 726 case DEVICEID_ATHEROS_AR8151_V2: 727 case DEVICEID_ATHEROS_AR8152_B: 728 case DEVICEID_ATHEROS_AR8152_B2: 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_ADDR, 0x00); 731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 732 ALC_MII_DBG_DATA); 733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 734 ALC_MII_DBG_DATA, val & 0xFF7F); 735 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 736 ALC_MII_DBG_ADDR, 0x3B); 737 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 738 ALC_MII_DBG_DATA); 739 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 740 ALC_MII_DBG_DATA, val | 0x0008); 741 DELAY(20); 742 break; 743 } 744 745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 748 CSR_READ_4(sc, ALC_WOL_CFG); 749 750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 751 TWSI_CFG_SW_LD_START); 752 for (i = 100; i > 0; i--) { 753 DELAY(1000); 754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 755 TWSI_CFG_SW_LD_START) == 0) 756 break; 757 } 758 if (i == 0) 759 device_printf(sc->alc_dev, 760 "reloading EEPROM timeout!\n"); 761 } else { 762 if (bootverbose) 763 device_printf(sc->alc_dev, "EEPROM not found!\n"); 764 } 765 if (eeprom != 0) { 766 switch (sc->alc_ident->deviceid) { 767 case DEVICEID_ATHEROS_AR8131: 768 case DEVICEID_ATHEROS_AR8132: 769 if ((opt & OPT_CFG_CLK_ENB) != 0) { 770 opt &= ~OPT_CFG_CLK_ENB; 771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 772 CSR_READ_4(sc, ALC_OPT_CFG); 773 DELAY(1000); 774 } 775 break; 776 case DEVICEID_ATHEROS_AR8151: 777 case DEVICEID_ATHEROS_AR8151_V2: 778 case DEVICEID_ATHEROS_AR8152_B: 779 case DEVICEID_ATHEROS_AR8152_B2: 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_ADDR, 0x00); 782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 783 ALC_MII_DBG_DATA); 784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 785 ALC_MII_DBG_DATA, val | 0x0080); 786 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x3B); 788 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA); 790 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 791 ALC_MII_DBG_DATA, val & 0xFFF7); 792 DELAY(20); 793 break; 794 } 795 } 796 797 alc_get_macaddr_par(sc); 798 } 799 800 static void 801 alc_get_macaddr_816x(struct alc_softc *sc) 802 { 803 uint32_t reg; 804 int i, reloaded; 805 806 reloaded = 0; 807 /* Try to reload station address via TWSI. */ 808 for (i = 100; i > 0; i--) { 809 reg = CSR_READ_4(sc, ALC_SLD); 810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 811 break; 812 DELAY(1000); 813 } 814 if (i != 0) { 815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 816 for (i = 100; i > 0; i--) { 817 DELAY(1000); 818 reg = CSR_READ_4(sc, ALC_SLD); 819 if ((reg & SLD_START) == 0) 820 break; 821 } 822 if (i != 0) 823 reloaded++; 824 else if (bootverbose) 825 device_printf(sc->alc_dev, 826 "reloading station address via TWSI timed out!\n"); 827 } 828 829 /* Try to reload station address from EEPROM or FLASH. */ 830 if (reloaded == 0) { 831 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 832 if ((reg & (EEPROM_LD_EEPROM_EXIST | 833 EEPROM_LD_FLASH_EXIST)) != 0) { 834 for (i = 100; i > 0; i--) { 835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 836 if ((reg & (EEPROM_LD_PROGRESS | 837 EEPROM_LD_START)) == 0) 838 break; 839 DELAY(1000); 840 } 841 if (i != 0) { 842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 843 EEPROM_LD_START); 844 for (i = 100; i > 0; i--) { 845 DELAY(1000); 846 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 847 if ((reg & EEPROM_LD_START) == 0) 848 break; 849 } 850 } else if (bootverbose) 851 device_printf(sc->alc_dev, 852 "reloading EEPROM/FLASH timed out!\n"); 853 } 854 } 855 856 alc_get_macaddr_par(sc); 857 } 858 859 static void 860 alc_get_macaddr_par(struct alc_softc *sc) 861 { 862 uint32_t ea[2]; 863 864 ea[0] = CSR_READ_4(sc, ALC_PAR0); 865 ea[1] = CSR_READ_4(sc, ALC_PAR1); 866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 872 } 873 874 static void 875 alc_disable_l0s_l1(struct alc_softc *sc) 876 { 877 uint32_t pmcfg; 878 879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 880 /* Another magic from vendor. */ 881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 882 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 883 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 884 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 885 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 886 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 888 } 889 } 890 891 static void 892 alc_phy_reset(struct alc_softc *sc) 893 { 894 895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 896 alc_phy_reset_816x(sc); 897 else 898 alc_phy_reset_813x(sc); 899 } 900 901 static void 902 alc_phy_reset_813x(struct alc_softc *sc) 903 { 904 uint16_t data; 905 906 /* Reset magic from Linux. */ 907 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 908 CSR_READ_2(sc, ALC_GPHY_CFG); 909 DELAY(10 * 1000); 910 911 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 912 GPHY_CFG_SEL_ANA_RESET); 913 CSR_READ_2(sc, ALC_GPHY_CFG); 914 DELAY(10 * 1000); 915 916 /* DSP fixup, Vendor magic. */ 917 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, 0x000A); 920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA); 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA, data & 0xDFFF); 924 } 925 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_ADDR, 0x003B); 931 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_DATA); 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_DATA, data & 0xFFF7); 935 DELAY(20 * 1000); 936 } 937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_ADDR, 0x0029); 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_DATA, 0x929D); 942 } 943 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 946 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_ADDR, 0x0029); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_DATA, 0xB6DD); 951 } 952 953 /* Load DSP codes, vendor magic. */ 954 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 955 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 957 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 959 ALC_MII_DBG_DATA, data); 960 961 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 962 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 963 ANA_SERDES_EN_LCKDT; 964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 965 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 967 ALC_MII_DBG_DATA, data); 968 969 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 970 ANA_LONG_CABLE_TH_100_MASK) | 971 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 972 ANA_SHORT_CABLE_TH_100_SHIFT) | 973 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_DATA, data); 978 979 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 980 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 981 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 982 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 984 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 986 ALC_MII_DBG_DATA, data); 987 988 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 989 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 990 ANA_OEN_125M; 991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 992 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 994 ALC_MII_DBG_DATA, data); 995 DELAY(1000); 996 997 /* Disable hibernation. */ 998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 999 0x0029); 1000 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1001 ALC_MII_DBG_DATA); 1002 data &= ~0x8000; 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1004 data); 1005 1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1007 0x000B); 1008 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1009 ALC_MII_DBG_DATA); 1010 data &= ~0x8000; 1011 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1012 data); 1013 } 1014 1015 static void 1016 alc_phy_reset_816x(struct alc_softc *sc) 1017 { 1018 uint32_t val; 1019 1020 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1021 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1022 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1023 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1024 val |= GPHY_CFG_SEL_ANA_RESET; 1025 #ifdef notyet 1026 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1027 #else 1028 /* Disable PHY hibernation. */ 1029 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1030 #endif 1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1032 DELAY(10); 1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1034 DELAY(800); 1035 1036 /* Vendor PHY magic. */ 1037 #ifdef notyet 1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1039 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1040 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1041 EXT_VDRVBIAS_DEFAULT); 1042 #else 1043 /* Disable PHY hibernation. */ 1044 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1045 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1046 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1047 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1048 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1049 #endif 1050 1051 /* XXX Disable EEE. */ 1052 val = CSR_READ_4(sc, ALC_LPI_CTL); 1053 val &= ~LPI_CTL_ENB; 1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1056 1057 /* PHY power saving. */ 1058 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1061 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1062 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1063 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1064 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1065 1066 /* RTL8139C, 120m issue. */ 1067 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1068 ANEG_NLP78_120M_DEFAULT); 1069 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1070 ANEG_S3DIG10_DEFAULT); 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1073 /* Turn off half amplitude. */ 1074 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1075 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1076 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1077 /* Turn off Green feature. */ 1078 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1079 val |= DBG_GREENCFG2_BP_GREEN; 1080 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1081 /* Turn off half bias. */ 1082 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1083 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1084 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1085 } 1086 } 1087 1088 static void 1089 alc_phy_down(struct alc_softc *sc) 1090 { 1091 uint32_t gphy; 1092 1093 switch (sc->alc_ident->deviceid) { 1094 case DEVICEID_ATHEROS_AR8161: 1095 case DEVICEID_ATHEROS_E2200: 1096 case DEVICEID_ATHEROS_E2400: 1097 case DEVICEID_ATHEROS_E2500: 1098 case DEVICEID_ATHEROS_AR8162: 1099 case DEVICEID_ATHEROS_AR8171: 1100 case DEVICEID_ATHEROS_AR8172: 1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1102 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1103 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1104 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1105 GPHY_CFG_SEL_ANA_RESET; 1106 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1108 break; 1109 case DEVICEID_ATHEROS_AR8151: 1110 case DEVICEID_ATHEROS_AR8151_V2: 1111 case DEVICEID_ATHEROS_AR8152_B: 1112 case DEVICEID_ATHEROS_AR8152_B2: 1113 /* 1114 * GPHY power down caused more problems on AR8151 v2.0. 1115 * When driver is reloaded after GPHY power down, 1116 * accesses to PHY/MAC registers hung the system. Only 1117 * cold boot recovered from it. I'm not sure whether 1118 * AR8151 v1.0 also requires this one though. I don't 1119 * have AR8151 v1.0 controller in hand. 1120 * The only option left is to isolate the PHY and 1121 * initiates power down the PHY which in turn saves 1122 * more power when driver is unloaded. 1123 */ 1124 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1125 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1126 break; 1127 default: 1128 /* Force PHY down. */ 1129 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1130 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1131 GPHY_CFG_PWDOWN_HW); 1132 DELAY(1000); 1133 break; 1134 } 1135 } 1136 1137 static void 1138 alc_aspm(struct alc_softc *sc, int init, int media) 1139 { 1140 1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1142 alc_aspm_816x(sc, init); 1143 else 1144 alc_aspm_813x(sc, media); 1145 } 1146 1147 static void 1148 alc_aspm_813x(struct alc_softc *sc, int media) 1149 { 1150 uint32_t pmcfg; 1151 uint16_t linkcfg; 1152 1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1154 return; 1155 1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1157 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1158 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1159 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1160 PCIER_LINK_CTL); 1161 else 1162 linkcfg = 0; 1163 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1164 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1165 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1166 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1167 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1168 1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1170 /* Disable extended sync except AR8152 B v1.0 */ 1171 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1173 sc->alc_rev == ATHEROS_AR8152_B_V10) 1174 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1175 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1176 linkcfg); 1177 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1178 PM_CFG_HOTRST); 1179 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1180 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1181 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1182 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1183 PM_CFG_PM_REQ_TIMER_SHIFT); 1184 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1185 } 1186 1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1189 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1191 pmcfg |= PM_CFG_ASPM_L1_ENB; 1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1193 if (sc->alc_ident->deviceid == 1194 DEVICEID_ATHEROS_AR8152_B) 1195 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1196 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1197 PM_CFG_SERDES_PLL_L1_ENB | 1198 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1199 pmcfg |= PM_CFG_CLK_SWH_L1; 1200 if (media == IFM_100_TX || media == IFM_1000_T) { 1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1202 switch (sc->alc_ident->deviceid) { 1203 case DEVICEID_ATHEROS_AR8152_B: 1204 pmcfg |= (7 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 case DEVICEID_ATHEROS_AR8152_B2: 1208 case DEVICEID_ATHEROS_AR8151_V2: 1209 pmcfg |= (4 << 1210 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1211 break; 1212 default: 1213 pmcfg |= (15 << 1214 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1215 break; 1216 } 1217 } 1218 } else { 1219 pmcfg |= PM_CFG_SERDES_L1_ENB | 1220 PM_CFG_SERDES_PLL_L1_ENB | 1221 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1222 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1223 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1224 } 1225 } else { 1226 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1227 PM_CFG_SERDES_PLL_L1_ENB); 1228 pmcfg |= PM_CFG_CLK_SWH_L1; 1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1230 pmcfg |= PM_CFG_ASPM_L1_ENB; 1231 } 1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1233 } 1234 1235 static void 1236 alc_aspm_816x(struct alc_softc *sc, int init) 1237 { 1238 uint32_t pmcfg; 1239 1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1241 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1242 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1243 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1244 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1245 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1246 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1247 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1248 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1249 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1250 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1251 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1252 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1253 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1254 (sc->alc_rev & 0x01) != 0) 1255 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1257 /* Link up, enable both L0s, L1s. */ 1258 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1259 PM_CFG_MAC_ASPM_CHK; 1260 } else { 1261 if (init != 0) 1262 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1263 PM_CFG_MAC_ASPM_CHK; 1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1265 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1266 } 1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1268 } 1269 1270 static void 1271 alc_init_pcie(struct alc_softc *sc) 1272 { 1273 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1274 uint32_t cap, ctl, val; 1275 int state; 1276 1277 /* Clear data link and flow-control protocol error. */ 1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1279 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1281 1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1287 PCIE_PHYMISC_FORCE_RCV_DET); 1288 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1289 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1291 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1292 PCIE_PHYMISC2_SERDES_TH_MASK); 1293 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1294 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1296 } 1297 /* Disable ASPM L0S and L1. */ 1298 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1300 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1302 sc->alc_rcb = DMA_CFG_RCB_128; 1303 if (bootverbose) 1304 device_printf(sc->alc_dev, "RCB %u bytes\n", 1305 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1306 state = ctl & PCIEM_LINK_CTL_ASPMC; 1307 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1308 sc->alc_flags |= ALC_FLAG_L0S; 1309 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1310 sc->alc_flags |= ALC_FLAG_L1S; 1311 if (bootverbose) 1312 device_printf(sc->alc_dev, "ASPM %s %s\n", 1313 aspm_state[state], 1314 state == 0 ? "disabled" : "enabled"); 1315 alc_disable_l0s_l1(sc); 1316 } else { 1317 if (bootverbose) 1318 device_printf(sc->alc_dev, 1319 "no ASPM support\n"); 1320 } 1321 } else { 1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1323 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1325 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1326 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1327 (sc->alc_rev & 0x01) != 0) { 1328 if ((val & MASTER_WAKEN_25M) == 0 || 1329 (val & MASTER_CLK_SEL_DIS) == 0) { 1330 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1332 } 1333 } else { 1334 if ((val & MASTER_WAKEN_25M) == 0 || 1335 (val & MASTER_CLK_SEL_DIS) != 0) { 1336 val |= MASTER_WAKEN_25M; 1337 val &= ~MASTER_CLK_SEL_DIS; 1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1339 } 1340 } 1341 } 1342 alc_aspm(sc, 1, IFM_UNKNOWN); 1343 } 1344 1345 static void 1346 alc_config_msi(struct alc_softc *sc) 1347 { 1348 uint32_t ctl, mod; 1349 1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1351 /* 1352 * It seems interrupt moderation is controlled by 1353 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1354 * Driver uses RX interrupt moderation parameter to 1355 * program ALC_MSI_RETRANS_TIMER register. 1356 */ 1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1358 ctl &= ~MSI_RETRANS_TIMER_MASK; 1359 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1360 mod = ALC_USECS(sc->alc_int_rx_mod); 1361 if (mod == 0) 1362 mod = 1; 1363 ctl |= mod; 1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_STD); 1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1369 MSI_RETRANS_MASK_SEL_LINE); 1370 else 1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1372 } 1373 } 1374 1375 static int 1376 alc_attach(device_t dev) 1377 { 1378 struct alc_softc *sc; 1379 if_t ifp; 1380 int base, error, i, msic, msixc; 1381 uint16_t burst; 1382 1383 error = 0; 1384 sc = device_get_softc(dev); 1385 sc->alc_dev = dev; 1386 sc->alc_rev = pci_get_revid(dev); 1387 1388 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1389 MTX_DEF); 1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1392 sc->alc_ident = alc_find_ident(dev); 1393 1394 /* Map the device. */ 1395 pci_enable_busmaster(dev); 1396 sc->alc_res_spec = alc_res_spec_mem; 1397 sc->alc_irq_spec = alc_irq_spec_legacy; 1398 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1399 if (error != 0) { 1400 device_printf(dev, "cannot allocate memory resources.\n"); 1401 goto fail; 1402 } 1403 1404 /* Set PHY address. */ 1405 sc->alc_phyaddr = ALC_PHY_ADDR; 1406 1407 /* 1408 * One odd thing is AR8132 uses the same PHY hardware(F1 1409 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1410 * the PHY supports 1000Mbps but that's not true. The PHY 1411 * used in AR8132 can't establish gigabit link even if it 1412 * shows the same PHY model/revision number of AR8131. 1413 */ 1414 switch (sc->alc_ident->deviceid) { 1415 case DEVICEID_ATHEROS_E2200: 1416 case DEVICEID_ATHEROS_E2400: 1417 case DEVICEID_ATHEROS_E2500: 1418 sc->alc_flags |= ALC_FLAG_E2X00; 1419 1420 /* 1421 * Disable MSI-X by default on Killer devices, since this is 1422 * reported by several users to not work well. 1423 */ 1424 if (msix_disable == 2) 1425 msix_disable = 1; 1426 1427 /* FALLTHROUGH */ 1428 case DEVICEID_ATHEROS_AR8161: 1429 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1431 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8171: 1434 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1435 break; 1436 case DEVICEID_ATHEROS_AR8162: 1437 case DEVICEID_ATHEROS_AR8172: 1438 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1439 break; 1440 case DEVICEID_ATHEROS_AR8152_B: 1441 case DEVICEID_ATHEROS_AR8152_B2: 1442 sc->alc_flags |= ALC_FLAG_APS; 1443 /* FALLTHROUGH */ 1444 case DEVICEID_ATHEROS_AR8132: 1445 sc->alc_flags |= ALC_FLAG_FASTETHER; 1446 break; 1447 case DEVICEID_ATHEROS_AR8151: 1448 case DEVICEID_ATHEROS_AR8151_V2: 1449 sc->alc_flags |= ALC_FLAG_APS; 1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1451 sc->alc_flags |= ALC_FLAG_MT; 1452 /* FALLTHROUGH */ 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * The default value of msix_disable is 2, which means auto-detect. If 1459 * we didn't auto-detect it, default to enabling it. 1460 */ 1461 if (msix_disable == 2) 1462 msix_disable = 0; 1463 1464 sc->alc_flags |= ALC_FLAG_JUMBO; 1465 1466 /* 1467 * It seems that AR813x/AR815x has silicon bug for SMB. In 1468 * addition, Atheros said that enabling SMB wouldn't improve 1469 * performance. However I think it's bad to access lots of 1470 * registers to extract MAC statistics. 1471 */ 1472 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1473 /* 1474 * Don't use Tx CMB. It is known to have silicon bug. 1475 */ 1476 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1478 MASTER_CHIP_REV_SHIFT; 1479 if (bootverbose) { 1480 device_printf(dev, "PCI device revision : 0x%04x\n", 1481 sc->alc_rev); 1482 device_printf(dev, "Chip id/revision : 0x%04x\n", 1483 sc->alc_chip_rev); 1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1485 device_printf(dev, "AR816x revision : 0x%x\n", 1486 AR816X_REV(sc->alc_rev)); 1487 } 1488 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1491 1492 /* Initialize DMA parameters. */ 1493 sc->alc_dma_rd_burst = 0; 1494 sc->alc_dma_wr_burst = 0; 1495 sc->alc_rcb = DMA_CFG_RCB_64; 1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1497 sc->alc_flags |= ALC_FLAG_PCIE; 1498 sc->alc_expcap = base; 1499 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1500 sc->alc_dma_rd_burst = 1501 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1502 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1503 if (bootverbose) { 1504 device_printf(dev, "Read request size : %u bytes.\n", 1505 alc_dma_burst[sc->alc_dma_rd_burst]); 1506 device_printf(dev, "TLP payload size : %u bytes.\n", 1507 alc_dma_burst[sc->alc_dma_wr_burst]); 1508 } 1509 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1510 sc->alc_dma_rd_burst = 3; 1511 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1512 sc->alc_dma_wr_burst = 3; 1513 /* 1514 * Force maximum payload size to 128 bytes for 1515 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1516 * Otherwise it triggers DMA write error. 1517 */ 1518 if ((sc->alc_flags & 1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1520 sc->alc_dma_wr_burst = 0; 1521 alc_init_pcie(sc); 1522 } 1523 1524 /* Reset PHY. */ 1525 alc_phy_reset(sc); 1526 1527 /* Reset the ethernet controller. */ 1528 alc_stop_mac(sc); 1529 alc_reset(sc); 1530 1531 /* Allocate IRQ resources. */ 1532 msixc = pci_msix_count(dev); 1533 msic = pci_msi_count(dev); 1534 if (bootverbose) { 1535 device_printf(dev, "MSIX count : %d\n", msixc); 1536 device_printf(dev, "MSI count : %d\n", msic); 1537 } 1538 if (msixc > 1) 1539 msixc = 1; 1540 if (msic > 1) 1541 msic = 1; 1542 /* 1543 * Prefer MSIX over MSI. 1544 * AR816x controller has a silicon bug that MSI interrupt 1545 * does not assert if PCIM_CMD_INTxDIS bit of command 1546 * register is set. pci(4) was taught to handle that case. 1547 */ 1548 if (msix_disable == 0 || msi_disable == 0) { 1549 if (msix_disable == 0 && msixc > 0 && 1550 pci_alloc_msix(dev, &msixc) == 0) { 1551 if (msic == 1) { 1552 device_printf(dev, 1553 "Using %d MSIX message(s).\n", msixc); 1554 sc->alc_flags |= ALC_FLAG_MSIX; 1555 sc->alc_irq_spec = alc_irq_spec_msix; 1556 } else 1557 pci_release_msi(dev); 1558 } 1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1561 if (msic == 1) { 1562 device_printf(dev, 1563 "Using %d MSI message(s).\n", msic); 1564 sc->alc_flags |= ALC_FLAG_MSI; 1565 sc->alc_irq_spec = alc_irq_spec_msi; 1566 } else 1567 pci_release_msi(dev); 1568 } 1569 } 1570 1571 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1572 if (error != 0) { 1573 device_printf(dev, "cannot allocate IRQ resources.\n"); 1574 goto fail; 1575 } 1576 1577 /* Create device sysctl node. */ 1578 alc_sysctl_node(sc); 1579 1580 if ((error = alc_dma_alloc(sc)) != 0) 1581 goto fail; 1582 1583 /* Load station address. */ 1584 alc_get_macaddr(sc); 1585 1586 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1587 if_setsoftc(ifp, sc); 1588 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1589 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1590 if_setioctlfn(ifp, alc_ioctl); 1591 if_setstartfn(ifp, alc_start); 1592 if_setinitfn(ifp, alc_init); 1593 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1594 if_setsendqready(ifp); 1595 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1596 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1597 if (pci_has_pm(dev)) { 1598 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1599 sc->alc_flags |= ALC_FLAG_PM; 1600 } 1601 if_setcapenable(ifp, if_getcapabilities(ifp)); 1602 1603 /* Set up MII bus. */ 1604 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1605 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1606 MIIF_DOPAUSE); 1607 if (error != 0) { 1608 device_printf(dev, "attaching PHYs failed\n"); 1609 goto fail; 1610 } 1611 1612 ether_ifattach(ifp, sc->alc_eaddr); 1613 1614 /* VLAN capability setup. */ 1615 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1616 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1617 if_setcapenable(ifp, if_getcapabilities(ifp)); 1618 /* 1619 * XXX 1620 * It seems enabling Tx checksum offloading makes more trouble. 1621 * Sometimes the controller does not receive any frames when 1622 * Tx checksum offloading is enabled. I'm not sure whether this 1623 * is a bug in Tx checksum offloading logic or I got broken 1624 * sample boards. To safety, don't enable Tx checksum offloading 1625 * by default but give chance to users to toggle it if they know 1626 * their controllers work without problems. 1627 * Fortunately, Tx checksum offloading for AR816x family 1628 * seems to work. 1629 */ 1630 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1631 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1632 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1633 } 1634 1635 /* Tell the upper layer(s) we support long frames. */ 1636 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1637 1638 /* Create local taskq. */ 1639 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1640 taskqueue_thread_enqueue, &sc->alc_tq); 1641 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1642 device_get_nameunit(sc->alc_dev)); 1643 1644 alc_config_msi(sc); 1645 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1646 msic = ALC_MSIX_MESSAGES; 1647 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1648 msic = ALC_MSI_MESSAGES; 1649 else 1650 msic = 1; 1651 for (i = 0; i < msic; i++) { 1652 error = bus_setup_intr(dev, sc->alc_irq[i], 1653 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1654 &sc->alc_intrhand[i]); 1655 if (error != 0) 1656 break; 1657 } 1658 if (error != 0) { 1659 device_printf(dev, "could not set up interrupt handler.\n"); 1660 taskqueue_free(sc->alc_tq); 1661 sc->alc_tq = NULL; 1662 ether_ifdetach(ifp); 1663 goto fail; 1664 } 1665 1666 /* Attach driver debugnet methods. */ 1667 DEBUGNET_SET(ifp, alc); 1668 1669 fail: 1670 if (error != 0) 1671 alc_detach(dev); 1672 1673 return (error); 1674 } 1675 1676 static int 1677 alc_detach(device_t dev) 1678 { 1679 struct alc_softc *sc; 1680 if_t ifp; 1681 int i, msic; 1682 1683 sc = device_get_softc(dev); 1684 1685 ifp = sc->alc_ifp; 1686 if (device_is_attached(dev)) { 1687 ether_ifdetach(ifp); 1688 ALC_LOCK(sc); 1689 alc_stop(sc); 1690 ALC_UNLOCK(sc); 1691 callout_drain(&sc->alc_tick_ch); 1692 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1693 } 1694 1695 if (sc->alc_tq != NULL) { 1696 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1697 taskqueue_free(sc->alc_tq); 1698 sc->alc_tq = NULL; 1699 } 1700 1701 bus_generic_detach(dev); 1702 alc_dma_free(sc); 1703 1704 if (ifp != NULL) { 1705 if_free(ifp); 1706 sc->alc_ifp = NULL; 1707 } 1708 1709 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1710 msic = ALC_MSIX_MESSAGES; 1711 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1712 msic = ALC_MSI_MESSAGES; 1713 else 1714 msic = 1; 1715 for (i = 0; i < msic; i++) { 1716 if (sc->alc_intrhand[i] != NULL) { 1717 bus_teardown_intr(dev, sc->alc_irq[i], 1718 sc->alc_intrhand[i]); 1719 sc->alc_intrhand[i] = NULL; 1720 } 1721 } 1722 if (sc->alc_res[0] != NULL) 1723 alc_phy_down(sc); 1724 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1725 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1726 pci_release_msi(dev); 1727 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1728 mtx_destroy(&sc->alc_mtx); 1729 1730 return (0); 1731 } 1732 1733 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1734 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1735 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1736 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1737 1738 static void 1739 alc_sysctl_node(struct alc_softc *sc) 1740 { 1741 struct sysctl_ctx_list *ctx; 1742 struct sysctl_oid_list *child, *parent; 1743 struct sysctl_oid *tree; 1744 struct alc_hw_stats *stats; 1745 int error; 1746 1747 stats = &sc->alc_stats; 1748 ctx = device_get_sysctl_ctx(sc->alc_dev); 1749 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1750 1751 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1752 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1753 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1754 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1755 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1756 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1757 /* Pull in device tunables. */ 1758 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1759 error = resource_int_value(device_get_name(sc->alc_dev), 1760 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1761 if (error == 0) { 1762 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1763 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1764 device_printf(sc->alc_dev, "int_rx_mod value out of " 1765 "range; using default: %d\n", 1766 ALC_IM_RX_TIMER_DEFAULT); 1767 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1768 } 1769 } 1770 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1771 error = resource_int_value(device_get_name(sc->alc_dev), 1772 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1773 if (error == 0) { 1774 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1775 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1776 device_printf(sc->alc_dev, "int_tx_mod value out of " 1777 "range; using default: %d\n", 1778 ALC_IM_TX_TIMER_DEFAULT); 1779 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1780 } 1781 } 1782 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1783 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1784 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1785 "max number of Rx events to process"); 1786 /* Pull in device tunables. */ 1787 sc->alc_process_limit = ALC_PROC_DEFAULT; 1788 error = resource_int_value(device_get_name(sc->alc_dev), 1789 device_get_unit(sc->alc_dev), "process_limit", 1790 &sc->alc_process_limit); 1791 if (error == 0) { 1792 if (sc->alc_process_limit < ALC_PROC_MIN || 1793 sc->alc_process_limit > ALC_PROC_MAX) { 1794 device_printf(sc->alc_dev, 1795 "process_limit value out of range; " 1796 "using default: %d\n", ALC_PROC_DEFAULT); 1797 sc->alc_process_limit = ALC_PROC_DEFAULT; 1798 } 1799 } 1800 1801 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1802 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1803 parent = SYSCTL_CHILDREN(tree); 1804 1805 /* Rx statistics. */ 1806 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1807 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1808 child = SYSCTL_CHILDREN(tree); 1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1810 &stats->rx_frames, "Good frames"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1812 &stats->rx_bcast_frames, "Good broadcast frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1814 &stats->rx_mcast_frames, "Good multicast frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1816 &stats->rx_pause_frames, "Pause control frames"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1818 &stats->rx_control_frames, "Control frames"); 1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1820 &stats->rx_crcerrs, "CRC errors"); 1821 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1822 &stats->rx_lenerrs, "Frames with length mismatched"); 1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1824 &stats->rx_bytes, "Good octets"); 1825 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1826 &stats->rx_bcast_bytes, "Good broadcast octets"); 1827 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1828 &stats->rx_mcast_bytes, "Good multicast octets"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1830 &stats->rx_runts, "Too short frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1832 &stats->rx_fragments, "Fragmented frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1834 &stats->rx_pkts_64, "64 bytes frames"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1836 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1838 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1840 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1842 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1844 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1846 &stats->rx_pkts_1519_max, "1519 to max frames"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1848 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1850 &stats->rx_fifo_oflows, "FIFO overflows"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1852 &stats->rx_rrs_errs, "Return status write-back errors"); 1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1854 &stats->rx_alignerrs, "Alignment errors"); 1855 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1856 &stats->rx_pkts_filtered, 1857 "Frames dropped due to address filtering"); 1858 1859 /* Tx statistics. */ 1860 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1861 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1862 child = SYSCTL_CHILDREN(tree); 1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1864 &stats->tx_frames, "Good frames"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1866 &stats->tx_bcast_frames, "Good broadcast frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1868 &stats->tx_mcast_frames, "Good multicast frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1870 &stats->tx_pause_frames, "Pause control frames"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1872 &stats->tx_control_frames, "Control frames"); 1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1874 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1875 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1876 &stats->tx_excess_defer, "Frames with derferrals"); 1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1878 &stats->tx_bytes, "Good octets"); 1879 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1880 &stats->tx_bcast_bytes, "Good broadcast octets"); 1881 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1882 &stats->tx_mcast_bytes, "Good multicast octets"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1884 &stats->tx_pkts_64, "64 bytes frames"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1886 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1888 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1890 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1892 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1894 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1896 &stats->tx_pkts_1519_max, "1519 to max frames"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1898 &stats->tx_single_colls, "Single collisions"); 1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1900 &stats->tx_multi_colls, "Multiple collisions"); 1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1902 &stats->tx_late_colls, "Late collisions"); 1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1904 &stats->tx_excess_colls, "Excessive collisions"); 1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1906 &stats->tx_underrun, "FIFO underruns"); 1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1908 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1909 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1910 &stats->tx_lenerrs, "Frames with length mismatched"); 1911 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1912 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1913 } 1914 1915 #undef ALC_SYSCTL_STAT_ADD32 1916 #undef ALC_SYSCTL_STAT_ADD64 1917 1918 struct alc_dmamap_arg { 1919 bus_addr_t alc_busaddr; 1920 }; 1921 1922 static void 1923 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1924 { 1925 struct alc_dmamap_arg *ctx; 1926 1927 if (error != 0) 1928 return; 1929 1930 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1931 1932 ctx = (struct alc_dmamap_arg *)arg; 1933 ctx->alc_busaddr = segs[0].ds_addr; 1934 } 1935 1936 /* 1937 * Normal and high Tx descriptors shares single Tx high address. 1938 * Four Rx descriptor/return rings and CMB shares the same Rx 1939 * high address. 1940 */ 1941 static int 1942 alc_check_boundary(struct alc_softc *sc) 1943 { 1944 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1945 1946 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1947 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1948 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1949 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1950 1951 /* 4GB boundary crossing is not allowed. */ 1952 if ((ALC_ADDR_HI(rx_ring_end) != 1953 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1954 (ALC_ADDR_HI(rr_ring_end) != 1955 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1956 (ALC_ADDR_HI(cmb_end) != 1957 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1958 (ALC_ADDR_HI(tx_ring_end) != 1959 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1960 return (EFBIG); 1961 /* 1962 * Make sure Rx return descriptor/Rx descriptor/CMB use 1963 * the same high address. 1964 */ 1965 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1966 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1967 return (EFBIG); 1968 1969 return (0); 1970 } 1971 1972 static int 1973 alc_dma_alloc(struct alc_softc *sc) 1974 { 1975 struct alc_txdesc *txd; 1976 struct alc_rxdesc *rxd; 1977 bus_addr_t lowaddr; 1978 struct alc_dmamap_arg ctx; 1979 int error, i; 1980 1981 lowaddr = BUS_SPACE_MAXADDR; 1982 if (sc->alc_flags & ALC_FLAG_MT) 1983 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1984 again: 1985 /* Create parent DMA tag. */ 1986 error = bus_dma_tag_create( 1987 bus_get_dma_tag(sc->alc_dev), /* parent */ 1988 1, 0, /* alignment, boundary */ 1989 lowaddr, /* lowaddr */ 1990 BUS_SPACE_MAXADDR, /* highaddr */ 1991 NULL, NULL, /* filter, filterarg */ 1992 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1993 0, /* nsegments */ 1994 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1995 0, /* flags */ 1996 NULL, NULL, /* lockfunc, lockarg */ 1997 &sc->alc_cdata.alc_parent_tag); 1998 if (error != 0) { 1999 device_printf(sc->alc_dev, 2000 "could not create parent DMA tag.\n"); 2001 goto fail; 2002 } 2003 2004 /* Create DMA tag for Tx descriptor ring. */ 2005 error = bus_dma_tag_create( 2006 sc->alc_cdata.alc_parent_tag, /* parent */ 2007 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2008 BUS_SPACE_MAXADDR, /* lowaddr */ 2009 BUS_SPACE_MAXADDR, /* highaddr */ 2010 NULL, NULL, /* filter, filterarg */ 2011 ALC_TX_RING_SZ, /* maxsize */ 2012 1, /* nsegments */ 2013 ALC_TX_RING_SZ, /* maxsegsize */ 2014 0, /* flags */ 2015 NULL, NULL, /* lockfunc, lockarg */ 2016 &sc->alc_cdata.alc_tx_ring_tag); 2017 if (error != 0) { 2018 device_printf(sc->alc_dev, 2019 "could not create Tx ring DMA tag.\n"); 2020 goto fail; 2021 } 2022 2023 /* Create DMA tag for Rx free descriptor ring. */ 2024 error = bus_dma_tag_create( 2025 sc->alc_cdata.alc_parent_tag, /* parent */ 2026 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2027 BUS_SPACE_MAXADDR, /* lowaddr */ 2028 BUS_SPACE_MAXADDR, /* highaddr */ 2029 NULL, NULL, /* filter, filterarg */ 2030 ALC_RX_RING_SZ, /* maxsize */ 2031 1, /* nsegments */ 2032 ALC_RX_RING_SZ, /* maxsegsize */ 2033 0, /* flags */ 2034 NULL, NULL, /* lockfunc, lockarg */ 2035 &sc->alc_cdata.alc_rx_ring_tag); 2036 if (error != 0) { 2037 device_printf(sc->alc_dev, 2038 "could not create Rx ring DMA tag.\n"); 2039 goto fail; 2040 } 2041 /* Create DMA tag for Rx return descriptor ring. */ 2042 error = bus_dma_tag_create( 2043 sc->alc_cdata.alc_parent_tag, /* parent */ 2044 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2045 BUS_SPACE_MAXADDR, /* lowaddr */ 2046 BUS_SPACE_MAXADDR, /* highaddr */ 2047 NULL, NULL, /* filter, filterarg */ 2048 ALC_RR_RING_SZ, /* maxsize */ 2049 1, /* nsegments */ 2050 ALC_RR_RING_SZ, /* maxsegsize */ 2051 0, /* flags */ 2052 NULL, NULL, /* lockfunc, lockarg */ 2053 &sc->alc_cdata.alc_rr_ring_tag); 2054 if (error != 0) { 2055 device_printf(sc->alc_dev, 2056 "could not create Rx return ring DMA tag.\n"); 2057 goto fail; 2058 } 2059 2060 /* Create DMA tag for coalescing message block. */ 2061 error = bus_dma_tag_create( 2062 sc->alc_cdata.alc_parent_tag, /* parent */ 2063 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2064 BUS_SPACE_MAXADDR, /* lowaddr */ 2065 BUS_SPACE_MAXADDR, /* highaddr */ 2066 NULL, NULL, /* filter, filterarg */ 2067 ALC_CMB_SZ, /* maxsize */ 2068 1, /* nsegments */ 2069 ALC_CMB_SZ, /* maxsegsize */ 2070 0, /* flags */ 2071 NULL, NULL, /* lockfunc, lockarg */ 2072 &sc->alc_cdata.alc_cmb_tag); 2073 if (error != 0) { 2074 device_printf(sc->alc_dev, 2075 "could not create CMB DMA tag.\n"); 2076 goto fail; 2077 } 2078 /* Create DMA tag for status message block. */ 2079 error = bus_dma_tag_create( 2080 sc->alc_cdata.alc_parent_tag, /* parent */ 2081 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2082 BUS_SPACE_MAXADDR, /* lowaddr */ 2083 BUS_SPACE_MAXADDR, /* highaddr */ 2084 NULL, NULL, /* filter, filterarg */ 2085 ALC_SMB_SZ, /* maxsize */ 2086 1, /* nsegments */ 2087 ALC_SMB_SZ, /* maxsegsize */ 2088 0, /* flags */ 2089 NULL, NULL, /* lockfunc, lockarg */ 2090 &sc->alc_cdata.alc_smb_tag); 2091 if (error != 0) { 2092 device_printf(sc->alc_dev, 2093 "could not create SMB DMA tag.\n"); 2094 goto fail; 2095 } 2096 2097 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2098 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2099 (void **)&sc->alc_rdata.alc_tx_ring, 2100 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2101 &sc->alc_cdata.alc_tx_ring_map); 2102 if (error != 0) { 2103 device_printf(sc->alc_dev, 2104 "could not allocate DMA'able memory for Tx ring.\n"); 2105 goto fail; 2106 } 2107 ctx.alc_busaddr = 0; 2108 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2109 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2110 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2111 if (error != 0 || ctx.alc_busaddr == 0) { 2112 device_printf(sc->alc_dev, 2113 "could not load DMA'able memory for Tx ring.\n"); 2114 goto fail; 2115 } 2116 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2117 2118 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2119 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2120 (void **)&sc->alc_rdata.alc_rx_ring, 2121 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2122 &sc->alc_cdata.alc_rx_ring_map); 2123 if (error != 0) { 2124 device_printf(sc->alc_dev, 2125 "could not allocate DMA'able memory for Rx ring.\n"); 2126 goto fail; 2127 } 2128 ctx.alc_busaddr = 0; 2129 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2130 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2131 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2132 if (error != 0 || ctx.alc_busaddr == 0) { 2133 device_printf(sc->alc_dev, 2134 "could not load DMA'able memory for Rx ring.\n"); 2135 goto fail; 2136 } 2137 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2138 2139 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2140 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2141 (void **)&sc->alc_rdata.alc_rr_ring, 2142 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2143 &sc->alc_cdata.alc_rr_ring_map); 2144 if (error != 0) { 2145 device_printf(sc->alc_dev, 2146 "could not allocate DMA'able memory for Rx return ring.\n"); 2147 goto fail; 2148 } 2149 ctx.alc_busaddr = 0; 2150 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2151 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2152 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2153 if (error != 0 || ctx.alc_busaddr == 0) { 2154 device_printf(sc->alc_dev, 2155 "could not load DMA'able memory for Tx ring.\n"); 2156 goto fail; 2157 } 2158 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2159 2160 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2161 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2162 (void **)&sc->alc_rdata.alc_cmb, 2163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2164 &sc->alc_cdata.alc_cmb_map); 2165 if (error != 0) { 2166 device_printf(sc->alc_dev, 2167 "could not allocate DMA'able memory for CMB.\n"); 2168 goto fail; 2169 } 2170 ctx.alc_busaddr = 0; 2171 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2172 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2173 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2174 if (error != 0 || ctx.alc_busaddr == 0) { 2175 device_printf(sc->alc_dev, 2176 "could not load DMA'able memory for CMB.\n"); 2177 goto fail; 2178 } 2179 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2180 2181 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2182 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2183 (void **)&sc->alc_rdata.alc_smb, 2184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2185 &sc->alc_cdata.alc_smb_map); 2186 if (error != 0) { 2187 device_printf(sc->alc_dev, 2188 "could not allocate DMA'able memory for SMB.\n"); 2189 goto fail; 2190 } 2191 ctx.alc_busaddr = 0; 2192 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2193 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2194 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2195 if (error != 0 || ctx.alc_busaddr == 0) { 2196 device_printf(sc->alc_dev, 2197 "could not load DMA'able memory for CMB.\n"); 2198 goto fail; 2199 } 2200 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2201 2202 /* Make sure we've not crossed 4GB boundary. */ 2203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2204 (error = alc_check_boundary(sc)) != 0) { 2205 device_printf(sc->alc_dev, "4GB boundary crossed, " 2206 "switching to 32bit DMA addressing mode.\n"); 2207 alc_dma_free(sc); 2208 /* 2209 * Limit max allowable DMA address space to 32bit 2210 * and try again. 2211 */ 2212 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2213 goto again; 2214 } 2215 2216 /* 2217 * Create Tx buffer parent tag. 2218 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2219 * so it needs separate parent DMA tag as parent DMA address 2220 * space could be restricted to be within 32bit address space 2221 * by 4GB boundary crossing. 2222 */ 2223 error = bus_dma_tag_create( 2224 bus_get_dma_tag(sc->alc_dev), /* parent */ 2225 1, 0, /* alignment, boundary */ 2226 lowaddr, /* lowaddr */ 2227 BUS_SPACE_MAXADDR, /* highaddr */ 2228 NULL, NULL, /* filter, filterarg */ 2229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2230 0, /* nsegments */ 2231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2232 0, /* flags */ 2233 NULL, NULL, /* lockfunc, lockarg */ 2234 &sc->alc_cdata.alc_buffer_tag); 2235 if (error != 0) { 2236 device_printf(sc->alc_dev, 2237 "could not create parent buffer DMA tag.\n"); 2238 goto fail; 2239 } 2240 2241 /* Create DMA tag for Tx buffers. */ 2242 error = bus_dma_tag_create( 2243 sc->alc_cdata.alc_buffer_tag, /* parent */ 2244 1, 0, /* alignment, boundary */ 2245 BUS_SPACE_MAXADDR, /* lowaddr */ 2246 BUS_SPACE_MAXADDR, /* highaddr */ 2247 NULL, NULL, /* filter, filterarg */ 2248 ALC_TSO_MAXSIZE, /* maxsize */ 2249 ALC_MAXTXSEGS, /* nsegments */ 2250 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2251 0, /* flags */ 2252 NULL, NULL, /* lockfunc, lockarg */ 2253 &sc->alc_cdata.alc_tx_tag); 2254 if (error != 0) { 2255 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2256 goto fail; 2257 } 2258 2259 /* Create DMA tag for Rx buffers. */ 2260 error = bus_dma_tag_create( 2261 sc->alc_cdata.alc_buffer_tag, /* parent */ 2262 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2263 BUS_SPACE_MAXADDR, /* lowaddr */ 2264 BUS_SPACE_MAXADDR, /* highaddr */ 2265 NULL, NULL, /* filter, filterarg */ 2266 MCLBYTES, /* maxsize */ 2267 1, /* nsegments */ 2268 MCLBYTES, /* maxsegsize */ 2269 0, /* flags */ 2270 NULL, NULL, /* lockfunc, lockarg */ 2271 &sc->alc_cdata.alc_rx_tag); 2272 if (error != 0) { 2273 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2274 goto fail; 2275 } 2276 /* Create DMA maps for Tx buffers. */ 2277 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2278 txd = &sc->alc_cdata.alc_txdesc[i]; 2279 txd->tx_m = NULL; 2280 txd->tx_dmamap = NULL; 2281 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2282 &txd->tx_dmamap); 2283 if (error != 0) { 2284 device_printf(sc->alc_dev, 2285 "could not create Tx dmamap.\n"); 2286 goto fail; 2287 } 2288 } 2289 /* Create DMA maps for Rx buffers. */ 2290 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2291 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2292 device_printf(sc->alc_dev, 2293 "could not create spare Rx dmamap.\n"); 2294 goto fail; 2295 } 2296 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2297 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2298 rxd->rx_m = NULL; 2299 rxd->rx_dmamap = NULL; 2300 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2301 &rxd->rx_dmamap); 2302 if (error != 0) { 2303 device_printf(sc->alc_dev, 2304 "could not create Rx dmamap.\n"); 2305 goto fail; 2306 } 2307 } 2308 2309 fail: 2310 return (error); 2311 } 2312 2313 static void 2314 alc_dma_free(struct alc_softc *sc) 2315 { 2316 struct alc_txdesc *txd; 2317 struct alc_rxdesc *rxd; 2318 int i; 2319 2320 /* Tx buffers. */ 2321 if (sc->alc_cdata.alc_tx_tag != NULL) { 2322 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2323 txd = &sc->alc_cdata.alc_txdesc[i]; 2324 if (txd->tx_dmamap != NULL) { 2325 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2326 txd->tx_dmamap); 2327 txd->tx_dmamap = NULL; 2328 } 2329 } 2330 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2331 sc->alc_cdata.alc_tx_tag = NULL; 2332 } 2333 /* Rx buffers */ 2334 if (sc->alc_cdata.alc_rx_tag != NULL) { 2335 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2336 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2337 if (rxd->rx_dmamap != NULL) { 2338 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2339 rxd->rx_dmamap); 2340 rxd->rx_dmamap = NULL; 2341 } 2342 } 2343 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2344 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2345 sc->alc_cdata.alc_rx_sparemap); 2346 sc->alc_cdata.alc_rx_sparemap = NULL; 2347 } 2348 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2349 sc->alc_cdata.alc_rx_tag = NULL; 2350 } 2351 /* Tx descriptor ring. */ 2352 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2353 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2354 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2355 sc->alc_cdata.alc_tx_ring_map); 2356 if (sc->alc_rdata.alc_tx_ring != NULL) 2357 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2358 sc->alc_rdata.alc_tx_ring, 2359 sc->alc_cdata.alc_tx_ring_map); 2360 sc->alc_rdata.alc_tx_ring_paddr = 0; 2361 sc->alc_rdata.alc_tx_ring = NULL; 2362 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2363 sc->alc_cdata.alc_tx_ring_tag = NULL; 2364 } 2365 /* Rx ring. */ 2366 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2367 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2368 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2369 sc->alc_cdata.alc_rx_ring_map); 2370 if (sc->alc_rdata.alc_rx_ring != NULL) 2371 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2372 sc->alc_rdata.alc_rx_ring, 2373 sc->alc_cdata.alc_rx_ring_map); 2374 sc->alc_rdata.alc_rx_ring_paddr = 0; 2375 sc->alc_rdata.alc_rx_ring = NULL; 2376 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2377 sc->alc_cdata.alc_rx_ring_tag = NULL; 2378 } 2379 /* Rx return ring. */ 2380 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2381 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2382 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2383 sc->alc_cdata.alc_rr_ring_map); 2384 if (sc->alc_rdata.alc_rr_ring != NULL) 2385 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2386 sc->alc_rdata.alc_rr_ring, 2387 sc->alc_cdata.alc_rr_ring_map); 2388 sc->alc_rdata.alc_rr_ring_paddr = 0; 2389 sc->alc_rdata.alc_rr_ring = NULL; 2390 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2391 sc->alc_cdata.alc_rr_ring_tag = NULL; 2392 } 2393 /* CMB block */ 2394 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2395 if (sc->alc_rdata.alc_cmb_paddr != 0) 2396 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2397 sc->alc_cdata.alc_cmb_map); 2398 if (sc->alc_rdata.alc_cmb != NULL) 2399 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2400 sc->alc_rdata.alc_cmb, 2401 sc->alc_cdata.alc_cmb_map); 2402 sc->alc_rdata.alc_cmb_paddr = 0; 2403 sc->alc_rdata.alc_cmb = NULL; 2404 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2405 sc->alc_cdata.alc_cmb_tag = NULL; 2406 } 2407 /* SMB block */ 2408 if (sc->alc_cdata.alc_smb_tag != NULL) { 2409 if (sc->alc_rdata.alc_smb_paddr != 0) 2410 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2411 sc->alc_cdata.alc_smb_map); 2412 if (sc->alc_rdata.alc_smb != NULL) 2413 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2414 sc->alc_rdata.alc_smb, 2415 sc->alc_cdata.alc_smb_map); 2416 sc->alc_rdata.alc_smb_paddr = 0; 2417 sc->alc_rdata.alc_smb = NULL; 2418 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2419 sc->alc_cdata.alc_smb_tag = NULL; 2420 } 2421 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2422 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2423 sc->alc_cdata.alc_buffer_tag = NULL; 2424 } 2425 if (sc->alc_cdata.alc_parent_tag != NULL) { 2426 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2427 sc->alc_cdata.alc_parent_tag = NULL; 2428 } 2429 } 2430 2431 static int 2432 alc_shutdown(device_t dev) 2433 { 2434 2435 return (alc_suspend(dev)); 2436 } 2437 2438 /* 2439 * Note, this driver resets the link speed to 10/100Mbps by 2440 * restarting auto-negotiation in suspend/shutdown phase but we 2441 * don't know whether that auto-negotiation would succeed or not 2442 * as driver has no control after powering off/suspend operation. 2443 * If the renegotiation fail WOL may not work. Running at 1Gbps 2444 * will draw more power than 375mA at 3.3V which is specified in 2445 * PCI specification and that would result in complete 2446 * shutdowning power to ethernet controller. 2447 * 2448 * TODO 2449 * Save current negotiated media speed/duplex/flow-control to 2450 * softc and restore the same link again after resuming. PHY 2451 * handling such as power down/resetting to 100Mbps may be better 2452 * handled in suspend method in phy driver. 2453 */ 2454 static void 2455 alc_setlinkspeed(struct alc_softc *sc) 2456 { 2457 struct mii_data *mii; 2458 int aneg, i; 2459 2460 mii = device_get_softc(sc->alc_miibus); 2461 mii_pollstat(mii); 2462 aneg = 0; 2463 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2464 (IFM_ACTIVE | IFM_AVALID)) { 2465 switch IFM_SUBTYPE(mii->mii_media_active) { 2466 case IFM_10_T: 2467 case IFM_100_TX: 2468 return; 2469 case IFM_1000_T: 2470 aneg++; 2471 break; 2472 default: 2473 break; 2474 } 2475 } 2476 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2478 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2479 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2480 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2481 DELAY(1000); 2482 if (aneg != 0) { 2483 /* 2484 * Poll link state until alc(4) get a 10/100Mbps link. 2485 */ 2486 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2487 mii_pollstat(mii); 2488 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2489 == (IFM_ACTIVE | IFM_AVALID)) { 2490 switch (IFM_SUBTYPE( 2491 mii->mii_media_active)) { 2492 case IFM_10_T: 2493 case IFM_100_TX: 2494 alc_mac_config(sc); 2495 return; 2496 default: 2497 break; 2498 } 2499 } 2500 ALC_UNLOCK(sc); 2501 pause("alclnk", hz); 2502 ALC_LOCK(sc); 2503 } 2504 if (i == MII_ANEGTICKS_GIGE) 2505 device_printf(sc->alc_dev, 2506 "establishing a link failed, WOL may not work!"); 2507 } 2508 /* 2509 * No link, force MAC to have 100Mbps, full-duplex link. 2510 * This is the last resort and may/may not work. 2511 */ 2512 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2513 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2514 alc_mac_config(sc); 2515 } 2516 2517 static void 2518 alc_setwol(struct alc_softc *sc) 2519 { 2520 2521 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2522 alc_setwol_816x(sc); 2523 else 2524 alc_setwol_813x(sc); 2525 } 2526 2527 static void 2528 alc_setwol_813x(struct alc_softc *sc) 2529 { 2530 if_t ifp; 2531 uint32_t reg, pmcs; 2532 2533 ALC_LOCK_ASSERT(sc); 2534 2535 alc_disable_l0s_l1(sc); 2536 ifp = sc->alc_ifp; 2537 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2538 /* Disable WOL. */ 2539 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2540 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2541 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2542 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2543 /* Force PHY power down. */ 2544 alc_phy_down(sc); 2545 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2546 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2547 return; 2548 } 2549 2550 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2551 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2552 alc_setlinkspeed(sc); 2553 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2554 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2555 } 2556 2557 pmcs = 0; 2558 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2559 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2560 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2561 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2562 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2563 MAC_CFG_BCAST); 2564 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2565 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2566 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2567 reg |= MAC_CFG_RX_ENB; 2568 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2569 2570 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2571 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2572 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2573 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2574 /* WOL disabled, PHY power down. */ 2575 alc_phy_down(sc); 2576 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2577 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2578 } 2579 /* Request PME. */ 2580 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2581 pci_enable_pme(sc->alc_dev); 2582 } 2583 2584 static void 2585 alc_setwol_816x(struct alc_softc *sc) 2586 { 2587 if_t ifp; 2588 uint32_t gphy, mac, master, pmcs, reg; 2589 2590 ALC_LOCK_ASSERT(sc); 2591 2592 ifp = sc->alc_ifp; 2593 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2594 master &= ~MASTER_CLK_SEL_DIS; 2595 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2596 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2597 GPHY_CFG_PHY_PLL_ON); 2598 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2599 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2600 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2601 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2602 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2603 } else { 2604 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2605 gphy |= GPHY_CFG_EXT_RESET; 2606 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2607 alc_setlinkspeed(sc); 2608 } 2609 pmcs = 0; 2610 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2611 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2612 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2613 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2614 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2615 MAC_CFG_BCAST); 2616 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2617 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2618 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2619 mac |= MAC_CFG_RX_ENB; 2620 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2621 ANEG_S3DIG10_SL); 2622 } 2623 2624 /* Enable OSC. */ 2625 reg = CSR_READ_4(sc, ALC_MISC); 2626 reg &= ~MISC_INTNLOSC_OPEN; 2627 CSR_WRITE_4(sc, ALC_MISC, reg); 2628 reg |= MISC_INTNLOSC_OPEN; 2629 CSR_WRITE_4(sc, ALC_MISC, reg); 2630 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2631 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2632 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2633 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2634 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2635 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2636 2637 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2638 /* Request PME. */ 2639 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2640 pci_enable_pme(sc->alc_dev); 2641 } 2642 } 2643 2644 static int 2645 alc_suspend(device_t dev) 2646 { 2647 struct alc_softc *sc; 2648 2649 sc = device_get_softc(dev); 2650 2651 ALC_LOCK(sc); 2652 alc_stop(sc); 2653 alc_setwol(sc); 2654 ALC_UNLOCK(sc); 2655 2656 return (0); 2657 } 2658 2659 static int 2660 alc_resume(device_t dev) 2661 { 2662 struct alc_softc *sc; 2663 if_t ifp; 2664 2665 sc = device_get_softc(dev); 2666 2667 /* Reset PHY. */ 2668 ALC_LOCK(sc); 2669 alc_phy_reset(sc); 2670 ifp = sc->alc_ifp; 2671 if ((if_getflags(ifp) & IFF_UP) != 0) { 2672 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2673 alc_init_locked(sc); 2674 } 2675 ALC_UNLOCK(sc); 2676 2677 return (0); 2678 } 2679 2680 static int 2681 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2682 { 2683 struct alc_txdesc *txd, *txd_last; 2684 struct tx_desc *desc; 2685 struct mbuf *m; 2686 struct ip *ip; 2687 struct tcphdr *tcp; 2688 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2689 bus_dmamap_t map; 2690 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2691 int error, idx, nsegs, prod; 2692 2693 ALC_LOCK_ASSERT(sc); 2694 2695 M_ASSERTPKTHDR((*m_head)); 2696 2697 m = *m_head; 2698 ip = NULL; 2699 tcp = NULL; 2700 ip_off = poff = 0; 2701 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2702 /* 2703 * AR81[3567]x requires offset of TCP/UDP header in its 2704 * Tx descriptor to perform Tx checksum offloading. TSO 2705 * also requires TCP header offset and modification of 2706 * IP/TCP header. This kind of operation takes many CPU 2707 * cycles on FreeBSD so fast host CPU is required to get 2708 * smooth TSO performance. 2709 */ 2710 struct ether_header *eh; 2711 2712 if (M_WRITABLE(m) == 0) { 2713 /* Get a writable copy. */ 2714 m = m_dup(*m_head, M_NOWAIT); 2715 /* Release original mbufs. */ 2716 m_freem(*m_head); 2717 if (m == NULL) { 2718 *m_head = NULL; 2719 return (ENOBUFS); 2720 } 2721 *m_head = m; 2722 } 2723 2724 ip_off = sizeof(struct ether_header); 2725 m = m_pullup(m, ip_off); 2726 if (m == NULL) { 2727 *m_head = NULL; 2728 return (ENOBUFS); 2729 } 2730 eh = mtod(m, struct ether_header *); 2731 /* 2732 * Check if hardware VLAN insertion is off. 2733 * Additional check for LLC/SNAP frame? 2734 */ 2735 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2736 ip_off = sizeof(struct ether_vlan_header); 2737 m = m_pullup(m, ip_off); 2738 if (m == NULL) { 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 } 2743 m = m_pullup(m, ip_off + sizeof(struct ip)); 2744 if (m == NULL) { 2745 *m_head = NULL; 2746 return (ENOBUFS); 2747 } 2748 ip = (struct ip *)(mtod(m, char *) + ip_off); 2749 poff = ip_off + (ip->ip_hl << 2); 2750 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2751 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2752 if (m == NULL) { 2753 *m_head = NULL; 2754 return (ENOBUFS); 2755 } 2756 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2757 m = m_pullup(m, poff + (tcp->th_off << 2)); 2758 if (m == NULL) { 2759 *m_head = NULL; 2760 return (ENOBUFS); 2761 } 2762 /* 2763 * Due to strict adherence of Microsoft NDIS 2764 * Large Send specification, hardware expects 2765 * a pseudo TCP checksum inserted by upper 2766 * stack. Unfortunately the pseudo TCP 2767 * checksum that NDIS refers to does not include 2768 * TCP payload length so driver should recompute 2769 * the pseudo checksum here. Hopefully this 2770 * wouldn't be much burden on modern CPUs. 2771 * 2772 * Reset IP checksum and recompute TCP pseudo 2773 * checksum as NDIS specification said. 2774 */ 2775 ip = (struct ip *)(mtod(m, char *) + ip_off); 2776 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2777 ip->ip_sum = 0; 2778 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2779 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2780 } 2781 *m_head = m; 2782 } 2783 2784 prod = sc->alc_cdata.alc_tx_prod; 2785 txd = &sc->alc_cdata.alc_txdesc[prod]; 2786 txd_last = txd; 2787 map = txd->tx_dmamap; 2788 2789 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2790 *m_head, txsegs, &nsegs, 0); 2791 if (error == EFBIG) { 2792 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2793 if (m == NULL) { 2794 m_freem(*m_head); 2795 *m_head = NULL; 2796 return (ENOMEM); 2797 } 2798 *m_head = m; 2799 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2800 *m_head, txsegs, &nsegs, 0); 2801 if (error != 0) { 2802 m_freem(*m_head); 2803 *m_head = NULL; 2804 return (error); 2805 } 2806 } else if (error != 0) 2807 return (error); 2808 if (nsegs == 0) { 2809 m_freem(*m_head); 2810 *m_head = NULL; 2811 return (EIO); 2812 } 2813 2814 /* Check descriptor overrun. */ 2815 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2816 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2817 return (ENOBUFS); 2818 } 2819 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2820 2821 m = *m_head; 2822 cflags = TD_ETHERNET; 2823 vtag = 0; 2824 desc = NULL; 2825 idx = 0; 2826 /* Configure VLAN hardware tag insertion. */ 2827 if ((m->m_flags & M_VLANTAG) != 0) { 2828 vtag = htons(m->m_pkthdr.ether_vtag); 2829 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2830 cflags |= TD_INS_VLAN_TAG; 2831 } 2832 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2833 /* Request TSO and set MSS. */ 2834 cflags |= TD_TSO | TD_TSO_DESCV1; 2835 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2836 TD_MSS_MASK; 2837 /* Set TCP header offset. */ 2838 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2839 TD_TCPHDR_OFFSET_MASK; 2840 /* 2841 * AR81[3567]x requires the first buffer should 2842 * only hold IP/TCP header data. Payload should 2843 * be handled in other descriptors. 2844 */ 2845 hdrlen = poff + (tcp->th_off << 2); 2846 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2847 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2848 desc->flags = htole32(cflags); 2849 desc->addr = htole64(txsegs[0].ds_addr); 2850 sc->alc_cdata.alc_tx_cnt++; 2851 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2852 if (m->m_len - hdrlen > 0) { 2853 /* Handle remaining payload of the first fragment. */ 2854 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2855 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2856 vtag)); 2857 desc->flags = htole32(cflags); 2858 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2859 sc->alc_cdata.alc_tx_cnt++; 2860 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2861 } 2862 /* Handle remaining fragments. */ 2863 idx = 1; 2864 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2865 /* Configure Tx checksum offload. */ 2866 #ifdef ALC_USE_CUSTOM_CSUM 2867 cflags |= TD_CUSTOM_CSUM; 2868 /* Set checksum start offset. */ 2869 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2870 TD_PLOAD_OFFSET_MASK; 2871 /* Set checksum insertion position of TCP/UDP. */ 2872 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2873 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2874 #else 2875 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2876 cflags |= TD_IPCSUM; 2877 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2878 cflags |= TD_TCPCSUM; 2879 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2880 cflags |= TD_UDPCSUM; 2881 /* Set TCP/UDP header offset. */ 2882 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2883 TD_L4HDR_OFFSET_MASK; 2884 #endif 2885 } 2886 for (; idx < nsegs; idx++) { 2887 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2888 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2889 desc->flags = htole32(cflags); 2890 desc->addr = htole64(txsegs[idx].ds_addr); 2891 sc->alc_cdata.alc_tx_cnt++; 2892 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2893 } 2894 /* Update producer index. */ 2895 sc->alc_cdata.alc_tx_prod = prod; 2896 2897 /* Finally set EOP on the last descriptor. */ 2898 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2899 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2900 desc->flags |= htole32(TD_EOP); 2901 2902 /* Swap dmamap of the first and the last. */ 2903 txd = &sc->alc_cdata.alc_txdesc[prod]; 2904 map = txd_last->tx_dmamap; 2905 txd_last->tx_dmamap = txd->tx_dmamap; 2906 txd->tx_dmamap = map; 2907 txd->tx_m = m; 2908 2909 return (0); 2910 } 2911 2912 static void 2913 alc_start(if_t ifp) 2914 { 2915 struct alc_softc *sc; 2916 2917 sc = if_getsoftc(ifp); 2918 ALC_LOCK(sc); 2919 alc_start_locked(ifp); 2920 ALC_UNLOCK(sc); 2921 } 2922 2923 static void 2924 alc_start_locked(if_t ifp) 2925 { 2926 struct alc_softc *sc; 2927 struct mbuf *m_head; 2928 int enq; 2929 2930 sc = if_getsoftc(ifp); 2931 2932 ALC_LOCK_ASSERT(sc); 2933 2934 /* Reclaim transmitted frames. */ 2935 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2936 alc_txeof(sc); 2937 2938 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2939 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2940 return; 2941 2942 for (enq = 0; !if_sendq_empty(ifp); ) { 2943 m_head = if_dequeue(ifp); 2944 if (m_head == NULL) 2945 break; 2946 /* 2947 * Pack the data into the transmit ring. If we 2948 * don't have room, set the OACTIVE flag and wait 2949 * for the NIC to drain the ring. 2950 */ 2951 if (alc_encap(sc, &m_head)) { 2952 if (m_head == NULL) 2953 break; 2954 if_sendq_prepend(ifp, m_head); 2955 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2956 break; 2957 } 2958 2959 enq++; 2960 /* 2961 * If there's a BPF listener, bounce a copy of this frame 2962 * to him. 2963 */ 2964 ETHER_BPF_MTAP(ifp, m_head); 2965 } 2966 2967 if (enq > 0) 2968 alc_start_tx(sc); 2969 } 2970 2971 static void 2972 alc_start_tx(struct alc_softc *sc) 2973 { 2974 2975 /* Sync descriptors. */ 2976 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2977 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2978 /* Kick. Assume we're using normal Tx priority queue. */ 2979 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2980 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2981 (uint16_t)sc->alc_cdata.alc_tx_prod); 2982 else 2983 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2984 (sc->alc_cdata.alc_tx_prod << 2985 MBOX_TD_PROD_LO_IDX_SHIFT) & 2986 MBOX_TD_PROD_LO_IDX_MASK); 2987 /* Set a timeout in case the chip goes out to lunch. */ 2988 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2989 } 2990 2991 static void 2992 alc_watchdog(struct alc_softc *sc) 2993 { 2994 if_t ifp; 2995 2996 ALC_LOCK_ASSERT(sc); 2997 2998 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2999 return; 3000 3001 ifp = sc->alc_ifp; 3002 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3003 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3004 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3005 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3006 alc_init_locked(sc); 3007 return; 3008 } 3009 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3010 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3011 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3012 alc_init_locked(sc); 3013 if (!if_sendq_empty(ifp)) 3014 alc_start_locked(ifp); 3015 } 3016 3017 static int 3018 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3019 { 3020 struct alc_softc *sc; 3021 struct ifreq *ifr; 3022 struct mii_data *mii; 3023 int error, mask; 3024 3025 sc = if_getsoftc(ifp); 3026 ifr = (struct ifreq *)data; 3027 error = 0; 3028 switch (cmd) { 3029 case SIOCSIFMTU: 3030 if (ifr->ifr_mtu < ETHERMIN || 3031 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3032 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3033 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3034 ifr->ifr_mtu > ETHERMTU)) 3035 error = EINVAL; 3036 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3037 ALC_LOCK(sc); 3038 if_setmtu(ifp, ifr->ifr_mtu); 3039 /* AR81[3567]x has 13 bits MSS field. */ 3040 if (if_getmtu(ifp) > ALC_TSO_MTU && 3041 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3042 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3043 if_sethwassistbits(ifp, 0, CSUM_TSO); 3044 VLAN_CAPABILITIES(ifp); 3045 } 3046 ALC_UNLOCK(sc); 3047 } 3048 break; 3049 case SIOCSIFFLAGS: 3050 ALC_LOCK(sc); 3051 if ((if_getflags(ifp) & IFF_UP) != 0) { 3052 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3053 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3054 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3055 alc_rxfilter(sc); 3056 else 3057 alc_init_locked(sc); 3058 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3059 alc_stop(sc); 3060 sc->alc_if_flags = if_getflags(ifp); 3061 ALC_UNLOCK(sc); 3062 break; 3063 case SIOCADDMULTI: 3064 case SIOCDELMULTI: 3065 ALC_LOCK(sc); 3066 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3067 alc_rxfilter(sc); 3068 ALC_UNLOCK(sc); 3069 break; 3070 case SIOCSIFMEDIA: 3071 case SIOCGIFMEDIA: 3072 mii = device_get_softc(sc->alc_miibus); 3073 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3074 break; 3075 case SIOCSIFCAP: 3076 ALC_LOCK(sc); 3077 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3078 if ((mask & IFCAP_TXCSUM) != 0 && 3079 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3080 if_togglecapenable(ifp, IFCAP_TXCSUM); 3081 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3082 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3083 else 3084 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3085 } 3086 if ((mask & IFCAP_TSO4) != 0 && 3087 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3088 if_togglecapenable(ifp, IFCAP_TSO4); 3089 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3090 /* AR81[3567]x has 13 bits MSS field. */ 3091 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3092 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3093 if_sethwassistbits(ifp, 0, CSUM_TSO); 3094 } else 3095 if_sethwassistbits(ifp, CSUM_TSO, 0); 3096 } else 3097 if_sethwassistbits(ifp, 0, CSUM_TSO); 3098 } 3099 if ((mask & IFCAP_WOL_MCAST) != 0 && 3100 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3101 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3102 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3103 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3104 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3105 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3106 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3107 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3108 alc_rxvlan(sc); 3109 } 3110 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3111 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3112 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3113 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3114 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3115 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3116 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3117 if_setcapenablebit(ifp, 0, 3118 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3119 ALC_UNLOCK(sc); 3120 VLAN_CAPABILITIES(ifp); 3121 break; 3122 default: 3123 error = ether_ioctl(ifp, cmd, data); 3124 break; 3125 } 3126 3127 return (error); 3128 } 3129 3130 static void 3131 alc_mac_config(struct alc_softc *sc) 3132 { 3133 struct mii_data *mii; 3134 uint32_t reg; 3135 3136 ALC_LOCK_ASSERT(sc); 3137 3138 mii = device_get_softc(sc->alc_miibus); 3139 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3140 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3141 MAC_CFG_SPEED_MASK); 3142 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3143 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3144 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3145 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3146 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3147 /* Reprogram MAC with resolved speed/duplex. */ 3148 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3149 case IFM_10_T: 3150 case IFM_100_TX: 3151 reg |= MAC_CFG_SPEED_10_100; 3152 break; 3153 case IFM_1000_T: 3154 reg |= MAC_CFG_SPEED_1000; 3155 break; 3156 } 3157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3158 reg |= MAC_CFG_FULL_DUPLEX; 3159 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3160 reg |= MAC_CFG_TX_FC; 3161 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3162 reg |= MAC_CFG_RX_FC; 3163 } 3164 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3165 } 3166 3167 static void 3168 alc_stats_clear(struct alc_softc *sc) 3169 { 3170 struct smb sb, *smb; 3171 uint32_t *reg; 3172 int i; 3173 3174 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3175 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3176 sc->alc_cdata.alc_smb_map, 3177 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3178 smb = sc->alc_rdata.alc_smb; 3179 /* Update done, clear. */ 3180 smb->updated = 0; 3181 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3182 sc->alc_cdata.alc_smb_map, 3183 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3184 } else { 3185 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3186 reg++) { 3187 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3188 i += sizeof(uint32_t); 3189 } 3190 /* Read Tx statistics. */ 3191 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3192 reg++) { 3193 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3194 i += sizeof(uint32_t); 3195 } 3196 } 3197 } 3198 3199 static void 3200 alc_stats_update(struct alc_softc *sc) 3201 { 3202 struct alc_hw_stats *stat; 3203 struct smb sb, *smb; 3204 if_t ifp; 3205 uint32_t *reg; 3206 int i; 3207 3208 ALC_LOCK_ASSERT(sc); 3209 3210 ifp = sc->alc_ifp; 3211 stat = &sc->alc_stats; 3212 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3213 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3214 sc->alc_cdata.alc_smb_map, 3215 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3216 smb = sc->alc_rdata.alc_smb; 3217 if (smb->updated == 0) 3218 return; 3219 } else { 3220 smb = &sb; 3221 /* Read Rx statistics. */ 3222 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3223 reg++) { 3224 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3225 i += sizeof(uint32_t); 3226 } 3227 /* Read Tx statistics. */ 3228 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3229 reg++) { 3230 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3231 i += sizeof(uint32_t); 3232 } 3233 } 3234 3235 /* Rx stats. */ 3236 stat->rx_frames += smb->rx_frames; 3237 stat->rx_bcast_frames += smb->rx_bcast_frames; 3238 stat->rx_mcast_frames += smb->rx_mcast_frames; 3239 stat->rx_pause_frames += smb->rx_pause_frames; 3240 stat->rx_control_frames += smb->rx_control_frames; 3241 stat->rx_crcerrs += smb->rx_crcerrs; 3242 stat->rx_lenerrs += smb->rx_lenerrs; 3243 stat->rx_bytes += smb->rx_bytes; 3244 stat->rx_runts += smb->rx_runts; 3245 stat->rx_fragments += smb->rx_fragments; 3246 stat->rx_pkts_64 += smb->rx_pkts_64; 3247 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3248 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3249 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3250 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3251 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3252 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3253 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3254 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3255 stat->rx_rrs_errs += smb->rx_rrs_errs; 3256 stat->rx_alignerrs += smb->rx_alignerrs; 3257 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3258 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3259 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3260 3261 /* Tx stats. */ 3262 stat->tx_frames += smb->tx_frames; 3263 stat->tx_bcast_frames += smb->tx_bcast_frames; 3264 stat->tx_mcast_frames += smb->tx_mcast_frames; 3265 stat->tx_pause_frames += smb->tx_pause_frames; 3266 stat->tx_excess_defer += smb->tx_excess_defer; 3267 stat->tx_control_frames += smb->tx_control_frames; 3268 stat->tx_deferred += smb->tx_deferred; 3269 stat->tx_bytes += smb->tx_bytes; 3270 stat->tx_pkts_64 += smb->tx_pkts_64; 3271 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3272 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3273 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3274 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3275 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3276 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3277 stat->tx_single_colls += smb->tx_single_colls; 3278 stat->tx_multi_colls += smb->tx_multi_colls; 3279 stat->tx_late_colls += smb->tx_late_colls; 3280 stat->tx_excess_colls += smb->tx_excess_colls; 3281 stat->tx_underrun += smb->tx_underrun; 3282 stat->tx_desc_underrun += smb->tx_desc_underrun; 3283 stat->tx_lenerrs += smb->tx_lenerrs; 3284 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3285 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3286 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3287 3288 /* Update counters in ifnet. */ 3289 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3290 3291 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3292 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3293 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3294 3295 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3296 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3297 3298 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3299 3300 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3301 smb->rx_crcerrs + smb->rx_lenerrs + 3302 smb->rx_runts + smb->rx_pkts_truncated + 3303 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3304 smb->rx_alignerrs); 3305 3306 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3307 /* Update done, clear. */ 3308 smb->updated = 0; 3309 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3310 sc->alc_cdata.alc_smb_map, 3311 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3312 } 3313 } 3314 3315 static int 3316 alc_intr(void *arg) 3317 { 3318 struct alc_softc *sc; 3319 uint32_t status; 3320 3321 sc = (struct alc_softc *)arg; 3322 3323 if (sc->alc_flags & ALC_FLAG_MT) { 3324 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3325 return (FILTER_HANDLED); 3326 } 3327 3328 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3329 if ((status & ALC_INTRS) == 0) 3330 return (FILTER_STRAY); 3331 /* Disable interrupts. */ 3332 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3333 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3334 3335 return (FILTER_HANDLED); 3336 } 3337 3338 static void 3339 alc_int_task(void *arg, int pending) 3340 { 3341 struct alc_softc *sc; 3342 if_t ifp; 3343 uint32_t status; 3344 int more; 3345 3346 sc = (struct alc_softc *)arg; 3347 ifp = sc->alc_ifp; 3348 3349 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3350 ALC_LOCK(sc); 3351 if (sc->alc_morework != 0) { 3352 sc->alc_morework = 0; 3353 status |= INTR_RX_PKT; 3354 } 3355 if ((status & ALC_INTRS) == 0) 3356 goto done; 3357 3358 /* Acknowledge interrupts but still disable interrupts. */ 3359 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3360 3361 more = 0; 3362 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3363 if ((status & INTR_RX_PKT) != 0) { 3364 more = alc_rxintr(sc, sc->alc_process_limit); 3365 if (more == EAGAIN) 3366 sc->alc_morework = 1; 3367 else if (more == EIO) { 3368 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3369 alc_init_locked(sc); 3370 ALC_UNLOCK(sc); 3371 return; 3372 } 3373 } 3374 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3375 INTR_TXQ_TO_RST)) != 0) { 3376 if ((status & INTR_DMA_RD_TO_RST) != 0) 3377 device_printf(sc->alc_dev, 3378 "DMA read error! -- resetting\n"); 3379 if ((status & INTR_DMA_WR_TO_RST) != 0) 3380 device_printf(sc->alc_dev, 3381 "DMA write error! -- resetting\n"); 3382 if ((status & INTR_TXQ_TO_RST) != 0) 3383 device_printf(sc->alc_dev, 3384 "TxQ reset! -- resetting\n"); 3385 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3386 alc_init_locked(sc); 3387 ALC_UNLOCK(sc); 3388 return; 3389 } 3390 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3391 !if_sendq_empty(ifp)) 3392 alc_start_locked(ifp); 3393 } 3394 3395 if (more == EAGAIN || 3396 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3397 ALC_UNLOCK(sc); 3398 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3399 return; 3400 } 3401 3402 done: 3403 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3404 /* Re-enable interrupts if we're running. */ 3405 if (sc->alc_flags & ALC_FLAG_MT) 3406 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3407 else 3408 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3409 } 3410 ALC_UNLOCK(sc); 3411 } 3412 3413 static void 3414 alc_txeof(struct alc_softc *sc) 3415 { 3416 if_t ifp; 3417 struct alc_txdesc *txd; 3418 uint32_t cons, prod; 3419 3420 ALC_LOCK_ASSERT(sc); 3421 3422 ifp = sc->alc_ifp; 3423 3424 if (sc->alc_cdata.alc_tx_cnt == 0) 3425 return; 3426 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3427 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3428 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3429 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3430 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3431 prod = sc->alc_rdata.alc_cmb->cons; 3432 } else { 3433 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3434 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3435 else { 3436 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3437 /* Assume we're using normal Tx priority queue. */ 3438 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3439 MBOX_TD_CONS_LO_IDX_SHIFT; 3440 } 3441 } 3442 cons = sc->alc_cdata.alc_tx_cons; 3443 /* 3444 * Go through our Tx list and free mbufs for those 3445 * frames which have been transmitted. 3446 */ 3447 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3448 if (sc->alc_cdata.alc_tx_cnt <= 0) 3449 break; 3450 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3451 sc->alc_cdata.alc_tx_cnt--; 3452 txd = &sc->alc_cdata.alc_txdesc[cons]; 3453 if (txd->tx_m != NULL) { 3454 /* Reclaim transmitted mbufs. */ 3455 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3456 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3457 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3458 txd->tx_dmamap); 3459 m_freem(txd->tx_m); 3460 txd->tx_m = NULL; 3461 } 3462 } 3463 3464 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3465 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3466 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3467 sc->alc_cdata.alc_tx_cons = cons; 3468 /* 3469 * Unarm watchdog timer only when there is no pending 3470 * frames in Tx queue. 3471 */ 3472 if (sc->alc_cdata.alc_tx_cnt == 0) 3473 sc->alc_watchdog_timer = 0; 3474 } 3475 3476 static int 3477 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3478 { 3479 struct mbuf *m; 3480 bus_dma_segment_t segs[1]; 3481 bus_dmamap_t map; 3482 int nsegs; 3483 3484 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3485 if (m == NULL) 3486 return (ENOBUFS); 3487 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3488 #ifndef __NO_STRICT_ALIGNMENT 3489 m_adj(m, sizeof(uint64_t)); 3490 #endif 3491 3492 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3493 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3494 m_freem(m); 3495 return (ENOBUFS); 3496 } 3497 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3498 3499 if (rxd->rx_m != NULL) { 3500 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3501 BUS_DMASYNC_POSTREAD); 3502 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3503 } 3504 map = rxd->rx_dmamap; 3505 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3506 sc->alc_cdata.alc_rx_sparemap = map; 3507 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3508 BUS_DMASYNC_PREREAD); 3509 rxd->rx_m = m; 3510 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3511 return (0); 3512 } 3513 3514 static int 3515 alc_rxintr(struct alc_softc *sc, int count) 3516 { 3517 if_t ifp; 3518 struct rx_rdesc *rrd; 3519 uint32_t nsegs, status; 3520 int rr_cons, prog; 3521 3522 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3523 sc->alc_cdata.alc_rr_ring_map, 3524 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3525 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3526 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3527 rr_cons = sc->alc_cdata.alc_rr_cons; 3528 ifp = sc->alc_ifp; 3529 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3530 if (count-- <= 0) 3531 break; 3532 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3533 status = le32toh(rrd->status); 3534 if ((status & RRD_VALID) == 0) 3535 break; 3536 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3537 if (nsegs == 0) { 3538 /* This should not happen! */ 3539 device_printf(sc->alc_dev, 3540 "unexpected segment count -- resetting\n"); 3541 return (EIO); 3542 } 3543 alc_rxeof(sc, rrd); 3544 /* Clear Rx return status. */ 3545 rrd->status = 0; 3546 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3547 sc->alc_cdata.alc_rx_cons += nsegs; 3548 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3549 prog += nsegs; 3550 } 3551 3552 if (prog > 0) { 3553 /* Update the consumer index. */ 3554 sc->alc_cdata.alc_rr_cons = rr_cons; 3555 /* Sync Rx return descriptors. */ 3556 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3557 sc->alc_cdata.alc_rr_ring_map, 3558 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3559 /* 3560 * Sync updated Rx descriptors such that controller see 3561 * modified buffer addresses. 3562 */ 3563 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3564 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3565 /* 3566 * Let controller know availability of new Rx buffers. 3567 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3568 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3569 * only when Rx buffer pre-fetching is required. In 3570 * addition we already set ALC_RX_RD_FREE_THRESH to 3571 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3572 * it still seems that pre-fetching needs more 3573 * experimentation. 3574 */ 3575 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3576 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3577 (uint16_t)sc->alc_cdata.alc_rx_cons); 3578 else 3579 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3580 sc->alc_cdata.alc_rx_cons); 3581 } 3582 3583 return (count > 0 ? 0 : EAGAIN); 3584 } 3585 3586 #ifndef __NO_STRICT_ALIGNMENT 3587 static struct mbuf * 3588 alc_fixup_rx(if_t ifp, struct mbuf *m) 3589 { 3590 struct mbuf *n; 3591 int i; 3592 uint16_t *src, *dst; 3593 3594 src = mtod(m, uint16_t *); 3595 dst = src - 3; 3596 3597 if (m->m_next == NULL) { 3598 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3599 *dst++ = *src++; 3600 m->m_data -= 6; 3601 return (m); 3602 } 3603 /* 3604 * Append a new mbuf to received mbuf chain and copy ethernet 3605 * header from the mbuf chain. This can save lots of CPU 3606 * cycles for jumbo frame. 3607 */ 3608 MGETHDR(n, M_NOWAIT, MT_DATA); 3609 if (n == NULL) { 3610 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3611 m_freem(m); 3612 return (NULL); 3613 } 3614 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3615 m->m_data += ETHER_HDR_LEN; 3616 m->m_len -= ETHER_HDR_LEN; 3617 n->m_len = ETHER_HDR_LEN; 3618 M_MOVE_PKTHDR(n, m); 3619 n->m_next = m; 3620 return (n); 3621 } 3622 #endif 3623 3624 /* Receive a frame. */ 3625 static void 3626 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3627 { 3628 struct alc_rxdesc *rxd; 3629 if_t ifp; 3630 struct mbuf *mp, *m; 3631 uint32_t rdinfo, status, vtag; 3632 int count, nsegs, rx_cons; 3633 3634 ifp = sc->alc_ifp; 3635 status = le32toh(rrd->status); 3636 rdinfo = le32toh(rrd->rdinfo); 3637 rx_cons = RRD_RD_IDX(rdinfo); 3638 nsegs = RRD_RD_CNT(rdinfo); 3639 3640 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3641 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3642 /* 3643 * We want to pass the following frames to upper 3644 * layer regardless of error status of Rx return 3645 * ring. 3646 * 3647 * o IP/TCP/UDP checksum is bad. 3648 * o frame length and protocol specific length 3649 * does not match. 3650 * 3651 * Force network stack compute checksum for 3652 * errored frames. 3653 */ 3654 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3655 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3656 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3657 return; 3658 } 3659 3660 for (count = 0; count < nsegs; count++, 3661 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3662 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3663 mp = rxd->rx_m; 3664 /* Add a new receive buffer to the ring. */ 3665 if (alc_newbuf(sc, rxd) != 0) { 3666 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3667 /* Reuse Rx buffers. */ 3668 if (sc->alc_cdata.alc_rxhead != NULL) 3669 m_freem(sc->alc_cdata.alc_rxhead); 3670 break; 3671 } 3672 3673 /* 3674 * Assume we've received a full sized frame. 3675 * Actual size is fixed when we encounter the end of 3676 * multi-segmented frame. 3677 */ 3678 mp->m_len = sc->alc_buf_size; 3679 3680 /* Chain received mbufs. */ 3681 if (sc->alc_cdata.alc_rxhead == NULL) { 3682 sc->alc_cdata.alc_rxhead = mp; 3683 sc->alc_cdata.alc_rxtail = mp; 3684 } else { 3685 mp->m_flags &= ~M_PKTHDR; 3686 sc->alc_cdata.alc_rxprev_tail = 3687 sc->alc_cdata.alc_rxtail; 3688 sc->alc_cdata.alc_rxtail->m_next = mp; 3689 sc->alc_cdata.alc_rxtail = mp; 3690 } 3691 3692 if (count == nsegs - 1) { 3693 /* Last desc. for this frame. */ 3694 m = sc->alc_cdata.alc_rxhead; 3695 m->m_flags |= M_PKTHDR; 3696 /* 3697 * It seems that L1C/L2C controller has no way 3698 * to tell hardware to strip CRC bytes. 3699 */ 3700 m->m_pkthdr.len = 3701 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3702 if (nsegs > 1) { 3703 /* Set last mbuf size. */ 3704 mp->m_len = sc->alc_cdata.alc_rxlen - 3705 (nsegs - 1) * sc->alc_buf_size; 3706 /* Remove the CRC bytes in chained mbufs. */ 3707 if (mp->m_len <= ETHER_CRC_LEN) { 3708 sc->alc_cdata.alc_rxtail = 3709 sc->alc_cdata.alc_rxprev_tail; 3710 sc->alc_cdata.alc_rxtail->m_len -= 3711 (ETHER_CRC_LEN - mp->m_len); 3712 sc->alc_cdata.alc_rxtail->m_next = NULL; 3713 m_freem(mp); 3714 } else { 3715 mp->m_len -= ETHER_CRC_LEN; 3716 } 3717 } else 3718 m->m_len = m->m_pkthdr.len; 3719 m->m_pkthdr.rcvif = ifp; 3720 /* 3721 * Due to hardware bugs, Rx checksum offloading 3722 * was intentionally disabled. 3723 */ 3724 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3725 (status & RRD_VLAN_TAG) != 0) { 3726 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3727 m->m_pkthdr.ether_vtag = ntohs(vtag); 3728 m->m_flags |= M_VLANTAG; 3729 } 3730 #ifndef __NO_STRICT_ALIGNMENT 3731 m = alc_fixup_rx(ifp, m); 3732 if (m != NULL) 3733 #endif 3734 { 3735 /* Pass it on. */ 3736 ALC_UNLOCK(sc); 3737 if_input(ifp, m); 3738 ALC_LOCK(sc); 3739 } 3740 } 3741 } 3742 /* Reset mbuf chains. */ 3743 ALC_RXCHAIN_RESET(sc); 3744 } 3745 3746 static void 3747 alc_tick(void *arg) 3748 { 3749 struct alc_softc *sc; 3750 struct mii_data *mii; 3751 3752 sc = (struct alc_softc *)arg; 3753 3754 ALC_LOCK_ASSERT(sc); 3755 3756 mii = device_get_softc(sc->alc_miibus); 3757 mii_tick(mii); 3758 alc_stats_update(sc); 3759 /* 3760 * alc(4) does not rely on Tx completion interrupts to reclaim 3761 * transferred buffers. Instead Tx completion interrupts are 3762 * used to hint for scheduling Tx task. So it's necessary to 3763 * release transmitted buffers by kicking Tx completion 3764 * handler. This limits the maximum reclamation delay to a hz. 3765 */ 3766 alc_txeof(sc); 3767 alc_watchdog(sc); 3768 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3769 } 3770 3771 static void 3772 alc_osc_reset(struct alc_softc *sc) 3773 { 3774 uint32_t reg; 3775 3776 reg = CSR_READ_4(sc, ALC_MISC3); 3777 reg &= ~MISC3_25M_BY_SW; 3778 reg |= MISC3_25M_NOTO_INTNL; 3779 CSR_WRITE_4(sc, ALC_MISC3, reg); 3780 3781 reg = CSR_READ_4(sc, ALC_MISC); 3782 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3783 /* 3784 * Restore over-current protection default value. 3785 * This value could be reset by MAC reset. 3786 */ 3787 reg &= ~MISC_PSW_OCP_MASK; 3788 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3789 reg &= ~MISC_INTNLOSC_OPEN; 3790 CSR_WRITE_4(sc, ALC_MISC, reg); 3791 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3792 reg = CSR_READ_4(sc, ALC_MISC2); 3793 reg &= ~MISC2_CALB_START; 3794 CSR_WRITE_4(sc, ALC_MISC2, reg); 3795 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3796 3797 } else { 3798 reg &= ~MISC_INTNLOSC_OPEN; 3799 /* Disable isolate for revision A devices. */ 3800 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3801 reg &= ~MISC_ISO_ENB; 3802 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3803 CSR_WRITE_4(sc, ALC_MISC, reg); 3804 } 3805 3806 DELAY(20); 3807 } 3808 3809 static void 3810 alc_reset(struct alc_softc *sc) 3811 { 3812 uint32_t pmcfg, reg; 3813 int i; 3814 3815 pmcfg = 0; 3816 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3817 /* Reset workaround. */ 3818 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3819 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3820 (sc->alc_rev & 0x01) != 0) { 3821 /* Disable L0s/L1s before reset. */ 3822 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3823 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3824 != 0) { 3825 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3826 PM_CFG_ASPM_L1_ENB); 3827 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3828 } 3829 } 3830 } 3831 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3832 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3833 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3834 3835 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3836 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3837 DELAY(10); 3838 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3839 break; 3840 } 3841 if (i == 0) 3842 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3843 } 3844 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3845 DELAY(10); 3846 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3847 break; 3848 } 3849 if (i == 0) 3850 device_printf(sc->alc_dev, "master reset timeout!\n"); 3851 3852 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3853 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3854 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3855 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3856 break; 3857 DELAY(10); 3858 } 3859 if (i == 0) 3860 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3861 3862 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3863 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3864 (sc->alc_rev & 0x01) != 0) { 3865 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3866 reg |= MASTER_CLK_SEL_DIS; 3867 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3868 /* Restore L0s/L1s config. */ 3869 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3870 != 0) 3871 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3872 } 3873 3874 alc_osc_reset(sc); 3875 reg = CSR_READ_4(sc, ALC_MISC3); 3876 reg &= ~MISC3_25M_BY_SW; 3877 reg |= MISC3_25M_NOTO_INTNL; 3878 CSR_WRITE_4(sc, ALC_MISC3, reg); 3879 reg = CSR_READ_4(sc, ALC_MISC); 3880 reg &= ~MISC_INTNLOSC_OPEN; 3881 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3882 reg &= ~MISC_ISO_ENB; 3883 CSR_WRITE_4(sc, ALC_MISC, reg); 3884 DELAY(20); 3885 } 3886 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3887 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3888 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3889 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3890 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3891 SERDES_PHY_CLK_SLOWDOWN); 3892 } 3893 3894 static void 3895 alc_init(void *xsc) 3896 { 3897 struct alc_softc *sc; 3898 3899 sc = (struct alc_softc *)xsc; 3900 ALC_LOCK(sc); 3901 alc_init_locked(sc); 3902 ALC_UNLOCK(sc); 3903 } 3904 3905 static void 3906 alc_init_locked(struct alc_softc *sc) 3907 { 3908 if_t ifp; 3909 uint8_t eaddr[ETHER_ADDR_LEN]; 3910 bus_addr_t paddr; 3911 uint32_t reg, rxf_hi, rxf_lo; 3912 3913 ALC_LOCK_ASSERT(sc); 3914 3915 ifp = sc->alc_ifp; 3916 3917 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3918 return; 3919 /* 3920 * Cancel any pending I/O. 3921 */ 3922 alc_stop(sc); 3923 /* 3924 * Reset the chip to a known state. 3925 */ 3926 alc_reset(sc); 3927 3928 /* Initialize Rx descriptors. */ 3929 if (alc_init_rx_ring(sc) != 0) { 3930 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3931 alc_stop(sc); 3932 return; 3933 } 3934 alc_init_rr_ring(sc); 3935 alc_init_tx_ring(sc); 3936 alc_init_cmb(sc); 3937 alc_init_smb(sc); 3938 3939 /* Enable all clocks. */ 3940 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3941 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3942 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3943 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3944 CLK_GATING_RXMAC_ENB); 3945 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3946 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3947 IDLE_DECISN_TIMER_DEFAULT_1MS); 3948 } else 3949 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3950 3951 /* Reprogram the station address. */ 3952 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3953 CSR_WRITE_4(sc, ALC_PAR0, 3954 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3955 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3956 /* 3957 * Clear WOL status and disable all WOL feature as WOL 3958 * would interfere Rx operation under normal environments. 3959 */ 3960 CSR_READ_4(sc, ALC_WOL_CFG); 3961 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3962 /* Set Tx descriptor base addresses. */ 3963 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3964 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3965 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3966 /* We don't use high priority ring. */ 3967 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3968 /* Set Tx descriptor counter. */ 3969 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3970 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3971 /* Set Rx descriptor base addresses. */ 3972 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3973 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3974 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3975 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3976 /* We use one Rx ring. */ 3977 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3978 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3979 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3980 } 3981 /* Set Rx descriptor counter. */ 3982 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3983 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3984 3985 /* 3986 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3987 * if it do not fit the buffer size. Rx return descriptor holds 3988 * a counter that indicates how many fragments were made by the 3989 * hardware. The buffer size should be multiple of 8 bytes. 3990 * Since hardware has limit on the size of buffer size, always 3991 * use the maximum value. 3992 * For strict-alignment architectures make sure to reduce buffer 3993 * size by 8 bytes to make room for alignment fixup. 3994 */ 3995 #ifndef __NO_STRICT_ALIGNMENT 3996 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3997 #else 3998 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3999 #endif 4000 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4001 4002 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4003 /* Set Rx return descriptor base addresses. */ 4004 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4005 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4006 /* We use one Rx return ring. */ 4007 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4008 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4009 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4010 } 4011 /* Set Rx return descriptor counter. */ 4012 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4013 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4014 paddr = sc->alc_rdata.alc_cmb_paddr; 4015 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4016 paddr = sc->alc_rdata.alc_smb_paddr; 4017 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4018 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4019 4020 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4021 /* Reconfigure SRAM - Vendor magic. */ 4022 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4023 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4024 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4025 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4026 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4027 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4028 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4029 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4030 } 4031 4032 /* Tell hardware that we're ready to load DMA blocks. */ 4033 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4034 4035 /* Configure interrupt moderation timer. */ 4036 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4037 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4038 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4039 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4040 /* 4041 * We don't want to automatic interrupt clear as task queue 4042 * for the interrupt should know interrupt status. 4043 */ 4044 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4045 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4046 reg |= MASTER_SA_TIMER_ENB; 4047 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4048 reg |= MASTER_IM_RX_TIMER_ENB; 4049 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4050 ALC_USECS(sc->alc_int_tx_mod) != 0) 4051 reg |= MASTER_IM_TX_TIMER_ENB; 4052 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4053 /* 4054 * Disable interrupt re-trigger timer. We don't want automatic 4055 * re-triggering of un-ACKed interrupts. 4056 */ 4057 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4058 /* Configure CMB. */ 4059 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4060 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4061 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4062 ALC_USECS(sc->alc_int_tx_mod)); 4063 } else { 4064 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4065 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4066 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4067 } else 4068 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4069 } 4070 /* 4071 * Hardware can be configured to issue SMB interrupt based 4072 * on programmed interval. Since there is a callout that is 4073 * invoked for every hz in driver we use that instead of 4074 * relying on periodic SMB interrupt. 4075 */ 4076 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4077 /* Clear MAC statistics. */ 4078 alc_stats_clear(sc); 4079 4080 /* 4081 * Always use maximum frame size that controller can support. 4082 * Otherwise received frames that has larger frame length 4083 * than alc(4) MTU would be silently dropped in hardware. This 4084 * would make path-MTU discovery hard as sender wouldn't get 4085 * any responses from receiver. alc(4) supports 4086 * multi-fragmented frames on Rx path so it has no issue on 4087 * assembling fragmented frames. Using maximum frame size also 4088 * removes the need to reinitialize hardware when interface 4089 * MTU configuration was changed. 4090 * 4091 * Be conservative in what you do, be liberal in what you 4092 * accept from others - RFC 793. 4093 */ 4094 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4095 4096 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4097 /* Disable header split(?) */ 4098 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4099 4100 /* Configure IPG/IFG parameters. */ 4101 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4102 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4103 IPG_IFG_IPGT_MASK) | 4104 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4105 IPG_IFG_MIFG_MASK) | 4106 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4107 IPG_IFG_IPG1_MASK) | 4108 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4109 IPG_IFG_IPG2_MASK)); 4110 /* Set parameters for half-duplex media. */ 4111 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4112 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4113 HDPX_CFG_LCOL_MASK) | 4114 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4115 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4116 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4117 HDPX_CFG_ABEBT_MASK) | 4118 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4119 HDPX_CFG_JAMIPG_MASK)); 4120 } 4121 4122 /* 4123 * Set TSO/checksum offload threshold. For frames that is 4124 * larger than this threshold, hardware wouldn't do 4125 * TSO/checksum offloading. 4126 */ 4127 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4128 TSO_OFFLOAD_THRESH_MASK; 4129 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4130 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4131 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4132 /* Configure TxQ. */ 4133 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4134 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4135 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4136 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4137 reg >>= 1; 4138 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4139 TXQ_CFG_TD_BURST_MASK; 4140 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4141 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4142 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4143 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4144 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4145 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4146 HQTD_CFG_BURST_ENB); 4147 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4148 reg = WRR_PRI_RESTRICT_NONE; 4149 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4150 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4151 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4152 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4153 CSR_WRITE_4(sc, ALC_WRR, reg); 4154 } else { 4155 /* Configure Rx free descriptor pre-fetching. */ 4156 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4157 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4158 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4159 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4160 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4161 } 4162 4163 /* 4164 * Configure flow control parameters. 4165 * XON : 80% of Rx FIFO 4166 * XOFF : 30% of Rx FIFO 4167 */ 4168 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4169 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4170 reg &= SRAM_RX_FIFO_LEN_MASK; 4171 reg *= 8; 4172 if (reg > 8 * 1024) 4173 reg -= RX_FIFO_PAUSE_816X_RSVD; 4174 else 4175 reg -= RX_BUF_SIZE_MAX; 4176 reg /= 8; 4177 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4178 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4179 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4180 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4181 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4182 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4183 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4184 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4185 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4186 rxf_hi = (reg * 8) / 10; 4187 rxf_lo = (reg * 3) / 10; 4188 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4189 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4190 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4191 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4192 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4193 } 4194 4195 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4196 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4197 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4198 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4199 } 4200 4201 /* Configure RxQ. */ 4202 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4203 RXQ_CFG_RD_BURST_MASK; 4204 reg |= RXQ_CFG_RSS_MODE_DIS; 4205 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4206 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4207 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4208 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4209 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4210 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4211 } else { 4212 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4213 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4214 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4215 } 4216 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4217 4218 /* Configure DMA parameters. */ 4219 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4220 reg |= sc->alc_rcb; 4221 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4222 reg |= DMA_CFG_CMB_ENB; 4223 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4224 reg |= DMA_CFG_SMB_ENB; 4225 else 4226 reg |= DMA_CFG_SMB_DIS; 4227 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4228 DMA_CFG_RD_BURST_SHIFT; 4229 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4230 DMA_CFG_WR_BURST_SHIFT; 4231 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4232 DMA_CFG_RD_DELAY_CNT_MASK; 4233 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4234 DMA_CFG_WR_DELAY_CNT_MASK; 4235 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4236 switch (AR816X_REV(sc->alc_rev)) { 4237 case AR816X_REV_A0: 4238 case AR816X_REV_A1: 4239 reg |= DMA_CFG_RD_CHNL_SEL_2; 4240 break; 4241 case AR816X_REV_B0: 4242 /* FALLTHROUGH */ 4243 default: 4244 reg |= DMA_CFG_RD_CHNL_SEL_4; 4245 break; 4246 } 4247 } 4248 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4249 4250 /* 4251 * Configure Tx/Rx MACs. 4252 * - Auto-padding for short frames. 4253 * - Enable CRC generation. 4254 * Actual reconfiguration of MAC for resolved speed/duplex 4255 * is followed after detection of link establishment. 4256 * AR813x/AR815x always does checksum computation regardless 4257 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4258 * have bug in protocol field in Rx return structure so 4259 * these controllers can't handle fragmented frames. Disable 4260 * Rx checksum offloading until there is a newer controller 4261 * that has sane implementation. 4262 */ 4263 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4264 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4265 MAC_CFG_PREAMBLE_MASK); 4266 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4267 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4268 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4269 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4270 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4271 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4272 reg |= MAC_CFG_SPEED_10_100; 4273 else 4274 reg |= MAC_CFG_SPEED_1000; 4275 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4276 4277 /* Set up the receive filter. */ 4278 alc_rxfilter(sc); 4279 alc_rxvlan(sc); 4280 4281 /* Acknowledge all pending interrupts and clear it. */ 4282 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4283 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4284 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4285 4286 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4287 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4288 4289 sc->alc_flags &= ~ALC_FLAG_LINK; 4290 /* Switch to the current media. */ 4291 alc_mediachange_locked(sc); 4292 4293 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4294 } 4295 4296 static void 4297 alc_stop(struct alc_softc *sc) 4298 { 4299 if_t ifp; 4300 struct alc_txdesc *txd; 4301 struct alc_rxdesc *rxd; 4302 uint32_t reg; 4303 int i; 4304 4305 ALC_LOCK_ASSERT(sc); 4306 /* 4307 * Mark the interface down and cancel the watchdog timer. 4308 */ 4309 ifp = sc->alc_ifp; 4310 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4311 sc->alc_flags &= ~ALC_FLAG_LINK; 4312 callout_stop(&sc->alc_tick_ch); 4313 sc->alc_watchdog_timer = 0; 4314 alc_stats_update(sc); 4315 /* Disable interrupts. */ 4316 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4317 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4318 /* Disable DMA. */ 4319 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4320 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4321 reg |= DMA_CFG_SMB_DIS; 4322 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4323 DELAY(1000); 4324 /* Stop Rx/Tx MACs. */ 4325 alc_stop_mac(sc); 4326 /* Disable interrupts which might be touched in taskq handler. */ 4327 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4328 /* Disable L0s/L1s */ 4329 alc_aspm(sc, 0, IFM_UNKNOWN); 4330 /* Reclaim Rx buffers that have been processed. */ 4331 if (sc->alc_cdata.alc_rxhead != NULL) 4332 m_freem(sc->alc_cdata.alc_rxhead); 4333 ALC_RXCHAIN_RESET(sc); 4334 /* 4335 * Free Tx/Rx mbufs still in the queues. 4336 */ 4337 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4338 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4339 if (rxd->rx_m != NULL) { 4340 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4341 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4342 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4343 rxd->rx_dmamap); 4344 m_freem(rxd->rx_m); 4345 rxd->rx_m = NULL; 4346 } 4347 } 4348 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4349 txd = &sc->alc_cdata.alc_txdesc[i]; 4350 if (txd->tx_m != NULL) { 4351 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4352 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4353 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4354 txd->tx_dmamap); 4355 m_freem(txd->tx_m); 4356 txd->tx_m = NULL; 4357 } 4358 } 4359 } 4360 4361 static void 4362 alc_stop_mac(struct alc_softc *sc) 4363 { 4364 uint32_t reg; 4365 int i; 4366 4367 alc_stop_queue(sc); 4368 /* Disable Rx/Tx MAC. */ 4369 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4370 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4371 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4372 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4373 } 4374 for (i = ALC_TIMEOUT; i > 0; i--) { 4375 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4376 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4377 break; 4378 DELAY(10); 4379 } 4380 if (i == 0) 4381 device_printf(sc->alc_dev, 4382 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4383 } 4384 4385 static void 4386 alc_start_queue(struct alc_softc *sc) 4387 { 4388 uint32_t qcfg[] = { 4389 0, 4390 RXQ_CFG_QUEUE0_ENB, 4391 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4392 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4393 RXQ_CFG_ENB 4394 }; 4395 uint32_t cfg; 4396 4397 ALC_LOCK_ASSERT(sc); 4398 4399 /* Enable RxQ. */ 4400 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4401 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4402 cfg &= ~RXQ_CFG_ENB; 4403 cfg |= qcfg[1]; 4404 } else 4405 cfg |= RXQ_CFG_QUEUE0_ENB; 4406 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4407 /* Enable TxQ. */ 4408 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4409 cfg |= TXQ_CFG_ENB; 4410 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4411 } 4412 4413 static void 4414 alc_stop_queue(struct alc_softc *sc) 4415 { 4416 uint32_t reg; 4417 int i; 4418 4419 /* Disable RxQ. */ 4420 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4421 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4422 if ((reg & RXQ_CFG_ENB) != 0) { 4423 reg &= ~RXQ_CFG_ENB; 4424 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4425 } 4426 } else { 4427 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4428 reg &= ~RXQ_CFG_QUEUE0_ENB; 4429 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4430 } 4431 } 4432 /* Disable TxQ. */ 4433 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4434 if ((reg & TXQ_CFG_ENB) != 0) { 4435 reg &= ~TXQ_CFG_ENB; 4436 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4437 } 4438 DELAY(40); 4439 for (i = ALC_TIMEOUT; i > 0; i--) { 4440 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4441 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4442 break; 4443 DELAY(10); 4444 } 4445 if (i == 0) 4446 device_printf(sc->alc_dev, 4447 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4448 } 4449 4450 static void 4451 alc_init_tx_ring(struct alc_softc *sc) 4452 { 4453 struct alc_ring_data *rd; 4454 struct alc_txdesc *txd; 4455 int i; 4456 4457 ALC_LOCK_ASSERT(sc); 4458 4459 sc->alc_cdata.alc_tx_prod = 0; 4460 sc->alc_cdata.alc_tx_cons = 0; 4461 sc->alc_cdata.alc_tx_cnt = 0; 4462 4463 rd = &sc->alc_rdata; 4464 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4465 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4466 txd = &sc->alc_cdata.alc_txdesc[i]; 4467 txd->tx_m = NULL; 4468 } 4469 4470 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4471 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4472 } 4473 4474 static int 4475 alc_init_rx_ring(struct alc_softc *sc) 4476 { 4477 struct alc_ring_data *rd; 4478 struct alc_rxdesc *rxd; 4479 int i; 4480 4481 ALC_LOCK_ASSERT(sc); 4482 4483 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4484 sc->alc_morework = 0; 4485 rd = &sc->alc_rdata; 4486 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4487 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4488 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4489 rxd->rx_m = NULL; 4490 rxd->rx_desc = &rd->alc_rx_ring[i]; 4491 if (alc_newbuf(sc, rxd) != 0) 4492 return (ENOBUFS); 4493 } 4494 4495 /* 4496 * Since controller does not update Rx descriptors, driver 4497 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4498 * is enough to ensure coherence. 4499 */ 4500 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4501 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4502 /* Let controller know availability of new Rx buffers. */ 4503 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4504 4505 return (0); 4506 } 4507 4508 static void 4509 alc_init_rr_ring(struct alc_softc *sc) 4510 { 4511 struct alc_ring_data *rd; 4512 4513 ALC_LOCK_ASSERT(sc); 4514 4515 sc->alc_cdata.alc_rr_cons = 0; 4516 ALC_RXCHAIN_RESET(sc); 4517 4518 rd = &sc->alc_rdata; 4519 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4520 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4521 sc->alc_cdata.alc_rr_ring_map, 4522 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4523 } 4524 4525 static void 4526 alc_init_cmb(struct alc_softc *sc) 4527 { 4528 struct alc_ring_data *rd; 4529 4530 ALC_LOCK_ASSERT(sc); 4531 4532 rd = &sc->alc_rdata; 4533 bzero(rd->alc_cmb, ALC_CMB_SZ); 4534 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4535 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4536 } 4537 4538 static void 4539 alc_init_smb(struct alc_softc *sc) 4540 { 4541 struct alc_ring_data *rd; 4542 4543 ALC_LOCK_ASSERT(sc); 4544 4545 rd = &sc->alc_rdata; 4546 bzero(rd->alc_smb, ALC_SMB_SZ); 4547 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4548 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4549 } 4550 4551 static void 4552 alc_rxvlan(struct alc_softc *sc) 4553 { 4554 if_t ifp; 4555 uint32_t reg; 4556 4557 ALC_LOCK_ASSERT(sc); 4558 4559 ifp = sc->alc_ifp; 4560 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4561 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4562 reg |= MAC_CFG_VLAN_TAG_STRIP; 4563 else 4564 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4565 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4566 } 4567 4568 static u_int 4569 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4570 { 4571 uint32_t *mchash = arg; 4572 uint32_t crc; 4573 4574 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4575 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4576 4577 return (1); 4578 } 4579 4580 static void 4581 alc_rxfilter(struct alc_softc *sc) 4582 { 4583 if_t ifp; 4584 uint32_t mchash[2]; 4585 uint32_t rxcfg; 4586 4587 ALC_LOCK_ASSERT(sc); 4588 4589 ifp = sc->alc_ifp; 4590 4591 bzero(mchash, sizeof(mchash)); 4592 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4593 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4594 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4595 rxcfg |= MAC_CFG_BCAST; 4596 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4597 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4598 rxcfg |= MAC_CFG_PROMISC; 4599 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4600 rxcfg |= MAC_CFG_ALLMULTI; 4601 mchash[0] = 0xFFFFFFFF; 4602 mchash[1] = 0xFFFFFFFF; 4603 goto chipit; 4604 } 4605 4606 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4607 4608 chipit: 4609 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4610 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4611 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4612 } 4613 4614 static int 4615 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4616 { 4617 int error, value; 4618 4619 if (arg1 == NULL) 4620 return (EINVAL); 4621 value = *(int *)arg1; 4622 error = sysctl_handle_int(oidp, &value, 0, req); 4623 if (error || req->newptr == NULL) 4624 return (error); 4625 if (value < low || value > high) 4626 return (EINVAL); 4627 *(int *)arg1 = value; 4628 4629 return (0); 4630 } 4631 4632 static int 4633 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4634 { 4635 return (sysctl_int_range(oidp, arg1, arg2, req, 4636 ALC_PROC_MIN, ALC_PROC_MAX)); 4637 } 4638 4639 static int 4640 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4641 { 4642 4643 return (sysctl_int_range(oidp, arg1, arg2, req, 4644 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4645 } 4646 4647 #ifdef DEBUGNET 4648 static void 4649 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4650 { 4651 struct alc_softc *sc __diagused; 4652 4653 sc = if_getsoftc(ifp); 4654 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4655 4656 *nrxr = ALC_RX_RING_CNT; 4657 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4658 *clsize = MCLBYTES; 4659 } 4660 4661 static void 4662 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4663 { 4664 } 4665 4666 static int 4667 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4668 { 4669 struct alc_softc *sc; 4670 int error; 4671 4672 sc = if_getsoftc(ifp); 4673 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4674 IFF_DRV_RUNNING) 4675 return (EBUSY); 4676 4677 error = alc_encap(sc, &m); 4678 if (error == 0) 4679 alc_start_tx(sc); 4680 return (error); 4681 } 4682 4683 static int 4684 alc_debugnet_poll(if_t ifp, int count) 4685 { 4686 struct alc_softc *sc; 4687 4688 sc = if_getsoftc(ifp); 4689 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4690 IFF_DRV_RUNNING) 4691 return (EBUSY); 4692 4693 alc_txeof(sc); 4694 return (alc_rxintr(sc, count)); 4695 } 4696 #endif /* DEBUGNET */ 4697