1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/debugnet.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 static int msix_disable = 0; 95 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98 /* 99 * Devices supported by this driver. 100 */ 101 static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 115 "Atheros AR8161 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 117 "Atheros AR8162 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 119 "Atheros AR8171 PCIe Gigabit Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 121 "Atheros AR8172 PCIe Fast Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 123 "Killer E2200 Gigabit Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 125 "Killer E2400 Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 127 "Killer E2500 Gigabit Ethernet" }, 128 { 0, 0, 0, NULL} 129 }; 130 131 static void alc_aspm(struct alc_softc *, int, int); 132 static void alc_aspm_813x(struct alc_softc *, int); 133 static void alc_aspm_816x(struct alc_softc *, int); 134 static int alc_attach(device_t); 135 static int alc_check_boundary(struct alc_softc *); 136 static void alc_config_msi(struct alc_softc *); 137 static int alc_detach(device_t); 138 static void alc_disable_l0s_l1(struct alc_softc *); 139 static int alc_dma_alloc(struct alc_softc *); 140 static void alc_dma_free(struct alc_softc *); 141 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 142 static void alc_dsp_fixup(struct alc_softc *, int); 143 static int alc_encap(struct alc_softc *, struct mbuf **); 144 static struct alc_ident * 145 alc_find_ident(device_t); 146 #ifndef __NO_STRICT_ALIGNMENT 147 static struct mbuf * 148 alc_fixup_rx(if_t, struct mbuf *); 149 #endif 150 static void alc_get_macaddr(struct alc_softc *); 151 static void alc_get_macaddr_813x(struct alc_softc *); 152 static void alc_get_macaddr_816x(struct alc_softc *); 153 static void alc_get_macaddr_par(struct alc_softc *); 154 static void alc_init(void *); 155 static void alc_init_cmb(struct alc_softc *); 156 static void alc_init_locked(struct alc_softc *); 157 static void alc_init_rr_ring(struct alc_softc *); 158 static int alc_init_rx_ring(struct alc_softc *); 159 static void alc_init_smb(struct alc_softc *); 160 static void alc_init_tx_ring(struct alc_softc *); 161 static void alc_int_task(void *, int); 162 static int alc_intr(void *); 163 static int alc_ioctl(if_t, u_long, caddr_t); 164 static void alc_mac_config(struct alc_softc *); 165 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 166 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 167 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 168 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 169 static int alc_miibus_readreg(device_t, int, int); 170 static void alc_miibus_statchg(device_t); 171 static int alc_miibus_writereg(device_t, int, int, int); 172 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 173 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 174 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 175 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 176 static int alc_mediachange(if_t); 177 static int alc_mediachange_locked(struct alc_softc *); 178 static void alc_mediastatus(if_t, struct ifmediareq *); 179 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 180 static void alc_osc_reset(struct alc_softc *); 181 static void alc_phy_down(struct alc_softc *); 182 static void alc_phy_reset(struct alc_softc *); 183 static void alc_phy_reset_813x(struct alc_softc *); 184 static void alc_phy_reset_816x(struct alc_softc *); 185 static int alc_probe(device_t); 186 static void alc_reset(struct alc_softc *); 187 static int alc_resume(device_t); 188 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 189 static int alc_rxintr(struct alc_softc *, int); 190 static void alc_rxfilter(struct alc_softc *); 191 static void alc_rxvlan(struct alc_softc *); 192 static void alc_setlinkspeed(struct alc_softc *); 193 static void alc_setwol(struct alc_softc *); 194 static void alc_setwol_813x(struct alc_softc *); 195 static void alc_setwol_816x(struct alc_softc *); 196 static int alc_shutdown(device_t); 197 static void alc_start(if_t); 198 static void alc_start_locked(if_t); 199 static void alc_start_queue(struct alc_softc *); 200 static void alc_start_tx(struct alc_softc *); 201 static void alc_stats_clear(struct alc_softc *); 202 static void alc_stats_update(struct alc_softc *); 203 static void alc_stop(struct alc_softc *); 204 static void alc_stop_mac(struct alc_softc *); 205 static void alc_stop_queue(struct alc_softc *); 206 static int alc_suspend(device_t); 207 static void alc_sysctl_node(struct alc_softc *); 208 static void alc_tick(void *); 209 static void alc_txeof(struct alc_softc *); 210 static void alc_watchdog(struct alc_softc *); 211 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 212 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 213 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 214 215 DEBUGNET_DEFINE(alc); 216 217 static device_method_t alc_methods[] = { 218 /* Device interface. */ 219 DEVMETHOD(device_probe, alc_probe), 220 DEVMETHOD(device_attach, alc_attach), 221 DEVMETHOD(device_detach, alc_detach), 222 DEVMETHOD(device_shutdown, alc_shutdown), 223 DEVMETHOD(device_suspend, alc_suspend), 224 DEVMETHOD(device_resume, alc_resume), 225 226 /* MII interface. */ 227 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 228 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 229 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 230 231 DEVMETHOD_END 232 }; 233 234 static driver_t alc_driver = { 235 "alc", 236 alc_methods, 237 sizeof(struct alc_softc) 238 }; 239 240 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 241 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 242 nitems(alc_ident_table) - 1); 243 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 244 245 static struct resource_spec alc_res_spec_mem[] = { 246 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 247 { -1, 0, 0 } 248 }; 249 250 static struct resource_spec alc_irq_spec_legacy[] = { 251 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 252 { -1, 0, 0 } 253 }; 254 255 static struct resource_spec alc_irq_spec_msi[] = { 256 { SYS_RES_IRQ, 1, RF_ACTIVE }, 257 { -1, 0, 0 } 258 }; 259 260 static struct resource_spec alc_irq_spec_msix[] = { 261 { SYS_RES_IRQ, 1, RF_ACTIVE }, 262 { -1, 0, 0 } 263 }; 264 265 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 266 267 static int 268 alc_miibus_readreg(device_t dev, int phy, int reg) 269 { 270 struct alc_softc *sc; 271 int v; 272 273 sc = device_get_softc(dev); 274 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 275 v = alc_mii_readreg_816x(sc, phy, reg); 276 else 277 v = alc_mii_readreg_813x(sc, phy, reg); 278 return (v); 279 } 280 281 static uint32_t 282 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 283 { 284 uint32_t v; 285 int i; 286 287 /* 288 * For AR8132 fast ethernet controller, do not report 1000baseT 289 * capability to mii(4). Even though AR8132 uses the same 290 * model/revision number of F1 gigabit PHY, the PHY has no 291 * ability to establish 1000baseT link. 292 */ 293 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 294 reg == MII_EXTSR) 295 return (0); 296 297 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 298 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 299 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 300 DELAY(5); 301 v = CSR_READ_4(sc, ALC_MDIO); 302 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 303 break; 304 } 305 306 if (i == 0) { 307 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 308 return (0); 309 } 310 311 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 312 } 313 314 static uint32_t 315 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 316 { 317 uint32_t clk, v; 318 int i; 319 320 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 321 clk = MDIO_CLK_25_128; 322 else 323 clk = MDIO_CLK_25_4; 324 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 325 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 326 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 327 DELAY(5); 328 v = CSR_READ_4(sc, ALC_MDIO); 329 if ((v & MDIO_OP_BUSY) == 0) 330 break; 331 } 332 333 if (i == 0) { 334 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 335 return (0); 336 } 337 338 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 339 } 340 341 static int 342 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 343 { 344 struct alc_softc *sc; 345 int v; 346 347 sc = device_get_softc(dev); 348 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 349 v = alc_mii_writereg_816x(sc, phy, reg, val); 350 else 351 v = alc_mii_writereg_813x(sc, phy, reg, val); 352 return (v); 353 } 354 355 static uint32_t 356 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 357 { 358 uint32_t v; 359 int i; 360 361 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 362 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 363 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 364 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 365 DELAY(5); 366 v = CSR_READ_4(sc, ALC_MDIO); 367 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 368 break; 369 } 370 371 if (i == 0) 372 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 373 374 return (0); 375 } 376 377 static uint32_t 378 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 379 { 380 uint32_t clk, v; 381 int i; 382 383 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 384 clk = MDIO_CLK_25_128; 385 else 386 clk = MDIO_CLK_25_4; 387 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 388 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 389 MDIO_SUP_PREAMBLE | clk); 390 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 391 DELAY(5); 392 v = CSR_READ_4(sc, ALC_MDIO); 393 if ((v & MDIO_OP_BUSY) == 0) 394 break; 395 } 396 397 if (i == 0) 398 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 399 400 return (0); 401 } 402 403 static void 404 alc_miibus_statchg(device_t dev) 405 { 406 struct alc_softc *sc; 407 struct mii_data *mii; 408 if_t ifp; 409 uint32_t reg; 410 411 sc = device_get_softc(dev); 412 413 mii = device_get_softc(sc->alc_miibus); 414 ifp = sc->alc_ifp; 415 if (mii == NULL || ifp == NULL || 416 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 417 return; 418 419 sc->alc_flags &= ~ALC_FLAG_LINK; 420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 421 (IFM_ACTIVE | IFM_AVALID)) { 422 switch (IFM_SUBTYPE(mii->mii_media_active)) { 423 case IFM_10_T: 424 case IFM_100_TX: 425 sc->alc_flags |= ALC_FLAG_LINK; 426 break; 427 case IFM_1000_T: 428 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 429 sc->alc_flags |= ALC_FLAG_LINK; 430 break; 431 default: 432 break; 433 } 434 } 435 /* Stop Rx/Tx MACs. */ 436 alc_stop_mac(sc); 437 438 /* Program MACs with resolved speed/duplex/flow-control. */ 439 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 440 alc_start_queue(sc); 441 alc_mac_config(sc); 442 /* Re-enable Tx/Rx MACs. */ 443 reg = CSR_READ_4(sc, ALC_MAC_CFG); 444 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 445 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 446 } 447 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 448 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 449 } 450 451 static uint32_t 452 alc_miidbg_readreg(struct alc_softc *sc, int reg) 453 { 454 455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 456 reg); 457 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 458 ALC_MII_DBG_DATA)); 459 } 460 461 static uint32_t 462 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 463 { 464 465 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 466 reg); 467 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 468 ALC_MII_DBG_DATA, val)); 469 } 470 471 static uint32_t 472 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 473 { 474 uint32_t clk, v; 475 int i; 476 477 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 478 EXT_MDIO_DEVADDR(devaddr)); 479 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 480 clk = MDIO_CLK_25_128; 481 else 482 clk = MDIO_CLK_25_4; 483 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 484 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 485 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 486 DELAY(5); 487 v = CSR_READ_4(sc, ALC_MDIO); 488 if ((v & MDIO_OP_BUSY) == 0) 489 break; 490 } 491 492 if (i == 0) { 493 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 494 devaddr, reg); 495 return (0); 496 } 497 498 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 499 } 500 501 static uint32_t 502 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 503 { 504 uint32_t clk, v; 505 int i; 506 507 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 508 EXT_MDIO_DEVADDR(devaddr)); 509 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 510 clk = MDIO_CLK_25_128; 511 else 512 clk = MDIO_CLK_25_4; 513 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 514 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 515 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 516 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 517 DELAY(5); 518 v = CSR_READ_4(sc, ALC_MDIO); 519 if ((v & MDIO_OP_BUSY) == 0) 520 break; 521 } 522 523 if (i == 0) 524 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 525 devaddr, reg); 526 527 return (0); 528 } 529 530 static void 531 alc_dsp_fixup(struct alc_softc *sc, int media) 532 { 533 uint16_t agc, len, val; 534 535 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 536 return; 537 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 538 return; 539 540 /* 541 * Vendor PHY magic. 542 * 1000BT/AZ, wrong cable length 543 */ 544 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 545 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 546 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 547 EXT_CLDCTL6_CAB_LEN_MASK; 548 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 549 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 550 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 551 agc > DBG_AGC_LONG1G_LIMT) || 552 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 553 agc > DBG_AGC_LONG1G_LIMT)) { 554 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 555 DBG_AZ_ANADECT_LONG); 556 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 557 MII_EXT_ANEG_AFE); 558 val |= ANEG_AFEE_10BT_100M_TH; 559 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 560 val); 561 } else { 562 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 563 DBG_AZ_ANADECT_DEFAULT); 564 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 565 MII_EXT_ANEG_AFE); 566 val &= ~ANEG_AFEE_10BT_100M_TH; 567 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 568 val); 569 } 570 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 571 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 572 if (media == IFM_1000_T) { 573 /* 574 * Giga link threshold, raise the tolerance of 575 * noise 50%. 576 */ 577 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 578 val &= ~DBG_MSE20DB_TH_MASK; 579 val |= (DBG_MSE20DB_TH_HI << 580 DBG_MSE20DB_TH_SHIFT); 581 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 582 } else if (media == IFM_100_TX) 583 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 584 DBG_MSE16DB_UP); 585 } 586 } else { 587 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 588 val &= ~ANEG_AFEE_10BT_100M_TH; 589 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 590 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 591 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 592 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 593 DBG_MSE16DB_DOWN); 594 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 595 val &= ~DBG_MSE20DB_TH_MASK; 596 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 597 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 598 } 599 } 600 } 601 602 static void 603 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 604 { 605 struct alc_softc *sc; 606 struct mii_data *mii; 607 608 sc = if_getsoftc(ifp); 609 ALC_LOCK(sc); 610 if ((if_getflags(ifp) & IFF_UP) == 0) { 611 ALC_UNLOCK(sc); 612 return; 613 } 614 mii = device_get_softc(sc->alc_miibus); 615 616 mii_pollstat(mii); 617 ifmr->ifm_status = mii->mii_media_status; 618 ifmr->ifm_active = mii->mii_media_active; 619 ALC_UNLOCK(sc); 620 } 621 622 static int 623 alc_mediachange(if_t ifp) 624 { 625 struct alc_softc *sc; 626 int error; 627 628 sc = if_getsoftc(ifp); 629 ALC_LOCK(sc); 630 error = alc_mediachange_locked(sc); 631 ALC_UNLOCK(sc); 632 633 return (error); 634 } 635 636 static int 637 alc_mediachange_locked(struct alc_softc *sc) 638 { 639 struct mii_data *mii; 640 struct mii_softc *miisc; 641 int error; 642 643 ALC_LOCK_ASSERT(sc); 644 645 mii = device_get_softc(sc->alc_miibus); 646 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 647 PHY_RESET(miisc); 648 error = mii_mediachg(mii); 649 650 return (error); 651 } 652 653 static struct alc_ident * 654 alc_find_ident(device_t dev) 655 { 656 struct alc_ident *ident; 657 uint16_t vendor, devid; 658 659 vendor = pci_get_vendor(dev); 660 devid = pci_get_device(dev); 661 for (ident = alc_ident_table; ident->name != NULL; ident++) { 662 if (vendor == ident->vendorid && devid == ident->deviceid) 663 return (ident); 664 } 665 666 return (NULL); 667 } 668 669 static int 670 alc_probe(device_t dev) 671 { 672 struct alc_ident *ident; 673 674 ident = alc_find_ident(dev); 675 if (ident != NULL) { 676 device_set_desc(dev, ident->name); 677 return (BUS_PROBE_DEFAULT); 678 } 679 680 return (ENXIO); 681 } 682 683 static void 684 alc_get_macaddr(struct alc_softc *sc) 685 { 686 687 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 688 alc_get_macaddr_816x(sc); 689 else 690 alc_get_macaddr_813x(sc); 691 } 692 693 static void 694 alc_get_macaddr_813x(struct alc_softc *sc) 695 { 696 uint32_t opt; 697 uint16_t val; 698 int eeprom, i; 699 700 eeprom = 0; 701 opt = CSR_READ_4(sc, ALC_OPT_CFG); 702 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 703 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 704 /* 705 * EEPROM found, let TWSI reload EEPROM configuration. 706 * This will set ethernet address of controller. 707 */ 708 eeprom++; 709 switch (sc->alc_ident->deviceid) { 710 case DEVICEID_ATHEROS_AR8131: 711 case DEVICEID_ATHEROS_AR8132: 712 if ((opt & OPT_CFG_CLK_ENB) == 0) { 713 opt |= OPT_CFG_CLK_ENB; 714 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 715 CSR_READ_4(sc, ALC_OPT_CFG); 716 DELAY(1000); 717 } 718 break; 719 case DEVICEID_ATHEROS_AR8151: 720 case DEVICEID_ATHEROS_AR8151_V2: 721 case DEVICEID_ATHEROS_AR8152_B: 722 case DEVICEID_ATHEROS_AR8152_B2: 723 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 724 ALC_MII_DBG_ADDR, 0x00); 725 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 726 ALC_MII_DBG_DATA); 727 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 728 ALC_MII_DBG_DATA, val & 0xFF7F); 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_ADDR, 0x3B); 731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 732 ALC_MII_DBG_DATA); 733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 734 ALC_MII_DBG_DATA, val | 0x0008); 735 DELAY(20); 736 break; 737 } 738 739 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 740 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 741 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 742 CSR_READ_4(sc, ALC_WOL_CFG); 743 744 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 745 TWSI_CFG_SW_LD_START); 746 for (i = 100; i > 0; i--) { 747 DELAY(1000); 748 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 749 TWSI_CFG_SW_LD_START) == 0) 750 break; 751 } 752 if (i == 0) 753 device_printf(sc->alc_dev, 754 "reloading EEPROM timeout!\n"); 755 } else { 756 if (bootverbose) 757 device_printf(sc->alc_dev, "EEPROM not found!\n"); 758 } 759 if (eeprom != 0) { 760 switch (sc->alc_ident->deviceid) { 761 case DEVICEID_ATHEROS_AR8131: 762 case DEVICEID_ATHEROS_AR8132: 763 if ((opt & OPT_CFG_CLK_ENB) != 0) { 764 opt &= ~OPT_CFG_CLK_ENB; 765 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 766 CSR_READ_4(sc, ALC_OPT_CFG); 767 DELAY(1000); 768 } 769 break; 770 case DEVICEID_ATHEROS_AR8151: 771 case DEVICEID_ATHEROS_AR8151_V2: 772 case DEVICEID_ATHEROS_AR8152_B: 773 case DEVICEID_ATHEROS_AR8152_B2: 774 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 775 ALC_MII_DBG_ADDR, 0x00); 776 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 777 ALC_MII_DBG_DATA); 778 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 779 ALC_MII_DBG_DATA, val | 0x0080); 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_ADDR, 0x3B); 782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 783 ALC_MII_DBG_DATA); 784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 785 ALC_MII_DBG_DATA, val & 0xFFF7); 786 DELAY(20); 787 break; 788 } 789 } 790 791 alc_get_macaddr_par(sc); 792 } 793 794 static void 795 alc_get_macaddr_816x(struct alc_softc *sc) 796 { 797 uint32_t reg; 798 int i, reloaded; 799 800 reloaded = 0; 801 /* Try to reload station address via TWSI. */ 802 for (i = 100; i > 0; i--) { 803 reg = CSR_READ_4(sc, ALC_SLD); 804 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 805 break; 806 DELAY(1000); 807 } 808 if (i != 0) { 809 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 810 for (i = 100; i > 0; i--) { 811 DELAY(1000); 812 reg = CSR_READ_4(sc, ALC_SLD); 813 if ((reg & SLD_START) == 0) 814 break; 815 } 816 if (i != 0) 817 reloaded++; 818 else if (bootverbose) 819 device_printf(sc->alc_dev, 820 "reloading station address via TWSI timed out!\n"); 821 } 822 823 /* Try to reload station address from EEPROM or FLASH. */ 824 if (reloaded == 0) { 825 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 826 if ((reg & (EEPROM_LD_EEPROM_EXIST | 827 EEPROM_LD_FLASH_EXIST)) != 0) { 828 for (i = 100; i > 0; i--) { 829 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 830 if ((reg & (EEPROM_LD_PROGRESS | 831 EEPROM_LD_START)) == 0) 832 break; 833 DELAY(1000); 834 } 835 if (i != 0) { 836 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 837 EEPROM_LD_START); 838 for (i = 100; i > 0; i--) { 839 DELAY(1000); 840 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 841 if ((reg & EEPROM_LD_START) == 0) 842 break; 843 } 844 } else if (bootverbose) 845 device_printf(sc->alc_dev, 846 "reloading EEPROM/FLASH timed out!\n"); 847 } 848 } 849 850 alc_get_macaddr_par(sc); 851 } 852 853 static void 854 alc_get_macaddr_par(struct alc_softc *sc) 855 { 856 uint32_t ea[2]; 857 858 ea[0] = CSR_READ_4(sc, ALC_PAR0); 859 ea[1] = CSR_READ_4(sc, ALC_PAR1); 860 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 861 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 862 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 863 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 864 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 865 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 866 } 867 868 static void 869 alc_disable_l0s_l1(struct alc_softc *sc) 870 { 871 uint32_t pmcfg; 872 873 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 874 /* Another magic from vendor. */ 875 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 876 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 877 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 878 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 879 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 880 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 881 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 882 } 883 } 884 885 static void 886 alc_phy_reset(struct alc_softc *sc) 887 { 888 889 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 890 alc_phy_reset_816x(sc); 891 else 892 alc_phy_reset_813x(sc); 893 } 894 895 static void 896 alc_phy_reset_813x(struct alc_softc *sc) 897 { 898 uint16_t data; 899 900 /* Reset magic from Linux. */ 901 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 902 CSR_READ_2(sc, ALC_GPHY_CFG); 903 DELAY(10 * 1000); 904 905 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 906 GPHY_CFG_SEL_ANA_RESET); 907 CSR_READ_2(sc, ALC_GPHY_CFG); 908 DELAY(10 * 1000); 909 910 /* DSP fixup, Vendor magic. */ 911 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 912 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 913 ALC_MII_DBG_ADDR, 0x000A); 914 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 915 ALC_MII_DBG_DATA); 916 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 917 ALC_MII_DBG_DATA, data & 0xDFFF); 918 } 919 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 920 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 921 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 922 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 923 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 924 ALC_MII_DBG_ADDR, 0x003B); 925 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 926 ALC_MII_DBG_DATA); 927 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 928 ALC_MII_DBG_DATA, data & 0xFFF7); 929 DELAY(20 * 1000); 930 } 931 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 932 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 933 ALC_MII_DBG_ADDR, 0x0029); 934 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 935 ALC_MII_DBG_DATA, 0x929D); 936 } 937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 938 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 939 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 940 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 941 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 942 ALC_MII_DBG_ADDR, 0x0029); 943 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 944 ALC_MII_DBG_DATA, 0xB6DD); 945 } 946 947 /* Load DSP codes, vendor magic. */ 948 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 949 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 950 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 951 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 952 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 953 ALC_MII_DBG_DATA, data); 954 955 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 956 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 957 ANA_SERDES_EN_LCKDT; 958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 959 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 960 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 961 ALC_MII_DBG_DATA, data); 962 963 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 964 ANA_LONG_CABLE_TH_100_MASK) | 965 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 966 ANA_SHORT_CABLE_TH_100_SHIFT) | 967 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 968 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 969 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 970 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 971 ALC_MII_DBG_DATA, data); 972 973 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 974 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 975 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 976 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 977 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 978 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 979 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 980 ALC_MII_DBG_DATA, data); 981 982 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 983 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 984 ANA_OEN_125M; 985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 986 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 987 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 988 ALC_MII_DBG_DATA, data); 989 DELAY(1000); 990 991 /* Disable hibernation. */ 992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 993 0x0029); 994 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 995 ALC_MII_DBG_DATA); 996 data &= ~0x8000; 997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 998 data); 999 1000 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1001 0x000B); 1002 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1003 ALC_MII_DBG_DATA); 1004 data &= ~0x8000; 1005 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1006 data); 1007 } 1008 1009 static void 1010 alc_phy_reset_816x(struct alc_softc *sc) 1011 { 1012 uint32_t val; 1013 1014 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1015 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1016 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1017 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1018 val |= GPHY_CFG_SEL_ANA_RESET; 1019 #ifdef notyet 1020 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1021 #else 1022 /* Disable PHY hibernation. */ 1023 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1024 #endif 1025 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1026 DELAY(10); 1027 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1028 DELAY(800); 1029 1030 /* Vendor PHY magic. */ 1031 #ifdef notyet 1032 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1033 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1034 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1035 EXT_VDRVBIAS_DEFAULT); 1036 #else 1037 /* Disable PHY hibernation. */ 1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1039 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1040 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1041 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1042 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1043 #endif 1044 1045 /* XXX Disable EEE. */ 1046 val = CSR_READ_4(sc, ALC_LPI_CTL); 1047 val &= ~LPI_CTL_ENB; 1048 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1049 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1050 1051 /* PHY power saving. */ 1052 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1053 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1054 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1055 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1056 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1057 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1058 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1059 1060 /* RTL8139C, 120m issue. */ 1061 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1062 ANEG_NLP78_120M_DEFAULT); 1063 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1064 ANEG_S3DIG10_DEFAULT); 1065 1066 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1067 /* Turn off half amplitude. */ 1068 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1069 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1070 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1071 /* Turn off Green feature. */ 1072 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1073 val |= DBG_GREENCFG2_BP_GREEN; 1074 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1075 /* Turn off half bias. */ 1076 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1077 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1078 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1079 } 1080 } 1081 1082 static void 1083 alc_phy_down(struct alc_softc *sc) 1084 { 1085 uint32_t gphy; 1086 1087 switch (sc->alc_ident->deviceid) { 1088 case DEVICEID_ATHEROS_AR8161: 1089 case DEVICEID_ATHEROS_E2200: 1090 case DEVICEID_ATHEROS_E2400: 1091 case DEVICEID_ATHEROS_E2500: 1092 case DEVICEID_ATHEROS_AR8162: 1093 case DEVICEID_ATHEROS_AR8171: 1094 case DEVICEID_ATHEROS_AR8172: 1095 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1096 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1097 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1098 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1099 GPHY_CFG_SEL_ANA_RESET; 1100 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1101 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1102 break; 1103 case DEVICEID_ATHEROS_AR8151: 1104 case DEVICEID_ATHEROS_AR8151_V2: 1105 case DEVICEID_ATHEROS_AR8152_B: 1106 case DEVICEID_ATHEROS_AR8152_B2: 1107 /* 1108 * GPHY power down caused more problems on AR8151 v2.0. 1109 * When driver is reloaded after GPHY power down, 1110 * accesses to PHY/MAC registers hung the system. Only 1111 * cold boot recovered from it. I'm not sure whether 1112 * AR8151 v1.0 also requires this one though. I don't 1113 * have AR8151 v1.0 controller in hand. 1114 * The only option left is to isolate the PHY and 1115 * initiates power down the PHY which in turn saves 1116 * more power when driver is unloaded. 1117 */ 1118 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1119 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1120 break; 1121 default: 1122 /* Force PHY down. */ 1123 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1124 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1125 GPHY_CFG_PWDOWN_HW); 1126 DELAY(1000); 1127 break; 1128 } 1129 } 1130 1131 static void 1132 alc_aspm(struct alc_softc *sc, int init, int media) 1133 { 1134 1135 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1136 alc_aspm_816x(sc, init); 1137 else 1138 alc_aspm_813x(sc, media); 1139 } 1140 1141 static void 1142 alc_aspm_813x(struct alc_softc *sc, int media) 1143 { 1144 uint32_t pmcfg; 1145 uint16_t linkcfg; 1146 1147 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1148 return; 1149 1150 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1151 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1152 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1153 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1154 PCIER_LINK_CTL); 1155 else 1156 linkcfg = 0; 1157 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1158 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1159 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1160 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1161 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1162 1163 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1164 /* Disable extended sync except AR8152 B v1.0 */ 1165 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1166 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1167 sc->alc_rev == ATHEROS_AR8152_B_V10) 1168 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1169 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1170 linkcfg); 1171 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1172 PM_CFG_HOTRST); 1173 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1174 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1175 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1176 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1177 PM_CFG_PM_REQ_TIMER_SHIFT); 1178 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1179 } 1180 1181 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1182 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1183 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1184 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1185 pmcfg |= PM_CFG_ASPM_L1_ENB; 1186 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1187 if (sc->alc_ident->deviceid == 1188 DEVICEID_ATHEROS_AR8152_B) 1189 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1190 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1191 PM_CFG_SERDES_PLL_L1_ENB | 1192 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1193 pmcfg |= PM_CFG_CLK_SWH_L1; 1194 if (media == IFM_100_TX || media == IFM_1000_T) { 1195 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1196 switch (sc->alc_ident->deviceid) { 1197 case DEVICEID_ATHEROS_AR8152_B: 1198 pmcfg |= (7 << 1199 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1200 break; 1201 case DEVICEID_ATHEROS_AR8152_B2: 1202 case DEVICEID_ATHEROS_AR8151_V2: 1203 pmcfg |= (4 << 1204 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1205 break; 1206 default: 1207 pmcfg |= (15 << 1208 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1209 break; 1210 } 1211 } 1212 } else { 1213 pmcfg |= PM_CFG_SERDES_L1_ENB | 1214 PM_CFG_SERDES_PLL_L1_ENB | 1215 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1216 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1217 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1218 } 1219 } else { 1220 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1221 PM_CFG_SERDES_PLL_L1_ENB); 1222 pmcfg |= PM_CFG_CLK_SWH_L1; 1223 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1224 pmcfg |= PM_CFG_ASPM_L1_ENB; 1225 } 1226 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1227 } 1228 1229 static void 1230 alc_aspm_816x(struct alc_softc *sc, int init) 1231 { 1232 uint32_t pmcfg; 1233 1234 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1235 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1236 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1237 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1238 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1239 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1240 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1241 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1242 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1243 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1244 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1245 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1246 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1247 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1248 (sc->alc_rev & 0x01) != 0) 1249 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1250 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1251 /* Link up, enable both L0s, L1s. */ 1252 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1253 PM_CFG_MAC_ASPM_CHK; 1254 } else { 1255 if (init != 0) 1256 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1257 PM_CFG_MAC_ASPM_CHK; 1258 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1259 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1260 } 1261 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1262 } 1263 1264 static void 1265 alc_init_pcie(struct alc_softc *sc) 1266 { 1267 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1268 uint32_t cap, ctl, val; 1269 int state; 1270 1271 /* Clear data link and flow-control protocol error. */ 1272 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1273 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1274 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1275 1276 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1277 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1278 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1279 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1280 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1281 PCIE_PHYMISC_FORCE_RCV_DET); 1282 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1283 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1284 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1285 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1286 PCIE_PHYMISC2_SERDES_TH_MASK); 1287 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1288 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1289 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1290 } 1291 /* Disable ASPM L0S and L1. */ 1292 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1293 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1294 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1295 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1296 sc->alc_rcb = DMA_CFG_RCB_128; 1297 if (bootverbose) 1298 device_printf(sc->alc_dev, "RCB %u bytes\n", 1299 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1300 state = ctl & PCIEM_LINK_CTL_ASPMC; 1301 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1302 sc->alc_flags |= ALC_FLAG_L0S; 1303 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1304 sc->alc_flags |= ALC_FLAG_L1S; 1305 if (bootverbose) 1306 device_printf(sc->alc_dev, "ASPM %s %s\n", 1307 aspm_state[state], 1308 state == 0 ? "disabled" : "enabled"); 1309 alc_disable_l0s_l1(sc); 1310 } else { 1311 if (bootverbose) 1312 device_printf(sc->alc_dev, 1313 "no ASPM support\n"); 1314 } 1315 } else { 1316 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1317 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1318 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1319 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1320 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1321 (sc->alc_rev & 0x01) != 0) { 1322 if ((val & MASTER_WAKEN_25M) == 0 || 1323 (val & MASTER_CLK_SEL_DIS) == 0) { 1324 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1325 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1326 } 1327 } else { 1328 if ((val & MASTER_WAKEN_25M) == 0 || 1329 (val & MASTER_CLK_SEL_DIS) != 0) { 1330 val |= MASTER_WAKEN_25M; 1331 val &= ~MASTER_CLK_SEL_DIS; 1332 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1333 } 1334 } 1335 } 1336 alc_aspm(sc, 1, IFM_UNKNOWN); 1337 } 1338 1339 static void 1340 alc_config_msi(struct alc_softc *sc) 1341 { 1342 uint32_t ctl, mod; 1343 1344 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1345 /* 1346 * It seems interrupt moderation is controlled by 1347 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1348 * Driver uses RX interrupt moderation parameter to 1349 * program ALC_MSI_RETRANS_TIMER register. 1350 */ 1351 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1352 ctl &= ~MSI_RETRANS_TIMER_MASK; 1353 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1354 mod = ALC_USECS(sc->alc_int_rx_mod); 1355 if (mod == 0) 1356 mod = 1; 1357 ctl |= mod; 1358 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1359 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1360 MSI_RETRANS_MASK_SEL_STD); 1361 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1362 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1363 MSI_RETRANS_MASK_SEL_LINE); 1364 else 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1366 } 1367 } 1368 1369 static int 1370 alc_attach(device_t dev) 1371 { 1372 struct alc_softc *sc; 1373 if_t ifp; 1374 int base, error, i, msic, msixc; 1375 uint16_t burst; 1376 1377 error = 0; 1378 sc = device_get_softc(dev); 1379 sc->alc_dev = dev; 1380 sc->alc_rev = pci_get_revid(dev); 1381 1382 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1383 MTX_DEF); 1384 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1385 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1386 sc->alc_ident = alc_find_ident(dev); 1387 1388 /* Map the device. */ 1389 pci_enable_busmaster(dev); 1390 sc->alc_res_spec = alc_res_spec_mem; 1391 sc->alc_irq_spec = alc_irq_spec_legacy; 1392 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1393 if (error != 0) { 1394 device_printf(dev, "cannot allocate memory resources.\n"); 1395 goto fail; 1396 } 1397 1398 /* Set PHY address. */ 1399 sc->alc_phyaddr = ALC_PHY_ADDR; 1400 1401 /* 1402 * One odd thing is AR8132 uses the same PHY hardware(F1 1403 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1404 * the PHY supports 1000Mbps but that's not true. The PHY 1405 * used in AR8132 can't establish gigabit link even if it 1406 * shows the same PHY model/revision number of AR8131. 1407 */ 1408 switch (sc->alc_ident->deviceid) { 1409 case DEVICEID_ATHEROS_E2200: 1410 case DEVICEID_ATHEROS_E2400: 1411 case DEVICEID_ATHEROS_E2500: 1412 sc->alc_flags |= ALC_FLAG_E2X00; 1413 /* FALLTHROUGH */ 1414 case DEVICEID_ATHEROS_AR8161: 1415 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1416 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1417 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1418 /* FALLTHROUGH */ 1419 case DEVICEID_ATHEROS_AR8171: 1420 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1421 break; 1422 case DEVICEID_ATHEROS_AR8162: 1423 case DEVICEID_ATHEROS_AR8172: 1424 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1425 break; 1426 case DEVICEID_ATHEROS_AR8152_B: 1427 case DEVICEID_ATHEROS_AR8152_B2: 1428 sc->alc_flags |= ALC_FLAG_APS; 1429 /* FALLTHROUGH */ 1430 case DEVICEID_ATHEROS_AR8132: 1431 sc->alc_flags |= ALC_FLAG_FASTETHER; 1432 break; 1433 case DEVICEID_ATHEROS_AR8151: 1434 case DEVICEID_ATHEROS_AR8151_V2: 1435 sc->alc_flags |= ALC_FLAG_APS; 1436 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1437 sc->alc_flags |= ALC_FLAG_MT; 1438 /* FALLTHROUGH */ 1439 default: 1440 break; 1441 } 1442 sc->alc_flags |= ALC_FLAG_JUMBO; 1443 1444 /* 1445 * It seems that AR813x/AR815x has silicon bug for SMB. In 1446 * addition, Atheros said that enabling SMB wouldn't improve 1447 * performance. However I think it's bad to access lots of 1448 * registers to extract MAC statistics. 1449 */ 1450 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1451 /* 1452 * Don't use Tx CMB. It is known to have silicon bug. 1453 */ 1454 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1455 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1456 MASTER_CHIP_REV_SHIFT; 1457 if (bootverbose) { 1458 device_printf(dev, "PCI device revision : 0x%04x\n", 1459 sc->alc_rev); 1460 device_printf(dev, "Chip id/revision : 0x%04x\n", 1461 sc->alc_chip_rev); 1462 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1463 device_printf(dev, "AR816x revision : 0x%x\n", 1464 AR816X_REV(sc->alc_rev)); 1465 } 1466 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1467 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1468 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1469 1470 /* Initialize DMA parameters. */ 1471 sc->alc_dma_rd_burst = 0; 1472 sc->alc_dma_wr_burst = 0; 1473 sc->alc_rcb = DMA_CFG_RCB_64; 1474 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1475 sc->alc_flags |= ALC_FLAG_PCIE; 1476 sc->alc_expcap = base; 1477 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1478 sc->alc_dma_rd_burst = 1479 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1480 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1481 if (bootverbose) { 1482 device_printf(dev, "Read request size : %u bytes.\n", 1483 alc_dma_burst[sc->alc_dma_rd_burst]); 1484 device_printf(dev, "TLP payload size : %u bytes.\n", 1485 alc_dma_burst[sc->alc_dma_wr_burst]); 1486 } 1487 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1488 sc->alc_dma_rd_burst = 3; 1489 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1490 sc->alc_dma_wr_burst = 3; 1491 /* 1492 * Force maximum payload size to 128 bytes for 1493 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1494 * Otherwise it triggers DMA write error. 1495 */ 1496 if ((sc->alc_flags & 1497 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1498 sc->alc_dma_wr_burst = 0; 1499 alc_init_pcie(sc); 1500 } 1501 1502 /* Reset PHY. */ 1503 alc_phy_reset(sc); 1504 1505 /* Reset the ethernet controller. */ 1506 alc_stop_mac(sc); 1507 alc_reset(sc); 1508 1509 /* Allocate IRQ resources. */ 1510 msixc = pci_msix_count(dev); 1511 msic = pci_msi_count(dev); 1512 if (bootverbose) { 1513 device_printf(dev, "MSIX count : %d\n", msixc); 1514 device_printf(dev, "MSI count : %d\n", msic); 1515 } 1516 if (msixc > 1) 1517 msixc = 1; 1518 if (msic > 1) 1519 msic = 1; 1520 /* 1521 * Prefer MSIX over MSI. 1522 * AR816x controller has a silicon bug that MSI interrupt 1523 * does not assert if PCIM_CMD_INTxDIS bit of command 1524 * register is set. pci(4) was taught to handle that case. 1525 */ 1526 if (msix_disable == 0 || msi_disable == 0) { 1527 if (msix_disable == 0 && msixc > 0 && 1528 pci_alloc_msix(dev, &msixc) == 0) { 1529 if (msic == 1) { 1530 device_printf(dev, 1531 "Using %d MSIX message(s).\n", msixc); 1532 sc->alc_flags |= ALC_FLAG_MSIX; 1533 sc->alc_irq_spec = alc_irq_spec_msix; 1534 } else 1535 pci_release_msi(dev); 1536 } 1537 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1538 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1539 if (msic == 1) { 1540 device_printf(dev, 1541 "Using %d MSI message(s).\n", msic); 1542 sc->alc_flags |= ALC_FLAG_MSI; 1543 sc->alc_irq_spec = alc_irq_spec_msi; 1544 } else 1545 pci_release_msi(dev); 1546 } 1547 } 1548 1549 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1550 if (error != 0) { 1551 device_printf(dev, "cannot allocate IRQ resources.\n"); 1552 goto fail; 1553 } 1554 1555 /* Create device sysctl node. */ 1556 alc_sysctl_node(sc); 1557 1558 if ((error = alc_dma_alloc(sc)) != 0) 1559 goto fail; 1560 1561 /* Load station address. */ 1562 alc_get_macaddr(sc); 1563 1564 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1565 if (ifp == NULL) { 1566 device_printf(dev, "cannot allocate ifnet structure.\n"); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 if_setsoftc(ifp, sc); 1572 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1573 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1574 if_setioctlfn(ifp, alc_ioctl); 1575 if_setstartfn(ifp, alc_start); 1576 if_setinitfn(ifp, alc_init); 1577 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1578 if_setsendqready(ifp); 1579 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1580 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1581 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1582 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1583 sc->alc_flags |= ALC_FLAG_PM; 1584 sc->alc_pmcap = base; 1585 } 1586 if_setcapenable(ifp, if_getcapabilities(ifp)); 1587 1588 /* Set up MII bus. */ 1589 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1590 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1591 MIIF_DOPAUSE); 1592 if (error != 0) { 1593 device_printf(dev, "attaching PHYs failed\n"); 1594 goto fail; 1595 } 1596 1597 ether_ifattach(ifp, sc->alc_eaddr); 1598 1599 /* VLAN capability setup. */ 1600 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1601 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1602 if_setcapenable(ifp, if_getcapabilities(ifp)); 1603 /* 1604 * XXX 1605 * It seems enabling Tx checksum offloading makes more trouble. 1606 * Sometimes the controller does not receive any frames when 1607 * Tx checksum offloading is enabled. I'm not sure whether this 1608 * is a bug in Tx checksum offloading logic or I got broken 1609 * sample boards. To safety, don't enable Tx checksum offloading 1610 * by default but give chance to users to toggle it if they know 1611 * their controllers work without problems. 1612 * Fortunately, Tx checksum offloading for AR816x family 1613 * seems to work. 1614 */ 1615 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1616 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1617 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1618 } 1619 1620 /* Tell the upper layer(s) we support long frames. */ 1621 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1622 1623 /* Create local taskq. */ 1624 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1625 taskqueue_thread_enqueue, &sc->alc_tq); 1626 if (sc->alc_tq == NULL) { 1627 device_printf(dev, "could not create taskqueue.\n"); 1628 ether_ifdetach(ifp); 1629 error = ENXIO; 1630 goto fail; 1631 } 1632 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1633 device_get_nameunit(sc->alc_dev)); 1634 1635 alc_config_msi(sc); 1636 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1637 msic = ALC_MSIX_MESSAGES; 1638 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1639 msic = ALC_MSI_MESSAGES; 1640 else 1641 msic = 1; 1642 for (i = 0; i < msic; i++) { 1643 error = bus_setup_intr(dev, sc->alc_irq[i], 1644 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1645 &sc->alc_intrhand[i]); 1646 if (error != 0) 1647 break; 1648 } 1649 if (error != 0) { 1650 device_printf(dev, "could not set up interrupt handler.\n"); 1651 taskqueue_free(sc->alc_tq); 1652 sc->alc_tq = NULL; 1653 ether_ifdetach(ifp); 1654 goto fail; 1655 } 1656 1657 /* Attach driver debugnet methods. */ 1658 DEBUGNET_SET(ifp, alc); 1659 1660 fail: 1661 if (error != 0) 1662 alc_detach(dev); 1663 1664 return (error); 1665 } 1666 1667 static int 1668 alc_detach(device_t dev) 1669 { 1670 struct alc_softc *sc; 1671 if_t ifp; 1672 int i, msic; 1673 1674 sc = device_get_softc(dev); 1675 1676 ifp = sc->alc_ifp; 1677 if (device_is_attached(dev)) { 1678 ether_ifdetach(ifp); 1679 ALC_LOCK(sc); 1680 alc_stop(sc); 1681 ALC_UNLOCK(sc); 1682 callout_drain(&sc->alc_tick_ch); 1683 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1684 } 1685 1686 if (sc->alc_tq != NULL) { 1687 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1688 taskqueue_free(sc->alc_tq); 1689 sc->alc_tq = NULL; 1690 } 1691 1692 if (sc->alc_miibus != NULL) { 1693 device_delete_child(dev, sc->alc_miibus); 1694 sc->alc_miibus = NULL; 1695 } 1696 bus_generic_detach(dev); 1697 alc_dma_free(sc); 1698 1699 if (ifp != NULL) { 1700 if_free(ifp); 1701 sc->alc_ifp = NULL; 1702 } 1703 1704 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1705 msic = ALC_MSIX_MESSAGES; 1706 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1707 msic = ALC_MSI_MESSAGES; 1708 else 1709 msic = 1; 1710 for (i = 0; i < msic; i++) { 1711 if (sc->alc_intrhand[i] != NULL) { 1712 bus_teardown_intr(dev, sc->alc_irq[i], 1713 sc->alc_intrhand[i]); 1714 sc->alc_intrhand[i] = NULL; 1715 } 1716 } 1717 if (sc->alc_res[0] != NULL) 1718 alc_phy_down(sc); 1719 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1720 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1721 pci_release_msi(dev); 1722 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1723 mtx_destroy(&sc->alc_mtx); 1724 1725 return (0); 1726 } 1727 1728 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1729 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1730 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1731 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1732 1733 static void 1734 alc_sysctl_node(struct alc_softc *sc) 1735 { 1736 struct sysctl_ctx_list *ctx; 1737 struct sysctl_oid_list *child, *parent; 1738 struct sysctl_oid *tree; 1739 struct alc_hw_stats *stats; 1740 int error; 1741 1742 stats = &sc->alc_stats; 1743 ctx = device_get_sysctl_ctx(sc->alc_dev); 1744 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1745 1746 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1747 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1748 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1749 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1750 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1751 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1752 /* Pull in device tunables. */ 1753 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1754 error = resource_int_value(device_get_name(sc->alc_dev), 1755 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1756 if (error == 0) { 1757 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1758 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1759 device_printf(sc->alc_dev, "int_rx_mod value out of " 1760 "range; using default: %d\n", 1761 ALC_IM_RX_TIMER_DEFAULT); 1762 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1763 } 1764 } 1765 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1766 error = resource_int_value(device_get_name(sc->alc_dev), 1767 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1768 if (error == 0) { 1769 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1770 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1771 device_printf(sc->alc_dev, "int_tx_mod value out of " 1772 "range; using default: %d\n", 1773 ALC_IM_TX_TIMER_DEFAULT); 1774 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1775 } 1776 } 1777 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1778 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1779 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1780 "max number of Rx events to process"); 1781 /* Pull in device tunables. */ 1782 sc->alc_process_limit = ALC_PROC_DEFAULT; 1783 error = resource_int_value(device_get_name(sc->alc_dev), 1784 device_get_unit(sc->alc_dev), "process_limit", 1785 &sc->alc_process_limit); 1786 if (error == 0) { 1787 if (sc->alc_process_limit < ALC_PROC_MIN || 1788 sc->alc_process_limit > ALC_PROC_MAX) { 1789 device_printf(sc->alc_dev, 1790 "process_limit value out of range; " 1791 "using default: %d\n", ALC_PROC_DEFAULT); 1792 sc->alc_process_limit = ALC_PROC_DEFAULT; 1793 } 1794 } 1795 1796 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1797 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1798 parent = SYSCTL_CHILDREN(tree); 1799 1800 /* Rx statistics. */ 1801 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1802 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1803 child = SYSCTL_CHILDREN(tree); 1804 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1805 &stats->rx_frames, "Good frames"); 1806 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1807 &stats->rx_bcast_frames, "Good broadcast frames"); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1809 &stats->rx_mcast_frames, "Good multicast frames"); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1811 &stats->rx_pause_frames, "Pause control frames"); 1812 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1813 &stats->rx_control_frames, "Control frames"); 1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1815 &stats->rx_crcerrs, "CRC errors"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1817 &stats->rx_lenerrs, "Frames with length mismatched"); 1818 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1819 &stats->rx_bytes, "Good octets"); 1820 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1821 &stats->rx_bcast_bytes, "Good broadcast octets"); 1822 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1823 &stats->rx_mcast_bytes, "Good multicast octets"); 1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1825 &stats->rx_runts, "Too short frames"); 1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1827 &stats->rx_fragments, "Fragmented frames"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1829 &stats->rx_pkts_64, "64 bytes frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1831 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1833 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1835 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1837 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1839 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1841 &stats->rx_pkts_1519_max, "1519 to max frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1843 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1845 &stats->rx_fifo_oflows, "FIFO overflows"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1847 &stats->rx_rrs_errs, "Return status write-back errors"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1849 &stats->rx_alignerrs, "Alignment errors"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1851 &stats->rx_pkts_filtered, 1852 "Frames dropped due to address filtering"); 1853 1854 /* Tx statistics. */ 1855 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1856 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1857 child = SYSCTL_CHILDREN(tree); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1859 &stats->tx_frames, "Good frames"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1861 &stats->tx_bcast_frames, "Good broadcast frames"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1863 &stats->tx_mcast_frames, "Good multicast frames"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1865 &stats->tx_pause_frames, "Pause control frames"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1867 &stats->tx_control_frames, "Control frames"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1869 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1871 &stats->tx_excess_defer, "Frames with derferrals"); 1872 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1873 &stats->tx_bytes, "Good octets"); 1874 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1875 &stats->tx_bcast_bytes, "Good broadcast octets"); 1876 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1877 &stats->tx_mcast_bytes, "Good multicast octets"); 1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1879 &stats->tx_pkts_64, "64 bytes frames"); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1881 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1883 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1885 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1887 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1889 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1891 &stats->tx_pkts_1519_max, "1519 to max frames"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1893 &stats->tx_single_colls, "Single collisions"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1895 &stats->tx_multi_colls, "Multiple collisions"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1897 &stats->tx_late_colls, "Late collisions"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1899 &stats->tx_excess_colls, "Excessive collisions"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1901 &stats->tx_underrun, "FIFO underruns"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1903 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1905 &stats->tx_lenerrs, "Frames with length mismatched"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1907 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1908 } 1909 1910 #undef ALC_SYSCTL_STAT_ADD32 1911 #undef ALC_SYSCTL_STAT_ADD64 1912 1913 struct alc_dmamap_arg { 1914 bus_addr_t alc_busaddr; 1915 }; 1916 1917 static void 1918 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1919 { 1920 struct alc_dmamap_arg *ctx; 1921 1922 if (error != 0) 1923 return; 1924 1925 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1926 1927 ctx = (struct alc_dmamap_arg *)arg; 1928 ctx->alc_busaddr = segs[0].ds_addr; 1929 } 1930 1931 /* 1932 * Normal and high Tx descriptors shares single Tx high address. 1933 * Four Rx descriptor/return rings and CMB shares the same Rx 1934 * high address. 1935 */ 1936 static int 1937 alc_check_boundary(struct alc_softc *sc) 1938 { 1939 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1940 1941 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1942 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1943 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1944 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1945 1946 /* 4GB boundary crossing is not allowed. */ 1947 if ((ALC_ADDR_HI(rx_ring_end) != 1948 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1949 (ALC_ADDR_HI(rr_ring_end) != 1950 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1951 (ALC_ADDR_HI(cmb_end) != 1952 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1953 (ALC_ADDR_HI(tx_ring_end) != 1954 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1955 return (EFBIG); 1956 /* 1957 * Make sure Rx return descriptor/Rx descriptor/CMB use 1958 * the same high address. 1959 */ 1960 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1961 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1962 return (EFBIG); 1963 1964 return (0); 1965 } 1966 1967 static int 1968 alc_dma_alloc(struct alc_softc *sc) 1969 { 1970 struct alc_txdesc *txd; 1971 struct alc_rxdesc *rxd; 1972 bus_addr_t lowaddr; 1973 struct alc_dmamap_arg ctx; 1974 int error, i; 1975 1976 lowaddr = BUS_SPACE_MAXADDR; 1977 if (sc->alc_flags & ALC_FLAG_MT) 1978 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1979 again: 1980 /* Create parent DMA tag. */ 1981 error = bus_dma_tag_create( 1982 bus_get_dma_tag(sc->alc_dev), /* parent */ 1983 1, 0, /* alignment, boundary */ 1984 lowaddr, /* lowaddr */ 1985 BUS_SPACE_MAXADDR, /* highaddr */ 1986 NULL, NULL, /* filter, filterarg */ 1987 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1988 0, /* nsegments */ 1989 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1990 0, /* flags */ 1991 NULL, NULL, /* lockfunc, lockarg */ 1992 &sc->alc_cdata.alc_parent_tag); 1993 if (error != 0) { 1994 device_printf(sc->alc_dev, 1995 "could not create parent DMA tag.\n"); 1996 goto fail; 1997 } 1998 1999 /* Create DMA tag for Tx descriptor ring. */ 2000 error = bus_dma_tag_create( 2001 sc->alc_cdata.alc_parent_tag, /* parent */ 2002 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2003 BUS_SPACE_MAXADDR, /* lowaddr */ 2004 BUS_SPACE_MAXADDR, /* highaddr */ 2005 NULL, NULL, /* filter, filterarg */ 2006 ALC_TX_RING_SZ, /* maxsize */ 2007 1, /* nsegments */ 2008 ALC_TX_RING_SZ, /* maxsegsize */ 2009 0, /* flags */ 2010 NULL, NULL, /* lockfunc, lockarg */ 2011 &sc->alc_cdata.alc_tx_ring_tag); 2012 if (error != 0) { 2013 device_printf(sc->alc_dev, 2014 "could not create Tx ring DMA tag.\n"); 2015 goto fail; 2016 } 2017 2018 /* Create DMA tag for Rx free descriptor ring. */ 2019 error = bus_dma_tag_create( 2020 sc->alc_cdata.alc_parent_tag, /* parent */ 2021 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2022 BUS_SPACE_MAXADDR, /* lowaddr */ 2023 BUS_SPACE_MAXADDR, /* highaddr */ 2024 NULL, NULL, /* filter, filterarg */ 2025 ALC_RX_RING_SZ, /* maxsize */ 2026 1, /* nsegments */ 2027 ALC_RX_RING_SZ, /* maxsegsize */ 2028 0, /* flags */ 2029 NULL, NULL, /* lockfunc, lockarg */ 2030 &sc->alc_cdata.alc_rx_ring_tag); 2031 if (error != 0) { 2032 device_printf(sc->alc_dev, 2033 "could not create Rx ring DMA tag.\n"); 2034 goto fail; 2035 } 2036 /* Create DMA tag for Rx return descriptor ring. */ 2037 error = bus_dma_tag_create( 2038 sc->alc_cdata.alc_parent_tag, /* parent */ 2039 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2040 BUS_SPACE_MAXADDR, /* lowaddr */ 2041 BUS_SPACE_MAXADDR, /* highaddr */ 2042 NULL, NULL, /* filter, filterarg */ 2043 ALC_RR_RING_SZ, /* maxsize */ 2044 1, /* nsegments */ 2045 ALC_RR_RING_SZ, /* maxsegsize */ 2046 0, /* flags */ 2047 NULL, NULL, /* lockfunc, lockarg */ 2048 &sc->alc_cdata.alc_rr_ring_tag); 2049 if (error != 0) { 2050 device_printf(sc->alc_dev, 2051 "could not create Rx return ring DMA tag.\n"); 2052 goto fail; 2053 } 2054 2055 /* Create DMA tag for coalescing message block. */ 2056 error = bus_dma_tag_create( 2057 sc->alc_cdata.alc_parent_tag, /* parent */ 2058 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2059 BUS_SPACE_MAXADDR, /* lowaddr */ 2060 BUS_SPACE_MAXADDR, /* highaddr */ 2061 NULL, NULL, /* filter, filterarg */ 2062 ALC_CMB_SZ, /* maxsize */ 2063 1, /* nsegments */ 2064 ALC_CMB_SZ, /* maxsegsize */ 2065 0, /* flags */ 2066 NULL, NULL, /* lockfunc, lockarg */ 2067 &sc->alc_cdata.alc_cmb_tag); 2068 if (error != 0) { 2069 device_printf(sc->alc_dev, 2070 "could not create CMB DMA tag.\n"); 2071 goto fail; 2072 } 2073 /* Create DMA tag for status message block. */ 2074 error = bus_dma_tag_create( 2075 sc->alc_cdata.alc_parent_tag, /* parent */ 2076 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2077 BUS_SPACE_MAXADDR, /* lowaddr */ 2078 BUS_SPACE_MAXADDR, /* highaddr */ 2079 NULL, NULL, /* filter, filterarg */ 2080 ALC_SMB_SZ, /* maxsize */ 2081 1, /* nsegments */ 2082 ALC_SMB_SZ, /* maxsegsize */ 2083 0, /* flags */ 2084 NULL, NULL, /* lockfunc, lockarg */ 2085 &sc->alc_cdata.alc_smb_tag); 2086 if (error != 0) { 2087 device_printf(sc->alc_dev, 2088 "could not create SMB DMA tag.\n"); 2089 goto fail; 2090 } 2091 2092 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2093 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2094 (void **)&sc->alc_rdata.alc_tx_ring, 2095 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2096 &sc->alc_cdata.alc_tx_ring_map); 2097 if (error != 0) { 2098 device_printf(sc->alc_dev, 2099 "could not allocate DMA'able memory for Tx ring.\n"); 2100 goto fail; 2101 } 2102 ctx.alc_busaddr = 0; 2103 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2104 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2105 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2106 if (error != 0 || ctx.alc_busaddr == 0) { 2107 device_printf(sc->alc_dev, 2108 "could not load DMA'able memory for Tx ring.\n"); 2109 goto fail; 2110 } 2111 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2112 2113 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2114 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2115 (void **)&sc->alc_rdata.alc_rx_ring, 2116 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2117 &sc->alc_cdata.alc_rx_ring_map); 2118 if (error != 0) { 2119 device_printf(sc->alc_dev, 2120 "could not allocate DMA'able memory for Rx ring.\n"); 2121 goto fail; 2122 } 2123 ctx.alc_busaddr = 0; 2124 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2125 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2126 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2127 if (error != 0 || ctx.alc_busaddr == 0) { 2128 device_printf(sc->alc_dev, 2129 "could not load DMA'able memory for Rx ring.\n"); 2130 goto fail; 2131 } 2132 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2133 2134 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2135 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2136 (void **)&sc->alc_rdata.alc_rr_ring, 2137 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2138 &sc->alc_cdata.alc_rr_ring_map); 2139 if (error != 0) { 2140 device_printf(sc->alc_dev, 2141 "could not allocate DMA'able memory for Rx return ring.\n"); 2142 goto fail; 2143 } 2144 ctx.alc_busaddr = 0; 2145 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2146 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2147 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2148 if (error != 0 || ctx.alc_busaddr == 0) { 2149 device_printf(sc->alc_dev, 2150 "could not load DMA'able memory for Tx ring.\n"); 2151 goto fail; 2152 } 2153 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2154 2155 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2156 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2157 (void **)&sc->alc_rdata.alc_cmb, 2158 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2159 &sc->alc_cdata.alc_cmb_map); 2160 if (error != 0) { 2161 device_printf(sc->alc_dev, 2162 "could not allocate DMA'able memory for CMB.\n"); 2163 goto fail; 2164 } 2165 ctx.alc_busaddr = 0; 2166 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2167 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2168 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2169 if (error != 0 || ctx.alc_busaddr == 0) { 2170 device_printf(sc->alc_dev, 2171 "could not load DMA'able memory for CMB.\n"); 2172 goto fail; 2173 } 2174 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2175 2176 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2177 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2178 (void **)&sc->alc_rdata.alc_smb, 2179 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2180 &sc->alc_cdata.alc_smb_map); 2181 if (error != 0) { 2182 device_printf(sc->alc_dev, 2183 "could not allocate DMA'able memory for SMB.\n"); 2184 goto fail; 2185 } 2186 ctx.alc_busaddr = 0; 2187 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2188 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2189 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2190 if (error != 0 || ctx.alc_busaddr == 0) { 2191 device_printf(sc->alc_dev, 2192 "could not load DMA'able memory for CMB.\n"); 2193 goto fail; 2194 } 2195 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2196 2197 /* Make sure we've not crossed 4GB boundary. */ 2198 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2199 (error = alc_check_boundary(sc)) != 0) { 2200 device_printf(sc->alc_dev, "4GB boundary crossed, " 2201 "switching to 32bit DMA addressing mode.\n"); 2202 alc_dma_free(sc); 2203 /* 2204 * Limit max allowable DMA address space to 32bit 2205 * and try again. 2206 */ 2207 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2208 goto again; 2209 } 2210 2211 /* 2212 * Create Tx buffer parent tag. 2213 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2214 * so it needs separate parent DMA tag as parent DMA address 2215 * space could be restricted to be within 32bit address space 2216 * by 4GB boundary crossing. 2217 */ 2218 error = bus_dma_tag_create( 2219 bus_get_dma_tag(sc->alc_dev), /* parent */ 2220 1, 0, /* alignment, boundary */ 2221 lowaddr, /* lowaddr */ 2222 BUS_SPACE_MAXADDR, /* highaddr */ 2223 NULL, NULL, /* filter, filterarg */ 2224 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2225 0, /* nsegments */ 2226 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2227 0, /* flags */ 2228 NULL, NULL, /* lockfunc, lockarg */ 2229 &sc->alc_cdata.alc_buffer_tag); 2230 if (error != 0) { 2231 device_printf(sc->alc_dev, 2232 "could not create parent buffer DMA tag.\n"); 2233 goto fail; 2234 } 2235 2236 /* Create DMA tag for Tx buffers. */ 2237 error = bus_dma_tag_create( 2238 sc->alc_cdata.alc_buffer_tag, /* parent */ 2239 1, 0, /* alignment, boundary */ 2240 BUS_SPACE_MAXADDR, /* lowaddr */ 2241 BUS_SPACE_MAXADDR, /* highaddr */ 2242 NULL, NULL, /* filter, filterarg */ 2243 ALC_TSO_MAXSIZE, /* maxsize */ 2244 ALC_MAXTXSEGS, /* nsegments */ 2245 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2246 0, /* flags */ 2247 NULL, NULL, /* lockfunc, lockarg */ 2248 &sc->alc_cdata.alc_tx_tag); 2249 if (error != 0) { 2250 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2251 goto fail; 2252 } 2253 2254 /* Create DMA tag for Rx buffers. */ 2255 error = bus_dma_tag_create( 2256 sc->alc_cdata.alc_buffer_tag, /* parent */ 2257 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2258 BUS_SPACE_MAXADDR, /* lowaddr */ 2259 BUS_SPACE_MAXADDR, /* highaddr */ 2260 NULL, NULL, /* filter, filterarg */ 2261 MCLBYTES, /* maxsize */ 2262 1, /* nsegments */ 2263 MCLBYTES, /* maxsegsize */ 2264 0, /* flags */ 2265 NULL, NULL, /* lockfunc, lockarg */ 2266 &sc->alc_cdata.alc_rx_tag); 2267 if (error != 0) { 2268 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2269 goto fail; 2270 } 2271 /* Create DMA maps for Tx buffers. */ 2272 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2273 txd = &sc->alc_cdata.alc_txdesc[i]; 2274 txd->tx_m = NULL; 2275 txd->tx_dmamap = NULL; 2276 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2277 &txd->tx_dmamap); 2278 if (error != 0) { 2279 device_printf(sc->alc_dev, 2280 "could not create Tx dmamap.\n"); 2281 goto fail; 2282 } 2283 } 2284 /* Create DMA maps for Rx buffers. */ 2285 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2286 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2287 device_printf(sc->alc_dev, 2288 "could not create spare Rx dmamap.\n"); 2289 goto fail; 2290 } 2291 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2292 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2293 rxd->rx_m = NULL; 2294 rxd->rx_dmamap = NULL; 2295 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2296 &rxd->rx_dmamap); 2297 if (error != 0) { 2298 device_printf(sc->alc_dev, 2299 "could not create Rx dmamap.\n"); 2300 goto fail; 2301 } 2302 } 2303 2304 fail: 2305 return (error); 2306 } 2307 2308 static void 2309 alc_dma_free(struct alc_softc *sc) 2310 { 2311 struct alc_txdesc *txd; 2312 struct alc_rxdesc *rxd; 2313 int i; 2314 2315 /* Tx buffers. */ 2316 if (sc->alc_cdata.alc_tx_tag != NULL) { 2317 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2318 txd = &sc->alc_cdata.alc_txdesc[i]; 2319 if (txd->tx_dmamap != NULL) { 2320 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2321 txd->tx_dmamap); 2322 txd->tx_dmamap = NULL; 2323 } 2324 } 2325 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2326 sc->alc_cdata.alc_tx_tag = NULL; 2327 } 2328 /* Rx buffers */ 2329 if (sc->alc_cdata.alc_rx_tag != NULL) { 2330 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2331 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2332 if (rxd->rx_dmamap != NULL) { 2333 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2334 rxd->rx_dmamap); 2335 rxd->rx_dmamap = NULL; 2336 } 2337 } 2338 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2339 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2340 sc->alc_cdata.alc_rx_sparemap); 2341 sc->alc_cdata.alc_rx_sparemap = NULL; 2342 } 2343 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2344 sc->alc_cdata.alc_rx_tag = NULL; 2345 } 2346 /* Tx descriptor ring. */ 2347 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2348 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2349 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2350 sc->alc_cdata.alc_tx_ring_map); 2351 if (sc->alc_rdata.alc_tx_ring != NULL) 2352 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2353 sc->alc_rdata.alc_tx_ring, 2354 sc->alc_cdata.alc_tx_ring_map); 2355 sc->alc_rdata.alc_tx_ring_paddr = 0; 2356 sc->alc_rdata.alc_tx_ring = NULL; 2357 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2358 sc->alc_cdata.alc_tx_ring_tag = NULL; 2359 } 2360 /* Rx ring. */ 2361 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2362 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2363 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2364 sc->alc_cdata.alc_rx_ring_map); 2365 if (sc->alc_rdata.alc_rx_ring != NULL) 2366 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2367 sc->alc_rdata.alc_rx_ring, 2368 sc->alc_cdata.alc_rx_ring_map); 2369 sc->alc_rdata.alc_rx_ring_paddr = 0; 2370 sc->alc_rdata.alc_rx_ring = NULL; 2371 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2372 sc->alc_cdata.alc_rx_ring_tag = NULL; 2373 } 2374 /* Rx return ring. */ 2375 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2376 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2377 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2378 sc->alc_cdata.alc_rr_ring_map); 2379 if (sc->alc_rdata.alc_rr_ring != NULL) 2380 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2381 sc->alc_rdata.alc_rr_ring, 2382 sc->alc_cdata.alc_rr_ring_map); 2383 sc->alc_rdata.alc_rr_ring_paddr = 0; 2384 sc->alc_rdata.alc_rr_ring = NULL; 2385 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2386 sc->alc_cdata.alc_rr_ring_tag = NULL; 2387 } 2388 /* CMB block */ 2389 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2390 if (sc->alc_rdata.alc_cmb_paddr != 0) 2391 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2392 sc->alc_cdata.alc_cmb_map); 2393 if (sc->alc_rdata.alc_cmb != NULL) 2394 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2395 sc->alc_rdata.alc_cmb, 2396 sc->alc_cdata.alc_cmb_map); 2397 sc->alc_rdata.alc_cmb_paddr = 0; 2398 sc->alc_rdata.alc_cmb = NULL; 2399 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2400 sc->alc_cdata.alc_cmb_tag = NULL; 2401 } 2402 /* SMB block */ 2403 if (sc->alc_cdata.alc_smb_tag != NULL) { 2404 if (sc->alc_rdata.alc_smb_paddr != 0) 2405 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2406 sc->alc_cdata.alc_smb_map); 2407 if (sc->alc_rdata.alc_smb != NULL) 2408 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2409 sc->alc_rdata.alc_smb, 2410 sc->alc_cdata.alc_smb_map); 2411 sc->alc_rdata.alc_smb_paddr = 0; 2412 sc->alc_rdata.alc_smb = NULL; 2413 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2414 sc->alc_cdata.alc_smb_tag = NULL; 2415 } 2416 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2417 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2418 sc->alc_cdata.alc_buffer_tag = NULL; 2419 } 2420 if (sc->alc_cdata.alc_parent_tag != NULL) { 2421 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2422 sc->alc_cdata.alc_parent_tag = NULL; 2423 } 2424 } 2425 2426 static int 2427 alc_shutdown(device_t dev) 2428 { 2429 2430 return (alc_suspend(dev)); 2431 } 2432 2433 /* 2434 * Note, this driver resets the link speed to 10/100Mbps by 2435 * restarting auto-negotiation in suspend/shutdown phase but we 2436 * don't know whether that auto-negotiation would succeed or not 2437 * as driver has no control after powering off/suspend operation. 2438 * If the renegotiation fail WOL may not work. Running at 1Gbps 2439 * will draw more power than 375mA at 3.3V which is specified in 2440 * PCI specification and that would result in complete 2441 * shutdowning power to ethernet controller. 2442 * 2443 * TODO 2444 * Save current negotiated media speed/duplex/flow-control to 2445 * softc and restore the same link again after resuming. PHY 2446 * handling such as power down/resetting to 100Mbps may be better 2447 * handled in suspend method in phy driver. 2448 */ 2449 static void 2450 alc_setlinkspeed(struct alc_softc *sc) 2451 { 2452 struct mii_data *mii; 2453 int aneg, i; 2454 2455 mii = device_get_softc(sc->alc_miibus); 2456 mii_pollstat(mii); 2457 aneg = 0; 2458 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2459 (IFM_ACTIVE | IFM_AVALID)) { 2460 switch IFM_SUBTYPE(mii->mii_media_active) { 2461 case IFM_10_T: 2462 case IFM_100_TX: 2463 return; 2464 case IFM_1000_T: 2465 aneg++; 2466 break; 2467 default: 2468 break; 2469 } 2470 } 2471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2472 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2473 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2474 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2475 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2476 DELAY(1000); 2477 if (aneg != 0) { 2478 /* 2479 * Poll link state until alc(4) get a 10/100Mbps link. 2480 */ 2481 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2482 mii_pollstat(mii); 2483 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2484 == (IFM_ACTIVE | IFM_AVALID)) { 2485 switch (IFM_SUBTYPE( 2486 mii->mii_media_active)) { 2487 case IFM_10_T: 2488 case IFM_100_TX: 2489 alc_mac_config(sc); 2490 return; 2491 default: 2492 break; 2493 } 2494 } 2495 ALC_UNLOCK(sc); 2496 pause("alclnk", hz); 2497 ALC_LOCK(sc); 2498 } 2499 if (i == MII_ANEGTICKS_GIGE) 2500 device_printf(sc->alc_dev, 2501 "establishing a link failed, WOL may not work!"); 2502 } 2503 /* 2504 * No link, force MAC to have 100Mbps, full-duplex link. 2505 * This is the last resort and may/may not work. 2506 */ 2507 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2508 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2509 alc_mac_config(sc); 2510 } 2511 2512 static void 2513 alc_setwol(struct alc_softc *sc) 2514 { 2515 2516 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2517 alc_setwol_816x(sc); 2518 else 2519 alc_setwol_813x(sc); 2520 } 2521 2522 static void 2523 alc_setwol_813x(struct alc_softc *sc) 2524 { 2525 if_t ifp; 2526 uint32_t reg, pmcs; 2527 uint16_t pmstat; 2528 2529 ALC_LOCK_ASSERT(sc); 2530 2531 alc_disable_l0s_l1(sc); 2532 ifp = sc->alc_ifp; 2533 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2534 /* Disable WOL. */ 2535 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2536 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2537 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2538 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2539 /* Force PHY power down. */ 2540 alc_phy_down(sc); 2541 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2542 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2543 return; 2544 } 2545 2546 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2547 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2548 alc_setlinkspeed(sc); 2549 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2550 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2551 } 2552 2553 pmcs = 0; 2554 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2555 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2556 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2557 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2558 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2559 MAC_CFG_BCAST); 2560 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2561 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2562 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2563 reg |= MAC_CFG_RX_ENB; 2564 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2565 2566 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2567 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2568 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2569 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2570 /* WOL disabled, PHY power down. */ 2571 alc_phy_down(sc); 2572 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2573 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2574 } 2575 /* Request PME. */ 2576 pmstat = pci_read_config(sc->alc_dev, 2577 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2578 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2579 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2580 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2581 pci_write_config(sc->alc_dev, 2582 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2583 } 2584 2585 static void 2586 alc_setwol_816x(struct alc_softc *sc) 2587 { 2588 if_t ifp; 2589 uint32_t gphy, mac, master, pmcs, reg; 2590 uint16_t pmstat; 2591 2592 ALC_LOCK_ASSERT(sc); 2593 2594 ifp = sc->alc_ifp; 2595 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2596 master &= ~MASTER_CLK_SEL_DIS; 2597 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2598 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2599 GPHY_CFG_PHY_PLL_ON); 2600 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2601 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2602 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2603 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2604 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2605 } else { 2606 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2607 gphy |= GPHY_CFG_EXT_RESET; 2608 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2609 alc_setlinkspeed(sc); 2610 } 2611 pmcs = 0; 2612 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2613 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2614 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2615 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2616 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2617 MAC_CFG_BCAST); 2618 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2619 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2620 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2621 mac |= MAC_CFG_RX_ENB; 2622 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2623 ANEG_S3DIG10_SL); 2624 } 2625 2626 /* Enable OSC. */ 2627 reg = CSR_READ_4(sc, ALC_MISC); 2628 reg &= ~MISC_INTNLOSC_OPEN; 2629 CSR_WRITE_4(sc, ALC_MISC, reg); 2630 reg |= MISC_INTNLOSC_OPEN; 2631 CSR_WRITE_4(sc, ALC_MISC, reg); 2632 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2633 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2634 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2635 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2636 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2637 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2638 2639 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2640 /* Request PME. */ 2641 pmstat = pci_read_config(sc->alc_dev, 2642 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2643 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2644 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2645 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2646 pci_write_config(sc->alc_dev, 2647 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2648 } 2649 } 2650 2651 static int 2652 alc_suspend(device_t dev) 2653 { 2654 struct alc_softc *sc; 2655 2656 sc = device_get_softc(dev); 2657 2658 ALC_LOCK(sc); 2659 alc_stop(sc); 2660 alc_setwol(sc); 2661 ALC_UNLOCK(sc); 2662 2663 return (0); 2664 } 2665 2666 static int 2667 alc_resume(device_t dev) 2668 { 2669 struct alc_softc *sc; 2670 if_t ifp; 2671 uint16_t pmstat; 2672 2673 sc = device_get_softc(dev); 2674 2675 ALC_LOCK(sc); 2676 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2677 /* Disable PME and clear PME status. */ 2678 pmstat = pci_read_config(sc->alc_dev, 2679 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2680 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2681 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2682 pci_write_config(sc->alc_dev, 2683 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2684 } 2685 } 2686 /* Reset PHY. */ 2687 alc_phy_reset(sc); 2688 ifp = sc->alc_ifp; 2689 if ((if_getflags(ifp) & IFF_UP) != 0) { 2690 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2691 alc_init_locked(sc); 2692 } 2693 ALC_UNLOCK(sc); 2694 2695 return (0); 2696 } 2697 2698 static int 2699 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2700 { 2701 struct alc_txdesc *txd, *txd_last; 2702 struct tx_desc *desc; 2703 struct mbuf *m; 2704 struct ip *ip; 2705 struct tcphdr *tcp; 2706 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2707 bus_dmamap_t map; 2708 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2709 int error, idx, nsegs, prod; 2710 2711 ALC_LOCK_ASSERT(sc); 2712 2713 M_ASSERTPKTHDR((*m_head)); 2714 2715 m = *m_head; 2716 ip = NULL; 2717 tcp = NULL; 2718 ip_off = poff = 0; 2719 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2720 /* 2721 * AR81[3567]x requires offset of TCP/UDP header in its 2722 * Tx descriptor to perform Tx checksum offloading. TSO 2723 * also requires TCP header offset and modification of 2724 * IP/TCP header. This kind of operation takes many CPU 2725 * cycles on FreeBSD so fast host CPU is required to get 2726 * smooth TSO performance. 2727 */ 2728 struct ether_header *eh; 2729 2730 if (M_WRITABLE(m) == 0) { 2731 /* Get a writable copy. */ 2732 m = m_dup(*m_head, M_NOWAIT); 2733 /* Release original mbufs. */ 2734 m_freem(*m_head); 2735 if (m == NULL) { 2736 *m_head = NULL; 2737 return (ENOBUFS); 2738 } 2739 *m_head = m; 2740 } 2741 2742 ip_off = sizeof(struct ether_header); 2743 m = m_pullup(m, ip_off); 2744 if (m == NULL) { 2745 *m_head = NULL; 2746 return (ENOBUFS); 2747 } 2748 eh = mtod(m, struct ether_header *); 2749 /* 2750 * Check if hardware VLAN insertion is off. 2751 * Additional check for LLC/SNAP frame? 2752 */ 2753 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2754 ip_off = sizeof(struct ether_vlan_header); 2755 m = m_pullup(m, ip_off); 2756 if (m == NULL) { 2757 *m_head = NULL; 2758 return (ENOBUFS); 2759 } 2760 } 2761 m = m_pullup(m, ip_off + sizeof(struct ip)); 2762 if (m == NULL) { 2763 *m_head = NULL; 2764 return (ENOBUFS); 2765 } 2766 ip = (struct ip *)(mtod(m, char *) + ip_off); 2767 poff = ip_off + (ip->ip_hl << 2); 2768 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2769 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2770 if (m == NULL) { 2771 *m_head = NULL; 2772 return (ENOBUFS); 2773 } 2774 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2775 m = m_pullup(m, poff + (tcp->th_off << 2)); 2776 if (m == NULL) { 2777 *m_head = NULL; 2778 return (ENOBUFS); 2779 } 2780 /* 2781 * Due to strict adherence of Microsoft NDIS 2782 * Large Send specification, hardware expects 2783 * a pseudo TCP checksum inserted by upper 2784 * stack. Unfortunately the pseudo TCP 2785 * checksum that NDIS refers to does not include 2786 * TCP payload length so driver should recompute 2787 * the pseudo checksum here. Hopefully this 2788 * wouldn't be much burden on modern CPUs. 2789 * 2790 * Reset IP checksum and recompute TCP pseudo 2791 * checksum as NDIS specification said. 2792 */ 2793 ip = (struct ip *)(mtod(m, char *) + ip_off); 2794 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2795 ip->ip_sum = 0; 2796 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2797 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2798 } 2799 *m_head = m; 2800 } 2801 2802 prod = sc->alc_cdata.alc_tx_prod; 2803 txd = &sc->alc_cdata.alc_txdesc[prod]; 2804 txd_last = txd; 2805 map = txd->tx_dmamap; 2806 2807 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2808 *m_head, txsegs, &nsegs, 0); 2809 if (error == EFBIG) { 2810 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2811 if (m == NULL) { 2812 m_freem(*m_head); 2813 *m_head = NULL; 2814 return (ENOMEM); 2815 } 2816 *m_head = m; 2817 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2818 *m_head, txsegs, &nsegs, 0); 2819 if (error != 0) { 2820 m_freem(*m_head); 2821 *m_head = NULL; 2822 return (error); 2823 } 2824 } else if (error != 0) 2825 return (error); 2826 if (nsegs == 0) { 2827 m_freem(*m_head); 2828 *m_head = NULL; 2829 return (EIO); 2830 } 2831 2832 /* Check descriptor overrun. */ 2833 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2834 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2835 return (ENOBUFS); 2836 } 2837 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2838 2839 m = *m_head; 2840 cflags = TD_ETHERNET; 2841 vtag = 0; 2842 desc = NULL; 2843 idx = 0; 2844 /* Configure VLAN hardware tag insertion. */ 2845 if ((m->m_flags & M_VLANTAG) != 0) { 2846 vtag = htons(m->m_pkthdr.ether_vtag); 2847 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2848 cflags |= TD_INS_VLAN_TAG; 2849 } 2850 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2851 /* Request TSO and set MSS. */ 2852 cflags |= TD_TSO | TD_TSO_DESCV1; 2853 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2854 TD_MSS_MASK; 2855 /* Set TCP header offset. */ 2856 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2857 TD_TCPHDR_OFFSET_MASK; 2858 /* 2859 * AR81[3567]x requires the first buffer should 2860 * only hold IP/TCP header data. Payload should 2861 * be handled in other descriptors. 2862 */ 2863 hdrlen = poff + (tcp->th_off << 2); 2864 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2865 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2866 desc->flags = htole32(cflags); 2867 desc->addr = htole64(txsegs[0].ds_addr); 2868 sc->alc_cdata.alc_tx_cnt++; 2869 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2870 if (m->m_len - hdrlen > 0) { 2871 /* Handle remaining payload of the first fragment. */ 2872 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2873 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2874 vtag)); 2875 desc->flags = htole32(cflags); 2876 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2877 sc->alc_cdata.alc_tx_cnt++; 2878 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2879 } 2880 /* Handle remaining fragments. */ 2881 idx = 1; 2882 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2883 /* Configure Tx checksum offload. */ 2884 #ifdef ALC_USE_CUSTOM_CSUM 2885 cflags |= TD_CUSTOM_CSUM; 2886 /* Set checksum start offset. */ 2887 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2888 TD_PLOAD_OFFSET_MASK; 2889 /* Set checksum insertion position of TCP/UDP. */ 2890 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2891 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2892 #else 2893 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2894 cflags |= TD_IPCSUM; 2895 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2896 cflags |= TD_TCPCSUM; 2897 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2898 cflags |= TD_UDPCSUM; 2899 /* Set TCP/UDP header offset. */ 2900 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2901 TD_L4HDR_OFFSET_MASK; 2902 #endif 2903 } 2904 for (; idx < nsegs; idx++) { 2905 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2906 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2907 desc->flags = htole32(cflags); 2908 desc->addr = htole64(txsegs[idx].ds_addr); 2909 sc->alc_cdata.alc_tx_cnt++; 2910 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2911 } 2912 /* Update producer index. */ 2913 sc->alc_cdata.alc_tx_prod = prod; 2914 2915 /* Finally set EOP on the last descriptor. */ 2916 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2917 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2918 desc->flags |= htole32(TD_EOP); 2919 2920 /* Swap dmamap of the first and the last. */ 2921 txd = &sc->alc_cdata.alc_txdesc[prod]; 2922 map = txd_last->tx_dmamap; 2923 txd_last->tx_dmamap = txd->tx_dmamap; 2924 txd->tx_dmamap = map; 2925 txd->tx_m = m; 2926 2927 return (0); 2928 } 2929 2930 static void 2931 alc_start(if_t ifp) 2932 { 2933 struct alc_softc *sc; 2934 2935 sc = if_getsoftc(ifp); 2936 ALC_LOCK(sc); 2937 alc_start_locked(ifp); 2938 ALC_UNLOCK(sc); 2939 } 2940 2941 static void 2942 alc_start_locked(if_t ifp) 2943 { 2944 struct alc_softc *sc; 2945 struct mbuf *m_head; 2946 int enq; 2947 2948 sc = if_getsoftc(ifp); 2949 2950 ALC_LOCK_ASSERT(sc); 2951 2952 /* Reclaim transmitted frames. */ 2953 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2954 alc_txeof(sc); 2955 2956 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2957 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2958 return; 2959 2960 for (enq = 0; !if_sendq_empty(ifp); ) { 2961 m_head = if_dequeue(ifp); 2962 if (m_head == NULL) 2963 break; 2964 /* 2965 * Pack the data into the transmit ring. If we 2966 * don't have room, set the OACTIVE flag and wait 2967 * for the NIC to drain the ring. 2968 */ 2969 if (alc_encap(sc, &m_head)) { 2970 if (m_head == NULL) 2971 break; 2972 if_sendq_prepend(ifp, m_head); 2973 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2974 break; 2975 } 2976 2977 enq++; 2978 /* 2979 * If there's a BPF listener, bounce a copy of this frame 2980 * to him. 2981 */ 2982 ETHER_BPF_MTAP(ifp, m_head); 2983 } 2984 2985 if (enq > 0) 2986 alc_start_tx(sc); 2987 } 2988 2989 static void 2990 alc_start_tx(struct alc_softc *sc) 2991 { 2992 2993 /* Sync descriptors. */ 2994 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2995 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2996 /* Kick. Assume we're using normal Tx priority queue. */ 2997 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2998 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2999 (uint16_t)sc->alc_cdata.alc_tx_prod); 3000 else 3001 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3002 (sc->alc_cdata.alc_tx_prod << 3003 MBOX_TD_PROD_LO_IDX_SHIFT) & 3004 MBOX_TD_PROD_LO_IDX_MASK); 3005 /* Set a timeout in case the chip goes out to lunch. */ 3006 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3007 } 3008 3009 static void 3010 alc_watchdog(struct alc_softc *sc) 3011 { 3012 if_t ifp; 3013 3014 ALC_LOCK_ASSERT(sc); 3015 3016 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3017 return; 3018 3019 ifp = sc->alc_ifp; 3020 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3021 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3022 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3023 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3024 alc_init_locked(sc); 3025 return; 3026 } 3027 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3028 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3029 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3030 alc_init_locked(sc); 3031 if (!if_sendq_empty(ifp)) 3032 alc_start_locked(ifp); 3033 } 3034 3035 static int 3036 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3037 { 3038 struct alc_softc *sc; 3039 struct ifreq *ifr; 3040 struct mii_data *mii; 3041 int error, mask; 3042 3043 sc = if_getsoftc(ifp); 3044 ifr = (struct ifreq *)data; 3045 error = 0; 3046 switch (cmd) { 3047 case SIOCSIFMTU: 3048 if (ifr->ifr_mtu < ETHERMIN || 3049 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3050 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3051 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3052 ifr->ifr_mtu > ETHERMTU)) 3053 error = EINVAL; 3054 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3055 ALC_LOCK(sc); 3056 if_setmtu(ifp, ifr->ifr_mtu); 3057 /* AR81[3567]x has 13 bits MSS field. */ 3058 if (if_getmtu(ifp) > ALC_TSO_MTU && 3059 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3060 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3061 if_sethwassistbits(ifp, 0, CSUM_TSO); 3062 VLAN_CAPABILITIES(ifp); 3063 } 3064 ALC_UNLOCK(sc); 3065 } 3066 break; 3067 case SIOCSIFFLAGS: 3068 ALC_LOCK(sc); 3069 if ((if_getflags(ifp) & IFF_UP) != 0) { 3070 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3071 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3072 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3073 alc_rxfilter(sc); 3074 else 3075 alc_init_locked(sc); 3076 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3077 alc_stop(sc); 3078 sc->alc_if_flags = if_getflags(ifp); 3079 ALC_UNLOCK(sc); 3080 break; 3081 case SIOCADDMULTI: 3082 case SIOCDELMULTI: 3083 ALC_LOCK(sc); 3084 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3085 alc_rxfilter(sc); 3086 ALC_UNLOCK(sc); 3087 break; 3088 case SIOCSIFMEDIA: 3089 case SIOCGIFMEDIA: 3090 mii = device_get_softc(sc->alc_miibus); 3091 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3092 break; 3093 case SIOCSIFCAP: 3094 ALC_LOCK(sc); 3095 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3096 if ((mask & IFCAP_TXCSUM) != 0 && 3097 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3098 if_togglecapenable(ifp, IFCAP_TXCSUM); 3099 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3100 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3101 else 3102 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3103 } 3104 if ((mask & IFCAP_TSO4) != 0 && 3105 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3106 if_togglecapenable(ifp, IFCAP_TSO4); 3107 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3108 /* AR81[3567]x has 13 bits MSS field. */ 3109 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3110 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3111 if_sethwassistbits(ifp, 0, CSUM_TSO); 3112 } else 3113 if_sethwassistbits(ifp, CSUM_TSO, 0); 3114 } else 3115 if_sethwassistbits(ifp, 0, CSUM_TSO); 3116 } 3117 if ((mask & IFCAP_WOL_MCAST) != 0 && 3118 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3119 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3120 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3121 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3122 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3123 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3124 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3125 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3126 alc_rxvlan(sc); 3127 } 3128 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3129 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3130 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3131 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3132 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3133 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3134 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3135 if_setcapenablebit(ifp, 0, 3136 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3137 ALC_UNLOCK(sc); 3138 VLAN_CAPABILITIES(ifp); 3139 break; 3140 default: 3141 error = ether_ioctl(ifp, cmd, data); 3142 break; 3143 } 3144 3145 return (error); 3146 } 3147 3148 static void 3149 alc_mac_config(struct alc_softc *sc) 3150 { 3151 struct mii_data *mii; 3152 uint32_t reg; 3153 3154 ALC_LOCK_ASSERT(sc); 3155 3156 mii = device_get_softc(sc->alc_miibus); 3157 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3158 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3159 MAC_CFG_SPEED_MASK); 3160 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3161 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3162 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3163 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3164 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3165 /* Reprogram MAC with resolved speed/duplex. */ 3166 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3167 case IFM_10_T: 3168 case IFM_100_TX: 3169 reg |= MAC_CFG_SPEED_10_100; 3170 break; 3171 case IFM_1000_T: 3172 reg |= MAC_CFG_SPEED_1000; 3173 break; 3174 } 3175 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3176 reg |= MAC_CFG_FULL_DUPLEX; 3177 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3178 reg |= MAC_CFG_TX_FC; 3179 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3180 reg |= MAC_CFG_RX_FC; 3181 } 3182 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3183 } 3184 3185 static void 3186 alc_stats_clear(struct alc_softc *sc) 3187 { 3188 struct smb sb, *smb; 3189 uint32_t *reg; 3190 int i; 3191 3192 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3193 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3194 sc->alc_cdata.alc_smb_map, 3195 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3196 smb = sc->alc_rdata.alc_smb; 3197 /* Update done, clear. */ 3198 smb->updated = 0; 3199 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3200 sc->alc_cdata.alc_smb_map, 3201 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3202 } else { 3203 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3204 reg++) { 3205 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3206 i += sizeof(uint32_t); 3207 } 3208 /* Read Tx statistics. */ 3209 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3210 reg++) { 3211 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3212 i += sizeof(uint32_t); 3213 } 3214 } 3215 } 3216 3217 static void 3218 alc_stats_update(struct alc_softc *sc) 3219 { 3220 struct alc_hw_stats *stat; 3221 struct smb sb, *smb; 3222 if_t ifp; 3223 uint32_t *reg; 3224 int i; 3225 3226 ALC_LOCK_ASSERT(sc); 3227 3228 ifp = sc->alc_ifp; 3229 stat = &sc->alc_stats; 3230 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3231 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3232 sc->alc_cdata.alc_smb_map, 3233 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3234 smb = sc->alc_rdata.alc_smb; 3235 if (smb->updated == 0) 3236 return; 3237 } else { 3238 smb = &sb; 3239 /* Read Rx statistics. */ 3240 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3241 reg++) { 3242 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3243 i += sizeof(uint32_t); 3244 } 3245 /* Read Tx statistics. */ 3246 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3247 reg++) { 3248 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3249 i += sizeof(uint32_t); 3250 } 3251 } 3252 3253 /* Rx stats. */ 3254 stat->rx_frames += smb->rx_frames; 3255 stat->rx_bcast_frames += smb->rx_bcast_frames; 3256 stat->rx_mcast_frames += smb->rx_mcast_frames; 3257 stat->rx_pause_frames += smb->rx_pause_frames; 3258 stat->rx_control_frames += smb->rx_control_frames; 3259 stat->rx_crcerrs += smb->rx_crcerrs; 3260 stat->rx_lenerrs += smb->rx_lenerrs; 3261 stat->rx_bytes += smb->rx_bytes; 3262 stat->rx_runts += smb->rx_runts; 3263 stat->rx_fragments += smb->rx_fragments; 3264 stat->rx_pkts_64 += smb->rx_pkts_64; 3265 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3266 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3267 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3268 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3269 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3270 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3271 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3272 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3273 stat->rx_rrs_errs += smb->rx_rrs_errs; 3274 stat->rx_alignerrs += smb->rx_alignerrs; 3275 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3276 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3277 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3278 3279 /* Tx stats. */ 3280 stat->tx_frames += smb->tx_frames; 3281 stat->tx_bcast_frames += smb->tx_bcast_frames; 3282 stat->tx_mcast_frames += smb->tx_mcast_frames; 3283 stat->tx_pause_frames += smb->tx_pause_frames; 3284 stat->tx_excess_defer += smb->tx_excess_defer; 3285 stat->tx_control_frames += smb->tx_control_frames; 3286 stat->tx_deferred += smb->tx_deferred; 3287 stat->tx_bytes += smb->tx_bytes; 3288 stat->tx_pkts_64 += smb->tx_pkts_64; 3289 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3290 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3291 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3292 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3293 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3294 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3295 stat->tx_single_colls += smb->tx_single_colls; 3296 stat->tx_multi_colls += smb->tx_multi_colls; 3297 stat->tx_late_colls += smb->tx_late_colls; 3298 stat->tx_excess_colls += smb->tx_excess_colls; 3299 stat->tx_underrun += smb->tx_underrun; 3300 stat->tx_desc_underrun += smb->tx_desc_underrun; 3301 stat->tx_lenerrs += smb->tx_lenerrs; 3302 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3303 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3304 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3305 3306 /* Update counters in ifnet. */ 3307 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3308 3309 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3310 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3311 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3312 3313 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3314 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3315 3316 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3317 3318 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3319 smb->rx_crcerrs + smb->rx_lenerrs + 3320 smb->rx_runts + smb->rx_pkts_truncated + 3321 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3322 smb->rx_alignerrs); 3323 3324 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3325 /* Update done, clear. */ 3326 smb->updated = 0; 3327 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3328 sc->alc_cdata.alc_smb_map, 3329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3330 } 3331 } 3332 3333 static int 3334 alc_intr(void *arg) 3335 { 3336 struct alc_softc *sc; 3337 uint32_t status; 3338 3339 sc = (struct alc_softc *)arg; 3340 3341 if (sc->alc_flags & ALC_FLAG_MT) { 3342 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3343 return (FILTER_HANDLED); 3344 } 3345 3346 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3347 if ((status & ALC_INTRS) == 0) 3348 return (FILTER_STRAY); 3349 /* Disable interrupts. */ 3350 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3351 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3352 3353 return (FILTER_HANDLED); 3354 } 3355 3356 static void 3357 alc_int_task(void *arg, int pending) 3358 { 3359 struct alc_softc *sc; 3360 if_t ifp; 3361 uint32_t status; 3362 int more; 3363 3364 sc = (struct alc_softc *)arg; 3365 ifp = sc->alc_ifp; 3366 3367 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3368 ALC_LOCK(sc); 3369 if (sc->alc_morework != 0) { 3370 sc->alc_morework = 0; 3371 status |= INTR_RX_PKT; 3372 } 3373 if ((status & ALC_INTRS) == 0) 3374 goto done; 3375 3376 /* Acknowledge interrupts but still disable interrupts. */ 3377 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3378 3379 more = 0; 3380 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3381 if ((status & INTR_RX_PKT) != 0) { 3382 more = alc_rxintr(sc, sc->alc_process_limit); 3383 if (more == EAGAIN) 3384 sc->alc_morework = 1; 3385 else if (more == EIO) { 3386 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3387 alc_init_locked(sc); 3388 ALC_UNLOCK(sc); 3389 return; 3390 } 3391 } 3392 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3393 INTR_TXQ_TO_RST)) != 0) { 3394 if ((status & INTR_DMA_RD_TO_RST) != 0) 3395 device_printf(sc->alc_dev, 3396 "DMA read error! -- resetting\n"); 3397 if ((status & INTR_DMA_WR_TO_RST) != 0) 3398 device_printf(sc->alc_dev, 3399 "DMA write error! -- resetting\n"); 3400 if ((status & INTR_TXQ_TO_RST) != 0) 3401 device_printf(sc->alc_dev, 3402 "TxQ reset! -- resetting\n"); 3403 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3404 alc_init_locked(sc); 3405 ALC_UNLOCK(sc); 3406 return; 3407 } 3408 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3409 !if_sendq_empty(ifp)) 3410 alc_start_locked(ifp); 3411 } 3412 3413 if (more == EAGAIN || 3414 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3415 ALC_UNLOCK(sc); 3416 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3417 return; 3418 } 3419 3420 done: 3421 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3422 /* Re-enable interrupts if we're running. */ 3423 if (sc->alc_flags & ALC_FLAG_MT) 3424 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3425 else 3426 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3427 } 3428 ALC_UNLOCK(sc); 3429 } 3430 3431 static void 3432 alc_txeof(struct alc_softc *sc) 3433 { 3434 if_t ifp; 3435 struct alc_txdesc *txd; 3436 uint32_t cons, prod; 3437 3438 ALC_LOCK_ASSERT(sc); 3439 3440 ifp = sc->alc_ifp; 3441 3442 if (sc->alc_cdata.alc_tx_cnt == 0) 3443 return; 3444 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3445 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3446 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3447 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3448 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3449 prod = sc->alc_rdata.alc_cmb->cons; 3450 } else { 3451 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3452 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3453 else { 3454 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3455 /* Assume we're using normal Tx priority queue. */ 3456 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3457 MBOX_TD_CONS_LO_IDX_SHIFT; 3458 } 3459 } 3460 cons = sc->alc_cdata.alc_tx_cons; 3461 /* 3462 * Go through our Tx list and free mbufs for those 3463 * frames which have been transmitted. 3464 */ 3465 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3466 if (sc->alc_cdata.alc_tx_cnt <= 0) 3467 break; 3468 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3469 sc->alc_cdata.alc_tx_cnt--; 3470 txd = &sc->alc_cdata.alc_txdesc[cons]; 3471 if (txd->tx_m != NULL) { 3472 /* Reclaim transmitted mbufs. */ 3473 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3474 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3475 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3476 txd->tx_dmamap); 3477 m_freem(txd->tx_m); 3478 txd->tx_m = NULL; 3479 } 3480 } 3481 3482 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3483 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3484 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3485 sc->alc_cdata.alc_tx_cons = cons; 3486 /* 3487 * Unarm watchdog timer only when there is no pending 3488 * frames in Tx queue. 3489 */ 3490 if (sc->alc_cdata.alc_tx_cnt == 0) 3491 sc->alc_watchdog_timer = 0; 3492 } 3493 3494 static int 3495 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3496 { 3497 struct mbuf *m; 3498 bus_dma_segment_t segs[1]; 3499 bus_dmamap_t map; 3500 int nsegs; 3501 3502 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3503 if (m == NULL) 3504 return (ENOBUFS); 3505 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3506 #ifndef __NO_STRICT_ALIGNMENT 3507 m_adj(m, sizeof(uint64_t)); 3508 #endif 3509 3510 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3511 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3512 m_freem(m); 3513 return (ENOBUFS); 3514 } 3515 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3516 3517 if (rxd->rx_m != NULL) { 3518 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3519 BUS_DMASYNC_POSTREAD); 3520 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3521 } 3522 map = rxd->rx_dmamap; 3523 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3524 sc->alc_cdata.alc_rx_sparemap = map; 3525 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3526 BUS_DMASYNC_PREREAD); 3527 rxd->rx_m = m; 3528 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3529 return (0); 3530 } 3531 3532 static int 3533 alc_rxintr(struct alc_softc *sc, int count) 3534 { 3535 if_t ifp; 3536 struct rx_rdesc *rrd; 3537 uint32_t nsegs, status; 3538 int rr_cons, prog; 3539 3540 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3541 sc->alc_cdata.alc_rr_ring_map, 3542 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3543 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3544 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3545 rr_cons = sc->alc_cdata.alc_rr_cons; 3546 ifp = sc->alc_ifp; 3547 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3548 if (count-- <= 0) 3549 break; 3550 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3551 status = le32toh(rrd->status); 3552 if ((status & RRD_VALID) == 0) 3553 break; 3554 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3555 if (nsegs == 0) { 3556 /* This should not happen! */ 3557 device_printf(sc->alc_dev, 3558 "unexpected segment count -- resetting\n"); 3559 return (EIO); 3560 } 3561 alc_rxeof(sc, rrd); 3562 /* Clear Rx return status. */ 3563 rrd->status = 0; 3564 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3565 sc->alc_cdata.alc_rx_cons += nsegs; 3566 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3567 prog += nsegs; 3568 } 3569 3570 if (prog > 0) { 3571 /* Update the consumer index. */ 3572 sc->alc_cdata.alc_rr_cons = rr_cons; 3573 /* Sync Rx return descriptors. */ 3574 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3575 sc->alc_cdata.alc_rr_ring_map, 3576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3577 /* 3578 * Sync updated Rx descriptors such that controller see 3579 * modified buffer addresses. 3580 */ 3581 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3582 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3583 /* 3584 * Let controller know availability of new Rx buffers. 3585 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3586 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3587 * only when Rx buffer pre-fetching is required. In 3588 * addition we already set ALC_RX_RD_FREE_THRESH to 3589 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3590 * it still seems that pre-fetching needs more 3591 * experimentation. 3592 */ 3593 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3594 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3595 (uint16_t)sc->alc_cdata.alc_rx_cons); 3596 else 3597 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3598 sc->alc_cdata.alc_rx_cons); 3599 } 3600 3601 return (count > 0 ? 0 : EAGAIN); 3602 } 3603 3604 #ifndef __NO_STRICT_ALIGNMENT 3605 static struct mbuf * 3606 alc_fixup_rx(if_t ifp, struct mbuf *m) 3607 { 3608 struct mbuf *n; 3609 int i; 3610 uint16_t *src, *dst; 3611 3612 src = mtod(m, uint16_t *); 3613 dst = src - 3; 3614 3615 if (m->m_next == NULL) { 3616 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3617 *dst++ = *src++; 3618 m->m_data -= 6; 3619 return (m); 3620 } 3621 /* 3622 * Append a new mbuf to received mbuf chain and copy ethernet 3623 * header from the mbuf chain. This can save lots of CPU 3624 * cycles for jumbo frame. 3625 */ 3626 MGETHDR(n, M_NOWAIT, MT_DATA); 3627 if (n == NULL) { 3628 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3629 m_freem(m); 3630 return (NULL); 3631 } 3632 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3633 m->m_data += ETHER_HDR_LEN; 3634 m->m_len -= ETHER_HDR_LEN; 3635 n->m_len = ETHER_HDR_LEN; 3636 M_MOVE_PKTHDR(n, m); 3637 n->m_next = m; 3638 return (n); 3639 } 3640 #endif 3641 3642 /* Receive a frame. */ 3643 static void 3644 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3645 { 3646 struct alc_rxdesc *rxd; 3647 if_t ifp; 3648 struct mbuf *mp, *m; 3649 uint32_t rdinfo, status, vtag; 3650 int count, nsegs, rx_cons; 3651 3652 ifp = sc->alc_ifp; 3653 status = le32toh(rrd->status); 3654 rdinfo = le32toh(rrd->rdinfo); 3655 rx_cons = RRD_RD_IDX(rdinfo); 3656 nsegs = RRD_RD_CNT(rdinfo); 3657 3658 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3659 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3660 /* 3661 * We want to pass the following frames to upper 3662 * layer regardless of error status of Rx return 3663 * ring. 3664 * 3665 * o IP/TCP/UDP checksum is bad. 3666 * o frame length and protocol specific length 3667 * does not match. 3668 * 3669 * Force network stack compute checksum for 3670 * errored frames. 3671 */ 3672 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3673 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3674 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3675 return; 3676 } 3677 3678 for (count = 0; count < nsegs; count++, 3679 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3680 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3681 mp = rxd->rx_m; 3682 /* Add a new receive buffer to the ring. */ 3683 if (alc_newbuf(sc, rxd) != 0) { 3684 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3685 /* Reuse Rx buffers. */ 3686 if (sc->alc_cdata.alc_rxhead != NULL) 3687 m_freem(sc->alc_cdata.alc_rxhead); 3688 break; 3689 } 3690 3691 /* 3692 * Assume we've received a full sized frame. 3693 * Actual size is fixed when we encounter the end of 3694 * multi-segmented frame. 3695 */ 3696 mp->m_len = sc->alc_buf_size; 3697 3698 /* Chain received mbufs. */ 3699 if (sc->alc_cdata.alc_rxhead == NULL) { 3700 sc->alc_cdata.alc_rxhead = mp; 3701 sc->alc_cdata.alc_rxtail = mp; 3702 } else { 3703 mp->m_flags &= ~M_PKTHDR; 3704 sc->alc_cdata.alc_rxprev_tail = 3705 sc->alc_cdata.alc_rxtail; 3706 sc->alc_cdata.alc_rxtail->m_next = mp; 3707 sc->alc_cdata.alc_rxtail = mp; 3708 } 3709 3710 if (count == nsegs - 1) { 3711 /* Last desc. for this frame. */ 3712 m = sc->alc_cdata.alc_rxhead; 3713 m->m_flags |= M_PKTHDR; 3714 /* 3715 * It seems that L1C/L2C controller has no way 3716 * to tell hardware to strip CRC bytes. 3717 */ 3718 m->m_pkthdr.len = 3719 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3720 if (nsegs > 1) { 3721 /* Set last mbuf size. */ 3722 mp->m_len = sc->alc_cdata.alc_rxlen - 3723 (nsegs - 1) * sc->alc_buf_size; 3724 /* Remove the CRC bytes in chained mbufs. */ 3725 if (mp->m_len <= ETHER_CRC_LEN) { 3726 sc->alc_cdata.alc_rxtail = 3727 sc->alc_cdata.alc_rxprev_tail; 3728 sc->alc_cdata.alc_rxtail->m_len -= 3729 (ETHER_CRC_LEN - mp->m_len); 3730 sc->alc_cdata.alc_rxtail->m_next = NULL; 3731 m_freem(mp); 3732 } else { 3733 mp->m_len -= ETHER_CRC_LEN; 3734 } 3735 } else 3736 m->m_len = m->m_pkthdr.len; 3737 m->m_pkthdr.rcvif = ifp; 3738 /* 3739 * Due to hardware bugs, Rx checksum offloading 3740 * was intentionally disabled. 3741 */ 3742 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3743 (status & RRD_VLAN_TAG) != 0) { 3744 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3745 m->m_pkthdr.ether_vtag = ntohs(vtag); 3746 m->m_flags |= M_VLANTAG; 3747 } 3748 #ifndef __NO_STRICT_ALIGNMENT 3749 m = alc_fixup_rx(ifp, m); 3750 if (m != NULL) 3751 #endif 3752 { 3753 /* Pass it on. */ 3754 ALC_UNLOCK(sc); 3755 if_input(ifp, m); 3756 ALC_LOCK(sc); 3757 } 3758 } 3759 } 3760 /* Reset mbuf chains. */ 3761 ALC_RXCHAIN_RESET(sc); 3762 } 3763 3764 static void 3765 alc_tick(void *arg) 3766 { 3767 struct alc_softc *sc; 3768 struct mii_data *mii; 3769 3770 sc = (struct alc_softc *)arg; 3771 3772 ALC_LOCK_ASSERT(sc); 3773 3774 mii = device_get_softc(sc->alc_miibus); 3775 mii_tick(mii); 3776 alc_stats_update(sc); 3777 /* 3778 * alc(4) does not rely on Tx completion interrupts to reclaim 3779 * transferred buffers. Instead Tx completion interrupts are 3780 * used to hint for scheduling Tx task. So it's necessary to 3781 * release transmitted buffers by kicking Tx completion 3782 * handler. This limits the maximum reclamation delay to a hz. 3783 */ 3784 alc_txeof(sc); 3785 alc_watchdog(sc); 3786 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3787 } 3788 3789 static void 3790 alc_osc_reset(struct alc_softc *sc) 3791 { 3792 uint32_t reg; 3793 3794 reg = CSR_READ_4(sc, ALC_MISC3); 3795 reg &= ~MISC3_25M_BY_SW; 3796 reg |= MISC3_25M_NOTO_INTNL; 3797 CSR_WRITE_4(sc, ALC_MISC3, reg); 3798 3799 reg = CSR_READ_4(sc, ALC_MISC); 3800 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3801 /* 3802 * Restore over-current protection default value. 3803 * This value could be reset by MAC reset. 3804 */ 3805 reg &= ~MISC_PSW_OCP_MASK; 3806 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3807 reg &= ~MISC_INTNLOSC_OPEN; 3808 CSR_WRITE_4(sc, ALC_MISC, reg); 3809 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3810 reg = CSR_READ_4(sc, ALC_MISC2); 3811 reg &= ~MISC2_CALB_START; 3812 CSR_WRITE_4(sc, ALC_MISC2, reg); 3813 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3814 3815 } else { 3816 reg &= ~MISC_INTNLOSC_OPEN; 3817 /* Disable isolate for revision A devices. */ 3818 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3819 reg &= ~MISC_ISO_ENB; 3820 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3821 CSR_WRITE_4(sc, ALC_MISC, reg); 3822 } 3823 3824 DELAY(20); 3825 } 3826 3827 static void 3828 alc_reset(struct alc_softc *sc) 3829 { 3830 uint32_t pmcfg, reg; 3831 int i; 3832 3833 pmcfg = 0; 3834 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3835 /* Reset workaround. */ 3836 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3837 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3838 (sc->alc_rev & 0x01) != 0) { 3839 /* Disable L0s/L1s before reset. */ 3840 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3841 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3842 != 0) { 3843 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3844 PM_CFG_ASPM_L1_ENB); 3845 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3846 } 3847 } 3848 } 3849 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3850 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3851 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3852 3853 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3854 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3855 DELAY(10); 3856 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3857 break; 3858 } 3859 if (i == 0) 3860 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3861 } 3862 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3863 DELAY(10); 3864 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3865 break; 3866 } 3867 if (i == 0) 3868 device_printf(sc->alc_dev, "master reset timeout!\n"); 3869 3870 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3871 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3872 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3873 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3874 break; 3875 DELAY(10); 3876 } 3877 if (i == 0) 3878 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3879 3880 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3881 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3882 (sc->alc_rev & 0x01) != 0) { 3883 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3884 reg |= MASTER_CLK_SEL_DIS; 3885 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3886 /* Restore L0s/L1s config. */ 3887 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3888 != 0) 3889 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3890 } 3891 3892 alc_osc_reset(sc); 3893 reg = CSR_READ_4(sc, ALC_MISC3); 3894 reg &= ~MISC3_25M_BY_SW; 3895 reg |= MISC3_25M_NOTO_INTNL; 3896 CSR_WRITE_4(sc, ALC_MISC3, reg); 3897 reg = CSR_READ_4(sc, ALC_MISC); 3898 reg &= ~MISC_INTNLOSC_OPEN; 3899 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3900 reg &= ~MISC_ISO_ENB; 3901 CSR_WRITE_4(sc, ALC_MISC, reg); 3902 DELAY(20); 3903 } 3904 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3905 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3906 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3907 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3908 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3909 SERDES_PHY_CLK_SLOWDOWN); 3910 } 3911 3912 static void 3913 alc_init(void *xsc) 3914 { 3915 struct alc_softc *sc; 3916 3917 sc = (struct alc_softc *)xsc; 3918 ALC_LOCK(sc); 3919 alc_init_locked(sc); 3920 ALC_UNLOCK(sc); 3921 } 3922 3923 static void 3924 alc_init_locked(struct alc_softc *sc) 3925 { 3926 if_t ifp; 3927 uint8_t eaddr[ETHER_ADDR_LEN]; 3928 bus_addr_t paddr; 3929 uint32_t reg, rxf_hi, rxf_lo; 3930 3931 ALC_LOCK_ASSERT(sc); 3932 3933 ifp = sc->alc_ifp; 3934 3935 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3936 return; 3937 /* 3938 * Cancel any pending I/O. 3939 */ 3940 alc_stop(sc); 3941 /* 3942 * Reset the chip to a known state. 3943 */ 3944 alc_reset(sc); 3945 3946 /* Initialize Rx descriptors. */ 3947 if (alc_init_rx_ring(sc) != 0) { 3948 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3949 alc_stop(sc); 3950 return; 3951 } 3952 alc_init_rr_ring(sc); 3953 alc_init_tx_ring(sc); 3954 alc_init_cmb(sc); 3955 alc_init_smb(sc); 3956 3957 /* Enable all clocks. */ 3958 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3959 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3960 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3961 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3962 CLK_GATING_RXMAC_ENB); 3963 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3964 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3965 IDLE_DECISN_TIMER_DEFAULT_1MS); 3966 } else 3967 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3968 3969 /* Reprogram the station address. */ 3970 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3971 CSR_WRITE_4(sc, ALC_PAR0, 3972 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3973 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3974 /* 3975 * Clear WOL status and disable all WOL feature as WOL 3976 * would interfere Rx operation under normal environments. 3977 */ 3978 CSR_READ_4(sc, ALC_WOL_CFG); 3979 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3980 /* Set Tx descriptor base addresses. */ 3981 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3982 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3983 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3984 /* We don't use high priority ring. */ 3985 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3986 /* Set Tx descriptor counter. */ 3987 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3988 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3989 /* Set Rx descriptor base addresses. */ 3990 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3991 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3992 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3993 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3994 /* We use one Rx ring. */ 3995 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3996 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3997 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3998 } 3999 /* Set Rx descriptor counter. */ 4000 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4001 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4002 4003 /* 4004 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4005 * if it do not fit the buffer size. Rx return descriptor holds 4006 * a counter that indicates how many fragments were made by the 4007 * hardware. The buffer size should be multiple of 8 bytes. 4008 * Since hardware has limit on the size of buffer size, always 4009 * use the maximum value. 4010 * For strict-alignment architectures make sure to reduce buffer 4011 * size by 8 bytes to make room for alignment fixup. 4012 */ 4013 #ifndef __NO_STRICT_ALIGNMENT 4014 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4015 #else 4016 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4017 #endif 4018 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4019 4020 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4021 /* Set Rx return descriptor base addresses. */ 4022 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4023 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4024 /* We use one Rx return ring. */ 4025 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4026 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4027 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4028 } 4029 /* Set Rx return descriptor counter. */ 4030 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4031 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4032 paddr = sc->alc_rdata.alc_cmb_paddr; 4033 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4034 paddr = sc->alc_rdata.alc_smb_paddr; 4035 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4036 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4037 4038 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4039 /* Reconfigure SRAM - Vendor magic. */ 4040 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4041 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4042 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4043 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4044 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4045 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4046 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4047 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4048 } 4049 4050 /* Tell hardware that we're ready to load DMA blocks. */ 4051 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4052 4053 /* Configure interrupt moderation timer. */ 4054 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4055 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4056 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4057 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4058 /* 4059 * We don't want to automatic interrupt clear as task queue 4060 * for the interrupt should know interrupt status. 4061 */ 4062 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4063 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4064 reg |= MASTER_SA_TIMER_ENB; 4065 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4066 reg |= MASTER_IM_RX_TIMER_ENB; 4067 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4068 ALC_USECS(sc->alc_int_tx_mod) != 0) 4069 reg |= MASTER_IM_TX_TIMER_ENB; 4070 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4071 /* 4072 * Disable interrupt re-trigger timer. We don't want automatic 4073 * re-triggering of un-ACKed interrupts. 4074 */ 4075 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4076 /* Configure CMB. */ 4077 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4078 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4079 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4080 ALC_USECS(sc->alc_int_tx_mod)); 4081 } else { 4082 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4083 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4084 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4085 } else 4086 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4087 } 4088 /* 4089 * Hardware can be configured to issue SMB interrupt based 4090 * on programmed interval. Since there is a callout that is 4091 * invoked for every hz in driver we use that instead of 4092 * relying on periodic SMB interrupt. 4093 */ 4094 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4095 /* Clear MAC statistics. */ 4096 alc_stats_clear(sc); 4097 4098 /* 4099 * Always use maximum frame size that controller can support. 4100 * Otherwise received frames that has larger frame length 4101 * than alc(4) MTU would be silently dropped in hardware. This 4102 * would make path-MTU discovery hard as sender wouldn't get 4103 * any responses from receiver. alc(4) supports 4104 * multi-fragmented frames on Rx path so it has no issue on 4105 * assembling fragmented frames. Using maximum frame size also 4106 * removes the need to reinitialize hardware when interface 4107 * MTU configuration was changed. 4108 * 4109 * Be conservative in what you do, be liberal in what you 4110 * accept from others - RFC 793. 4111 */ 4112 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4113 4114 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4115 /* Disable header split(?) */ 4116 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4117 4118 /* Configure IPG/IFG parameters. */ 4119 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4120 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4121 IPG_IFG_IPGT_MASK) | 4122 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4123 IPG_IFG_MIFG_MASK) | 4124 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4125 IPG_IFG_IPG1_MASK) | 4126 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4127 IPG_IFG_IPG2_MASK)); 4128 /* Set parameters for half-duplex media. */ 4129 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4130 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4131 HDPX_CFG_LCOL_MASK) | 4132 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4133 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4134 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4135 HDPX_CFG_ABEBT_MASK) | 4136 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4137 HDPX_CFG_JAMIPG_MASK)); 4138 } 4139 4140 /* 4141 * Set TSO/checksum offload threshold. For frames that is 4142 * larger than this threshold, hardware wouldn't do 4143 * TSO/checksum offloading. 4144 */ 4145 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4146 TSO_OFFLOAD_THRESH_MASK; 4147 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4148 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4149 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4150 /* Configure TxQ. */ 4151 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4152 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4153 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4154 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4155 reg >>= 1; 4156 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4157 TXQ_CFG_TD_BURST_MASK; 4158 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4159 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4160 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4161 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4162 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4163 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4164 HQTD_CFG_BURST_ENB); 4165 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4166 reg = WRR_PRI_RESTRICT_NONE; 4167 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4168 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4169 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4170 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4171 CSR_WRITE_4(sc, ALC_WRR, reg); 4172 } else { 4173 /* Configure Rx free descriptor pre-fetching. */ 4174 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4175 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4176 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4177 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4178 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4179 } 4180 4181 /* 4182 * Configure flow control parameters. 4183 * XON : 80% of Rx FIFO 4184 * XOFF : 30% of Rx FIFO 4185 */ 4186 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4187 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4188 reg &= SRAM_RX_FIFO_LEN_MASK; 4189 reg *= 8; 4190 if (reg > 8 * 1024) 4191 reg -= RX_FIFO_PAUSE_816X_RSVD; 4192 else 4193 reg -= RX_BUF_SIZE_MAX; 4194 reg /= 8; 4195 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4196 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4197 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4198 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4199 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4200 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4201 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4202 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4203 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4204 rxf_hi = (reg * 8) / 10; 4205 rxf_lo = (reg * 3) / 10; 4206 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4207 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4208 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4209 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4210 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4211 } 4212 4213 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4214 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4215 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4216 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4217 } 4218 4219 /* Configure RxQ. */ 4220 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4221 RXQ_CFG_RD_BURST_MASK; 4222 reg |= RXQ_CFG_RSS_MODE_DIS; 4223 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4224 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4225 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4226 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4227 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4228 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4229 } else { 4230 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4231 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4232 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4233 } 4234 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4235 4236 /* Configure DMA parameters. */ 4237 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4238 reg |= sc->alc_rcb; 4239 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4240 reg |= DMA_CFG_CMB_ENB; 4241 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4242 reg |= DMA_CFG_SMB_ENB; 4243 else 4244 reg |= DMA_CFG_SMB_DIS; 4245 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4246 DMA_CFG_RD_BURST_SHIFT; 4247 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4248 DMA_CFG_WR_BURST_SHIFT; 4249 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4250 DMA_CFG_RD_DELAY_CNT_MASK; 4251 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4252 DMA_CFG_WR_DELAY_CNT_MASK; 4253 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4254 switch (AR816X_REV(sc->alc_rev)) { 4255 case AR816X_REV_A0: 4256 case AR816X_REV_A1: 4257 reg |= DMA_CFG_RD_CHNL_SEL_2; 4258 break; 4259 case AR816X_REV_B0: 4260 /* FALLTHROUGH */ 4261 default: 4262 reg |= DMA_CFG_RD_CHNL_SEL_4; 4263 break; 4264 } 4265 } 4266 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4267 4268 /* 4269 * Configure Tx/Rx MACs. 4270 * - Auto-padding for short frames. 4271 * - Enable CRC generation. 4272 * Actual reconfiguration of MAC for resolved speed/duplex 4273 * is followed after detection of link establishment. 4274 * AR813x/AR815x always does checksum computation regardless 4275 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4276 * have bug in protocol field in Rx return structure so 4277 * these controllers can't handle fragmented frames. Disable 4278 * Rx checksum offloading until there is a newer controller 4279 * that has sane implementation. 4280 */ 4281 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4282 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4283 MAC_CFG_PREAMBLE_MASK); 4284 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4285 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4286 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4287 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4288 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4289 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4290 reg |= MAC_CFG_SPEED_10_100; 4291 else 4292 reg |= MAC_CFG_SPEED_1000; 4293 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4294 4295 /* Set up the receive filter. */ 4296 alc_rxfilter(sc); 4297 alc_rxvlan(sc); 4298 4299 /* Acknowledge all pending interrupts and clear it. */ 4300 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4301 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4302 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4303 4304 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4305 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4306 4307 sc->alc_flags &= ~ALC_FLAG_LINK; 4308 /* Switch to the current media. */ 4309 alc_mediachange_locked(sc); 4310 4311 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4312 } 4313 4314 static void 4315 alc_stop(struct alc_softc *sc) 4316 { 4317 if_t ifp; 4318 struct alc_txdesc *txd; 4319 struct alc_rxdesc *rxd; 4320 uint32_t reg; 4321 int i; 4322 4323 ALC_LOCK_ASSERT(sc); 4324 /* 4325 * Mark the interface down and cancel the watchdog timer. 4326 */ 4327 ifp = sc->alc_ifp; 4328 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4329 sc->alc_flags &= ~ALC_FLAG_LINK; 4330 callout_stop(&sc->alc_tick_ch); 4331 sc->alc_watchdog_timer = 0; 4332 alc_stats_update(sc); 4333 /* Disable interrupts. */ 4334 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4335 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4336 /* Disable DMA. */ 4337 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4338 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4339 reg |= DMA_CFG_SMB_DIS; 4340 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4341 DELAY(1000); 4342 /* Stop Rx/Tx MACs. */ 4343 alc_stop_mac(sc); 4344 /* Disable interrupts which might be touched in taskq handler. */ 4345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4346 /* Disable L0s/L1s */ 4347 alc_aspm(sc, 0, IFM_UNKNOWN); 4348 /* Reclaim Rx buffers that have been processed. */ 4349 if (sc->alc_cdata.alc_rxhead != NULL) 4350 m_freem(sc->alc_cdata.alc_rxhead); 4351 ALC_RXCHAIN_RESET(sc); 4352 /* 4353 * Free Tx/Rx mbufs still in the queues. 4354 */ 4355 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4356 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4357 if (rxd->rx_m != NULL) { 4358 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4359 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4360 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4361 rxd->rx_dmamap); 4362 m_freem(rxd->rx_m); 4363 rxd->rx_m = NULL; 4364 } 4365 } 4366 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4367 txd = &sc->alc_cdata.alc_txdesc[i]; 4368 if (txd->tx_m != NULL) { 4369 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4370 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4371 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4372 txd->tx_dmamap); 4373 m_freem(txd->tx_m); 4374 txd->tx_m = NULL; 4375 } 4376 } 4377 } 4378 4379 static void 4380 alc_stop_mac(struct alc_softc *sc) 4381 { 4382 uint32_t reg; 4383 int i; 4384 4385 alc_stop_queue(sc); 4386 /* Disable Rx/Tx MAC. */ 4387 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4388 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4389 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4390 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4391 } 4392 for (i = ALC_TIMEOUT; i > 0; i--) { 4393 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4394 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4395 break; 4396 DELAY(10); 4397 } 4398 if (i == 0) 4399 device_printf(sc->alc_dev, 4400 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4401 } 4402 4403 static void 4404 alc_start_queue(struct alc_softc *sc) 4405 { 4406 uint32_t qcfg[] = { 4407 0, 4408 RXQ_CFG_QUEUE0_ENB, 4409 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4410 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4411 RXQ_CFG_ENB 4412 }; 4413 uint32_t cfg; 4414 4415 ALC_LOCK_ASSERT(sc); 4416 4417 /* Enable RxQ. */ 4418 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4419 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4420 cfg &= ~RXQ_CFG_ENB; 4421 cfg |= qcfg[1]; 4422 } else 4423 cfg |= RXQ_CFG_QUEUE0_ENB; 4424 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4425 /* Enable TxQ. */ 4426 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4427 cfg |= TXQ_CFG_ENB; 4428 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4429 } 4430 4431 static void 4432 alc_stop_queue(struct alc_softc *sc) 4433 { 4434 uint32_t reg; 4435 int i; 4436 4437 /* Disable RxQ. */ 4438 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4439 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4440 if ((reg & RXQ_CFG_ENB) != 0) { 4441 reg &= ~RXQ_CFG_ENB; 4442 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4443 } 4444 } else { 4445 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4446 reg &= ~RXQ_CFG_QUEUE0_ENB; 4447 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4448 } 4449 } 4450 /* Disable TxQ. */ 4451 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4452 if ((reg & TXQ_CFG_ENB) != 0) { 4453 reg &= ~TXQ_CFG_ENB; 4454 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4455 } 4456 DELAY(40); 4457 for (i = ALC_TIMEOUT; i > 0; i--) { 4458 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4459 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4460 break; 4461 DELAY(10); 4462 } 4463 if (i == 0) 4464 device_printf(sc->alc_dev, 4465 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4466 } 4467 4468 static void 4469 alc_init_tx_ring(struct alc_softc *sc) 4470 { 4471 struct alc_ring_data *rd; 4472 struct alc_txdesc *txd; 4473 int i; 4474 4475 ALC_LOCK_ASSERT(sc); 4476 4477 sc->alc_cdata.alc_tx_prod = 0; 4478 sc->alc_cdata.alc_tx_cons = 0; 4479 sc->alc_cdata.alc_tx_cnt = 0; 4480 4481 rd = &sc->alc_rdata; 4482 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4483 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4484 txd = &sc->alc_cdata.alc_txdesc[i]; 4485 txd->tx_m = NULL; 4486 } 4487 4488 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4489 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4490 } 4491 4492 static int 4493 alc_init_rx_ring(struct alc_softc *sc) 4494 { 4495 struct alc_ring_data *rd; 4496 struct alc_rxdesc *rxd; 4497 int i; 4498 4499 ALC_LOCK_ASSERT(sc); 4500 4501 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4502 sc->alc_morework = 0; 4503 rd = &sc->alc_rdata; 4504 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4505 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4506 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4507 rxd->rx_m = NULL; 4508 rxd->rx_desc = &rd->alc_rx_ring[i]; 4509 if (alc_newbuf(sc, rxd) != 0) 4510 return (ENOBUFS); 4511 } 4512 4513 /* 4514 * Since controller does not update Rx descriptors, driver 4515 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4516 * is enough to ensure coherence. 4517 */ 4518 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4519 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4520 /* Let controller know availability of new Rx buffers. */ 4521 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4522 4523 return (0); 4524 } 4525 4526 static void 4527 alc_init_rr_ring(struct alc_softc *sc) 4528 { 4529 struct alc_ring_data *rd; 4530 4531 ALC_LOCK_ASSERT(sc); 4532 4533 sc->alc_cdata.alc_rr_cons = 0; 4534 ALC_RXCHAIN_RESET(sc); 4535 4536 rd = &sc->alc_rdata; 4537 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4538 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4539 sc->alc_cdata.alc_rr_ring_map, 4540 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4541 } 4542 4543 static void 4544 alc_init_cmb(struct alc_softc *sc) 4545 { 4546 struct alc_ring_data *rd; 4547 4548 ALC_LOCK_ASSERT(sc); 4549 4550 rd = &sc->alc_rdata; 4551 bzero(rd->alc_cmb, ALC_CMB_SZ); 4552 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4554 } 4555 4556 static void 4557 alc_init_smb(struct alc_softc *sc) 4558 { 4559 struct alc_ring_data *rd; 4560 4561 ALC_LOCK_ASSERT(sc); 4562 4563 rd = &sc->alc_rdata; 4564 bzero(rd->alc_smb, ALC_SMB_SZ); 4565 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4566 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4567 } 4568 4569 static void 4570 alc_rxvlan(struct alc_softc *sc) 4571 { 4572 if_t ifp; 4573 uint32_t reg; 4574 4575 ALC_LOCK_ASSERT(sc); 4576 4577 ifp = sc->alc_ifp; 4578 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4579 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4580 reg |= MAC_CFG_VLAN_TAG_STRIP; 4581 else 4582 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4583 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4584 } 4585 4586 static u_int 4587 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4588 { 4589 uint32_t *mchash = arg; 4590 uint32_t crc; 4591 4592 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4593 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4594 4595 return (1); 4596 } 4597 4598 static void 4599 alc_rxfilter(struct alc_softc *sc) 4600 { 4601 if_t ifp; 4602 uint32_t mchash[2]; 4603 uint32_t rxcfg; 4604 4605 ALC_LOCK_ASSERT(sc); 4606 4607 ifp = sc->alc_ifp; 4608 4609 bzero(mchash, sizeof(mchash)); 4610 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4611 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4612 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4613 rxcfg |= MAC_CFG_BCAST; 4614 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4615 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4616 rxcfg |= MAC_CFG_PROMISC; 4617 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4618 rxcfg |= MAC_CFG_ALLMULTI; 4619 mchash[0] = 0xFFFFFFFF; 4620 mchash[1] = 0xFFFFFFFF; 4621 goto chipit; 4622 } 4623 4624 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4625 4626 chipit: 4627 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4628 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4629 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4630 } 4631 4632 static int 4633 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4634 { 4635 int error, value; 4636 4637 if (arg1 == NULL) 4638 return (EINVAL); 4639 value = *(int *)arg1; 4640 error = sysctl_handle_int(oidp, &value, 0, req); 4641 if (error || req->newptr == NULL) 4642 return (error); 4643 if (value < low || value > high) 4644 return (EINVAL); 4645 *(int *)arg1 = value; 4646 4647 return (0); 4648 } 4649 4650 static int 4651 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4652 { 4653 return (sysctl_int_range(oidp, arg1, arg2, req, 4654 ALC_PROC_MIN, ALC_PROC_MAX)); 4655 } 4656 4657 static int 4658 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4659 { 4660 4661 return (sysctl_int_range(oidp, arg1, arg2, req, 4662 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4663 } 4664 4665 #ifdef DEBUGNET 4666 static void 4667 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4668 { 4669 struct alc_softc *sc __diagused; 4670 4671 sc = if_getsoftc(ifp); 4672 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4673 4674 *nrxr = ALC_RX_RING_CNT; 4675 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4676 *clsize = MCLBYTES; 4677 } 4678 4679 static void 4680 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4681 { 4682 } 4683 4684 static int 4685 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4686 { 4687 struct alc_softc *sc; 4688 int error; 4689 4690 sc = if_getsoftc(ifp); 4691 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4692 IFF_DRV_RUNNING) 4693 return (EBUSY); 4694 4695 error = alc_encap(sc, &m); 4696 if (error == 0) 4697 alc_start_tx(sc); 4698 return (error); 4699 } 4700 4701 static int 4702 alc_debugnet_poll(if_t ifp, int count) 4703 { 4704 struct alc_softc *sc; 4705 4706 sc = if_getsoftc(ifp); 4707 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4708 IFF_DRV_RUNNING) 4709 return (EBUSY); 4710 4711 alc_txeof(sc); 4712 return (alc_rxintr(sc, count)); 4713 } 4714 #endif /* DEBUGNET */ 4715