1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/atomic.h> 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 #ifndef IFCAP_VLAN_HWTSO 88 #define IFCAP_VLAN_HWTSO 0 89 #endif 90 91 MODULE_DEPEND(alc, pci, 1, 1, 1); 92 MODULE_DEPEND(alc, ether, 1, 1, 1); 93 MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95 /* Tunables. */ 96 static int msi_disable = 0; 97 static int msix_disable = 0; 98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101 /* 102 * Devices supported by this driver. 103 */ 104 static struct alc_dev { 105 uint16_t alc_vendorid; 106 uint16_t alc_deviceid; 107 const char *alc_name; 108 } alc_devs[] = { 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 110 "Atheros AR8131 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 112 "Atheros AR8132 PCIe Fast Ethernet" } 113 }; 114 115 static void alc_aspm(struct alc_softc *); 116 static int alc_attach(device_t); 117 static int alc_check_boundary(struct alc_softc *); 118 static int alc_detach(device_t); 119 static void alc_disable_l0s_l1(struct alc_softc *); 120 static int alc_dma_alloc(struct alc_softc *); 121 static void alc_dma_free(struct alc_softc *); 122 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 123 static int alc_encap(struct alc_softc *, struct mbuf **); 124 #ifndef __NO_STRICT_ALIGNMENT 125 static struct mbuf * 126 alc_fixup_rx(struct ifnet *, struct mbuf *); 127 #endif 128 static void alc_get_macaddr(struct alc_softc *); 129 static void alc_init(void *); 130 static void alc_init_cmb(struct alc_softc *); 131 static void alc_init_locked(struct alc_softc *); 132 static void alc_init_rr_ring(struct alc_softc *); 133 static int alc_init_rx_ring(struct alc_softc *); 134 static void alc_init_smb(struct alc_softc *); 135 static void alc_init_tx_ring(struct alc_softc *); 136 static void alc_int_task(void *, int); 137 static int alc_intr(void *); 138 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 139 static void alc_mac_config(struct alc_softc *); 140 static int alc_miibus_readreg(device_t, int, int); 141 static void alc_miibus_statchg(device_t); 142 static int alc_miibus_writereg(device_t, int, int, int); 143 static int alc_mediachange(struct ifnet *); 144 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 145 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 146 static void alc_phy_down(struct alc_softc *); 147 static void alc_phy_reset(struct alc_softc *); 148 static int alc_probe(device_t); 149 static void alc_reset(struct alc_softc *); 150 static int alc_resume(device_t); 151 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 152 static int alc_rxintr(struct alc_softc *, int); 153 static void alc_rxfilter(struct alc_softc *); 154 static void alc_rxvlan(struct alc_softc *); 155 static void alc_setlinkspeed(struct alc_softc *); 156 static void alc_setwol(struct alc_softc *); 157 static int alc_shutdown(device_t); 158 static void alc_start(struct ifnet *); 159 static void alc_start_queue(struct alc_softc *); 160 static void alc_stats_clear(struct alc_softc *); 161 static void alc_stats_update(struct alc_softc *); 162 static void alc_stop(struct alc_softc *); 163 static void alc_stop_mac(struct alc_softc *); 164 static void alc_stop_queue(struct alc_softc *); 165 static int alc_suspend(device_t); 166 static void alc_sysctl_node(struct alc_softc *); 167 static void alc_tick(void *); 168 static void alc_tx_task(void *, int); 169 static void alc_txeof(struct alc_softc *); 170 static void alc_watchdog(struct alc_softc *); 171 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 172 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 173 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 174 175 static device_method_t alc_methods[] = { 176 /* Device interface. */ 177 DEVMETHOD(device_probe, alc_probe), 178 DEVMETHOD(device_attach, alc_attach), 179 DEVMETHOD(device_detach, alc_detach), 180 DEVMETHOD(device_shutdown, alc_shutdown), 181 DEVMETHOD(device_suspend, alc_suspend), 182 DEVMETHOD(device_resume, alc_resume), 183 184 /* MII interface. */ 185 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 186 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 187 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 188 189 { NULL, NULL } 190 }; 191 192 static driver_t alc_driver = { 193 "alc", 194 alc_methods, 195 sizeof(struct alc_softc) 196 }; 197 198 static devclass_t alc_devclass; 199 200 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 201 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 202 203 static struct resource_spec alc_res_spec_mem[] = { 204 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 205 { -1, 0, 0 } 206 }; 207 208 static struct resource_spec alc_irq_spec_legacy[] = { 209 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 210 { -1, 0, 0 } 211 }; 212 213 static struct resource_spec alc_irq_spec_msi[] = { 214 { SYS_RES_IRQ, 1, RF_ACTIVE }, 215 { -1, 0, 0 } 216 }; 217 218 static struct resource_spec alc_irq_spec_msix[] = { 219 { SYS_RES_IRQ, 1, RF_ACTIVE }, 220 { -1, 0, 0 } 221 }; 222 223 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 224 225 static int 226 alc_miibus_readreg(device_t dev, int phy, int reg) 227 { 228 struct alc_softc *sc; 229 uint32_t v; 230 int i; 231 232 sc = device_get_softc(dev); 233 234 if (phy != sc->alc_phyaddr) 235 return (0); 236 237 /* 238 * For AR8132 fast ethernet controller, do not report 1000baseT 239 * capability to mii(4). Even though AR8132 uses the same 240 * model/revision number of F1 gigabit PHY, the PHY has no 241 * ability to establish 1000baseT link. 242 */ 243 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 244 reg == MII_EXTSR) 245 return (0); 246 247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALC_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) { 257 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262 } 263 264 static int 265 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266 { 267 struct alc_softc *sc; 268 uint32_t v; 269 int i; 270 271 sc = device_get_softc(dev); 272 273 if (phy != sc->alc_phyaddr) 274 return (0); 275 276 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 277 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 278 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 279 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 280 DELAY(5); 281 v = CSR_READ_4(sc, ALC_MDIO); 282 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 283 break; 284 } 285 286 if (i == 0) 287 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 288 289 return (0); 290 } 291 292 static void 293 alc_miibus_statchg(device_t dev) 294 { 295 struct alc_softc *sc; 296 struct mii_data *mii; 297 struct ifnet *ifp; 298 uint32_t reg; 299 300 sc = device_get_softc(dev); 301 302 mii = device_get_softc(sc->alc_miibus); 303 ifp = sc->alc_ifp; 304 if (mii == NULL || ifp == NULL || 305 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 306 return; 307 308 sc->alc_flags &= ~ALC_FLAG_LINK; 309 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 310 (IFM_ACTIVE | IFM_AVALID)) { 311 switch (IFM_SUBTYPE(mii->mii_media_active)) { 312 case IFM_10_T: 313 case IFM_100_TX: 314 sc->alc_flags |= ALC_FLAG_LINK; 315 break; 316 case IFM_1000_T: 317 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 318 sc->alc_flags |= ALC_FLAG_LINK; 319 break; 320 default: 321 break; 322 } 323 } 324 alc_stop_queue(sc); 325 /* Stop Rx/Tx MACs. */ 326 alc_stop_mac(sc); 327 328 /* Program MACs with resolved speed/duplex/flow-control. */ 329 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 330 alc_start_queue(sc); 331 alc_mac_config(sc); 332 /* Re-enable Tx/Rx MACs. */ 333 reg = CSR_READ_4(sc, ALC_MAC_CFG); 334 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 335 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 336 } 337 alc_aspm(sc); 338 } 339 340 static void 341 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 342 { 343 struct alc_softc *sc; 344 struct mii_data *mii; 345 346 sc = ifp->if_softc; 347 ALC_LOCK(sc); 348 if ((ifp->if_flags & IFF_UP) == 0) { 349 ALC_UNLOCK(sc); 350 return; 351 } 352 mii = device_get_softc(sc->alc_miibus); 353 354 mii_pollstat(mii); 355 ALC_UNLOCK(sc); 356 ifmr->ifm_status = mii->mii_media_status; 357 ifmr->ifm_active = mii->mii_media_active; 358 } 359 360 static int 361 alc_mediachange(struct ifnet *ifp) 362 { 363 struct alc_softc *sc; 364 struct mii_data *mii; 365 struct mii_softc *miisc; 366 int error; 367 368 sc = ifp->if_softc; 369 ALC_LOCK(sc); 370 mii = device_get_softc(sc->alc_miibus); 371 if (mii->mii_instance != 0) { 372 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 373 mii_phy_reset(miisc); 374 } 375 error = mii_mediachg(mii); 376 ALC_UNLOCK(sc); 377 378 return (error); 379 } 380 381 static int 382 alc_probe(device_t dev) 383 { 384 struct alc_dev *sp; 385 int i; 386 uint16_t vendor, devid; 387 388 vendor = pci_get_vendor(dev); 389 devid = pci_get_device(dev); 390 sp = alc_devs; 391 for (i = 0; i < sizeof(alc_devs) / sizeof(alc_devs[0]); i++) { 392 if (vendor == sp->alc_vendorid && 393 devid == sp->alc_deviceid) { 394 device_set_desc(dev, sp->alc_name); 395 return (BUS_PROBE_DEFAULT); 396 } 397 sp++; 398 } 399 400 return (ENXIO); 401 } 402 403 static void 404 alc_get_macaddr(struct alc_softc *sc) 405 { 406 uint32_t ea[2], opt; 407 int i; 408 409 opt = CSR_READ_4(sc, ALC_OPT_CFG); 410 if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 411 /* 412 * EEPROM found, let TWSI reload EEPROM configuration. 413 * This will set ethernet address of controller. 414 */ 415 if ((opt & OPT_CFG_CLK_ENB) == 0) { 416 opt |= OPT_CFG_CLK_ENB; 417 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 418 CSR_READ_4(sc, ALC_OPT_CFG); 419 DELAY(1000); 420 } 421 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 422 TWSI_CFG_SW_LD_START); 423 for (i = 100; i > 0; i--) { 424 DELAY(1000); 425 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 426 TWSI_CFG_SW_LD_START) == 0) 427 break; 428 } 429 if (i == 0) 430 device_printf(sc->alc_dev, 431 "reloading EEPROM timeout!\n"); 432 } else { 433 if (bootverbose) 434 device_printf(sc->alc_dev, "EEPROM not found!\n"); 435 } 436 if ((opt & OPT_CFG_CLK_ENB) != 0) { 437 opt &= ~OPT_CFG_CLK_ENB; 438 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 439 CSR_READ_4(sc, ALC_OPT_CFG); 440 DELAY(1000); 441 } 442 443 ea[0] = CSR_READ_4(sc, ALC_PAR0); 444 ea[1] = CSR_READ_4(sc, ALC_PAR1); 445 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 446 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 447 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 448 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 449 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 450 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 451 } 452 453 static void 454 alc_disable_l0s_l1(struct alc_softc *sc) 455 { 456 uint32_t pmcfg; 457 458 /* Another magic from vendor. */ 459 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 460 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 461 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 462 PM_CFG_SERDES_PD_EX_L1); 463 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 464 PM_CFG_SERDES_L1_ENB; 465 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 466 } 467 468 static void 469 alc_phy_reset(struct alc_softc *sc) 470 { 471 uint16_t data; 472 473 /* Reset magic from Linux. */ 474 CSR_WRITE_2(sc, ALC_GPHY_CFG, 475 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 476 CSR_READ_2(sc, ALC_GPHY_CFG); 477 DELAY(10 * 1000); 478 479 CSR_WRITE_2(sc, ALC_GPHY_CFG, 480 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 481 GPHY_CFG_SEL_ANA_RESET); 482 CSR_READ_2(sc, ALC_GPHY_CFG); 483 DELAY(10 * 1000); 484 485 /* Load DSP codes, vendor magic. */ 486 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 487 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 488 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 490 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 491 ALC_MII_DBG_DATA, data); 492 493 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 494 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 495 ANA_SERDES_EN_LCKDT; 496 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 498 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 499 ALC_MII_DBG_DATA, data); 500 501 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 502 ANA_LONG_CABLE_TH_100_MASK) | 503 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 504 ANA_SHORT_CABLE_TH_100_SHIFT) | 505 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 506 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 507 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 508 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 509 ALC_MII_DBG_DATA, data); 510 511 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 512 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 513 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 514 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 515 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 516 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 517 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 518 ALC_MII_DBG_DATA, data); 519 520 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 521 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 522 ANA_OEN_125M; 523 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 524 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 525 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 526 ALC_MII_DBG_DATA, data); 527 DELAY(1000); 528 } 529 530 static void 531 alc_phy_down(struct alc_softc *sc) 532 { 533 534 /* Force PHY down. */ 535 CSR_WRITE_2(sc, ALC_GPHY_CFG, 536 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 537 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); 538 DELAY(1000); 539 } 540 541 static void 542 alc_aspm(struct alc_softc *sc) 543 { 544 uint32_t pmcfg; 545 546 ALC_LOCK_ASSERT(sc); 547 548 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 549 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 550 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB; 551 pmcfg |= PM_CFG_SERDES_L1_ENB; 552 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 553 pmcfg |= PM_CFG_MAC_ASPM_CHK; 554 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 555 pmcfg |= PM_CFG_SERDES_PLL_L1_ENB; 556 pmcfg &= ~PM_CFG_CLK_SWH_L1; 557 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 558 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 559 } else { 560 pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB; 561 pmcfg |= PM_CFG_CLK_SWH_L1; 562 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 563 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 564 } 565 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 566 } 567 568 static int 569 alc_attach(device_t dev) 570 { 571 struct alc_softc *sc; 572 struct ifnet *ifp; 573 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" }; 574 uint16_t burst; 575 int base, error, i, msic, msixc, pmc, state; 576 uint32_t cap, ctl, val; 577 578 error = 0; 579 sc = device_get_softc(dev); 580 sc->alc_dev = dev; 581 582 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 583 MTX_DEF); 584 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 585 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 586 587 /* Map the device. */ 588 pci_enable_busmaster(dev); 589 sc->alc_res_spec = alc_res_spec_mem; 590 sc->alc_irq_spec = alc_irq_spec_legacy; 591 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 592 if (error != 0) { 593 device_printf(dev, "cannot allocate memory resources.\n"); 594 goto fail; 595 } 596 597 /* Set PHY address. */ 598 sc->alc_phyaddr = ALC_PHY_ADDR; 599 600 /* Initialize DMA parameters. */ 601 sc->alc_dma_rd_burst = 0; 602 sc->alc_dma_wr_burst = 0; 603 sc->alc_rcb = DMA_CFG_RCB_64; 604 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 605 sc->alc_flags |= ALC_FLAG_PCIE; 606 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 607 sc->alc_dma_rd_burst = 608 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 609 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 610 if (bootverbose) { 611 device_printf(dev, "Read request size : %u bytes.\n", 612 alc_dma_burst[sc->alc_dma_rd_burst]); 613 device_printf(dev, "TLP payload size : %u bytes.\n", 614 alc_dma_burst[sc->alc_dma_wr_burst]); 615 } 616 /* Clear data link and flow-control protocol error. */ 617 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 618 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 619 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 620 /* Disable ASPM L0S and L1. */ 621 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 622 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 623 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 624 if ((ctl & 0x08) != 0) 625 sc->alc_rcb = DMA_CFG_RCB_128; 626 if (bootverbose) 627 device_printf(dev, "RCB %u bytes\n", 628 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 629 state = ctl & 0x03; 630 if (bootverbose) 631 device_printf(sc->alc_dev, "ASPM %s %s\n", 632 aspm_state[state], 633 state == 0 ? "disabled" : "enabled"); 634 if (state != 0) 635 alc_disable_l0s_l1(sc); 636 } 637 } 638 639 /* Reset PHY. */ 640 alc_phy_reset(sc); 641 642 /* Reset the ethernet controller. */ 643 alc_reset(sc); 644 645 /* 646 * One odd thing is AR8132 uses the same PHY hardware(F1 647 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 648 * the PHY supports 1000Mbps but that's not true. The PHY 649 * used in AR8132 can't establish gigabit link even if it 650 * shows the same PHY model/revision number of AR8131. 651 */ 652 if (pci_get_device(dev) == DEVICEID_ATHEROS_AR8132) 653 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO; 654 else 655 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 656 /* 657 * It seems that AR8131/AR8132 has silicon bug for SMB. In 658 * addition, Atheros said that enabling SMB wouldn't improve 659 * performance. However I think it's bad to access lots of 660 * registers to extract MAC statistics. 661 */ 662 sc->alc_flags |= ALC_FLAG_SMB_BUG; 663 /* 664 * Don't use Tx CMB. It is known to have silicon bug. 665 */ 666 sc->alc_flags |= ALC_FLAG_CMB_BUG; 667 sc->alc_rev = pci_get_revid(dev); 668 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 669 MASTER_CHIP_REV_SHIFT; 670 if (bootverbose) { 671 device_printf(dev, "PCI device revision : 0x%04x\n", 672 sc->alc_rev); 673 device_printf(dev, "Chip id/revision : 0x%04x\n", 674 sc->alc_chip_rev); 675 } 676 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 677 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 678 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 679 680 /* Allocate IRQ resources. */ 681 msixc = pci_msix_count(dev); 682 msic = pci_msi_count(dev); 683 if (bootverbose) { 684 device_printf(dev, "MSIX count : %d\n", msixc); 685 device_printf(dev, "MSI count : %d\n", msic); 686 } 687 /* Prefer MSIX over MSI. */ 688 if (msix_disable == 0 || msi_disable == 0) { 689 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 690 pci_alloc_msix(dev, &msixc) == 0) { 691 if (msic == ALC_MSIX_MESSAGES) { 692 device_printf(dev, 693 "Using %d MSIX message(s).\n", msixc); 694 sc->alc_flags |= ALC_FLAG_MSIX; 695 sc->alc_irq_spec = alc_irq_spec_msix; 696 } else 697 pci_release_msi(dev); 698 } 699 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 700 msic == ALC_MSI_MESSAGES && 701 pci_alloc_msi(dev, &msic) == 0) { 702 if (msic == ALC_MSI_MESSAGES) { 703 device_printf(dev, 704 "Using %d MSI message(s).\n", msic); 705 sc->alc_flags |= ALC_FLAG_MSI; 706 sc->alc_irq_spec = alc_irq_spec_msi; 707 } else 708 pci_release_msi(dev); 709 } 710 } 711 712 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 713 if (error != 0) { 714 device_printf(dev, "cannot allocate IRQ resources.\n"); 715 goto fail; 716 } 717 718 /* Create device sysctl node. */ 719 alc_sysctl_node(sc); 720 721 if ((error = alc_dma_alloc(sc) != 0)) 722 goto fail; 723 724 /* Load station address. */ 725 alc_get_macaddr(sc); 726 727 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 728 if (ifp == NULL) { 729 device_printf(dev, "cannot allocate ifnet structure.\n"); 730 error = ENXIO; 731 goto fail; 732 } 733 734 ifp->if_softc = sc; 735 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 736 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 737 ifp->if_ioctl = alc_ioctl; 738 ifp->if_start = alc_start; 739 ifp->if_init = alc_init; 740 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 741 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 742 IFQ_SET_READY(&ifp->if_snd); 743 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 744 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 745 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 746 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 747 ifp->if_capenable = ifp->if_capabilities; 748 749 /* Set up MII bus. */ 750 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 751 alc_mediastatus)) != 0) { 752 device_printf(dev, "no PHY found!\n"); 753 goto fail; 754 } 755 756 ether_ifattach(ifp, sc->alc_eaddr); 757 758 /* VLAN capability setup. */ 759 ifp->if_capabilities |= IFCAP_VLAN_MTU; 760 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 761 ifp->if_capenable = ifp->if_capabilities; 762 /* 763 * XXX 764 * It seems enabling Tx checksum offloading makes more trouble. 765 * Sometimes the controller does not receive any frames when 766 * Tx checksum offloading is enabled. I'm not sure whether this 767 * is a bug in Tx checksum offloading logic or I got broken 768 * sample boards. To safety, don't enable Tx checksum offloading 769 * by default but give chance to users to toggle it if they know 770 * their controllers work without problems. 771 */ 772 ifp->if_capenable &= ~IFCAP_TXCSUM; 773 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 774 775 /* Tell the upper layer(s) we support long frames. */ 776 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 777 778 /* Create local taskq. */ 779 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 780 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 781 taskqueue_thread_enqueue, &sc->alc_tq); 782 if (sc->alc_tq == NULL) { 783 device_printf(dev, "could not create taskqueue.\n"); 784 ether_ifdetach(ifp); 785 error = ENXIO; 786 goto fail; 787 } 788 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 789 device_get_nameunit(sc->alc_dev)); 790 791 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 792 msic = ALC_MSIX_MESSAGES; 793 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 794 msic = ALC_MSI_MESSAGES; 795 else 796 msic = 1; 797 for (i = 0; i < msic; i++) { 798 error = bus_setup_intr(dev, sc->alc_irq[i], 799 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 800 &sc->alc_intrhand[i]); 801 if (error != 0) 802 break; 803 } 804 if (error != 0) { 805 device_printf(dev, "could not set up interrupt handler.\n"); 806 taskqueue_free(sc->alc_tq); 807 sc->alc_tq = NULL; 808 ether_ifdetach(ifp); 809 goto fail; 810 } 811 812 fail: 813 if (error != 0) 814 alc_detach(dev); 815 816 return (error); 817 } 818 819 static int 820 alc_detach(device_t dev) 821 { 822 struct alc_softc *sc; 823 struct ifnet *ifp; 824 int i, msic; 825 826 sc = device_get_softc(dev); 827 828 ifp = sc->alc_ifp; 829 if (device_is_attached(dev)) { 830 ALC_LOCK(sc); 831 sc->alc_flags |= ALC_FLAG_DETACH; 832 alc_stop(sc); 833 ALC_UNLOCK(sc); 834 callout_drain(&sc->alc_tick_ch); 835 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 836 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 837 ether_ifdetach(ifp); 838 } 839 840 if (sc->alc_tq != NULL) { 841 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 842 taskqueue_free(sc->alc_tq); 843 sc->alc_tq = NULL; 844 } 845 846 if (sc->alc_miibus != NULL) { 847 device_delete_child(dev, sc->alc_miibus); 848 sc->alc_miibus = NULL; 849 } 850 bus_generic_detach(dev); 851 alc_dma_free(sc); 852 853 if (ifp != NULL) { 854 if_free(ifp); 855 sc->alc_ifp = NULL; 856 } 857 858 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 859 msic = ALC_MSIX_MESSAGES; 860 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 861 msic = ALC_MSI_MESSAGES; 862 else 863 msic = 1; 864 for (i = 0; i < msic; i++) { 865 if (sc->alc_intrhand[i] != NULL) { 866 bus_teardown_intr(dev, sc->alc_irq[i], 867 sc->alc_intrhand[i]); 868 sc->alc_intrhand[i] = NULL; 869 } 870 } 871 if (sc->alc_res[0] != NULL) 872 alc_phy_down(sc); 873 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 874 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 875 pci_release_msi(dev); 876 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 877 mtx_destroy(&sc->alc_mtx); 878 879 return (0); 880 } 881 882 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 883 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 884 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 885 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 886 887 static void 888 alc_sysctl_node(struct alc_softc *sc) 889 { 890 struct sysctl_ctx_list *ctx; 891 struct sysctl_oid_list *child, *parent; 892 struct sysctl_oid *tree; 893 struct alc_hw_stats *stats; 894 int error; 895 896 stats = &sc->alc_stats; 897 ctx = device_get_sysctl_ctx(sc->alc_dev); 898 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 899 900 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 901 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 902 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 903 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 904 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 905 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 906 /* Pull in device tunables. */ 907 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 908 error = resource_int_value(device_get_name(sc->alc_dev), 909 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 910 if (error == 0) { 911 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 912 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 913 device_printf(sc->alc_dev, "int_rx_mod value out of " 914 "range; using default: %d\n", 915 ALC_IM_RX_TIMER_DEFAULT); 916 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 917 } 918 } 919 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 920 error = resource_int_value(device_get_name(sc->alc_dev), 921 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 922 if (error == 0) { 923 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 924 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 925 device_printf(sc->alc_dev, "int_tx_mod value out of " 926 "range; using default: %d\n", 927 ALC_IM_TX_TIMER_DEFAULT); 928 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 929 } 930 } 931 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 932 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 933 sysctl_hw_alc_proc_limit, "I", 934 "max number of Rx events to process"); 935 /* Pull in device tunables. */ 936 sc->alc_process_limit = ALC_PROC_DEFAULT; 937 error = resource_int_value(device_get_name(sc->alc_dev), 938 device_get_unit(sc->alc_dev), "process_limit", 939 &sc->alc_process_limit); 940 if (error == 0) { 941 if (sc->alc_process_limit < ALC_PROC_MIN || 942 sc->alc_process_limit > ALC_PROC_MAX) { 943 device_printf(sc->alc_dev, 944 "process_limit value out of range; " 945 "using default: %d\n", ALC_PROC_DEFAULT); 946 sc->alc_process_limit = ALC_PROC_DEFAULT; 947 } 948 } 949 950 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 951 NULL, "ALC statistics"); 952 parent = SYSCTL_CHILDREN(tree); 953 954 /* Rx statistics. */ 955 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 956 NULL, "Rx MAC statistics"); 957 child = SYSCTL_CHILDREN(tree); 958 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 959 &stats->rx_frames, "Good frames"); 960 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 961 &stats->rx_bcast_frames, "Good broadcast frames"); 962 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 963 &stats->rx_mcast_frames, "Good multicast frames"); 964 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 965 &stats->rx_pause_frames, "Pause control frames"); 966 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 967 &stats->rx_control_frames, "Control frames"); 968 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 969 &stats->rx_crcerrs, "CRC errors"); 970 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 971 &stats->rx_lenerrs, "Frames with length mismatched"); 972 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 973 &stats->rx_bytes, "Good octets"); 974 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 975 &stats->rx_bcast_bytes, "Good broadcast octets"); 976 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 977 &stats->rx_mcast_bytes, "Good multicast octets"); 978 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 979 &stats->rx_runts, "Too short frames"); 980 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 981 &stats->rx_fragments, "Fragmented frames"); 982 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 983 &stats->rx_pkts_64, "64 bytes frames"); 984 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 985 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 986 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 987 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 988 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 989 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 990 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 991 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 992 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 993 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 994 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 995 &stats->rx_pkts_1519_max, "1519 to max frames"); 996 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 997 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 998 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 999 &stats->rx_fifo_oflows, "FIFO overflows"); 1000 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1001 &stats->rx_rrs_errs, "Return status write-back errors"); 1002 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1003 &stats->rx_alignerrs, "Alignment errors"); 1004 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1005 &stats->rx_pkts_filtered, 1006 "Frames dropped due to address filtering"); 1007 1008 /* Tx statistics. */ 1009 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1010 NULL, "Tx MAC statistics"); 1011 child = SYSCTL_CHILDREN(tree); 1012 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1013 &stats->tx_frames, "Good frames"); 1014 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1015 &stats->tx_bcast_frames, "Good broadcast frames"); 1016 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1017 &stats->tx_mcast_frames, "Good multicast frames"); 1018 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1019 &stats->tx_pause_frames, "Pause control frames"); 1020 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1021 &stats->tx_control_frames, "Control frames"); 1022 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1023 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1024 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1025 &stats->tx_excess_defer, "Frames with derferrals"); 1026 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1027 &stats->tx_bytes, "Good octets"); 1028 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1029 &stats->tx_bcast_bytes, "Good broadcast octets"); 1030 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1031 &stats->tx_mcast_bytes, "Good multicast octets"); 1032 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1033 &stats->tx_pkts_64, "64 bytes frames"); 1034 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1035 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1036 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1037 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1038 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1039 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1040 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1041 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1042 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1043 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1044 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1045 &stats->tx_pkts_1519_max, "1519 to max frames"); 1046 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1047 &stats->tx_single_colls, "Single collisions"); 1048 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1049 &stats->tx_multi_colls, "Multiple collisions"); 1050 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1051 &stats->tx_late_colls, "Late collisions"); 1052 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1053 &stats->tx_excess_colls, "Excessive collisions"); 1054 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1055 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1056 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1057 &stats->tx_underrun, "FIFO underruns"); 1058 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1059 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1060 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1061 &stats->tx_lenerrs, "Frames with length mismatched"); 1062 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1063 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1064 } 1065 1066 #undef ALC_SYSCTL_STAT_ADD32 1067 #undef ALC_SYSCTL_STAT_ADD64 1068 1069 struct alc_dmamap_arg { 1070 bus_addr_t alc_busaddr; 1071 }; 1072 1073 static void 1074 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1075 { 1076 struct alc_dmamap_arg *ctx; 1077 1078 if (error != 0) 1079 return; 1080 1081 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1082 1083 ctx = (struct alc_dmamap_arg *)arg; 1084 ctx->alc_busaddr = segs[0].ds_addr; 1085 } 1086 1087 /* 1088 * Normal and high Tx descriptors shares single Tx high address. 1089 * Four Rx descriptor/return rings and CMB shares the same Rx 1090 * high address. 1091 */ 1092 static int 1093 alc_check_boundary(struct alc_softc *sc) 1094 { 1095 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1096 1097 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1098 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1099 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1100 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1101 1102 /* 4GB boundary crossing is not allowed. */ 1103 if ((ALC_ADDR_HI(rx_ring_end) != 1104 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1105 (ALC_ADDR_HI(rr_ring_end) != 1106 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1107 (ALC_ADDR_HI(cmb_end) != 1108 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1109 (ALC_ADDR_HI(tx_ring_end) != 1110 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1111 return (EFBIG); 1112 /* 1113 * Make sure Rx return descriptor/Rx descriptor/CMB use 1114 * the same high address. 1115 */ 1116 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1117 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1118 return (EFBIG); 1119 1120 return (0); 1121 } 1122 1123 static int 1124 alc_dma_alloc(struct alc_softc *sc) 1125 { 1126 struct alc_txdesc *txd; 1127 struct alc_rxdesc *rxd; 1128 bus_addr_t lowaddr; 1129 struct alc_dmamap_arg ctx; 1130 int error, i; 1131 1132 lowaddr = BUS_SPACE_MAXADDR; 1133 again: 1134 /* Create parent DMA tag. */ 1135 error = bus_dma_tag_create( 1136 bus_get_dma_tag(sc->alc_dev), /* parent */ 1137 1, 0, /* alignment, boundary */ 1138 lowaddr, /* lowaddr */ 1139 BUS_SPACE_MAXADDR, /* highaddr */ 1140 NULL, NULL, /* filter, filterarg */ 1141 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1142 0, /* nsegments */ 1143 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1144 0, /* flags */ 1145 NULL, NULL, /* lockfunc, lockarg */ 1146 &sc->alc_cdata.alc_parent_tag); 1147 if (error != 0) { 1148 device_printf(sc->alc_dev, 1149 "could not create parent DMA tag.\n"); 1150 goto fail; 1151 } 1152 1153 /* Create DMA tag for Tx descriptor ring. */ 1154 error = bus_dma_tag_create( 1155 sc->alc_cdata.alc_parent_tag, /* parent */ 1156 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1157 BUS_SPACE_MAXADDR, /* lowaddr */ 1158 BUS_SPACE_MAXADDR, /* highaddr */ 1159 NULL, NULL, /* filter, filterarg */ 1160 ALC_TX_RING_SZ, /* maxsize */ 1161 1, /* nsegments */ 1162 ALC_TX_RING_SZ, /* maxsegsize */ 1163 0, /* flags */ 1164 NULL, NULL, /* lockfunc, lockarg */ 1165 &sc->alc_cdata.alc_tx_ring_tag); 1166 if (error != 0) { 1167 device_printf(sc->alc_dev, 1168 "could not create Tx ring DMA tag.\n"); 1169 goto fail; 1170 } 1171 1172 /* Create DMA tag for Rx free descriptor ring. */ 1173 error = bus_dma_tag_create( 1174 sc->alc_cdata.alc_parent_tag, /* parent */ 1175 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1176 BUS_SPACE_MAXADDR, /* lowaddr */ 1177 BUS_SPACE_MAXADDR, /* highaddr */ 1178 NULL, NULL, /* filter, filterarg */ 1179 ALC_RX_RING_SZ, /* maxsize */ 1180 1, /* nsegments */ 1181 ALC_RX_RING_SZ, /* maxsegsize */ 1182 0, /* flags */ 1183 NULL, NULL, /* lockfunc, lockarg */ 1184 &sc->alc_cdata.alc_rx_ring_tag); 1185 if (error != 0) { 1186 device_printf(sc->alc_dev, 1187 "could not create Rx ring DMA tag.\n"); 1188 goto fail; 1189 } 1190 /* Create DMA tag for Rx return descriptor ring. */ 1191 error = bus_dma_tag_create( 1192 sc->alc_cdata.alc_parent_tag, /* parent */ 1193 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1194 BUS_SPACE_MAXADDR, /* lowaddr */ 1195 BUS_SPACE_MAXADDR, /* highaddr */ 1196 NULL, NULL, /* filter, filterarg */ 1197 ALC_RR_RING_SZ, /* maxsize */ 1198 1, /* nsegments */ 1199 ALC_RR_RING_SZ, /* maxsegsize */ 1200 0, /* flags */ 1201 NULL, NULL, /* lockfunc, lockarg */ 1202 &sc->alc_cdata.alc_rr_ring_tag); 1203 if (error != 0) { 1204 device_printf(sc->alc_dev, 1205 "could not create Rx return ring DMA tag.\n"); 1206 goto fail; 1207 } 1208 1209 /* Create DMA tag for coalescing message block. */ 1210 error = bus_dma_tag_create( 1211 sc->alc_cdata.alc_parent_tag, /* parent */ 1212 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1213 BUS_SPACE_MAXADDR, /* lowaddr */ 1214 BUS_SPACE_MAXADDR, /* highaddr */ 1215 NULL, NULL, /* filter, filterarg */ 1216 ALC_CMB_SZ, /* maxsize */ 1217 1, /* nsegments */ 1218 ALC_CMB_SZ, /* maxsegsize */ 1219 0, /* flags */ 1220 NULL, NULL, /* lockfunc, lockarg */ 1221 &sc->alc_cdata.alc_cmb_tag); 1222 if (error != 0) { 1223 device_printf(sc->alc_dev, 1224 "could not create CMB DMA tag.\n"); 1225 goto fail; 1226 } 1227 /* Create DMA tag for status message block. */ 1228 error = bus_dma_tag_create( 1229 sc->alc_cdata.alc_parent_tag, /* parent */ 1230 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1231 BUS_SPACE_MAXADDR, /* lowaddr */ 1232 BUS_SPACE_MAXADDR, /* highaddr */ 1233 NULL, NULL, /* filter, filterarg */ 1234 ALC_SMB_SZ, /* maxsize */ 1235 1, /* nsegments */ 1236 ALC_SMB_SZ, /* maxsegsize */ 1237 0, /* flags */ 1238 NULL, NULL, /* lockfunc, lockarg */ 1239 &sc->alc_cdata.alc_smb_tag); 1240 if (error != 0) { 1241 device_printf(sc->alc_dev, 1242 "could not create SMB DMA tag.\n"); 1243 goto fail; 1244 } 1245 1246 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1247 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1248 (void **)&sc->alc_rdata.alc_tx_ring, 1249 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1250 &sc->alc_cdata.alc_tx_ring_map); 1251 if (error != 0) { 1252 device_printf(sc->alc_dev, 1253 "could not allocate DMA'able memory for Tx ring.\n"); 1254 goto fail; 1255 } 1256 ctx.alc_busaddr = 0; 1257 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1258 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1259 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1260 if (error != 0 || ctx.alc_busaddr == 0) { 1261 device_printf(sc->alc_dev, 1262 "could not load DMA'able memory for Tx ring.\n"); 1263 goto fail; 1264 } 1265 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1266 1267 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1268 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1269 (void **)&sc->alc_rdata.alc_rx_ring, 1270 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1271 &sc->alc_cdata.alc_rx_ring_map); 1272 if (error != 0) { 1273 device_printf(sc->alc_dev, 1274 "could not allocate DMA'able memory for Rx ring.\n"); 1275 goto fail; 1276 } 1277 ctx.alc_busaddr = 0; 1278 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1279 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1280 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1281 if (error != 0 || ctx.alc_busaddr == 0) { 1282 device_printf(sc->alc_dev, 1283 "could not load DMA'able memory for Rx ring.\n"); 1284 goto fail; 1285 } 1286 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1287 1288 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1289 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1290 (void **)&sc->alc_rdata.alc_rr_ring, 1291 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1292 &sc->alc_cdata.alc_rr_ring_map); 1293 if (error != 0) { 1294 device_printf(sc->alc_dev, 1295 "could not allocate DMA'able memory for Rx return ring.\n"); 1296 goto fail; 1297 } 1298 ctx.alc_busaddr = 0; 1299 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1300 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1301 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1302 if (error != 0 || ctx.alc_busaddr == 0) { 1303 device_printf(sc->alc_dev, 1304 "could not load DMA'able memory for Tx ring.\n"); 1305 goto fail; 1306 } 1307 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1308 1309 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1310 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1311 (void **)&sc->alc_rdata.alc_cmb, 1312 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1313 &sc->alc_cdata.alc_cmb_map); 1314 if (error != 0) { 1315 device_printf(sc->alc_dev, 1316 "could not allocate DMA'able memory for CMB.\n"); 1317 goto fail; 1318 } 1319 ctx.alc_busaddr = 0; 1320 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1321 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1322 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1323 if (error != 0 || ctx.alc_busaddr == 0) { 1324 device_printf(sc->alc_dev, 1325 "could not load DMA'able memory for CMB.\n"); 1326 goto fail; 1327 } 1328 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1329 1330 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1331 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1332 (void **)&sc->alc_rdata.alc_smb, 1333 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1334 &sc->alc_cdata.alc_smb_map); 1335 if (error != 0) { 1336 device_printf(sc->alc_dev, 1337 "could not allocate DMA'able memory for SMB.\n"); 1338 goto fail; 1339 } 1340 ctx.alc_busaddr = 0; 1341 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1342 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1343 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1344 if (error != 0 || ctx.alc_busaddr == 0) { 1345 device_printf(sc->alc_dev, 1346 "could not load DMA'able memory for CMB.\n"); 1347 goto fail; 1348 } 1349 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1350 1351 /* Make sure we've not crossed 4GB boundary. */ 1352 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1353 (error = alc_check_boundary(sc)) != 0) { 1354 device_printf(sc->alc_dev, "4GB boundary crossed, " 1355 "switching to 32bit DMA addressing mode.\n"); 1356 alc_dma_free(sc); 1357 /* 1358 * Limit max allowable DMA address space to 32bit 1359 * and try again. 1360 */ 1361 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1362 goto again; 1363 } 1364 1365 /* 1366 * Create Tx buffer parent tag. 1367 * AR8131/AR8132 allows 64bit DMA addressing of Tx/Rx buffers 1368 * so it needs separate parent DMA tag as parent DMA address 1369 * space could be restricted to be within 32bit address space 1370 * by 4GB boundary crossing. 1371 */ 1372 error = bus_dma_tag_create( 1373 bus_get_dma_tag(sc->alc_dev), /* parent */ 1374 1, 0, /* alignment, boundary */ 1375 BUS_SPACE_MAXADDR, /* lowaddr */ 1376 BUS_SPACE_MAXADDR, /* highaddr */ 1377 NULL, NULL, /* filter, filterarg */ 1378 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1379 0, /* nsegments */ 1380 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1381 0, /* flags */ 1382 NULL, NULL, /* lockfunc, lockarg */ 1383 &sc->alc_cdata.alc_buffer_tag); 1384 if (error != 0) { 1385 device_printf(sc->alc_dev, 1386 "could not create parent buffer DMA tag.\n"); 1387 goto fail; 1388 } 1389 1390 /* Create DMA tag for Tx buffers. */ 1391 error = bus_dma_tag_create( 1392 sc->alc_cdata.alc_buffer_tag, /* parent */ 1393 1, 0, /* alignment, boundary */ 1394 BUS_SPACE_MAXADDR, /* lowaddr */ 1395 BUS_SPACE_MAXADDR, /* highaddr */ 1396 NULL, NULL, /* filter, filterarg */ 1397 ALC_TSO_MAXSIZE, /* maxsize */ 1398 ALC_MAXTXSEGS, /* nsegments */ 1399 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1400 0, /* flags */ 1401 NULL, NULL, /* lockfunc, lockarg */ 1402 &sc->alc_cdata.alc_tx_tag); 1403 if (error != 0) { 1404 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1405 goto fail; 1406 } 1407 1408 /* Create DMA tag for Rx buffers. */ 1409 error = bus_dma_tag_create( 1410 sc->alc_cdata.alc_buffer_tag, /* parent */ 1411 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1412 BUS_SPACE_MAXADDR, /* lowaddr */ 1413 BUS_SPACE_MAXADDR, /* highaddr */ 1414 NULL, NULL, /* filter, filterarg */ 1415 MCLBYTES, /* maxsize */ 1416 1, /* nsegments */ 1417 MCLBYTES, /* maxsegsize */ 1418 0, /* flags */ 1419 NULL, NULL, /* lockfunc, lockarg */ 1420 &sc->alc_cdata.alc_rx_tag); 1421 if (error != 0) { 1422 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1423 goto fail; 1424 } 1425 /* Create DMA maps for Tx buffers. */ 1426 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1427 txd = &sc->alc_cdata.alc_txdesc[i]; 1428 txd->tx_m = NULL; 1429 txd->tx_dmamap = NULL; 1430 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1431 &txd->tx_dmamap); 1432 if (error != 0) { 1433 device_printf(sc->alc_dev, 1434 "could not create Tx dmamap.\n"); 1435 goto fail; 1436 } 1437 } 1438 /* Create DMA maps for Rx buffers. */ 1439 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1440 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1441 device_printf(sc->alc_dev, 1442 "could not create spare Rx dmamap.\n"); 1443 goto fail; 1444 } 1445 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1446 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1447 rxd->rx_m = NULL; 1448 rxd->rx_dmamap = NULL; 1449 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1450 &rxd->rx_dmamap); 1451 if (error != 0) { 1452 device_printf(sc->alc_dev, 1453 "could not create Rx dmamap.\n"); 1454 goto fail; 1455 } 1456 } 1457 1458 fail: 1459 return (error); 1460 } 1461 1462 static void 1463 alc_dma_free(struct alc_softc *sc) 1464 { 1465 struct alc_txdesc *txd; 1466 struct alc_rxdesc *rxd; 1467 int i; 1468 1469 /* Tx buffers. */ 1470 if (sc->alc_cdata.alc_tx_tag != NULL) { 1471 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1472 txd = &sc->alc_cdata.alc_txdesc[i]; 1473 if (txd->tx_dmamap != NULL) { 1474 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1475 txd->tx_dmamap); 1476 txd->tx_dmamap = NULL; 1477 } 1478 } 1479 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1480 sc->alc_cdata.alc_tx_tag = NULL; 1481 } 1482 /* Rx buffers */ 1483 if (sc->alc_cdata.alc_rx_tag != NULL) { 1484 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1485 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1486 if (rxd->rx_dmamap != NULL) { 1487 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1488 rxd->rx_dmamap); 1489 rxd->rx_dmamap = NULL; 1490 } 1491 } 1492 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1493 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1494 sc->alc_cdata.alc_rx_sparemap); 1495 sc->alc_cdata.alc_rx_sparemap = NULL; 1496 } 1497 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1498 sc->alc_cdata.alc_rx_tag = NULL; 1499 } 1500 /* Tx descriptor ring. */ 1501 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1502 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1503 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1504 sc->alc_cdata.alc_tx_ring_map); 1505 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1506 sc->alc_rdata.alc_tx_ring != NULL) 1507 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1508 sc->alc_rdata.alc_tx_ring, 1509 sc->alc_cdata.alc_tx_ring_map); 1510 sc->alc_rdata.alc_tx_ring = NULL; 1511 sc->alc_cdata.alc_tx_ring_map = NULL; 1512 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1513 sc->alc_cdata.alc_tx_ring_tag = NULL; 1514 } 1515 /* Rx ring. */ 1516 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1517 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1518 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1519 sc->alc_cdata.alc_rx_ring_map); 1520 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1521 sc->alc_rdata.alc_rx_ring != NULL) 1522 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1523 sc->alc_rdata.alc_rx_ring, 1524 sc->alc_cdata.alc_rx_ring_map); 1525 sc->alc_rdata.alc_rx_ring = NULL; 1526 sc->alc_cdata.alc_rx_ring_map = NULL; 1527 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1528 sc->alc_cdata.alc_rx_ring_tag = NULL; 1529 } 1530 /* Rx return ring. */ 1531 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1532 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1533 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1534 sc->alc_cdata.alc_rr_ring_map); 1535 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1536 sc->alc_rdata.alc_rr_ring != NULL) 1537 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1538 sc->alc_rdata.alc_rr_ring, 1539 sc->alc_cdata.alc_rr_ring_map); 1540 sc->alc_rdata.alc_rr_ring = NULL; 1541 sc->alc_cdata.alc_rr_ring_map = NULL; 1542 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1543 sc->alc_cdata.alc_rr_ring_tag = NULL; 1544 } 1545 /* CMB block */ 1546 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1547 if (sc->alc_cdata.alc_cmb_map != NULL) 1548 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1549 sc->alc_cdata.alc_cmb_map); 1550 if (sc->alc_cdata.alc_cmb_map != NULL && 1551 sc->alc_rdata.alc_cmb != NULL) 1552 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1553 sc->alc_rdata.alc_cmb, 1554 sc->alc_cdata.alc_cmb_map); 1555 sc->alc_rdata.alc_cmb = NULL; 1556 sc->alc_cdata.alc_cmb_map = NULL; 1557 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1558 sc->alc_cdata.alc_cmb_tag = NULL; 1559 } 1560 /* SMB block */ 1561 if (sc->alc_cdata.alc_smb_tag != NULL) { 1562 if (sc->alc_cdata.alc_smb_map != NULL) 1563 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1564 sc->alc_cdata.alc_smb_map); 1565 if (sc->alc_cdata.alc_smb_map != NULL && 1566 sc->alc_rdata.alc_smb != NULL) 1567 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1568 sc->alc_rdata.alc_smb, 1569 sc->alc_cdata.alc_smb_map); 1570 sc->alc_rdata.alc_smb = NULL; 1571 sc->alc_cdata.alc_smb_map = NULL; 1572 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1573 sc->alc_cdata.alc_smb_tag = NULL; 1574 } 1575 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1576 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1577 sc->alc_cdata.alc_buffer_tag = NULL; 1578 } 1579 if (sc->alc_cdata.alc_parent_tag != NULL) { 1580 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1581 sc->alc_cdata.alc_parent_tag = NULL; 1582 } 1583 } 1584 1585 static int 1586 alc_shutdown(device_t dev) 1587 { 1588 1589 return (alc_suspend(dev)); 1590 } 1591 1592 /* 1593 * Note, this driver resets the link speed to 10/100Mbps by 1594 * restarting auto-negotiation in suspend/shutdown phase but we 1595 * don't know whether that auto-negotiation would succeed or not 1596 * as driver has no control after powering off/suspend operation. 1597 * If the renegotiation fail WOL may not work. Running at 1Gbps 1598 * will draw more power than 375mA at 3.3V which is specified in 1599 * PCI specification and that would result in complete 1600 * shutdowning power to ethernet controller. 1601 * 1602 * TODO 1603 * Save current negotiated media speed/duplex/flow-control to 1604 * softc and restore the same link again after resuming. PHY 1605 * handling such as power down/resetting to 100Mbps may be better 1606 * handled in suspend method in phy driver. 1607 */ 1608 static void 1609 alc_setlinkspeed(struct alc_softc *sc) 1610 { 1611 struct mii_data *mii; 1612 int aneg, i; 1613 1614 mii = device_get_softc(sc->alc_miibus); 1615 mii_pollstat(mii); 1616 aneg = 0; 1617 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1618 (IFM_ACTIVE | IFM_AVALID)) { 1619 switch IFM_SUBTYPE(mii->mii_media_active) { 1620 case IFM_10_T: 1621 case IFM_100_TX: 1622 return; 1623 case IFM_1000_T: 1624 aneg++; 1625 break; 1626 default: 1627 break; 1628 } 1629 } 1630 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1631 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1632 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1633 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1634 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1635 DELAY(1000); 1636 if (aneg != 0) { 1637 /* 1638 * Poll link state until alc(4) get a 10/100Mbps link. 1639 */ 1640 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1641 mii_pollstat(mii); 1642 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1643 == (IFM_ACTIVE | IFM_AVALID)) { 1644 switch (IFM_SUBTYPE( 1645 mii->mii_media_active)) { 1646 case IFM_10_T: 1647 case IFM_100_TX: 1648 alc_mac_config(sc); 1649 return; 1650 default: 1651 break; 1652 } 1653 } 1654 ALC_UNLOCK(sc); 1655 pause("alclnk", hz); 1656 ALC_LOCK(sc); 1657 } 1658 if (i == MII_ANEGTICKS_GIGE) 1659 device_printf(sc->alc_dev, 1660 "establishing a link failed, WOL may not work!"); 1661 } 1662 /* 1663 * No link, force MAC to have 100Mbps, full-duplex link. 1664 * This is the last resort and may/may not work. 1665 */ 1666 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1667 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1668 alc_mac_config(sc); 1669 } 1670 1671 static void 1672 alc_setwol(struct alc_softc *sc) 1673 { 1674 struct ifnet *ifp; 1675 uint32_t cap, reg, pmcs; 1676 uint16_t pmstat; 1677 int base, pmc; 1678 1679 ALC_LOCK_ASSERT(sc); 1680 1681 if (pci_find_extcap(sc->alc_dev, PCIY_EXPRESS, &base) == 0) { 1682 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 1683 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1684 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 1685 alc_disable_l0s_l1(sc); 1686 } 1687 } 1688 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) { 1689 /* Disable WOL. */ 1690 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1691 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1692 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1693 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1694 /* Force PHY power down. */ 1695 alc_phy_down(sc); 1696 return; 1697 } 1698 1699 ifp = sc->alc_ifp; 1700 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1701 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1702 alc_setlinkspeed(sc); 1703 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 1704 reg &= ~MASTER_CLK_SEL_DIS; 1705 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 1706 } 1707 1708 pmcs = 0; 1709 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1710 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1711 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1712 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1713 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1714 MAC_CFG_BCAST); 1715 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1716 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1717 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1718 reg |= MAC_CFG_RX_ENB; 1719 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1720 1721 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1722 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1723 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1724 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1725 /* WOL disabled, PHY power down. */ 1726 alc_phy_down(sc); 1727 } 1728 /* Request PME. */ 1729 pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2); 1730 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1731 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1732 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1733 pci_write_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1734 } 1735 1736 static int 1737 alc_suspend(device_t dev) 1738 { 1739 struct alc_softc *sc; 1740 1741 sc = device_get_softc(dev); 1742 1743 ALC_LOCK(sc); 1744 alc_stop(sc); 1745 alc_setwol(sc); 1746 ALC_UNLOCK(sc); 1747 1748 return (0); 1749 } 1750 1751 static int 1752 alc_resume(device_t dev) 1753 { 1754 struct alc_softc *sc; 1755 struct ifnet *ifp; 1756 int pmc; 1757 uint16_t pmstat; 1758 1759 sc = device_get_softc(dev); 1760 1761 ALC_LOCK(sc); 1762 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) == 0) { 1763 /* Disable PME and clear PME status. */ 1764 pmstat = pci_read_config(sc->alc_dev, 1765 pmc + PCIR_POWER_STATUS, 2); 1766 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1767 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1768 pci_write_config(sc->alc_dev, 1769 pmc + PCIR_POWER_STATUS, pmstat, 2); 1770 } 1771 } 1772 /* Reset PHY. */ 1773 alc_phy_reset(sc); 1774 ifp = sc->alc_ifp; 1775 if ((ifp->if_flags & IFF_UP) != 0) { 1776 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1777 alc_init_locked(sc); 1778 } 1779 ALC_UNLOCK(sc); 1780 1781 return (0); 1782 } 1783 1784 static int 1785 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1786 { 1787 struct alc_txdesc *txd, *txd_last; 1788 struct tx_desc *desc; 1789 struct mbuf *m; 1790 struct ip *ip; 1791 struct tcphdr *tcp; 1792 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 1793 bus_dmamap_t map; 1794 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1795 int error, idx, nsegs, prod; 1796 1797 ALC_LOCK_ASSERT(sc); 1798 1799 M_ASSERTPKTHDR((*m_head)); 1800 1801 m = *m_head; 1802 ip = NULL; 1803 tcp = NULL; 1804 ip_off = poff = 0; 1805 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 1806 /* 1807 * AR8131/AR8132 requires offset of TCP/UDP header in its 1808 * Tx descriptor to perform Tx checksum offloading. TSO 1809 * also requires TCP header offset and modification of 1810 * IP/TCP header. This kind of operation takes many CPU 1811 * cycles on FreeBSD so fast host CPU is required to get 1812 * smooth TSO performance. 1813 */ 1814 struct ether_header *eh; 1815 1816 if (M_WRITABLE(m) == 0) { 1817 /* Get a writable copy. */ 1818 m = m_dup(*m_head, M_DONTWAIT); 1819 /* Release original mbufs. */ 1820 m_freem(*m_head); 1821 if (m == NULL) { 1822 *m_head = NULL; 1823 return (ENOBUFS); 1824 } 1825 *m_head = m; 1826 } 1827 1828 ip_off = sizeof(struct ether_header); 1829 m = m_pullup(m, ip_off); 1830 if (m == NULL) { 1831 *m_head = NULL; 1832 return (ENOBUFS); 1833 } 1834 eh = mtod(m, struct ether_header *); 1835 /* 1836 * Check if hardware VLAN insertion is off. 1837 * Additional check for LLC/SNAP frame? 1838 */ 1839 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1840 ip_off = sizeof(struct ether_vlan_header); 1841 m = m_pullup(m, ip_off); 1842 if (m == NULL) { 1843 *m_head = NULL; 1844 return (ENOBUFS); 1845 } 1846 } 1847 m = m_pullup(m, ip_off + sizeof(struct ip)); 1848 if (m == NULL) { 1849 *m_head = NULL; 1850 return (ENOBUFS); 1851 } 1852 ip = (struct ip *)(mtod(m, char *) + ip_off); 1853 poff = ip_off + (ip->ip_hl << 2); 1854 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1855 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1856 if (m == NULL) { 1857 *m_head = NULL; 1858 return (ENOBUFS); 1859 } 1860 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1861 m = m_pullup(m, poff + (tcp->th_off << 2)); 1862 if (m == NULL) { 1863 *m_head = NULL; 1864 return (ENOBUFS); 1865 } 1866 /* 1867 * Due to strict adherence of Microsoft NDIS 1868 * Large Send specification, hardware expects 1869 * a pseudo TCP checksum inserted by upper 1870 * stack. Unfortunately the pseudo TCP 1871 * checksum that NDIS refers to does not include 1872 * TCP payload length so driver should recompute 1873 * the pseudo checksum here. Hopefully this 1874 * wouldn't be much burden on modern CPUs. 1875 * 1876 * Reset IP checksum and recompute TCP pseudo 1877 * checksum as NDIS specification said. 1878 */ 1879 ip->ip_sum = 0; 1880 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1881 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1882 } 1883 *m_head = m; 1884 } 1885 1886 prod = sc->alc_cdata.alc_tx_prod; 1887 txd = &sc->alc_cdata.alc_txdesc[prod]; 1888 txd_last = txd; 1889 map = txd->tx_dmamap; 1890 1891 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1892 *m_head, txsegs, &nsegs, 0); 1893 if (error == EFBIG) { 1894 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 1895 if (m == NULL) { 1896 m_freem(*m_head); 1897 *m_head = NULL; 1898 return (ENOMEM); 1899 } 1900 *m_head = m; 1901 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1902 *m_head, txsegs, &nsegs, 0); 1903 if (error != 0) { 1904 m_freem(*m_head); 1905 *m_head = NULL; 1906 return (error); 1907 } 1908 } else if (error != 0) 1909 return (error); 1910 if (nsegs == 0) { 1911 m_freem(*m_head); 1912 *m_head = NULL; 1913 return (EIO); 1914 } 1915 1916 /* Check descriptor overrun. */ 1917 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1918 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 1919 return (ENOBUFS); 1920 } 1921 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 1922 1923 m = *m_head; 1924 cflags = TD_ETHERNET; 1925 vtag = 0; 1926 desc = NULL; 1927 idx = 0; 1928 /* Configure VLAN hardware tag insertion. */ 1929 if ((m->m_flags & M_VLANTAG) != 0) { 1930 vtag = htons(m->m_pkthdr.ether_vtag); 1931 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1932 cflags |= TD_INS_VLAN_TAG; 1933 } 1934 /* Configure Tx checksum offload. */ 1935 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1936 #ifdef ALC_USE_CUSTOM_CSUM 1937 cflags |= TD_CUSTOM_CSUM; 1938 /* Set checksum start offset. */ 1939 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1940 TD_PLOAD_OFFSET_MASK; 1941 /* Set checksum insertion position of TCP/UDP. */ 1942 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 1943 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 1944 #else 1945 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1946 cflags |= TD_IPCSUM; 1947 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1948 cflags |= TD_TCPCSUM; 1949 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1950 cflags |= TD_UDPCSUM; 1951 /* Set TCP/UDP header offset. */ 1952 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 1953 TD_L4HDR_OFFSET_MASK; 1954 #endif 1955 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1956 /* Request TSO and set MSS. */ 1957 cflags |= TD_TSO | TD_TSO_DESCV1; 1958 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 1959 TD_MSS_MASK; 1960 /* Set TCP header offset. */ 1961 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 1962 TD_TCPHDR_OFFSET_MASK; 1963 /* 1964 * AR8131/AR8132 requires the first buffer should 1965 * only hold IP/TCP header data. Payload should 1966 * be handled in other descriptors. 1967 */ 1968 hdrlen = poff + (tcp->th_off << 2); 1969 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1970 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 1971 desc->flags = htole32(cflags); 1972 desc->addr = htole64(txsegs[0].ds_addr); 1973 sc->alc_cdata.alc_tx_cnt++; 1974 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1975 if (m->m_len - hdrlen > 0) { 1976 /* Handle remaining payload of the first fragment. */ 1977 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1978 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 1979 vtag)); 1980 desc->flags = htole32(cflags); 1981 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1982 sc->alc_cdata.alc_tx_cnt++; 1983 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1984 } 1985 /* Handle remaining fragments. */ 1986 idx = 1; 1987 } 1988 for (; idx < nsegs; idx++) { 1989 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1990 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 1991 desc->flags = htole32(cflags); 1992 desc->addr = htole64(txsegs[idx].ds_addr); 1993 sc->alc_cdata.alc_tx_cnt++; 1994 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1995 } 1996 /* Update producer index. */ 1997 sc->alc_cdata.alc_tx_prod = prod; 1998 1999 /* Finally set EOP on the last descriptor. */ 2000 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2001 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2002 desc->flags |= htole32(TD_EOP); 2003 2004 /* Swap dmamap of the first and the last. */ 2005 txd = &sc->alc_cdata.alc_txdesc[prod]; 2006 map = txd_last->tx_dmamap; 2007 txd_last->tx_dmamap = txd->tx_dmamap; 2008 txd->tx_dmamap = map; 2009 txd->tx_m = m; 2010 2011 return (0); 2012 } 2013 2014 static void 2015 alc_tx_task(void *arg, int pending) 2016 { 2017 struct ifnet *ifp; 2018 2019 ifp = (struct ifnet *)arg; 2020 alc_start(ifp); 2021 } 2022 2023 static void 2024 alc_start(struct ifnet *ifp) 2025 { 2026 struct alc_softc *sc; 2027 struct mbuf *m_head; 2028 int enq; 2029 2030 sc = ifp->if_softc; 2031 2032 ALC_LOCK(sc); 2033 2034 /* Reclaim transmitted frames. */ 2035 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2036 alc_txeof(sc); 2037 2038 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2039 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2040 ALC_UNLOCK(sc); 2041 return; 2042 } 2043 2044 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2045 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2046 if (m_head == NULL) 2047 break; 2048 /* 2049 * Pack the data into the transmit ring. If we 2050 * don't have room, set the OACTIVE flag and wait 2051 * for the NIC to drain the ring. 2052 */ 2053 if (alc_encap(sc, &m_head)) { 2054 if (m_head == NULL) 2055 break; 2056 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2057 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2058 break; 2059 } 2060 2061 enq++; 2062 /* 2063 * If there's a BPF listener, bounce a copy of this frame 2064 * to him. 2065 */ 2066 ETHER_BPF_MTAP(ifp, m_head); 2067 } 2068 2069 if (enq > 0) { 2070 /* Sync descriptors. */ 2071 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2072 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2073 /* Kick. Assume we're using normal Tx priority queue. */ 2074 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2075 (sc->alc_cdata.alc_tx_prod << 2076 MBOX_TD_PROD_LO_IDX_SHIFT) & 2077 MBOX_TD_PROD_LO_IDX_MASK); 2078 /* Set a timeout in case the chip goes out to lunch. */ 2079 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2080 } 2081 2082 ALC_UNLOCK(sc); 2083 } 2084 2085 static void 2086 alc_watchdog(struct alc_softc *sc) 2087 { 2088 struct ifnet *ifp; 2089 2090 ALC_LOCK_ASSERT(sc); 2091 2092 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2093 return; 2094 2095 ifp = sc->alc_ifp; 2096 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2097 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2098 ifp->if_oerrors++; 2099 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2100 alc_init_locked(sc); 2101 return; 2102 } 2103 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2104 ifp->if_oerrors++; 2105 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2106 alc_init_locked(sc); 2107 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2108 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2109 } 2110 2111 static int 2112 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2113 { 2114 struct alc_softc *sc; 2115 struct ifreq *ifr; 2116 struct mii_data *mii; 2117 int error, mask; 2118 2119 sc = ifp->if_softc; 2120 ifr = (struct ifreq *)data; 2121 error = 0; 2122 switch (cmd) { 2123 case SIOCSIFMTU: 2124 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALC_JUMBO_MTU || 2125 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2126 ifr->ifr_mtu > ETHERMTU)) 2127 error = EINVAL; 2128 else if (ifp->if_mtu != ifr->ifr_mtu) { 2129 ALC_LOCK(sc); 2130 ifp->if_mtu = ifr->ifr_mtu; 2131 /* AR8131/AR8132 has 13 bits MSS field. */ 2132 if (ifp->if_mtu > ALC_TSO_MTU && 2133 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2134 ifp->if_capenable &= ~IFCAP_TSO4; 2135 ifp->if_hwassist &= ~CSUM_TSO; 2136 } 2137 ALC_UNLOCK(sc); 2138 } 2139 break; 2140 case SIOCSIFFLAGS: 2141 ALC_LOCK(sc); 2142 if ((ifp->if_flags & IFF_UP) != 0) { 2143 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2144 ((ifp->if_flags ^ sc->alc_if_flags) & 2145 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2146 alc_rxfilter(sc); 2147 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2148 alc_init_locked(sc); 2149 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2150 alc_stop(sc); 2151 sc->alc_if_flags = ifp->if_flags; 2152 ALC_UNLOCK(sc); 2153 break; 2154 case SIOCADDMULTI: 2155 case SIOCDELMULTI: 2156 ALC_LOCK(sc); 2157 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2158 alc_rxfilter(sc); 2159 ALC_UNLOCK(sc); 2160 break; 2161 case SIOCSIFMEDIA: 2162 case SIOCGIFMEDIA: 2163 mii = device_get_softc(sc->alc_miibus); 2164 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2165 break; 2166 case SIOCSIFCAP: 2167 ALC_LOCK(sc); 2168 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2169 if ((mask & IFCAP_TXCSUM) != 0 && 2170 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2171 ifp->if_capenable ^= IFCAP_TXCSUM; 2172 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2173 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2174 else 2175 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2176 } 2177 if ((mask & IFCAP_TSO4) != 0 && 2178 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2179 ifp->if_capenable ^= IFCAP_TSO4; 2180 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2181 /* AR8131/AR8132 has 13 bits MSS field. */ 2182 if (ifp->if_mtu > ALC_TSO_MTU) { 2183 ifp->if_capenable &= ~IFCAP_TSO4; 2184 ifp->if_hwassist &= ~CSUM_TSO; 2185 } else 2186 ifp->if_hwassist |= CSUM_TSO; 2187 } else 2188 ifp->if_hwassist &= ~CSUM_TSO; 2189 } 2190 if ((mask & IFCAP_WOL_MCAST) != 0 && 2191 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2192 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2193 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2194 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2195 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2196 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2197 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2198 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2199 alc_rxvlan(sc); 2200 } 2201 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2202 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2203 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2204 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2205 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2206 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2207 /* 2208 * VLAN hardware tagging is required to do checksum 2209 * offload or TSO on VLAN interface. Checksum offload 2210 * on VLAN interface also requires hardware checksum 2211 * offload of parent interface. 2212 */ 2213 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2214 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2215 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2216 ifp->if_capenable &= 2217 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2218 ALC_UNLOCK(sc); 2219 VLAN_CAPABILITIES(ifp); 2220 break; 2221 default: 2222 error = ether_ioctl(ifp, cmd, data); 2223 break; 2224 } 2225 2226 return (error); 2227 } 2228 2229 static void 2230 alc_mac_config(struct alc_softc *sc) 2231 { 2232 struct mii_data *mii; 2233 uint32_t reg; 2234 2235 ALC_LOCK_ASSERT(sc); 2236 2237 mii = device_get_softc(sc->alc_miibus); 2238 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2239 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2240 MAC_CFG_SPEED_MASK); 2241 /* Reprogram MAC with resolved speed/duplex. */ 2242 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2243 case IFM_10_T: 2244 case IFM_100_TX: 2245 reg |= MAC_CFG_SPEED_10_100; 2246 break; 2247 case IFM_1000_T: 2248 reg |= MAC_CFG_SPEED_1000; 2249 break; 2250 } 2251 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2252 reg |= MAC_CFG_FULL_DUPLEX; 2253 #ifdef notyet 2254 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2255 reg |= MAC_CFG_TX_FC; 2256 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2257 reg |= MAC_CFG_RX_FC; 2258 #endif 2259 } 2260 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2261 } 2262 2263 static void 2264 alc_stats_clear(struct alc_softc *sc) 2265 { 2266 struct smb sb, *smb; 2267 uint32_t *reg; 2268 int i; 2269 2270 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2271 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2272 sc->alc_cdata.alc_smb_map, 2273 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2274 smb = sc->alc_rdata.alc_smb; 2275 /* Update done, clear. */ 2276 smb->updated = 0; 2277 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2278 sc->alc_cdata.alc_smb_map, 2279 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2280 } else { 2281 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2282 reg++) { 2283 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2284 i += sizeof(uint32_t); 2285 } 2286 /* Read Tx statistics. */ 2287 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2288 reg++) { 2289 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2290 i += sizeof(uint32_t); 2291 } 2292 } 2293 } 2294 2295 static void 2296 alc_stats_update(struct alc_softc *sc) 2297 { 2298 struct alc_hw_stats *stat; 2299 struct smb sb, *smb; 2300 struct ifnet *ifp; 2301 uint32_t *reg; 2302 int i; 2303 2304 ALC_LOCK_ASSERT(sc); 2305 2306 ifp = sc->alc_ifp; 2307 stat = &sc->alc_stats; 2308 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2309 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2310 sc->alc_cdata.alc_smb_map, 2311 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2312 smb = sc->alc_rdata.alc_smb; 2313 if (smb->updated == 0) 2314 return; 2315 } else { 2316 smb = &sb; 2317 /* Read Rx statistics. */ 2318 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2319 reg++) { 2320 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2321 i += sizeof(uint32_t); 2322 } 2323 /* Read Tx statistics. */ 2324 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2325 reg++) { 2326 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2327 i += sizeof(uint32_t); 2328 } 2329 } 2330 2331 /* Rx stats. */ 2332 stat->rx_frames += smb->rx_frames; 2333 stat->rx_bcast_frames += smb->rx_bcast_frames; 2334 stat->rx_mcast_frames += smb->rx_mcast_frames; 2335 stat->rx_pause_frames += smb->rx_pause_frames; 2336 stat->rx_control_frames += smb->rx_control_frames; 2337 stat->rx_crcerrs += smb->rx_crcerrs; 2338 stat->rx_lenerrs += smb->rx_lenerrs; 2339 stat->rx_bytes += smb->rx_bytes; 2340 stat->rx_runts += smb->rx_runts; 2341 stat->rx_fragments += smb->rx_fragments; 2342 stat->rx_pkts_64 += smb->rx_pkts_64; 2343 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2344 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2345 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2346 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2347 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2348 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2349 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2350 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2351 stat->rx_rrs_errs += smb->rx_rrs_errs; 2352 stat->rx_alignerrs += smb->rx_alignerrs; 2353 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2354 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2355 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2356 2357 /* Tx stats. */ 2358 stat->tx_frames += smb->tx_frames; 2359 stat->tx_bcast_frames += smb->tx_bcast_frames; 2360 stat->tx_mcast_frames += smb->tx_mcast_frames; 2361 stat->tx_pause_frames += smb->tx_pause_frames; 2362 stat->tx_excess_defer += smb->tx_excess_defer; 2363 stat->tx_control_frames += smb->tx_control_frames; 2364 stat->tx_deferred += smb->tx_deferred; 2365 stat->tx_bytes += smb->tx_bytes; 2366 stat->tx_pkts_64 += smb->tx_pkts_64; 2367 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2368 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2369 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2370 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2371 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2372 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2373 stat->tx_single_colls += smb->tx_single_colls; 2374 stat->tx_multi_colls += smb->tx_multi_colls; 2375 stat->tx_late_colls += smb->tx_late_colls; 2376 stat->tx_excess_colls += smb->tx_excess_colls; 2377 stat->tx_abort += smb->tx_abort; 2378 stat->tx_underrun += smb->tx_underrun; 2379 stat->tx_desc_underrun += smb->tx_desc_underrun; 2380 stat->tx_lenerrs += smb->tx_lenerrs; 2381 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2382 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2383 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2384 2385 /* Update counters in ifnet. */ 2386 ifp->if_opackets += smb->tx_frames; 2387 2388 ifp->if_collisions += smb->tx_single_colls + 2389 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2390 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2391 2392 /* 2393 * XXX 2394 * tx_pkts_truncated counter looks suspicious. It constantly 2395 * increments with no sign of Tx errors. This may indicate 2396 * the counter name is not correct one so I've removed the 2397 * counter in output errors. 2398 */ 2399 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2400 smb->tx_underrun; 2401 2402 ifp->if_ipackets += smb->rx_frames; 2403 2404 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2405 smb->rx_runts + smb->rx_pkts_truncated + 2406 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2407 smb->rx_alignerrs; 2408 2409 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2410 /* Update done, clear. */ 2411 smb->updated = 0; 2412 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2413 sc->alc_cdata.alc_smb_map, 2414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2415 } 2416 } 2417 2418 static int 2419 alc_intr(void *arg) 2420 { 2421 struct alc_softc *sc; 2422 uint32_t status; 2423 2424 sc = (struct alc_softc *)arg; 2425 2426 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2427 if ((status & ALC_INTRS) == 0) 2428 return (FILTER_STRAY); 2429 /* Disable interrupts. */ 2430 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2431 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2432 2433 return (FILTER_HANDLED); 2434 } 2435 2436 static void 2437 alc_int_task(void *arg, int pending) 2438 { 2439 struct alc_softc *sc; 2440 struct ifnet *ifp; 2441 uint32_t status; 2442 int more; 2443 2444 sc = (struct alc_softc *)arg; 2445 ifp = sc->alc_ifp; 2446 2447 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2448 more = atomic_readandclear_int(&sc->alc_morework); 2449 if (more != 0) 2450 status |= INTR_RX_PKT; 2451 if ((status & ALC_INTRS) == 0) 2452 goto done; 2453 2454 /* Acknowledge interrupts but still disable interrupts. */ 2455 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2456 2457 more = 0; 2458 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2459 if ((status & INTR_RX_PKT) != 0) { 2460 more = alc_rxintr(sc, sc->alc_process_limit); 2461 if (more == EAGAIN) 2462 atomic_set_int(&sc->alc_morework, 1); 2463 else if (more == EIO) { 2464 ALC_LOCK(sc); 2465 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2466 alc_init_locked(sc); 2467 ALC_UNLOCK(sc); 2468 return; 2469 } 2470 } 2471 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2472 INTR_TXQ_TO_RST)) != 0) { 2473 if ((status & INTR_DMA_RD_TO_RST) != 0) 2474 device_printf(sc->alc_dev, 2475 "DMA read error! -- resetting\n"); 2476 if ((status & INTR_DMA_WR_TO_RST) != 0) 2477 device_printf(sc->alc_dev, 2478 "DMA write error! -- resetting\n"); 2479 if ((status & INTR_TXQ_TO_RST) != 0) 2480 device_printf(sc->alc_dev, 2481 "TxQ reset! -- resetting\n"); 2482 ALC_LOCK(sc); 2483 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2484 alc_init_locked(sc); 2485 ALC_UNLOCK(sc); 2486 return; 2487 } 2488 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2489 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2490 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2491 } 2492 2493 if (more == EAGAIN || 2494 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2495 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2496 return; 2497 } 2498 2499 done: 2500 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2501 /* Re-enable interrupts if we're running. */ 2502 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2503 } 2504 } 2505 2506 static void 2507 alc_txeof(struct alc_softc *sc) 2508 { 2509 struct ifnet *ifp; 2510 struct alc_txdesc *txd; 2511 uint32_t cons, prod; 2512 int prog; 2513 2514 ALC_LOCK_ASSERT(sc); 2515 2516 ifp = sc->alc_ifp; 2517 2518 if (sc->alc_cdata.alc_tx_cnt == 0) 2519 return; 2520 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2521 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2522 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2523 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2524 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2525 prod = sc->alc_rdata.alc_cmb->cons; 2526 } else 2527 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2528 /* Assume we're using normal Tx priority queue. */ 2529 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2530 MBOX_TD_CONS_LO_IDX_SHIFT; 2531 cons = sc->alc_cdata.alc_tx_cons; 2532 /* 2533 * Go through our Tx list and free mbufs for those 2534 * frames which have been transmitted. 2535 */ 2536 for (prog = 0; cons != prod; prog++, 2537 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2538 if (sc->alc_cdata.alc_tx_cnt <= 0) 2539 break; 2540 prog++; 2541 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2542 sc->alc_cdata.alc_tx_cnt--; 2543 txd = &sc->alc_cdata.alc_txdesc[cons]; 2544 if (txd->tx_m != NULL) { 2545 /* Reclaim transmitted mbufs. */ 2546 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2547 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2548 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2549 txd->tx_dmamap); 2550 m_freem(txd->tx_m); 2551 txd->tx_m = NULL; 2552 } 2553 } 2554 2555 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2556 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2557 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2558 sc->alc_cdata.alc_tx_cons = cons; 2559 /* 2560 * Unarm watchdog timer only when there is no pending 2561 * frames in Tx queue. 2562 */ 2563 if (sc->alc_cdata.alc_tx_cnt == 0) 2564 sc->alc_watchdog_timer = 0; 2565 } 2566 2567 static int 2568 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2569 { 2570 struct mbuf *m; 2571 bus_dma_segment_t segs[1]; 2572 bus_dmamap_t map; 2573 int nsegs; 2574 2575 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2576 if (m == NULL) 2577 return (ENOBUFS); 2578 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2579 #ifndef __NO_STRICT_ALIGNMENT 2580 m_adj(m, sizeof(uint64_t)); 2581 #endif 2582 2583 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2584 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2585 m_freem(m); 2586 return (ENOBUFS); 2587 } 2588 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2589 2590 if (rxd->rx_m != NULL) { 2591 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2592 BUS_DMASYNC_POSTREAD); 2593 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2594 } 2595 map = rxd->rx_dmamap; 2596 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2597 sc->alc_cdata.alc_rx_sparemap = map; 2598 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2599 BUS_DMASYNC_PREREAD); 2600 rxd->rx_m = m; 2601 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2602 return (0); 2603 } 2604 2605 static int 2606 alc_rxintr(struct alc_softc *sc, int count) 2607 { 2608 struct ifnet *ifp; 2609 struct rx_rdesc *rrd; 2610 uint32_t nsegs, status; 2611 int rr_cons, prog; 2612 2613 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2614 sc->alc_cdata.alc_rr_ring_map, 2615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2616 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2617 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2618 rr_cons = sc->alc_cdata.alc_rr_cons; 2619 ifp = sc->alc_ifp; 2620 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2621 if (count-- <= 0) 2622 break; 2623 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2624 status = le32toh(rrd->status); 2625 if ((status & RRD_VALID) == 0) 2626 break; 2627 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2628 if (nsegs == 0) { 2629 /* This should not happen! */ 2630 device_printf(sc->alc_dev, 2631 "unexpected segment count -- resetting\n"); 2632 return (EIO); 2633 } 2634 alc_rxeof(sc, rrd); 2635 /* Clear Rx return status. */ 2636 rrd->status = 0; 2637 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2638 sc->alc_cdata.alc_rx_cons += nsegs; 2639 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2640 prog += nsegs; 2641 } 2642 2643 if (prog > 0) { 2644 /* Update the consumer index. */ 2645 sc->alc_cdata.alc_rr_cons = rr_cons; 2646 /* Sync Rx return descriptors. */ 2647 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2648 sc->alc_cdata.alc_rr_ring_map, 2649 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2650 /* 2651 * Sync updated Rx descriptors such that controller see 2652 * modified buffer addresses. 2653 */ 2654 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2655 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2656 /* 2657 * Let controller know availability of new Rx buffers. 2658 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2659 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2660 * only when Rx buffer pre-fetching is required. In 2661 * addition we already set ALC_RX_RD_FREE_THRESH to 2662 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2663 * it still seems that pre-fetching needs more 2664 * experimentation. 2665 */ 2666 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2667 sc->alc_cdata.alc_rx_cons); 2668 } 2669 2670 return (count > 0 ? 0 : EAGAIN); 2671 } 2672 2673 #ifndef __NO_STRICT_ALIGNMENT 2674 static struct mbuf * 2675 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2676 { 2677 struct mbuf *n; 2678 int i; 2679 uint16_t *src, *dst; 2680 2681 src = mtod(m, uint16_t *); 2682 dst = src - 3; 2683 2684 if (m->m_next == NULL) { 2685 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2686 *dst++ = *src++; 2687 m->m_data -= 6; 2688 return (m); 2689 } 2690 /* 2691 * Append a new mbuf to received mbuf chain and copy ethernet 2692 * header from the mbuf chain. This can save lots of CPU 2693 * cycles for jumbo frame. 2694 */ 2695 MGETHDR(n, M_DONTWAIT, MT_DATA); 2696 if (n == NULL) { 2697 ifp->if_iqdrops++; 2698 m_freem(m); 2699 return (NULL); 2700 } 2701 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2702 m->m_data += ETHER_HDR_LEN; 2703 m->m_len -= ETHER_HDR_LEN; 2704 n->m_len = ETHER_HDR_LEN; 2705 M_MOVE_PKTHDR(n, m); 2706 n->m_next = m; 2707 return (n); 2708 } 2709 #endif 2710 2711 /* Receive a frame. */ 2712 static void 2713 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2714 { 2715 struct alc_rxdesc *rxd; 2716 struct ifnet *ifp; 2717 struct mbuf *mp, *m; 2718 uint32_t rdinfo, status, vtag; 2719 int count, nsegs, rx_cons; 2720 2721 ifp = sc->alc_ifp; 2722 status = le32toh(rrd->status); 2723 rdinfo = le32toh(rrd->rdinfo); 2724 rx_cons = RRD_RD_IDX(rdinfo); 2725 nsegs = RRD_RD_CNT(rdinfo); 2726 2727 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2728 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2729 /* 2730 * We want to pass the following frames to upper 2731 * layer regardless of error status of Rx return 2732 * ring. 2733 * 2734 * o IP/TCP/UDP checksum is bad. 2735 * o frame length and protocol specific length 2736 * does not match. 2737 * 2738 * Force network stack compute checksum for 2739 * errored frames. 2740 */ 2741 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2742 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 2743 RRD_ERR_RUNT) != 0) 2744 return; 2745 } 2746 2747 for (count = 0; count < nsegs; count++, 2748 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2749 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2750 mp = rxd->rx_m; 2751 /* Add a new receive buffer to the ring. */ 2752 if (alc_newbuf(sc, rxd) != 0) { 2753 ifp->if_iqdrops++; 2754 /* Reuse Rx buffers. */ 2755 if (sc->alc_cdata.alc_rxhead != NULL) 2756 m_freem(sc->alc_cdata.alc_rxhead); 2757 break; 2758 } 2759 2760 /* 2761 * Assume we've received a full sized frame. 2762 * Actual size is fixed when we encounter the end of 2763 * multi-segmented frame. 2764 */ 2765 mp->m_len = sc->alc_buf_size; 2766 2767 /* Chain received mbufs. */ 2768 if (sc->alc_cdata.alc_rxhead == NULL) { 2769 sc->alc_cdata.alc_rxhead = mp; 2770 sc->alc_cdata.alc_rxtail = mp; 2771 } else { 2772 mp->m_flags &= ~M_PKTHDR; 2773 sc->alc_cdata.alc_rxprev_tail = 2774 sc->alc_cdata.alc_rxtail; 2775 sc->alc_cdata.alc_rxtail->m_next = mp; 2776 sc->alc_cdata.alc_rxtail = mp; 2777 } 2778 2779 if (count == nsegs - 1) { 2780 /* Last desc. for this frame. */ 2781 m = sc->alc_cdata.alc_rxhead; 2782 m->m_flags |= M_PKTHDR; 2783 /* 2784 * It seems that L1C/L2C controller has no way 2785 * to tell hardware to strip CRC bytes. 2786 */ 2787 m->m_pkthdr.len = 2788 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2789 if (nsegs > 1) { 2790 /* Set last mbuf size. */ 2791 mp->m_len = sc->alc_cdata.alc_rxlen - 2792 (nsegs - 1) * sc->alc_buf_size; 2793 /* Remove the CRC bytes in chained mbufs. */ 2794 if (mp->m_len <= ETHER_CRC_LEN) { 2795 sc->alc_cdata.alc_rxtail = 2796 sc->alc_cdata.alc_rxprev_tail; 2797 sc->alc_cdata.alc_rxtail->m_len -= 2798 (ETHER_CRC_LEN - mp->m_len); 2799 sc->alc_cdata.alc_rxtail->m_next = NULL; 2800 m_freem(mp); 2801 } else { 2802 mp->m_len -= ETHER_CRC_LEN; 2803 } 2804 } else 2805 m->m_len = m->m_pkthdr.len; 2806 m->m_pkthdr.rcvif = ifp; 2807 /* 2808 * Due to hardware bugs, Rx checksum offloading 2809 * was intentionally disabled. 2810 */ 2811 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2812 (status & RRD_VLAN_TAG) != 0) { 2813 vtag = RRD_VLAN(le32toh(rrd->vtag)); 2814 m->m_pkthdr.ether_vtag = ntohs(vtag); 2815 m->m_flags |= M_VLANTAG; 2816 } 2817 #ifndef __NO_STRICT_ALIGNMENT 2818 m = alc_fixup_rx(ifp, m); 2819 if (m != NULL) 2820 #endif 2821 { 2822 /* Pass it on. */ 2823 (*ifp->if_input)(ifp, m); 2824 } 2825 } 2826 } 2827 /* Reset mbuf chains. */ 2828 ALC_RXCHAIN_RESET(sc); 2829 } 2830 2831 static void 2832 alc_tick(void *arg) 2833 { 2834 struct alc_softc *sc; 2835 struct mii_data *mii; 2836 2837 sc = (struct alc_softc *)arg; 2838 2839 ALC_LOCK_ASSERT(sc); 2840 2841 mii = device_get_softc(sc->alc_miibus); 2842 mii_tick(mii); 2843 alc_stats_update(sc); 2844 /* 2845 * alc(4) does not rely on Tx completion interrupts to reclaim 2846 * transferred buffers. Instead Tx completion interrupts are 2847 * used to hint for scheduling Tx task. So it's necessary to 2848 * release transmitted buffers by kicking Tx completion 2849 * handler. This limits the maximum reclamation delay to a hz. 2850 */ 2851 alc_txeof(sc); 2852 alc_watchdog(sc); 2853 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 2854 } 2855 2856 static void 2857 alc_reset(struct alc_softc *sc) 2858 { 2859 uint32_t reg; 2860 int i; 2861 2862 CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET); 2863 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2864 DELAY(10); 2865 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2866 break; 2867 } 2868 if (i == 0) 2869 device_printf(sc->alc_dev, "master reset timeout!\n"); 2870 2871 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2872 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2873 break; 2874 DELAY(10); 2875 } 2876 2877 if (i == 0) 2878 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 2879 } 2880 2881 static void 2882 alc_init(void *xsc) 2883 { 2884 struct alc_softc *sc; 2885 2886 sc = (struct alc_softc *)xsc; 2887 ALC_LOCK(sc); 2888 alc_init_locked(sc); 2889 ALC_UNLOCK(sc); 2890 } 2891 2892 static void 2893 alc_init_locked(struct alc_softc *sc) 2894 { 2895 struct ifnet *ifp; 2896 struct mii_data *mii; 2897 uint8_t eaddr[ETHER_ADDR_LEN]; 2898 bus_addr_t paddr; 2899 uint32_t reg, rxf_hi, rxf_lo; 2900 2901 ALC_LOCK_ASSERT(sc); 2902 2903 ifp = sc->alc_ifp; 2904 mii = device_get_softc(sc->alc_miibus); 2905 2906 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2907 return; 2908 /* 2909 * Cancel any pending I/O. 2910 */ 2911 alc_stop(sc); 2912 /* 2913 * Reset the chip to a known state. 2914 */ 2915 alc_reset(sc); 2916 2917 /* Initialize Rx descriptors. */ 2918 if (alc_init_rx_ring(sc) != 0) { 2919 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 2920 alc_stop(sc); 2921 return; 2922 } 2923 alc_init_rr_ring(sc); 2924 alc_init_tx_ring(sc); 2925 alc_init_cmb(sc); 2926 alc_init_smb(sc); 2927 2928 /* Reprogram the station address. */ 2929 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2930 CSR_WRITE_4(sc, ALC_PAR0, 2931 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2932 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2933 /* 2934 * Clear WOL status and disable all WOL feature as WOL 2935 * would interfere Rx operation under normal environments. 2936 */ 2937 CSR_READ_4(sc, ALC_WOL_CFG); 2938 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2939 /* Set Tx descriptor base addresses. */ 2940 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2941 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2942 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2943 /* We don't use high priority ring. */ 2944 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2945 /* Set Tx descriptor counter. */ 2946 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2947 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2948 /* Set Rx descriptor base addresses. */ 2949 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2950 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2951 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2952 /* We use one Rx ring. */ 2953 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2954 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2955 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2956 /* Set Rx descriptor counter. */ 2957 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2958 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2959 2960 /* 2961 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2962 * if it do not fit the buffer size. Rx return descriptor holds 2963 * a counter that indicates how many fragments were made by the 2964 * hardware. The buffer size should be multiple of 8 bytes. 2965 * Since hardware has limit on the size of buffer size, always 2966 * use the maximum value. 2967 * For strict-alignment architectures make sure to reduce buffer 2968 * size by 8 bytes to make room for alignment fixup. 2969 */ 2970 #ifndef __NO_STRICT_ALIGNMENT 2971 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 2972 #else 2973 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2974 #endif 2975 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2976 2977 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2978 /* Set Rx return descriptor base addresses. */ 2979 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2980 /* We use one Rx return ring. */ 2981 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2982 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2983 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2984 /* Set Rx return descriptor counter. */ 2985 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2986 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2987 paddr = sc->alc_rdata.alc_cmb_paddr; 2988 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2989 paddr = sc->alc_rdata.alc_smb_paddr; 2990 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2991 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2992 2993 /* Tell hardware that we're ready to load DMA blocks. */ 2994 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2995 2996 /* Configure interrupt moderation timer. */ 2997 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2998 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2999 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3000 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3001 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 3002 /* 3003 * We don't want to automatic interrupt clear as task queue 3004 * for the interrupt should know interrupt status. 3005 */ 3006 reg &= ~MASTER_INTR_RD_CLR; 3007 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 3008 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3009 reg |= MASTER_IM_RX_TIMER_ENB; 3010 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3011 reg |= MASTER_IM_TX_TIMER_ENB; 3012 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3013 /* 3014 * Disable interrupt re-trigger timer. We don't want automatic 3015 * re-triggering of un-ACKed interrupts. 3016 */ 3017 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3018 /* Configure CMB. */ 3019 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3020 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3021 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3022 else 3023 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3024 /* 3025 * Hardware can be configured to issue SMB interrupt based 3026 * on programmed interval. Since there is a callout that is 3027 * invoked for every hz in driver we use that instead of 3028 * relying on periodic SMB interrupt. 3029 */ 3030 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3031 /* Clear MAC statistics. */ 3032 alc_stats_clear(sc); 3033 3034 /* 3035 * Always use maximum frame size that controller can support. 3036 * Otherwise received frames that has larger frame length 3037 * than alc(4) MTU would be silently dropped in hardware. This 3038 * would make path-MTU discovery hard as sender wouldn't get 3039 * any responses from receiver. alc(4) supports 3040 * multi-fragmented frames on Rx path so it has no issue on 3041 * assembling fragmented frames. Using maximum frame size also 3042 * removes the need to reinitialize hardware when interface 3043 * MTU configuration was changed. 3044 * 3045 * Be conservative in what you do, be liberal in what you 3046 * accept from others - RFC 793. 3047 */ 3048 CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN); 3049 3050 /* Disable header split(?) */ 3051 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3052 3053 /* Configure IPG/IFG parameters. */ 3054 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3055 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3056 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3057 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3058 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3059 /* Set parameters for half-duplex media. */ 3060 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3061 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3062 HDPX_CFG_LCOL_MASK) | 3063 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3064 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3065 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3066 HDPX_CFG_ABEBT_MASK) | 3067 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3068 HDPX_CFG_JAMIPG_MASK)); 3069 /* 3070 * Set TSO/checksum offload threshold. For frames that is 3071 * larger than this threshold, hardware wouldn't do 3072 * TSO/checksum offloading. 3073 */ 3074 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3075 (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3076 TSO_OFFLOAD_THRESH_MASK); 3077 /* Configure TxQ. */ 3078 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3079 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3080 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3081 TXQ_CFG_TD_BURST_MASK; 3082 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3083 3084 /* Configure Rx free descriptor pre-fetching. */ 3085 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3086 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3087 RX_RD_FREE_THRESH_HI_MASK) | 3088 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3089 RX_RD_FREE_THRESH_LO_MASK)); 3090 3091 /* 3092 * Configure flow control parameters. 3093 * XON : 80% of Rx FIFO 3094 * XOFF : 30% of Rx FIFO 3095 */ 3096 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3097 rxf_hi = (reg * 8) / 10; 3098 rxf_lo = (reg * 3)/ 10; 3099 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3100 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3101 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3102 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3103 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3104 3105 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3106 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3107 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3108 3109 /* Configure RxQ. */ 3110 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3111 RXQ_CFG_RD_BURST_MASK; 3112 reg |= RXQ_CFG_RSS_MODE_DIS; 3113 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3114 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 3115 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3116 3117 /* Configure Rx DMAW request thresold. */ 3118 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 3119 ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) & 3120 RD_DMA_CFG_THRESH_MASK) | 3121 ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) & 3122 RD_DMA_CFG_TIMER_MASK)); 3123 /* Configure DMA parameters. */ 3124 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3125 reg |= sc->alc_rcb; 3126 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3127 reg |= DMA_CFG_CMB_ENB; 3128 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3129 reg |= DMA_CFG_SMB_ENB; 3130 else 3131 reg |= DMA_CFG_SMB_DIS; 3132 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3133 DMA_CFG_RD_BURST_SHIFT; 3134 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3135 DMA_CFG_WR_BURST_SHIFT; 3136 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3137 DMA_CFG_RD_DELAY_CNT_MASK; 3138 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3139 DMA_CFG_WR_DELAY_CNT_MASK; 3140 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3141 3142 /* 3143 * Configure Tx/Rx MACs. 3144 * - Auto-padding for short frames. 3145 * - Enable CRC generation. 3146 * Actual reconfiguration of MAC for resolved speed/duplex 3147 * is followed after detection of link establishment. 3148 * AR8131/AR8132 always does checksum computation regardless 3149 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3150 * have bug in protocol field in Rx return structure so 3151 * these controllers can't handle fragmented frames. Disable 3152 * Rx checksum offloading until there is a newer controller 3153 * that has sane implementation. 3154 */ 3155 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3156 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3157 MAC_CFG_PREAMBLE_MASK); 3158 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3159 reg |= MAC_CFG_SPEED_10_100; 3160 else 3161 reg |= MAC_CFG_SPEED_1000; 3162 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3163 3164 /* Set up the receive filter. */ 3165 alc_rxfilter(sc); 3166 alc_rxvlan(sc); 3167 3168 /* Acknowledge all pending interrupts and clear it. */ 3169 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3170 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3171 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3172 3173 sc->alc_flags &= ~ALC_FLAG_LINK; 3174 /* Switch to the current media. */ 3175 mii_mediachg(mii); 3176 3177 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3178 3179 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3180 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3181 } 3182 3183 static void 3184 alc_stop(struct alc_softc *sc) 3185 { 3186 struct ifnet *ifp; 3187 struct alc_txdesc *txd; 3188 struct alc_rxdesc *rxd; 3189 uint32_t reg; 3190 int i; 3191 3192 ALC_LOCK_ASSERT(sc); 3193 /* 3194 * Mark the interface down and cancel the watchdog timer. 3195 */ 3196 ifp = sc->alc_ifp; 3197 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3198 sc->alc_flags &= ~ALC_FLAG_LINK; 3199 callout_stop(&sc->alc_tick_ch); 3200 sc->alc_watchdog_timer = 0; 3201 alc_stats_update(sc); 3202 /* Disable interrupts. */ 3203 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3204 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3205 alc_stop_queue(sc); 3206 /* Disable DMA. */ 3207 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3208 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3209 reg |= DMA_CFG_SMB_DIS; 3210 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3211 DELAY(1000); 3212 /* Stop Rx/Tx MACs. */ 3213 alc_stop_mac(sc); 3214 /* Disable interrupts which might be touched in taskq handler. */ 3215 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3216 3217 /* Reclaim Rx buffers that have been processed. */ 3218 if (sc->alc_cdata.alc_rxhead != NULL) 3219 m_freem(sc->alc_cdata.alc_rxhead); 3220 ALC_RXCHAIN_RESET(sc); 3221 /* 3222 * Free Tx/Rx mbufs still in the queues. 3223 */ 3224 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3225 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3226 if (rxd->rx_m != NULL) { 3227 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3228 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3229 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3230 rxd->rx_dmamap); 3231 m_freem(rxd->rx_m); 3232 rxd->rx_m = NULL; 3233 } 3234 } 3235 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3236 txd = &sc->alc_cdata.alc_txdesc[i]; 3237 if (txd->tx_m != NULL) { 3238 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3239 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3240 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3241 txd->tx_dmamap); 3242 m_freem(txd->tx_m); 3243 txd->tx_m = NULL; 3244 } 3245 } 3246 } 3247 3248 static void 3249 alc_stop_mac(struct alc_softc *sc) 3250 { 3251 uint32_t reg; 3252 int i; 3253 3254 ALC_LOCK_ASSERT(sc); 3255 3256 /* Disable Rx/Tx MAC. */ 3257 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3258 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3259 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3260 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3261 } 3262 for (i = ALC_TIMEOUT; i > 0; i--) { 3263 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3264 if (reg == 0) 3265 break; 3266 DELAY(10); 3267 } 3268 if (i == 0) 3269 device_printf(sc->alc_dev, 3270 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3271 } 3272 3273 static void 3274 alc_start_queue(struct alc_softc *sc) 3275 { 3276 uint32_t qcfg[] = { 3277 0, 3278 RXQ_CFG_QUEUE0_ENB, 3279 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3280 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3281 RXQ_CFG_ENB 3282 }; 3283 uint32_t cfg; 3284 3285 ALC_LOCK_ASSERT(sc); 3286 3287 /* Enable RxQ. */ 3288 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3289 cfg &= ~RXQ_CFG_ENB; 3290 cfg |= qcfg[1]; 3291 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3292 /* Enable TxQ. */ 3293 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3294 cfg |= TXQ_CFG_ENB; 3295 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3296 } 3297 3298 static void 3299 alc_stop_queue(struct alc_softc *sc) 3300 { 3301 uint32_t reg; 3302 int i; 3303 3304 ALC_LOCK_ASSERT(sc); 3305 3306 /* Disable RxQ. */ 3307 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3308 if ((reg & RXQ_CFG_ENB) != 0) { 3309 reg &= ~RXQ_CFG_ENB; 3310 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3311 } 3312 /* Disable TxQ. */ 3313 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3314 if ((reg & TXQ_CFG_ENB) == 0) { 3315 reg &= ~TXQ_CFG_ENB; 3316 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3317 } 3318 for (i = ALC_TIMEOUT; i > 0; i--) { 3319 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3320 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3321 break; 3322 DELAY(10); 3323 } 3324 if (i == 0) 3325 device_printf(sc->alc_dev, 3326 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3327 } 3328 3329 static void 3330 alc_init_tx_ring(struct alc_softc *sc) 3331 { 3332 struct alc_ring_data *rd; 3333 struct alc_txdesc *txd; 3334 int i; 3335 3336 ALC_LOCK_ASSERT(sc); 3337 3338 sc->alc_cdata.alc_tx_prod = 0; 3339 sc->alc_cdata.alc_tx_cons = 0; 3340 sc->alc_cdata.alc_tx_cnt = 0; 3341 3342 rd = &sc->alc_rdata; 3343 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3344 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3345 txd = &sc->alc_cdata.alc_txdesc[i]; 3346 txd->tx_m = NULL; 3347 } 3348 3349 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3350 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3351 } 3352 3353 static int 3354 alc_init_rx_ring(struct alc_softc *sc) 3355 { 3356 struct alc_ring_data *rd; 3357 struct alc_rxdesc *rxd; 3358 int i; 3359 3360 ALC_LOCK_ASSERT(sc); 3361 3362 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3363 sc->alc_morework = 0; 3364 rd = &sc->alc_rdata; 3365 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3366 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3367 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3368 rxd->rx_m = NULL; 3369 rxd->rx_desc = &rd->alc_rx_ring[i]; 3370 if (alc_newbuf(sc, rxd) != 0) 3371 return (ENOBUFS); 3372 } 3373 3374 /* 3375 * Since controller does not update Rx descriptors, driver 3376 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3377 * is enough to ensure coherence. 3378 */ 3379 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3380 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3381 /* Let controller know availability of new Rx buffers. */ 3382 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3383 3384 return (0); 3385 } 3386 3387 static void 3388 alc_init_rr_ring(struct alc_softc *sc) 3389 { 3390 struct alc_ring_data *rd; 3391 3392 ALC_LOCK_ASSERT(sc); 3393 3394 sc->alc_cdata.alc_rr_cons = 0; 3395 ALC_RXCHAIN_RESET(sc); 3396 3397 rd = &sc->alc_rdata; 3398 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3399 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3400 sc->alc_cdata.alc_rr_ring_map, 3401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3402 } 3403 3404 static void 3405 alc_init_cmb(struct alc_softc *sc) 3406 { 3407 struct alc_ring_data *rd; 3408 3409 ALC_LOCK_ASSERT(sc); 3410 3411 rd = &sc->alc_rdata; 3412 bzero(rd->alc_cmb, ALC_CMB_SZ); 3413 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3415 } 3416 3417 static void 3418 alc_init_smb(struct alc_softc *sc) 3419 { 3420 struct alc_ring_data *rd; 3421 3422 ALC_LOCK_ASSERT(sc); 3423 3424 rd = &sc->alc_rdata; 3425 bzero(rd->alc_smb, ALC_SMB_SZ); 3426 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3427 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3428 } 3429 3430 static void 3431 alc_rxvlan(struct alc_softc *sc) 3432 { 3433 struct ifnet *ifp; 3434 uint32_t reg; 3435 3436 ALC_LOCK_ASSERT(sc); 3437 3438 ifp = sc->alc_ifp; 3439 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3440 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3441 reg |= MAC_CFG_VLAN_TAG_STRIP; 3442 else 3443 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3444 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3445 } 3446 3447 static void 3448 alc_rxfilter(struct alc_softc *sc) 3449 { 3450 struct ifnet *ifp; 3451 struct ifmultiaddr *ifma; 3452 uint32_t crc; 3453 uint32_t mchash[2]; 3454 uint32_t rxcfg; 3455 3456 ALC_LOCK_ASSERT(sc); 3457 3458 ifp = sc->alc_ifp; 3459 3460 bzero(mchash, sizeof(mchash)); 3461 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3462 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3463 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3464 rxcfg |= MAC_CFG_BCAST; 3465 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3466 if ((ifp->if_flags & IFF_PROMISC) != 0) 3467 rxcfg |= MAC_CFG_PROMISC; 3468 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3469 rxcfg |= MAC_CFG_ALLMULTI; 3470 mchash[0] = 0xFFFFFFFF; 3471 mchash[1] = 0xFFFFFFFF; 3472 goto chipit; 3473 } 3474 3475 if_maddr_rlock(ifp); 3476 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3477 if (ifma->ifma_addr->sa_family != AF_LINK) 3478 continue; 3479 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3480 ifma->ifma_addr), ETHER_ADDR_LEN); 3481 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3482 } 3483 if_maddr_runlock(ifp); 3484 3485 chipit: 3486 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3487 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3488 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3489 } 3490 3491 static int 3492 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3493 { 3494 int error, value; 3495 3496 if (arg1 == NULL) 3497 return (EINVAL); 3498 value = *(int *)arg1; 3499 error = sysctl_handle_int(oidp, &value, 0, req); 3500 if (error || req->newptr == NULL) 3501 return (error); 3502 if (value < low || value > high) 3503 return (EINVAL); 3504 *(int *)arg1 = value; 3505 3506 return (0); 3507 } 3508 3509 static int 3510 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3511 { 3512 return (sysctl_int_range(oidp, arg1, arg2, req, 3513 ALC_PROC_MIN, ALC_PROC_MAX)); 3514 } 3515 3516 static int 3517 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3518 { 3519 3520 return (sysctl_int_range(oidp, arg1, arg2, req, 3521 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3522 } 3523