1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/debugnet.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 96 /* 97 * The default value of msix_disable is 2, which means to decide whether to 98 * enable MSI-X in alc_attach() depending on the card type. The operator can 99 * set this to 0 or 1 to override the default. 100 */ 101 static int msix_disable = 2; 102 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 103 104 /* 105 * Devices supported by this driver. 106 */ 107 static struct alc_ident alc_ident_table[] = { 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 109 "Atheros AR8131 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 111 "Atheros AR8132 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 117 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 121 "Atheros AR8161 PCIe Gigabit Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 123 "Atheros AR8162 PCIe Fast Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 125 "Atheros AR8171 PCIe Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 127 "Atheros AR8172 PCIe Fast Ethernet" }, 128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 129 "Killer E2200 Gigabit Ethernet" }, 130 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 131 "Killer E2400 Gigabit Ethernet" }, 132 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 133 "Killer E2500 Gigabit Ethernet" }, 134 { 0, 0, 0, NULL} 135 }; 136 137 static void alc_aspm(struct alc_softc *, int, int); 138 static void alc_aspm_813x(struct alc_softc *, int); 139 static void alc_aspm_816x(struct alc_softc *, int); 140 static int alc_attach(device_t); 141 static int alc_check_boundary(struct alc_softc *); 142 static void alc_config_msi(struct alc_softc *); 143 static int alc_detach(device_t); 144 static void alc_disable_l0s_l1(struct alc_softc *); 145 static int alc_dma_alloc(struct alc_softc *); 146 static void alc_dma_free(struct alc_softc *); 147 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 148 static void alc_dsp_fixup(struct alc_softc *, int); 149 static int alc_encap(struct alc_softc *, struct mbuf **); 150 static struct alc_ident * 151 alc_find_ident(device_t); 152 #ifndef __NO_STRICT_ALIGNMENT 153 static struct mbuf * 154 alc_fixup_rx(if_t, struct mbuf *); 155 #endif 156 static void alc_get_macaddr(struct alc_softc *); 157 static void alc_get_macaddr_813x(struct alc_softc *); 158 static void alc_get_macaddr_816x(struct alc_softc *); 159 static void alc_get_macaddr_par(struct alc_softc *); 160 static void alc_init(void *); 161 static void alc_init_cmb(struct alc_softc *); 162 static void alc_init_locked(struct alc_softc *); 163 static void alc_init_rr_ring(struct alc_softc *); 164 static int alc_init_rx_ring(struct alc_softc *); 165 static void alc_init_smb(struct alc_softc *); 166 static void alc_init_tx_ring(struct alc_softc *); 167 static void alc_int_task(void *, int); 168 static int alc_intr(void *); 169 static int alc_ioctl(if_t, u_long, caddr_t); 170 static void alc_mac_config(struct alc_softc *); 171 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 172 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 173 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 174 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 175 static int alc_miibus_readreg(device_t, int, int); 176 static void alc_miibus_statchg(device_t); 177 static int alc_miibus_writereg(device_t, int, int, int); 178 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 179 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 180 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 181 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 182 static int alc_mediachange(if_t); 183 static int alc_mediachange_locked(struct alc_softc *); 184 static void alc_mediastatus(if_t, struct ifmediareq *); 185 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 186 static void alc_osc_reset(struct alc_softc *); 187 static void alc_phy_down(struct alc_softc *); 188 static void alc_phy_reset(struct alc_softc *); 189 static void alc_phy_reset_813x(struct alc_softc *); 190 static void alc_phy_reset_816x(struct alc_softc *); 191 static int alc_probe(device_t); 192 static void alc_reset(struct alc_softc *); 193 static int alc_resume(device_t); 194 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 195 static int alc_rxintr(struct alc_softc *, int); 196 static void alc_rxfilter(struct alc_softc *); 197 static void alc_rxvlan(struct alc_softc *); 198 static void alc_setlinkspeed(struct alc_softc *); 199 static void alc_setwol(struct alc_softc *); 200 static void alc_setwol_813x(struct alc_softc *); 201 static void alc_setwol_816x(struct alc_softc *); 202 static int alc_shutdown(device_t); 203 static void alc_start(if_t); 204 static void alc_start_locked(if_t); 205 static void alc_start_queue(struct alc_softc *); 206 static void alc_start_tx(struct alc_softc *); 207 static void alc_stats_clear(struct alc_softc *); 208 static void alc_stats_update(struct alc_softc *); 209 static void alc_stop(struct alc_softc *); 210 static void alc_stop_mac(struct alc_softc *); 211 static void alc_stop_queue(struct alc_softc *); 212 static int alc_suspend(device_t); 213 static void alc_sysctl_node(struct alc_softc *); 214 static void alc_tick(void *); 215 static void alc_txeof(struct alc_softc *); 216 static void alc_watchdog(struct alc_softc *); 217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 218 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 219 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 220 221 DEBUGNET_DEFINE(alc); 222 223 static device_method_t alc_methods[] = { 224 /* Device interface. */ 225 DEVMETHOD(device_probe, alc_probe), 226 DEVMETHOD(device_attach, alc_attach), 227 DEVMETHOD(device_detach, alc_detach), 228 DEVMETHOD(device_shutdown, alc_shutdown), 229 DEVMETHOD(device_suspend, alc_suspend), 230 DEVMETHOD(device_resume, alc_resume), 231 232 /* MII interface. */ 233 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 234 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 235 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 236 237 DEVMETHOD_END 238 }; 239 240 static driver_t alc_driver = { 241 "alc", 242 alc_methods, 243 sizeof(struct alc_softc) 244 }; 245 246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 247 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 248 nitems(alc_ident_table) - 1); 249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 250 251 static struct resource_spec alc_res_spec_mem[] = { 252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 253 { -1, 0, 0 } 254 }; 255 256 static struct resource_spec alc_irq_spec_legacy[] = { 257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 258 { -1, 0, 0 } 259 }; 260 261 static struct resource_spec alc_irq_spec_msi[] = { 262 { SYS_RES_IRQ, 1, RF_ACTIVE }, 263 { -1, 0, 0 } 264 }; 265 266 static struct resource_spec alc_irq_spec_msix[] = { 267 { SYS_RES_IRQ, 1, RF_ACTIVE }, 268 { -1, 0, 0 } 269 }; 270 271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 272 273 static int 274 alc_miibus_readreg(device_t dev, int phy, int reg) 275 { 276 struct alc_softc *sc; 277 int v; 278 279 sc = device_get_softc(dev); 280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 281 v = alc_mii_readreg_816x(sc, phy, reg); 282 else 283 v = alc_mii_readreg_813x(sc, phy, reg); 284 return (v); 285 } 286 287 static uint32_t 288 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 289 { 290 uint32_t v; 291 int i; 292 293 /* 294 * For AR8132 fast ethernet controller, do not report 1000baseT 295 * capability to mii(4). Even though AR8132 uses the same 296 * model/revision number of F1 gigabit PHY, the PHY has no 297 * ability to establish 1000baseT link. 298 */ 299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 300 reg == MII_EXTSR) 301 return (0); 302 303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 304 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 306 DELAY(5); 307 v = CSR_READ_4(sc, ALC_MDIO); 308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 309 break; 310 } 311 312 if (i == 0) { 313 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 314 return (0); 315 } 316 317 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 318 } 319 320 static uint32_t 321 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 322 { 323 uint32_t clk, v; 324 int i; 325 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 327 clk = MDIO_CLK_25_128; 328 else 329 clk = MDIO_CLK_25_4; 330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 331 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 333 DELAY(5); 334 v = CSR_READ_4(sc, ALC_MDIO); 335 if ((v & MDIO_OP_BUSY) == 0) 336 break; 337 } 338 339 if (i == 0) { 340 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 341 return (0); 342 } 343 344 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 345 } 346 347 static int 348 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 349 { 350 struct alc_softc *sc; 351 int v; 352 353 sc = device_get_softc(dev); 354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 355 v = alc_mii_writereg_816x(sc, phy, reg, val); 356 else 357 v = alc_mii_writereg_813x(sc, phy, reg, val); 358 return (v); 359 } 360 361 static uint32_t 362 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 363 { 364 uint32_t v; 365 int i; 366 367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 368 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 369 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 v = CSR_READ_4(sc, ALC_MDIO); 373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 374 break; 375 } 376 377 if (i == 0) 378 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 379 380 return (0); 381 } 382 383 static uint32_t 384 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 385 { 386 uint32_t clk, v; 387 int i; 388 389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 390 clk = MDIO_CLK_25_128; 391 else 392 clk = MDIO_CLK_25_4; 393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 394 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 395 MDIO_SUP_PREAMBLE | clk); 396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 397 DELAY(5); 398 v = CSR_READ_4(sc, ALC_MDIO); 399 if ((v & MDIO_OP_BUSY) == 0) 400 break; 401 } 402 403 if (i == 0) 404 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 405 406 return (0); 407 } 408 409 static void 410 alc_miibus_statchg(device_t dev) 411 { 412 struct alc_softc *sc; 413 struct mii_data *mii; 414 if_t ifp; 415 uint32_t reg; 416 417 sc = device_get_softc(dev); 418 419 mii = device_get_softc(sc->alc_miibus); 420 ifp = sc->alc_ifp; 421 if (mii == NULL || ifp == NULL || 422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 423 return; 424 425 sc->alc_flags &= ~ALC_FLAG_LINK; 426 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 427 (IFM_ACTIVE | IFM_AVALID)) { 428 switch (IFM_SUBTYPE(mii->mii_media_active)) { 429 case IFM_10_T: 430 case IFM_100_TX: 431 sc->alc_flags |= ALC_FLAG_LINK; 432 break; 433 case IFM_1000_T: 434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 435 sc->alc_flags |= ALC_FLAG_LINK; 436 break; 437 default: 438 break; 439 } 440 } 441 /* Stop Rx/Tx MACs. */ 442 alc_stop_mac(sc); 443 444 /* Program MACs with resolved speed/duplex/flow-control. */ 445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 446 alc_start_queue(sc); 447 alc_mac_config(sc); 448 /* Re-enable Tx/Rx MACs. */ 449 reg = CSR_READ_4(sc, ALC_MAC_CFG); 450 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 452 } 453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 454 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 455 } 456 457 static uint32_t 458 alc_miidbg_readreg(struct alc_softc *sc, int reg) 459 { 460 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 462 reg); 463 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA)); 465 } 466 467 static uint32_t 468 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 469 { 470 471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 472 reg); 473 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 474 ALC_MII_DBG_DATA, val)); 475 } 476 477 static uint32_t 478 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 479 { 480 uint32_t clk, v; 481 int i; 482 483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 484 EXT_MDIO_DEVADDR(devaddr)); 485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 486 clk = MDIO_CLK_25_128; 487 else 488 clk = MDIO_CLK_25_4; 489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 490 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 492 DELAY(5); 493 v = CSR_READ_4(sc, ALC_MDIO); 494 if ((v & MDIO_OP_BUSY) == 0) 495 break; 496 } 497 498 if (i == 0) { 499 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 500 devaddr, reg); 501 return (0); 502 } 503 504 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 505 } 506 507 static uint32_t 508 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 509 { 510 uint32_t clk, v; 511 int i; 512 513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 514 EXT_MDIO_DEVADDR(devaddr)); 515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 516 clk = MDIO_CLK_25_128; 517 else 518 clk = MDIO_CLK_25_4; 519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 520 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 521 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 523 DELAY(5); 524 v = CSR_READ_4(sc, ALC_MDIO); 525 if ((v & MDIO_OP_BUSY) == 0) 526 break; 527 } 528 529 if (i == 0) 530 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 531 devaddr, reg); 532 533 return (0); 534 } 535 536 static void 537 alc_dsp_fixup(struct alc_softc *sc, int media) 538 { 539 uint16_t agc, len, val; 540 541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 542 return; 543 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 544 return; 545 546 /* 547 * Vendor PHY magic. 548 * 1000BT/AZ, wrong cable length 549 */ 550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 551 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 552 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 553 EXT_CLDCTL6_CAB_LEN_MASK; 554 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 555 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 556 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 557 agc > DBG_AGC_LONG1G_LIMT) || 558 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 559 agc > DBG_AGC_LONG1G_LIMT)) { 560 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 561 DBG_AZ_ANADECT_LONG); 562 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 563 MII_EXT_ANEG_AFE); 564 val |= ANEG_AFEE_10BT_100M_TH; 565 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 566 val); 567 } else { 568 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 569 DBG_AZ_ANADECT_DEFAULT); 570 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 571 MII_EXT_ANEG_AFE); 572 val &= ~ANEG_AFEE_10BT_100M_TH; 573 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 574 val); 575 } 576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 577 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 578 if (media == IFM_1000_T) { 579 /* 580 * Giga link threshold, raise the tolerance of 581 * noise 50%. 582 */ 583 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 584 val &= ~DBG_MSE20DB_TH_MASK; 585 val |= (DBG_MSE20DB_TH_HI << 586 DBG_MSE20DB_TH_SHIFT); 587 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 588 } else if (media == IFM_100_TX) 589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 590 DBG_MSE16DB_UP); 591 } 592 } else { 593 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 594 val &= ~ANEG_AFEE_10BT_100M_TH; 595 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 597 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 598 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 599 DBG_MSE16DB_DOWN); 600 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 601 val &= ~DBG_MSE20DB_TH_MASK; 602 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 603 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 604 } 605 } 606 } 607 608 static void 609 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 610 { 611 struct alc_softc *sc; 612 struct mii_data *mii; 613 614 sc = if_getsoftc(ifp); 615 ALC_LOCK(sc); 616 if ((if_getflags(ifp) & IFF_UP) == 0) { 617 ALC_UNLOCK(sc); 618 return; 619 } 620 mii = device_get_softc(sc->alc_miibus); 621 622 mii_pollstat(mii); 623 ifmr->ifm_status = mii->mii_media_status; 624 ifmr->ifm_active = mii->mii_media_active; 625 ALC_UNLOCK(sc); 626 } 627 628 static int 629 alc_mediachange(if_t ifp) 630 { 631 struct alc_softc *sc; 632 int error; 633 634 sc = if_getsoftc(ifp); 635 ALC_LOCK(sc); 636 error = alc_mediachange_locked(sc); 637 ALC_UNLOCK(sc); 638 639 return (error); 640 } 641 642 static int 643 alc_mediachange_locked(struct alc_softc *sc) 644 { 645 struct mii_data *mii; 646 struct mii_softc *miisc; 647 int error; 648 649 ALC_LOCK_ASSERT(sc); 650 651 mii = device_get_softc(sc->alc_miibus); 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 PHY_RESET(miisc); 654 error = mii_mediachg(mii); 655 656 return (error); 657 } 658 659 static struct alc_ident * 660 alc_find_ident(device_t dev) 661 { 662 struct alc_ident *ident; 663 uint16_t vendor, devid; 664 665 vendor = pci_get_vendor(dev); 666 devid = pci_get_device(dev); 667 for (ident = alc_ident_table; ident->name != NULL; ident++) { 668 if (vendor == ident->vendorid && devid == ident->deviceid) 669 return (ident); 670 } 671 672 return (NULL); 673 } 674 675 static int 676 alc_probe(device_t dev) 677 { 678 struct alc_ident *ident; 679 680 ident = alc_find_ident(dev); 681 if (ident != NULL) { 682 device_set_desc(dev, ident->name); 683 return (BUS_PROBE_DEFAULT); 684 } 685 686 return (ENXIO); 687 } 688 689 static void 690 alc_get_macaddr(struct alc_softc *sc) 691 { 692 693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 694 alc_get_macaddr_816x(sc); 695 else 696 alc_get_macaddr_813x(sc); 697 } 698 699 static void 700 alc_get_macaddr_813x(struct alc_softc *sc) 701 { 702 uint32_t opt; 703 uint16_t val; 704 int eeprom, i; 705 706 eeprom = 0; 707 opt = CSR_READ_4(sc, ALC_OPT_CFG); 708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 710 /* 711 * EEPROM found, let TWSI reload EEPROM configuration. 712 * This will set ethernet address of controller. 713 */ 714 eeprom++; 715 switch (sc->alc_ident->deviceid) { 716 case DEVICEID_ATHEROS_AR8131: 717 case DEVICEID_ATHEROS_AR8132: 718 if ((opt & OPT_CFG_CLK_ENB) == 0) { 719 opt |= OPT_CFG_CLK_ENB; 720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 721 CSR_READ_4(sc, ALC_OPT_CFG); 722 DELAY(1000); 723 } 724 break; 725 case DEVICEID_ATHEROS_AR8151: 726 case DEVICEID_ATHEROS_AR8151_V2: 727 case DEVICEID_ATHEROS_AR8152_B: 728 case DEVICEID_ATHEROS_AR8152_B2: 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_ADDR, 0x00); 731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 732 ALC_MII_DBG_DATA); 733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 734 ALC_MII_DBG_DATA, val & 0xFF7F); 735 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 736 ALC_MII_DBG_ADDR, 0x3B); 737 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 738 ALC_MII_DBG_DATA); 739 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 740 ALC_MII_DBG_DATA, val | 0x0008); 741 DELAY(20); 742 break; 743 } 744 745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 748 CSR_READ_4(sc, ALC_WOL_CFG); 749 750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 751 TWSI_CFG_SW_LD_START); 752 for (i = 100; i > 0; i--) { 753 DELAY(1000); 754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 755 TWSI_CFG_SW_LD_START) == 0) 756 break; 757 } 758 if (i == 0) 759 device_printf(sc->alc_dev, 760 "reloading EEPROM timeout!\n"); 761 } else { 762 if (bootverbose) 763 device_printf(sc->alc_dev, "EEPROM not found!\n"); 764 } 765 if (eeprom != 0) { 766 switch (sc->alc_ident->deviceid) { 767 case DEVICEID_ATHEROS_AR8131: 768 case DEVICEID_ATHEROS_AR8132: 769 if ((opt & OPT_CFG_CLK_ENB) != 0) { 770 opt &= ~OPT_CFG_CLK_ENB; 771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 772 CSR_READ_4(sc, ALC_OPT_CFG); 773 DELAY(1000); 774 } 775 break; 776 case DEVICEID_ATHEROS_AR8151: 777 case DEVICEID_ATHEROS_AR8151_V2: 778 case DEVICEID_ATHEROS_AR8152_B: 779 case DEVICEID_ATHEROS_AR8152_B2: 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_ADDR, 0x00); 782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 783 ALC_MII_DBG_DATA); 784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 785 ALC_MII_DBG_DATA, val | 0x0080); 786 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x3B); 788 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA); 790 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 791 ALC_MII_DBG_DATA, val & 0xFFF7); 792 DELAY(20); 793 break; 794 } 795 } 796 797 alc_get_macaddr_par(sc); 798 } 799 800 static void 801 alc_get_macaddr_816x(struct alc_softc *sc) 802 { 803 uint32_t reg; 804 int i, reloaded; 805 806 reloaded = 0; 807 /* Try to reload station address via TWSI. */ 808 for (i = 100; i > 0; i--) { 809 reg = CSR_READ_4(sc, ALC_SLD); 810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 811 break; 812 DELAY(1000); 813 } 814 if (i != 0) { 815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 816 for (i = 100; i > 0; i--) { 817 DELAY(1000); 818 reg = CSR_READ_4(sc, ALC_SLD); 819 if ((reg & SLD_START) == 0) 820 break; 821 } 822 if (i != 0) 823 reloaded++; 824 else if (bootverbose) 825 device_printf(sc->alc_dev, 826 "reloading station address via TWSI timed out!\n"); 827 } 828 829 /* Try to reload station address from EEPROM or FLASH. */ 830 if (reloaded == 0) { 831 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 832 if ((reg & (EEPROM_LD_EEPROM_EXIST | 833 EEPROM_LD_FLASH_EXIST)) != 0) { 834 for (i = 100; i > 0; i--) { 835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 836 if ((reg & (EEPROM_LD_PROGRESS | 837 EEPROM_LD_START)) == 0) 838 break; 839 DELAY(1000); 840 } 841 if (i != 0) { 842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 843 EEPROM_LD_START); 844 for (i = 100; i > 0; i--) { 845 DELAY(1000); 846 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 847 if ((reg & EEPROM_LD_START) == 0) 848 break; 849 } 850 } else if (bootverbose) 851 device_printf(sc->alc_dev, 852 "reloading EEPROM/FLASH timed out!\n"); 853 } 854 } 855 856 alc_get_macaddr_par(sc); 857 } 858 859 static void 860 alc_get_macaddr_par(struct alc_softc *sc) 861 { 862 uint32_t ea[2]; 863 864 ea[0] = CSR_READ_4(sc, ALC_PAR0); 865 ea[1] = CSR_READ_4(sc, ALC_PAR1); 866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 872 } 873 874 static void 875 alc_disable_l0s_l1(struct alc_softc *sc) 876 { 877 uint32_t pmcfg; 878 879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 880 /* Another magic from vendor. */ 881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 882 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 883 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 884 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 885 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 886 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 888 } 889 } 890 891 static void 892 alc_phy_reset(struct alc_softc *sc) 893 { 894 895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 896 alc_phy_reset_816x(sc); 897 else 898 alc_phy_reset_813x(sc); 899 } 900 901 static void 902 alc_phy_reset_813x(struct alc_softc *sc) 903 { 904 uint16_t data; 905 906 /* Reset magic from Linux. */ 907 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 908 CSR_READ_2(sc, ALC_GPHY_CFG); 909 DELAY(10 * 1000); 910 911 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 912 GPHY_CFG_SEL_ANA_RESET); 913 CSR_READ_2(sc, ALC_GPHY_CFG); 914 DELAY(10 * 1000); 915 916 /* DSP fixup, Vendor magic. */ 917 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, 0x000A); 920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA); 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA, data & 0xDFFF); 924 } 925 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_ADDR, 0x003B); 931 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_DATA); 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_DATA, data & 0xFFF7); 935 DELAY(20 * 1000); 936 } 937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_ADDR, 0x0029); 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_DATA, 0x929D); 942 } 943 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 946 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_ADDR, 0x0029); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_DATA, 0xB6DD); 951 } 952 953 /* Load DSP codes, vendor magic. */ 954 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 955 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 957 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 959 ALC_MII_DBG_DATA, data); 960 961 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 962 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 963 ANA_SERDES_EN_LCKDT; 964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 965 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 967 ALC_MII_DBG_DATA, data); 968 969 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 970 ANA_LONG_CABLE_TH_100_MASK) | 971 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 972 ANA_SHORT_CABLE_TH_100_SHIFT) | 973 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_DATA, data); 978 979 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 980 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 981 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 982 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 984 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 986 ALC_MII_DBG_DATA, data); 987 988 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 989 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 990 ANA_OEN_125M; 991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 992 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 994 ALC_MII_DBG_DATA, data); 995 DELAY(1000); 996 997 /* Disable hibernation. */ 998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 999 0x0029); 1000 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1001 ALC_MII_DBG_DATA); 1002 data &= ~0x8000; 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1004 data); 1005 1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1007 0x000B); 1008 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1009 ALC_MII_DBG_DATA); 1010 data &= ~0x8000; 1011 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1012 data); 1013 } 1014 1015 static void 1016 alc_phy_reset_816x(struct alc_softc *sc) 1017 { 1018 uint32_t val; 1019 1020 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1021 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1022 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1023 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1024 val |= GPHY_CFG_SEL_ANA_RESET; 1025 #ifdef notyet 1026 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1027 #else 1028 /* Disable PHY hibernation. */ 1029 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1030 #endif 1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1032 DELAY(10); 1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1034 DELAY(800); 1035 1036 /* Vendor PHY magic. */ 1037 #ifdef notyet 1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1039 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1040 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1041 EXT_VDRVBIAS_DEFAULT); 1042 #else 1043 /* Disable PHY hibernation. */ 1044 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1045 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1046 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1047 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1048 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1049 #endif 1050 1051 /* XXX Disable EEE. */ 1052 val = CSR_READ_4(sc, ALC_LPI_CTL); 1053 val &= ~LPI_CTL_ENB; 1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1056 1057 /* PHY power saving. */ 1058 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1061 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1062 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1063 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1064 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1065 1066 /* RTL8139C, 120m issue. */ 1067 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1068 ANEG_NLP78_120M_DEFAULT); 1069 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1070 ANEG_S3DIG10_DEFAULT); 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1073 /* Turn off half amplitude. */ 1074 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1075 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1076 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1077 /* Turn off Green feature. */ 1078 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1079 val |= DBG_GREENCFG2_BP_GREEN; 1080 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1081 /* Turn off half bias. */ 1082 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1083 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1084 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1085 } 1086 } 1087 1088 static void 1089 alc_phy_down(struct alc_softc *sc) 1090 { 1091 uint32_t gphy; 1092 1093 switch (sc->alc_ident->deviceid) { 1094 case DEVICEID_ATHEROS_AR8161: 1095 case DEVICEID_ATHEROS_E2200: 1096 case DEVICEID_ATHEROS_E2400: 1097 case DEVICEID_ATHEROS_E2500: 1098 case DEVICEID_ATHEROS_AR8162: 1099 case DEVICEID_ATHEROS_AR8171: 1100 case DEVICEID_ATHEROS_AR8172: 1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1102 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1103 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1104 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1105 GPHY_CFG_SEL_ANA_RESET; 1106 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1108 break; 1109 case DEVICEID_ATHEROS_AR8151: 1110 case DEVICEID_ATHEROS_AR8151_V2: 1111 case DEVICEID_ATHEROS_AR8152_B: 1112 case DEVICEID_ATHEROS_AR8152_B2: 1113 /* 1114 * GPHY power down caused more problems on AR8151 v2.0. 1115 * When driver is reloaded after GPHY power down, 1116 * accesses to PHY/MAC registers hung the system. Only 1117 * cold boot recovered from it. I'm not sure whether 1118 * AR8151 v1.0 also requires this one though. I don't 1119 * have AR8151 v1.0 controller in hand. 1120 * The only option left is to isolate the PHY and 1121 * initiates power down the PHY which in turn saves 1122 * more power when driver is unloaded. 1123 */ 1124 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1125 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1126 break; 1127 default: 1128 /* Force PHY down. */ 1129 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1130 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1131 GPHY_CFG_PWDOWN_HW); 1132 DELAY(1000); 1133 break; 1134 } 1135 } 1136 1137 static void 1138 alc_aspm(struct alc_softc *sc, int init, int media) 1139 { 1140 1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1142 alc_aspm_816x(sc, init); 1143 else 1144 alc_aspm_813x(sc, media); 1145 } 1146 1147 static void 1148 alc_aspm_813x(struct alc_softc *sc, int media) 1149 { 1150 uint32_t pmcfg; 1151 uint16_t linkcfg; 1152 1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1154 return; 1155 1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1157 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1158 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1159 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1160 PCIER_LINK_CTL); 1161 else 1162 linkcfg = 0; 1163 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1164 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1165 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1166 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1167 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1168 1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1170 /* Disable extended sync except AR8152 B v1.0 */ 1171 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1173 sc->alc_rev == ATHEROS_AR8152_B_V10) 1174 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1175 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1176 linkcfg); 1177 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1178 PM_CFG_HOTRST); 1179 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1180 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1181 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1182 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1183 PM_CFG_PM_REQ_TIMER_SHIFT); 1184 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1185 } 1186 1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1189 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1191 pmcfg |= PM_CFG_ASPM_L1_ENB; 1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1193 if (sc->alc_ident->deviceid == 1194 DEVICEID_ATHEROS_AR8152_B) 1195 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1196 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1197 PM_CFG_SERDES_PLL_L1_ENB | 1198 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1199 pmcfg |= PM_CFG_CLK_SWH_L1; 1200 if (media == IFM_100_TX || media == IFM_1000_T) { 1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1202 switch (sc->alc_ident->deviceid) { 1203 case DEVICEID_ATHEROS_AR8152_B: 1204 pmcfg |= (7 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 case DEVICEID_ATHEROS_AR8152_B2: 1208 case DEVICEID_ATHEROS_AR8151_V2: 1209 pmcfg |= (4 << 1210 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1211 break; 1212 default: 1213 pmcfg |= (15 << 1214 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1215 break; 1216 } 1217 } 1218 } else { 1219 pmcfg |= PM_CFG_SERDES_L1_ENB | 1220 PM_CFG_SERDES_PLL_L1_ENB | 1221 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1222 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1223 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1224 } 1225 } else { 1226 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1227 PM_CFG_SERDES_PLL_L1_ENB); 1228 pmcfg |= PM_CFG_CLK_SWH_L1; 1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1230 pmcfg |= PM_CFG_ASPM_L1_ENB; 1231 } 1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1233 } 1234 1235 static void 1236 alc_aspm_816x(struct alc_softc *sc, int init) 1237 { 1238 uint32_t pmcfg; 1239 1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1241 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1242 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1243 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1244 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1245 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1246 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1247 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1248 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1249 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1250 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1251 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1252 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1253 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1254 (sc->alc_rev & 0x01) != 0) 1255 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1257 /* Link up, enable both L0s, L1s. */ 1258 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1259 PM_CFG_MAC_ASPM_CHK; 1260 } else { 1261 if (init != 0) 1262 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1263 PM_CFG_MAC_ASPM_CHK; 1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1265 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1266 } 1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1268 } 1269 1270 static void 1271 alc_init_pcie(struct alc_softc *sc) 1272 { 1273 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1274 uint32_t cap, ctl, val; 1275 int state; 1276 1277 /* Clear data link and flow-control protocol error. */ 1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1279 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1281 1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1287 PCIE_PHYMISC_FORCE_RCV_DET); 1288 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1289 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1291 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1292 PCIE_PHYMISC2_SERDES_TH_MASK); 1293 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1294 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1296 } 1297 /* Disable ASPM L0S and L1. */ 1298 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1300 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1302 sc->alc_rcb = DMA_CFG_RCB_128; 1303 if (bootverbose) 1304 device_printf(sc->alc_dev, "RCB %u bytes\n", 1305 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1306 state = ctl & PCIEM_LINK_CTL_ASPMC; 1307 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1308 sc->alc_flags |= ALC_FLAG_L0S; 1309 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1310 sc->alc_flags |= ALC_FLAG_L1S; 1311 if (bootverbose) 1312 device_printf(sc->alc_dev, "ASPM %s %s\n", 1313 aspm_state[state], 1314 state == 0 ? "disabled" : "enabled"); 1315 alc_disable_l0s_l1(sc); 1316 } else { 1317 if (bootverbose) 1318 device_printf(sc->alc_dev, 1319 "no ASPM support\n"); 1320 } 1321 } else { 1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1323 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1325 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1326 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1327 (sc->alc_rev & 0x01) != 0) { 1328 if ((val & MASTER_WAKEN_25M) == 0 || 1329 (val & MASTER_CLK_SEL_DIS) == 0) { 1330 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1332 } 1333 } else { 1334 if ((val & MASTER_WAKEN_25M) == 0 || 1335 (val & MASTER_CLK_SEL_DIS) != 0) { 1336 val |= MASTER_WAKEN_25M; 1337 val &= ~MASTER_CLK_SEL_DIS; 1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1339 } 1340 } 1341 } 1342 alc_aspm(sc, 1, IFM_UNKNOWN); 1343 } 1344 1345 static void 1346 alc_config_msi(struct alc_softc *sc) 1347 { 1348 uint32_t ctl, mod; 1349 1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1351 /* 1352 * It seems interrupt moderation is controlled by 1353 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1354 * Driver uses RX interrupt moderation parameter to 1355 * program ALC_MSI_RETRANS_TIMER register. 1356 */ 1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1358 ctl &= ~MSI_RETRANS_TIMER_MASK; 1359 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1360 mod = ALC_USECS(sc->alc_int_rx_mod); 1361 if (mod == 0) 1362 mod = 1; 1363 ctl |= mod; 1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_STD); 1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1369 MSI_RETRANS_MASK_SEL_LINE); 1370 else 1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1372 } 1373 } 1374 1375 static int 1376 alc_attach(device_t dev) 1377 { 1378 struct alc_softc *sc; 1379 if_t ifp; 1380 int base, error, i, msic, msixc; 1381 uint16_t burst; 1382 1383 error = 0; 1384 sc = device_get_softc(dev); 1385 sc->alc_dev = dev; 1386 sc->alc_rev = pci_get_revid(dev); 1387 1388 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1389 MTX_DEF); 1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1392 sc->alc_ident = alc_find_ident(dev); 1393 1394 /* Map the device. */ 1395 pci_enable_busmaster(dev); 1396 sc->alc_res_spec = alc_res_spec_mem; 1397 sc->alc_irq_spec = alc_irq_spec_legacy; 1398 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1399 if (error != 0) { 1400 device_printf(dev, "cannot allocate memory resources.\n"); 1401 goto fail; 1402 } 1403 1404 /* Set PHY address. */ 1405 sc->alc_phyaddr = ALC_PHY_ADDR; 1406 1407 /* 1408 * One odd thing is AR8132 uses the same PHY hardware(F1 1409 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1410 * the PHY supports 1000Mbps but that's not true. The PHY 1411 * used in AR8132 can't establish gigabit link even if it 1412 * shows the same PHY model/revision number of AR8131. 1413 */ 1414 switch (sc->alc_ident->deviceid) { 1415 case DEVICEID_ATHEROS_E2200: 1416 case DEVICEID_ATHEROS_E2400: 1417 case DEVICEID_ATHEROS_E2500: 1418 sc->alc_flags |= ALC_FLAG_E2X00; 1419 1420 /* 1421 * Disable MSI-X by default on Killer devices, since this is 1422 * reported by several users to not work well. 1423 */ 1424 if (msix_disable == 2) 1425 msix_disable = 1; 1426 1427 /* FALLTHROUGH */ 1428 case DEVICEID_ATHEROS_AR8161: 1429 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1431 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8171: 1434 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1435 break; 1436 case DEVICEID_ATHEROS_AR8162: 1437 case DEVICEID_ATHEROS_AR8172: 1438 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1439 break; 1440 case DEVICEID_ATHEROS_AR8152_B: 1441 case DEVICEID_ATHEROS_AR8152_B2: 1442 sc->alc_flags |= ALC_FLAG_APS; 1443 /* FALLTHROUGH */ 1444 case DEVICEID_ATHEROS_AR8132: 1445 sc->alc_flags |= ALC_FLAG_FASTETHER; 1446 break; 1447 case DEVICEID_ATHEROS_AR8151: 1448 case DEVICEID_ATHEROS_AR8151_V2: 1449 sc->alc_flags |= ALC_FLAG_APS; 1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1451 sc->alc_flags |= ALC_FLAG_MT; 1452 /* FALLTHROUGH */ 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * The default value of msix_disable is 2, which means auto-detect. If 1459 * we didn't auto-detect it, default to enabling it. 1460 */ 1461 if (msix_disable == 2) 1462 msix_disable = 0; 1463 1464 sc->alc_flags |= ALC_FLAG_JUMBO; 1465 1466 /* 1467 * It seems that AR813x/AR815x has silicon bug for SMB. In 1468 * addition, Atheros said that enabling SMB wouldn't improve 1469 * performance. However I think it's bad to access lots of 1470 * registers to extract MAC statistics. 1471 */ 1472 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1473 /* 1474 * Don't use Tx CMB. It is known to have silicon bug. 1475 */ 1476 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1478 MASTER_CHIP_REV_SHIFT; 1479 if (bootverbose) { 1480 device_printf(dev, "PCI device revision : 0x%04x\n", 1481 sc->alc_rev); 1482 device_printf(dev, "Chip id/revision : 0x%04x\n", 1483 sc->alc_chip_rev); 1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1485 device_printf(dev, "AR816x revision : 0x%x\n", 1486 AR816X_REV(sc->alc_rev)); 1487 } 1488 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1491 1492 /* Initialize DMA parameters. */ 1493 sc->alc_dma_rd_burst = 0; 1494 sc->alc_dma_wr_burst = 0; 1495 sc->alc_rcb = DMA_CFG_RCB_64; 1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1497 sc->alc_flags |= ALC_FLAG_PCIE; 1498 sc->alc_expcap = base; 1499 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1500 sc->alc_dma_rd_burst = 1501 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1502 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1503 if (bootverbose) { 1504 device_printf(dev, "Read request size : %u bytes.\n", 1505 alc_dma_burst[sc->alc_dma_rd_burst]); 1506 device_printf(dev, "TLP payload size : %u bytes.\n", 1507 alc_dma_burst[sc->alc_dma_wr_burst]); 1508 } 1509 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1510 sc->alc_dma_rd_burst = 3; 1511 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1512 sc->alc_dma_wr_burst = 3; 1513 /* 1514 * Force maximum payload size to 128 bytes for 1515 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1516 * Otherwise it triggers DMA write error. 1517 */ 1518 if ((sc->alc_flags & 1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1520 sc->alc_dma_wr_burst = 0; 1521 alc_init_pcie(sc); 1522 } 1523 1524 /* Reset PHY. */ 1525 alc_phy_reset(sc); 1526 1527 /* Reset the ethernet controller. */ 1528 alc_stop_mac(sc); 1529 alc_reset(sc); 1530 1531 /* Allocate IRQ resources. */ 1532 msixc = pci_msix_count(dev); 1533 msic = pci_msi_count(dev); 1534 if (bootverbose) { 1535 device_printf(dev, "MSIX count : %d\n", msixc); 1536 device_printf(dev, "MSI count : %d\n", msic); 1537 } 1538 if (msixc > 1) 1539 msixc = 1; 1540 if (msic > 1) 1541 msic = 1; 1542 /* 1543 * Prefer MSIX over MSI. 1544 * AR816x controller has a silicon bug that MSI interrupt 1545 * does not assert if PCIM_CMD_INTxDIS bit of command 1546 * register is set. pci(4) was taught to handle that case. 1547 */ 1548 if (msix_disable == 0 || msi_disable == 0) { 1549 if (msix_disable == 0 && msixc > 0 && 1550 pci_alloc_msix(dev, &msixc) == 0) { 1551 if (msic == 1) { 1552 device_printf(dev, 1553 "Using %d MSIX message(s).\n", msixc); 1554 sc->alc_flags |= ALC_FLAG_MSIX; 1555 sc->alc_irq_spec = alc_irq_spec_msix; 1556 } else 1557 pci_release_msi(dev); 1558 } 1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1561 if (msic == 1) { 1562 device_printf(dev, 1563 "Using %d MSI message(s).\n", msic); 1564 sc->alc_flags |= ALC_FLAG_MSI; 1565 sc->alc_irq_spec = alc_irq_spec_msi; 1566 } else 1567 pci_release_msi(dev); 1568 } 1569 } 1570 1571 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1572 if (error != 0) { 1573 device_printf(dev, "cannot allocate IRQ resources.\n"); 1574 goto fail; 1575 } 1576 1577 /* Create device sysctl node. */ 1578 alc_sysctl_node(sc); 1579 1580 if ((error = alc_dma_alloc(sc)) != 0) 1581 goto fail; 1582 1583 /* Load station address. */ 1584 alc_get_macaddr(sc); 1585 1586 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1587 if_setsoftc(ifp, sc); 1588 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1589 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1590 if_setioctlfn(ifp, alc_ioctl); 1591 if_setstartfn(ifp, alc_start); 1592 if_setinitfn(ifp, alc_init); 1593 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1594 if_setsendqready(ifp); 1595 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1596 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1597 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1598 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1599 sc->alc_flags |= ALC_FLAG_PM; 1600 sc->alc_pmcap = base; 1601 } 1602 if_setcapenable(ifp, if_getcapabilities(ifp)); 1603 1604 /* Set up MII bus. */ 1605 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1606 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1607 MIIF_DOPAUSE); 1608 if (error != 0) { 1609 device_printf(dev, "attaching PHYs failed\n"); 1610 goto fail; 1611 } 1612 1613 ether_ifattach(ifp, sc->alc_eaddr); 1614 1615 /* VLAN capability setup. */ 1616 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1617 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1618 if_setcapenable(ifp, if_getcapabilities(ifp)); 1619 /* 1620 * XXX 1621 * It seems enabling Tx checksum offloading makes more trouble. 1622 * Sometimes the controller does not receive any frames when 1623 * Tx checksum offloading is enabled. I'm not sure whether this 1624 * is a bug in Tx checksum offloading logic or I got broken 1625 * sample boards. To safety, don't enable Tx checksum offloading 1626 * by default but give chance to users to toggle it if they know 1627 * their controllers work without problems. 1628 * Fortunately, Tx checksum offloading for AR816x family 1629 * seems to work. 1630 */ 1631 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1632 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1633 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1634 } 1635 1636 /* Tell the upper layer(s) we support long frames. */ 1637 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1638 1639 /* Create local taskq. */ 1640 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1641 taskqueue_thread_enqueue, &sc->alc_tq); 1642 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1643 device_get_nameunit(sc->alc_dev)); 1644 1645 alc_config_msi(sc); 1646 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1647 msic = ALC_MSIX_MESSAGES; 1648 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1649 msic = ALC_MSI_MESSAGES; 1650 else 1651 msic = 1; 1652 for (i = 0; i < msic; i++) { 1653 error = bus_setup_intr(dev, sc->alc_irq[i], 1654 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1655 &sc->alc_intrhand[i]); 1656 if (error != 0) 1657 break; 1658 } 1659 if (error != 0) { 1660 device_printf(dev, "could not set up interrupt handler.\n"); 1661 taskqueue_free(sc->alc_tq); 1662 sc->alc_tq = NULL; 1663 ether_ifdetach(ifp); 1664 goto fail; 1665 } 1666 1667 /* Attach driver debugnet methods. */ 1668 DEBUGNET_SET(ifp, alc); 1669 1670 fail: 1671 if (error != 0) 1672 alc_detach(dev); 1673 1674 return (error); 1675 } 1676 1677 static int 1678 alc_detach(device_t dev) 1679 { 1680 struct alc_softc *sc; 1681 if_t ifp; 1682 int i, msic; 1683 1684 sc = device_get_softc(dev); 1685 1686 ifp = sc->alc_ifp; 1687 if (device_is_attached(dev)) { 1688 ether_ifdetach(ifp); 1689 ALC_LOCK(sc); 1690 alc_stop(sc); 1691 ALC_UNLOCK(sc); 1692 callout_drain(&sc->alc_tick_ch); 1693 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1694 } 1695 1696 if (sc->alc_tq != NULL) { 1697 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1698 taskqueue_free(sc->alc_tq); 1699 sc->alc_tq = NULL; 1700 } 1701 1702 bus_generic_detach(dev); 1703 alc_dma_free(sc); 1704 1705 if (ifp != NULL) { 1706 if_free(ifp); 1707 sc->alc_ifp = NULL; 1708 } 1709 1710 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1711 msic = ALC_MSIX_MESSAGES; 1712 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1713 msic = ALC_MSI_MESSAGES; 1714 else 1715 msic = 1; 1716 for (i = 0; i < msic; i++) { 1717 if (sc->alc_intrhand[i] != NULL) { 1718 bus_teardown_intr(dev, sc->alc_irq[i], 1719 sc->alc_intrhand[i]); 1720 sc->alc_intrhand[i] = NULL; 1721 } 1722 } 1723 if (sc->alc_res[0] != NULL) 1724 alc_phy_down(sc); 1725 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1726 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1727 pci_release_msi(dev); 1728 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1729 mtx_destroy(&sc->alc_mtx); 1730 1731 return (0); 1732 } 1733 1734 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1735 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1736 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1737 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1738 1739 static void 1740 alc_sysctl_node(struct alc_softc *sc) 1741 { 1742 struct sysctl_ctx_list *ctx; 1743 struct sysctl_oid_list *child, *parent; 1744 struct sysctl_oid *tree; 1745 struct alc_hw_stats *stats; 1746 int error; 1747 1748 stats = &sc->alc_stats; 1749 ctx = device_get_sysctl_ctx(sc->alc_dev); 1750 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1751 1752 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1753 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1754 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1755 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1756 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1757 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1758 /* Pull in device tunables. */ 1759 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1760 error = resource_int_value(device_get_name(sc->alc_dev), 1761 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1762 if (error == 0) { 1763 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1764 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1765 device_printf(sc->alc_dev, "int_rx_mod value out of " 1766 "range; using default: %d\n", 1767 ALC_IM_RX_TIMER_DEFAULT); 1768 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1769 } 1770 } 1771 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1772 error = resource_int_value(device_get_name(sc->alc_dev), 1773 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1774 if (error == 0) { 1775 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1776 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1777 device_printf(sc->alc_dev, "int_tx_mod value out of " 1778 "range; using default: %d\n", 1779 ALC_IM_TX_TIMER_DEFAULT); 1780 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1781 } 1782 } 1783 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1784 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1785 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1786 "max number of Rx events to process"); 1787 /* Pull in device tunables. */ 1788 sc->alc_process_limit = ALC_PROC_DEFAULT; 1789 error = resource_int_value(device_get_name(sc->alc_dev), 1790 device_get_unit(sc->alc_dev), "process_limit", 1791 &sc->alc_process_limit); 1792 if (error == 0) { 1793 if (sc->alc_process_limit < ALC_PROC_MIN || 1794 sc->alc_process_limit > ALC_PROC_MAX) { 1795 device_printf(sc->alc_dev, 1796 "process_limit value out of range; " 1797 "using default: %d\n", ALC_PROC_DEFAULT); 1798 sc->alc_process_limit = ALC_PROC_DEFAULT; 1799 } 1800 } 1801 1802 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1803 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1804 parent = SYSCTL_CHILDREN(tree); 1805 1806 /* Rx statistics. */ 1807 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1808 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1809 child = SYSCTL_CHILDREN(tree); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1811 &stats->rx_frames, "Good frames"); 1812 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1813 &stats->rx_bcast_frames, "Good broadcast frames"); 1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1815 &stats->rx_mcast_frames, "Good multicast frames"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1817 &stats->rx_pause_frames, "Pause control frames"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1819 &stats->rx_control_frames, "Control frames"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1821 &stats->rx_crcerrs, "CRC errors"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1823 &stats->rx_lenerrs, "Frames with length mismatched"); 1824 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1825 &stats->rx_bytes, "Good octets"); 1826 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1827 &stats->rx_bcast_bytes, "Good broadcast octets"); 1828 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1829 &stats->rx_mcast_bytes, "Good multicast octets"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1831 &stats->rx_runts, "Too short frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1833 &stats->rx_fragments, "Fragmented frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1835 &stats->rx_pkts_64, "64 bytes frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1837 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1839 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1841 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1843 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1845 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1847 &stats->rx_pkts_1519_max, "1519 to max frames"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1849 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1851 &stats->rx_fifo_oflows, "FIFO overflows"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1853 &stats->rx_rrs_errs, "Return status write-back errors"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1855 &stats->rx_alignerrs, "Alignment errors"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1857 &stats->rx_pkts_filtered, 1858 "Frames dropped due to address filtering"); 1859 1860 /* Tx statistics. */ 1861 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1862 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1863 child = SYSCTL_CHILDREN(tree); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1865 &stats->tx_frames, "Good frames"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1867 &stats->tx_bcast_frames, "Good broadcast frames"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1869 &stats->tx_mcast_frames, "Good multicast frames"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1871 &stats->tx_pause_frames, "Pause control frames"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1873 &stats->tx_control_frames, "Control frames"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1875 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1877 &stats->tx_excess_defer, "Frames with derferrals"); 1878 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1879 &stats->tx_bytes, "Good octets"); 1880 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1881 &stats->tx_bcast_bytes, "Good broadcast octets"); 1882 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1883 &stats->tx_mcast_bytes, "Good multicast octets"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1885 &stats->tx_pkts_64, "64 bytes frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1887 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1889 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1891 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1893 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1895 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1897 &stats->tx_pkts_1519_max, "1519 to max frames"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1899 &stats->tx_single_colls, "Single collisions"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1901 &stats->tx_multi_colls, "Multiple collisions"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1903 &stats->tx_late_colls, "Late collisions"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1905 &stats->tx_excess_colls, "Excessive collisions"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1907 &stats->tx_underrun, "FIFO underruns"); 1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1909 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1911 &stats->tx_lenerrs, "Frames with length mismatched"); 1912 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1913 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1914 } 1915 1916 #undef ALC_SYSCTL_STAT_ADD32 1917 #undef ALC_SYSCTL_STAT_ADD64 1918 1919 struct alc_dmamap_arg { 1920 bus_addr_t alc_busaddr; 1921 }; 1922 1923 static void 1924 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1925 { 1926 struct alc_dmamap_arg *ctx; 1927 1928 if (error != 0) 1929 return; 1930 1931 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1932 1933 ctx = (struct alc_dmamap_arg *)arg; 1934 ctx->alc_busaddr = segs[0].ds_addr; 1935 } 1936 1937 /* 1938 * Normal and high Tx descriptors shares single Tx high address. 1939 * Four Rx descriptor/return rings and CMB shares the same Rx 1940 * high address. 1941 */ 1942 static int 1943 alc_check_boundary(struct alc_softc *sc) 1944 { 1945 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1946 1947 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1948 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1949 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1950 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1951 1952 /* 4GB boundary crossing is not allowed. */ 1953 if ((ALC_ADDR_HI(rx_ring_end) != 1954 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1955 (ALC_ADDR_HI(rr_ring_end) != 1956 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1957 (ALC_ADDR_HI(cmb_end) != 1958 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1959 (ALC_ADDR_HI(tx_ring_end) != 1960 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1961 return (EFBIG); 1962 /* 1963 * Make sure Rx return descriptor/Rx descriptor/CMB use 1964 * the same high address. 1965 */ 1966 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1967 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1968 return (EFBIG); 1969 1970 return (0); 1971 } 1972 1973 static int 1974 alc_dma_alloc(struct alc_softc *sc) 1975 { 1976 struct alc_txdesc *txd; 1977 struct alc_rxdesc *rxd; 1978 bus_addr_t lowaddr; 1979 struct alc_dmamap_arg ctx; 1980 int error, i; 1981 1982 lowaddr = BUS_SPACE_MAXADDR; 1983 if (sc->alc_flags & ALC_FLAG_MT) 1984 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1985 again: 1986 /* Create parent DMA tag. */ 1987 error = bus_dma_tag_create( 1988 bus_get_dma_tag(sc->alc_dev), /* parent */ 1989 1, 0, /* alignment, boundary */ 1990 lowaddr, /* lowaddr */ 1991 BUS_SPACE_MAXADDR, /* highaddr */ 1992 NULL, NULL, /* filter, filterarg */ 1993 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1994 0, /* nsegments */ 1995 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1996 0, /* flags */ 1997 NULL, NULL, /* lockfunc, lockarg */ 1998 &sc->alc_cdata.alc_parent_tag); 1999 if (error != 0) { 2000 device_printf(sc->alc_dev, 2001 "could not create parent DMA tag.\n"); 2002 goto fail; 2003 } 2004 2005 /* Create DMA tag for Tx descriptor ring. */ 2006 error = bus_dma_tag_create( 2007 sc->alc_cdata.alc_parent_tag, /* parent */ 2008 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2009 BUS_SPACE_MAXADDR, /* lowaddr */ 2010 BUS_SPACE_MAXADDR, /* highaddr */ 2011 NULL, NULL, /* filter, filterarg */ 2012 ALC_TX_RING_SZ, /* maxsize */ 2013 1, /* nsegments */ 2014 ALC_TX_RING_SZ, /* maxsegsize */ 2015 0, /* flags */ 2016 NULL, NULL, /* lockfunc, lockarg */ 2017 &sc->alc_cdata.alc_tx_ring_tag); 2018 if (error != 0) { 2019 device_printf(sc->alc_dev, 2020 "could not create Tx ring DMA tag.\n"); 2021 goto fail; 2022 } 2023 2024 /* Create DMA tag for Rx free descriptor ring. */ 2025 error = bus_dma_tag_create( 2026 sc->alc_cdata.alc_parent_tag, /* parent */ 2027 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2028 BUS_SPACE_MAXADDR, /* lowaddr */ 2029 BUS_SPACE_MAXADDR, /* highaddr */ 2030 NULL, NULL, /* filter, filterarg */ 2031 ALC_RX_RING_SZ, /* maxsize */ 2032 1, /* nsegments */ 2033 ALC_RX_RING_SZ, /* maxsegsize */ 2034 0, /* flags */ 2035 NULL, NULL, /* lockfunc, lockarg */ 2036 &sc->alc_cdata.alc_rx_ring_tag); 2037 if (error != 0) { 2038 device_printf(sc->alc_dev, 2039 "could not create Rx ring DMA tag.\n"); 2040 goto fail; 2041 } 2042 /* Create DMA tag for Rx return descriptor ring. */ 2043 error = bus_dma_tag_create( 2044 sc->alc_cdata.alc_parent_tag, /* parent */ 2045 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2046 BUS_SPACE_MAXADDR, /* lowaddr */ 2047 BUS_SPACE_MAXADDR, /* highaddr */ 2048 NULL, NULL, /* filter, filterarg */ 2049 ALC_RR_RING_SZ, /* maxsize */ 2050 1, /* nsegments */ 2051 ALC_RR_RING_SZ, /* maxsegsize */ 2052 0, /* flags */ 2053 NULL, NULL, /* lockfunc, lockarg */ 2054 &sc->alc_cdata.alc_rr_ring_tag); 2055 if (error != 0) { 2056 device_printf(sc->alc_dev, 2057 "could not create Rx return ring DMA tag.\n"); 2058 goto fail; 2059 } 2060 2061 /* Create DMA tag for coalescing message block. */ 2062 error = bus_dma_tag_create( 2063 sc->alc_cdata.alc_parent_tag, /* parent */ 2064 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2065 BUS_SPACE_MAXADDR, /* lowaddr */ 2066 BUS_SPACE_MAXADDR, /* highaddr */ 2067 NULL, NULL, /* filter, filterarg */ 2068 ALC_CMB_SZ, /* maxsize */ 2069 1, /* nsegments */ 2070 ALC_CMB_SZ, /* maxsegsize */ 2071 0, /* flags */ 2072 NULL, NULL, /* lockfunc, lockarg */ 2073 &sc->alc_cdata.alc_cmb_tag); 2074 if (error != 0) { 2075 device_printf(sc->alc_dev, 2076 "could not create CMB DMA tag.\n"); 2077 goto fail; 2078 } 2079 /* Create DMA tag for status message block. */ 2080 error = bus_dma_tag_create( 2081 sc->alc_cdata.alc_parent_tag, /* parent */ 2082 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2083 BUS_SPACE_MAXADDR, /* lowaddr */ 2084 BUS_SPACE_MAXADDR, /* highaddr */ 2085 NULL, NULL, /* filter, filterarg */ 2086 ALC_SMB_SZ, /* maxsize */ 2087 1, /* nsegments */ 2088 ALC_SMB_SZ, /* maxsegsize */ 2089 0, /* flags */ 2090 NULL, NULL, /* lockfunc, lockarg */ 2091 &sc->alc_cdata.alc_smb_tag); 2092 if (error != 0) { 2093 device_printf(sc->alc_dev, 2094 "could not create SMB DMA tag.\n"); 2095 goto fail; 2096 } 2097 2098 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2099 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2100 (void **)&sc->alc_rdata.alc_tx_ring, 2101 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2102 &sc->alc_cdata.alc_tx_ring_map); 2103 if (error != 0) { 2104 device_printf(sc->alc_dev, 2105 "could not allocate DMA'able memory for Tx ring.\n"); 2106 goto fail; 2107 } 2108 ctx.alc_busaddr = 0; 2109 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2110 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2111 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2112 if (error != 0 || ctx.alc_busaddr == 0) { 2113 device_printf(sc->alc_dev, 2114 "could not load DMA'able memory for Tx ring.\n"); 2115 goto fail; 2116 } 2117 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2118 2119 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2120 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2121 (void **)&sc->alc_rdata.alc_rx_ring, 2122 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2123 &sc->alc_cdata.alc_rx_ring_map); 2124 if (error != 0) { 2125 device_printf(sc->alc_dev, 2126 "could not allocate DMA'able memory for Rx ring.\n"); 2127 goto fail; 2128 } 2129 ctx.alc_busaddr = 0; 2130 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2131 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2132 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2133 if (error != 0 || ctx.alc_busaddr == 0) { 2134 device_printf(sc->alc_dev, 2135 "could not load DMA'able memory for Rx ring.\n"); 2136 goto fail; 2137 } 2138 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2139 2140 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2141 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2142 (void **)&sc->alc_rdata.alc_rr_ring, 2143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2144 &sc->alc_cdata.alc_rr_ring_map); 2145 if (error != 0) { 2146 device_printf(sc->alc_dev, 2147 "could not allocate DMA'able memory for Rx return ring.\n"); 2148 goto fail; 2149 } 2150 ctx.alc_busaddr = 0; 2151 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2152 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2153 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2154 if (error != 0 || ctx.alc_busaddr == 0) { 2155 device_printf(sc->alc_dev, 2156 "could not load DMA'able memory for Tx ring.\n"); 2157 goto fail; 2158 } 2159 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2160 2161 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2162 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2163 (void **)&sc->alc_rdata.alc_cmb, 2164 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2165 &sc->alc_cdata.alc_cmb_map); 2166 if (error != 0) { 2167 device_printf(sc->alc_dev, 2168 "could not allocate DMA'able memory for CMB.\n"); 2169 goto fail; 2170 } 2171 ctx.alc_busaddr = 0; 2172 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2173 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2174 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2175 if (error != 0 || ctx.alc_busaddr == 0) { 2176 device_printf(sc->alc_dev, 2177 "could not load DMA'able memory for CMB.\n"); 2178 goto fail; 2179 } 2180 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2181 2182 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2183 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2184 (void **)&sc->alc_rdata.alc_smb, 2185 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2186 &sc->alc_cdata.alc_smb_map); 2187 if (error != 0) { 2188 device_printf(sc->alc_dev, 2189 "could not allocate DMA'able memory for SMB.\n"); 2190 goto fail; 2191 } 2192 ctx.alc_busaddr = 0; 2193 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2194 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2195 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2196 if (error != 0 || ctx.alc_busaddr == 0) { 2197 device_printf(sc->alc_dev, 2198 "could not load DMA'able memory for CMB.\n"); 2199 goto fail; 2200 } 2201 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2202 2203 /* Make sure we've not crossed 4GB boundary. */ 2204 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2205 (error = alc_check_boundary(sc)) != 0) { 2206 device_printf(sc->alc_dev, "4GB boundary crossed, " 2207 "switching to 32bit DMA addressing mode.\n"); 2208 alc_dma_free(sc); 2209 /* 2210 * Limit max allowable DMA address space to 32bit 2211 * and try again. 2212 */ 2213 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2214 goto again; 2215 } 2216 2217 /* 2218 * Create Tx buffer parent tag. 2219 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2220 * so it needs separate parent DMA tag as parent DMA address 2221 * space could be restricted to be within 32bit address space 2222 * by 4GB boundary crossing. 2223 */ 2224 error = bus_dma_tag_create( 2225 bus_get_dma_tag(sc->alc_dev), /* parent */ 2226 1, 0, /* alignment, boundary */ 2227 lowaddr, /* lowaddr */ 2228 BUS_SPACE_MAXADDR, /* highaddr */ 2229 NULL, NULL, /* filter, filterarg */ 2230 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2231 0, /* nsegments */ 2232 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2233 0, /* flags */ 2234 NULL, NULL, /* lockfunc, lockarg */ 2235 &sc->alc_cdata.alc_buffer_tag); 2236 if (error != 0) { 2237 device_printf(sc->alc_dev, 2238 "could not create parent buffer DMA tag.\n"); 2239 goto fail; 2240 } 2241 2242 /* Create DMA tag for Tx buffers. */ 2243 error = bus_dma_tag_create( 2244 sc->alc_cdata.alc_buffer_tag, /* parent */ 2245 1, 0, /* alignment, boundary */ 2246 BUS_SPACE_MAXADDR, /* lowaddr */ 2247 BUS_SPACE_MAXADDR, /* highaddr */ 2248 NULL, NULL, /* filter, filterarg */ 2249 ALC_TSO_MAXSIZE, /* maxsize */ 2250 ALC_MAXTXSEGS, /* nsegments */ 2251 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2252 0, /* flags */ 2253 NULL, NULL, /* lockfunc, lockarg */ 2254 &sc->alc_cdata.alc_tx_tag); 2255 if (error != 0) { 2256 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2257 goto fail; 2258 } 2259 2260 /* Create DMA tag for Rx buffers. */ 2261 error = bus_dma_tag_create( 2262 sc->alc_cdata.alc_buffer_tag, /* parent */ 2263 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2264 BUS_SPACE_MAXADDR, /* lowaddr */ 2265 BUS_SPACE_MAXADDR, /* highaddr */ 2266 NULL, NULL, /* filter, filterarg */ 2267 MCLBYTES, /* maxsize */ 2268 1, /* nsegments */ 2269 MCLBYTES, /* maxsegsize */ 2270 0, /* flags */ 2271 NULL, NULL, /* lockfunc, lockarg */ 2272 &sc->alc_cdata.alc_rx_tag); 2273 if (error != 0) { 2274 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2275 goto fail; 2276 } 2277 /* Create DMA maps for Tx buffers. */ 2278 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2279 txd = &sc->alc_cdata.alc_txdesc[i]; 2280 txd->tx_m = NULL; 2281 txd->tx_dmamap = NULL; 2282 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2283 &txd->tx_dmamap); 2284 if (error != 0) { 2285 device_printf(sc->alc_dev, 2286 "could not create Tx dmamap.\n"); 2287 goto fail; 2288 } 2289 } 2290 /* Create DMA maps for Rx buffers. */ 2291 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2292 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2293 device_printf(sc->alc_dev, 2294 "could not create spare Rx dmamap.\n"); 2295 goto fail; 2296 } 2297 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2298 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2299 rxd->rx_m = NULL; 2300 rxd->rx_dmamap = NULL; 2301 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2302 &rxd->rx_dmamap); 2303 if (error != 0) { 2304 device_printf(sc->alc_dev, 2305 "could not create Rx dmamap.\n"); 2306 goto fail; 2307 } 2308 } 2309 2310 fail: 2311 return (error); 2312 } 2313 2314 static void 2315 alc_dma_free(struct alc_softc *sc) 2316 { 2317 struct alc_txdesc *txd; 2318 struct alc_rxdesc *rxd; 2319 int i; 2320 2321 /* Tx buffers. */ 2322 if (sc->alc_cdata.alc_tx_tag != NULL) { 2323 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2324 txd = &sc->alc_cdata.alc_txdesc[i]; 2325 if (txd->tx_dmamap != NULL) { 2326 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2327 txd->tx_dmamap); 2328 txd->tx_dmamap = NULL; 2329 } 2330 } 2331 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2332 sc->alc_cdata.alc_tx_tag = NULL; 2333 } 2334 /* Rx buffers */ 2335 if (sc->alc_cdata.alc_rx_tag != NULL) { 2336 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2337 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2338 if (rxd->rx_dmamap != NULL) { 2339 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2340 rxd->rx_dmamap); 2341 rxd->rx_dmamap = NULL; 2342 } 2343 } 2344 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2345 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2346 sc->alc_cdata.alc_rx_sparemap); 2347 sc->alc_cdata.alc_rx_sparemap = NULL; 2348 } 2349 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2350 sc->alc_cdata.alc_rx_tag = NULL; 2351 } 2352 /* Tx descriptor ring. */ 2353 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2354 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2355 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2356 sc->alc_cdata.alc_tx_ring_map); 2357 if (sc->alc_rdata.alc_tx_ring != NULL) 2358 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2359 sc->alc_rdata.alc_tx_ring, 2360 sc->alc_cdata.alc_tx_ring_map); 2361 sc->alc_rdata.alc_tx_ring_paddr = 0; 2362 sc->alc_rdata.alc_tx_ring = NULL; 2363 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2364 sc->alc_cdata.alc_tx_ring_tag = NULL; 2365 } 2366 /* Rx ring. */ 2367 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2368 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2369 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2370 sc->alc_cdata.alc_rx_ring_map); 2371 if (sc->alc_rdata.alc_rx_ring != NULL) 2372 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2373 sc->alc_rdata.alc_rx_ring, 2374 sc->alc_cdata.alc_rx_ring_map); 2375 sc->alc_rdata.alc_rx_ring_paddr = 0; 2376 sc->alc_rdata.alc_rx_ring = NULL; 2377 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2378 sc->alc_cdata.alc_rx_ring_tag = NULL; 2379 } 2380 /* Rx return ring. */ 2381 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2382 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2383 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2384 sc->alc_cdata.alc_rr_ring_map); 2385 if (sc->alc_rdata.alc_rr_ring != NULL) 2386 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2387 sc->alc_rdata.alc_rr_ring, 2388 sc->alc_cdata.alc_rr_ring_map); 2389 sc->alc_rdata.alc_rr_ring_paddr = 0; 2390 sc->alc_rdata.alc_rr_ring = NULL; 2391 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2392 sc->alc_cdata.alc_rr_ring_tag = NULL; 2393 } 2394 /* CMB block */ 2395 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2396 if (sc->alc_rdata.alc_cmb_paddr != 0) 2397 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2398 sc->alc_cdata.alc_cmb_map); 2399 if (sc->alc_rdata.alc_cmb != NULL) 2400 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2401 sc->alc_rdata.alc_cmb, 2402 sc->alc_cdata.alc_cmb_map); 2403 sc->alc_rdata.alc_cmb_paddr = 0; 2404 sc->alc_rdata.alc_cmb = NULL; 2405 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2406 sc->alc_cdata.alc_cmb_tag = NULL; 2407 } 2408 /* SMB block */ 2409 if (sc->alc_cdata.alc_smb_tag != NULL) { 2410 if (sc->alc_rdata.alc_smb_paddr != 0) 2411 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2412 sc->alc_cdata.alc_smb_map); 2413 if (sc->alc_rdata.alc_smb != NULL) 2414 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2415 sc->alc_rdata.alc_smb, 2416 sc->alc_cdata.alc_smb_map); 2417 sc->alc_rdata.alc_smb_paddr = 0; 2418 sc->alc_rdata.alc_smb = NULL; 2419 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2420 sc->alc_cdata.alc_smb_tag = NULL; 2421 } 2422 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2423 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2424 sc->alc_cdata.alc_buffer_tag = NULL; 2425 } 2426 if (sc->alc_cdata.alc_parent_tag != NULL) { 2427 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2428 sc->alc_cdata.alc_parent_tag = NULL; 2429 } 2430 } 2431 2432 static int 2433 alc_shutdown(device_t dev) 2434 { 2435 2436 return (alc_suspend(dev)); 2437 } 2438 2439 /* 2440 * Note, this driver resets the link speed to 10/100Mbps by 2441 * restarting auto-negotiation in suspend/shutdown phase but we 2442 * don't know whether that auto-negotiation would succeed or not 2443 * as driver has no control after powering off/suspend operation. 2444 * If the renegotiation fail WOL may not work. Running at 1Gbps 2445 * will draw more power than 375mA at 3.3V which is specified in 2446 * PCI specification and that would result in complete 2447 * shutdowning power to ethernet controller. 2448 * 2449 * TODO 2450 * Save current negotiated media speed/duplex/flow-control to 2451 * softc and restore the same link again after resuming. PHY 2452 * handling such as power down/resetting to 100Mbps may be better 2453 * handled in suspend method in phy driver. 2454 */ 2455 static void 2456 alc_setlinkspeed(struct alc_softc *sc) 2457 { 2458 struct mii_data *mii; 2459 int aneg, i; 2460 2461 mii = device_get_softc(sc->alc_miibus); 2462 mii_pollstat(mii); 2463 aneg = 0; 2464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2465 (IFM_ACTIVE | IFM_AVALID)) { 2466 switch IFM_SUBTYPE(mii->mii_media_active) { 2467 case IFM_10_T: 2468 case IFM_100_TX: 2469 return; 2470 case IFM_1000_T: 2471 aneg++; 2472 break; 2473 default: 2474 break; 2475 } 2476 } 2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2478 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2479 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2480 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2481 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2482 DELAY(1000); 2483 if (aneg != 0) { 2484 /* 2485 * Poll link state until alc(4) get a 10/100Mbps link. 2486 */ 2487 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2488 mii_pollstat(mii); 2489 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2490 == (IFM_ACTIVE | IFM_AVALID)) { 2491 switch (IFM_SUBTYPE( 2492 mii->mii_media_active)) { 2493 case IFM_10_T: 2494 case IFM_100_TX: 2495 alc_mac_config(sc); 2496 return; 2497 default: 2498 break; 2499 } 2500 } 2501 ALC_UNLOCK(sc); 2502 pause("alclnk", hz); 2503 ALC_LOCK(sc); 2504 } 2505 if (i == MII_ANEGTICKS_GIGE) 2506 device_printf(sc->alc_dev, 2507 "establishing a link failed, WOL may not work!"); 2508 } 2509 /* 2510 * No link, force MAC to have 100Mbps, full-duplex link. 2511 * This is the last resort and may/may not work. 2512 */ 2513 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2514 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2515 alc_mac_config(sc); 2516 } 2517 2518 static void 2519 alc_setwol(struct alc_softc *sc) 2520 { 2521 2522 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2523 alc_setwol_816x(sc); 2524 else 2525 alc_setwol_813x(sc); 2526 } 2527 2528 static void 2529 alc_setwol_813x(struct alc_softc *sc) 2530 { 2531 if_t ifp; 2532 uint32_t reg, pmcs; 2533 uint16_t pmstat; 2534 2535 ALC_LOCK_ASSERT(sc); 2536 2537 alc_disable_l0s_l1(sc); 2538 ifp = sc->alc_ifp; 2539 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2540 /* Disable WOL. */ 2541 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2542 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2543 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2544 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2545 /* Force PHY power down. */ 2546 alc_phy_down(sc); 2547 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2548 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2549 return; 2550 } 2551 2552 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2553 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2554 alc_setlinkspeed(sc); 2555 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2556 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2557 } 2558 2559 pmcs = 0; 2560 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2561 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2562 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2563 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2564 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2565 MAC_CFG_BCAST); 2566 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2567 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2568 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2569 reg |= MAC_CFG_RX_ENB; 2570 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2571 2572 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2573 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2574 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2575 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2576 /* WOL disabled, PHY power down. */ 2577 alc_phy_down(sc); 2578 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2579 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2580 } 2581 /* Request PME. */ 2582 pmstat = pci_read_config(sc->alc_dev, 2583 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2584 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2585 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2586 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2587 pci_write_config(sc->alc_dev, 2588 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2589 } 2590 2591 static void 2592 alc_setwol_816x(struct alc_softc *sc) 2593 { 2594 if_t ifp; 2595 uint32_t gphy, mac, master, pmcs, reg; 2596 uint16_t pmstat; 2597 2598 ALC_LOCK_ASSERT(sc); 2599 2600 ifp = sc->alc_ifp; 2601 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2602 master &= ~MASTER_CLK_SEL_DIS; 2603 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2604 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2605 GPHY_CFG_PHY_PLL_ON); 2606 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2607 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2608 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2609 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2610 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2611 } else { 2612 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2613 gphy |= GPHY_CFG_EXT_RESET; 2614 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2615 alc_setlinkspeed(sc); 2616 } 2617 pmcs = 0; 2618 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2619 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2620 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2621 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2622 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2623 MAC_CFG_BCAST); 2624 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2625 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2626 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2627 mac |= MAC_CFG_RX_ENB; 2628 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2629 ANEG_S3DIG10_SL); 2630 } 2631 2632 /* Enable OSC. */ 2633 reg = CSR_READ_4(sc, ALC_MISC); 2634 reg &= ~MISC_INTNLOSC_OPEN; 2635 CSR_WRITE_4(sc, ALC_MISC, reg); 2636 reg |= MISC_INTNLOSC_OPEN; 2637 CSR_WRITE_4(sc, ALC_MISC, reg); 2638 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2639 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2640 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2641 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2642 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2643 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2644 2645 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2646 /* Request PME. */ 2647 pmstat = pci_read_config(sc->alc_dev, 2648 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2649 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2650 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2651 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2652 pci_write_config(sc->alc_dev, 2653 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2654 } 2655 } 2656 2657 static int 2658 alc_suspend(device_t dev) 2659 { 2660 struct alc_softc *sc; 2661 2662 sc = device_get_softc(dev); 2663 2664 ALC_LOCK(sc); 2665 alc_stop(sc); 2666 alc_setwol(sc); 2667 ALC_UNLOCK(sc); 2668 2669 return (0); 2670 } 2671 2672 static int 2673 alc_resume(device_t dev) 2674 { 2675 struct alc_softc *sc; 2676 if_t ifp; 2677 uint16_t pmstat; 2678 2679 sc = device_get_softc(dev); 2680 2681 ALC_LOCK(sc); 2682 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2683 /* Disable PME and clear PME status. */ 2684 pmstat = pci_read_config(sc->alc_dev, 2685 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2686 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2687 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2688 pci_write_config(sc->alc_dev, 2689 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2690 } 2691 } 2692 /* Reset PHY. */ 2693 alc_phy_reset(sc); 2694 ifp = sc->alc_ifp; 2695 if ((if_getflags(ifp) & IFF_UP) != 0) { 2696 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2697 alc_init_locked(sc); 2698 } 2699 ALC_UNLOCK(sc); 2700 2701 return (0); 2702 } 2703 2704 static int 2705 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2706 { 2707 struct alc_txdesc *txd, *txd_last; 2708 struct tx_desc *desc; 2709 struct mbuf *m; 2710 struct ip *ip; 2711 struct tcphdr *tcp; 2712 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2713 bus_dmamap_t map; 2714 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2715 int error, idx, nsegs, prod; 2716 2717 ALC_LOCK_ASSERT(sc); 2718 2719 M_ASSERTPKTHDR((*m_head)); 2720 2721 m = *m_head; 2722 ip = NULL; 2723 tcp = NULL; 2724 ip_off = poff = 0; 2725 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2726 /* 2727 * AR81[3567]x requires offset of TCP/UDP header in its 2728 * Tx descriptor to perform Tx checksum offloading. TSO 2729 * also requires TCP header offset and modification of 2730 * IP/TCP header. This kind of operation takes many CPU 2731 * cycles on FreeBSD so fast host CPU is required to get 2732 * smooth TSO performance. 2733 */ 2734 struct ether_header *eh; 2735 2736 if (M_WRITABLE(m) == 0) { 2737 /* Get a writable copy. */ 2738 m = m_dup(*m_head, M_NOWAIT); 2739 /* Release original mbufs. */ 2740 m_freem(*m_head); 2741 if (m == NULL) { 2742 *m_head = NULL; 2743 return (ENOBUFS); 2744 } 2745 *m_head = m; 2746 } 2747 2748 ip_off = sizeof(struct ether_header); 2749 m = m_pullup(m, ip_off); 2750 if (m == NULL) { 2751 *m_head = NULL; 2752 return (ENOBUFS); 2753 } 2754 eh = mtod(m, struct ether_header *); 2755 /* 2756 * Check if hardware VLAN insertion is off. 2757 * Additional check for LLC/SNAP frame? 2758 */ 2759 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2760 ip_off = sizeof(struct ether_vlan_header); 2761 m = m_pullup(m, ip_off); 2762 if (m == NULL) { 2763 *m_head = NULL; 2764 return (ENOBUFS); 2765 } 2766 } 2767 m = m_pullup(m, ip_off + sizeof(struct ip)); 2768 if (m == NULL) { 2769 *m_head = NULL; 2770 return (ENOBUFS); 2771 } 2772 ip = (struct ip *)(mtod(m, char *) + ip_off); 2773 poff = ip_off + (ip->ip_hl << 2); 2774 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2775 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2776 if (m == NULL) { 2777 *m_head = NULL; 2778 return (ENOBUFS); 2779 } 2780 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2781 m = m_pullup(m, poff + (tcp->th_off << 2)); 2782 if (m == NULL) { 2783 *m_head = NULL; 2784 return (ENOBUFS); 2785 } 2786 /* 2787 * Due to strict adherence of Microsoft NDIS 2788 * Large Send specification, hardware expects 2789 * a pseudo TCP checksum inserted by upper 2790 * stack. Unfortunately the pseudo TCP 2791 * checksum that NDIS refers to does not include 2792 * TCP payload length so driver should recompute 2793 * the pseudo checksum here. Hopefully this 2794 * wouldn't be much burden on modern CPUs. 2795 * 2796 * Reset IP checksum and recompute TCP pseudo 2797 * checksum as NDIS specification said. 2798 */ 2799 ip = (struct ip *)(mtod(m, char *) + ip_off); 2800 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2801 ip->ip_sum = 0; 2802 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2803 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2804 } 2805 *m_head = m; 2806 } 2807 2808 prod = sc->alc_cdata.alc_tx_prod; 2809 txd = &sc->alc_cdata.alc_txdesc[prod]; 2810 txd_last = txd; 2811 map = txd->tx_dmamap; 2812 2813 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2814 *m_head, txsegs, &nsegs, 0); 2815 if (error == EFBIG) { 2816 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2817 if (m == NULL) { 2818 m_freem(*m_head); 2819 *m_head = NULL; 2820 return (ENOMEM); 2821 } 2822 *m_head = m; 2823 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2824 *m_head, txsegs, &nsegs, 0); 2825 if (error != 0) { 2826 m_freem(*m_head); 2827 *m_head = NULL; 2828 return (error); 2829 } 2830 } else if (error != 0) 2831 return (error); 2832 if (nsegs == 0) { 2833 m_freem(*m_head); 2834 *m_head = NULL; 2835 return (EIO); 2836 } 2837 2838 /* Check descriptor overrun. */ 2839 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2840 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2841 return (ENOBUFS); 2842 } 2843 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2844 2845 m = *m_head; 2846 cflags = TD_ETHERNET; 2847 vtag = 0; 2848 desc = NULL; 2849 idx = 0; 2850 /* Configure VLAN hardware tag insertion. */ 2851 if ((m->m_flags & M_VLANTAG) != 0) { 2852 vtag = htons(m->m_pkthdr.ether_vtag); 2853 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2854 cflags |= TD_INS_VLAN_TAG; 2855 } 2856 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2857 /* Request TSO and set MSS. */ 2858 cflags |= TD_TSO | TD_TSO_DESCV1; 2859 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2860 TD_MSS_MASK; 2861 /* Set TCP header offset. */ 2862 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2863 TD_TCPHDR_OFFSET_MASK; 2864 /* 2865 * AR81[3567]x requires the first buffer should 2866 * only hold IP/TCP header data. Payload should 2867 * be handled in other descriptors. 2868 */ 2869 hdrlen = poff + (tcp->th_off << 2); 2870 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2871 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2872 desc->flags = htole32(cflags); 2873 desc->addr = htole64(txsegs[0].ds_addr); 2874 sc->alc_cdata.alc_tx_cnt++; 2875 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2876 if (m->m_len - hdrlen > 0) { 2877 /* Handle remaining payload of the first fragment. */ 2878 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2879 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2880 vtag)); 2881 desc->flags = htole32(cflags); 2882 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2883 sc->alc_cdata.alc_tx_cnt++; 2884 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2885 } 2886 /* Handle remaining fragments. */ 2887 idx = 1; 2888 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2889 /* Configure Tx checksum offload. */ 2890 #ifdef ALC_USE_CUSTOM_CSUM 2891 cflags |= TD_CUSTOM_CSUM; 2892 /* Set checksum start offset. */ 2893 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2894 TD_PLOAD_OFFSET_MASK; 2895 /* Set checksum insertion position of TCP/UDP. */ 2896 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2897 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2898 #else 2899 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2900 cflags |= TD_IPCSUM; 2901 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2902 cflags |= TD_TCPCSUM; 2903 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2904 cflags |= TD_UDPCSUM; 2905 /* Set TCP/UDP header offset. */ 2906 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2907 TD_L4HDR_OFFSET_MASK; 2908 #endif 2909 } 2910 for (; idx < nsegs; idx++) { 2911 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2912 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2913 desc->flags = htole32(cflags); 2914 desc->addr = htole64(txsegs[idx].ds_addr); 2915 sc->alc_cdata.alc_tx_cnt++; 2916 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2917 } 2918 /* Update producer index. */ 2919 sc->alc_cdata.alc_tx_prod = prod; 2920 2921 /* Finally set EOP on the last descriptor. */ 2922 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2923 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2924 desc->flags |= htole32(TD_EOP); 2925 2926 /* Swap dmamap of the first and the last. */ 2927 txd = &sc->alc_cdata.alc_txdesc[prod]; 2928 map = txd_last->tx_dmamap; 2929 txd_last->tx_dmamap = txd->tx_dmamap; 2930 txd->tx_dmamap = map; 2931 txd->tx_m = m; 2932 2933 return (0); 2934 } 2935 2936 static void 2937 alc_start(if_t ifp) 2938 { 2939 struct alc_softc *sc; 2940 2941 sc = if_getsoftc(ifp); 2942 ALC_LOCK(sc); 2943 alc_start_locked(ifp); 2944 ALC_UNLOCK(sc); 2945 } 2946 2947 static void 2948 alc_start_locked(if_t ifp) 2949 { 2950 struct alc_softc *sc; 2951 struct mbuf *m_head; 2952 int enq; 2953 2954 sc = if_getsoftc(ifp); 2955 2956 ALC_LOCK_ASSERT(sc); 2957 2958 /* Reclaim transmitted frames. */ 2959 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2960 alc_txeof(sc); 2961 2962 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2963 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2964 return; 2965 2966 for (enq = 0; !if_sendq_empty(ifp); ) { 2967 m_head = if_dequeue(ifp); 2968 if (m_head == NULL) 2969 break; 2970 /* 2971 * Pack the data into the transmit ring. If we 2972 * don't have room, set the OACTIVE flag and wait 2973 * for the NIC to drain the ring. 2974 */ 2975 if (alc_encap(sc, &m_head)) { 2976 if (m_head == NULL) 2977 break; 2978 if_sendq_prepend(ifp, m_head); 2979 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2980 break; 2981 } 2982 2983 enq++; 2984 /* 2985 * If there's a BPF listener, bounce a copy of this frame 2986 * to him. 2987 */ 2988 ETHER_BPF_MTAP(ifp, m_head); 2989 } 2990 2991 if (enq > 0) 2992 alc_start_tx(sc); 2993 } 2994 2995 static void 2996 alc_start_tx(struct alc_softc *sc) 2997 { 2998 2999 /* Sync descriptors. */ 3000 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3001 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3002 /* Kick. Assume we're using normal Tx priority queue. */ 3003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3004 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3005 (uint16_t)sc->alc_cdata.alc_tx_prod); 3006 else 3007 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3008 (sc->alc_cdata.alc_tx_prod << 3009 MBOX_TD_PROD_LO_IDX_SHIFT) & 3010 MBOX_TD_PROD_LO_IDX_MASK); 3011 /* Set a timeout in case the chip goes out to lunch. */ 3012 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3013 } 3014 3015 static void 3016 alc_watchdog(struct alc_softc *sc) 3017 { 3018 if_t ifp; 3019 3020 ALC_LOCK_ASSERT(sc); 3021 3022 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3023 return; 3024 3025 ifp = sc->alc_ifp; 3026 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3027 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3028 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3029 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3030 alc_init_locked(sc); 3031 return; 3032 } 3033 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3034 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3035 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3036 alc_init_locked(sc); 3037 if (!if_sendq_empty(ifp)) 3038 alc_start_locked(ifp); 3039 } 3040 3041 static int 3042 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3043 { 3044 struct alc_softc *sc; 3045 struct ifreq *ifr; 3046 struct mii_data *mii; 3047 int error, mask; 3048 3049 sc = if_getsoftc(ifp); 3050 ifr = (struct ifreq *)data; 3051 error = 0; 3052 switch (cmd) { 3053 case SIOCSIFMTU: 3054 if (ifr->ifr_mtu < ETHERMIN || 3055 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3056 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3057 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3058 ifr->ifr_mtu > ETHERMTU)) 3059 error = EINVAL; 3060 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3061 ALC_LOCK(sc); 3062 if_setmtu(ifp, ifr->ifr_mtu); 3063 /* AR81[3567]x has 13 bits MSS field. */ 3064 if (if_getmtu(ifp) > ALC_TSO_MTU && 3065 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3066 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3067 if_sethwassistbits(ifp, 0, CSUM_TSO); 3068 VLAN_CAPABILITIES(ifp); 3069 } 3070 ALC_UNLOCK(sc); 3071 } 3072 break; 3073 case SIOCSIFFLAGS: 3074 ALC_LOCK(sc); 3075 if ((if_getflags(ifp) & IFF_UP) != 0) { 3076 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3077 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3078 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3079 alc_rxfilter(sc); 3080 else 3081 alc_init_locked(sc); 3082 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3083 alc_stop(sc); 3084 sc->alc_if_flags = if_getflags(ifp); 3085 ALC_UNLOCK(sc); 3086 break; 3087 case SIOCADDMULTI: 3088 case SIOCDELMULTI: 3089 ALC_LOCK(sc); 3090 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3091 alc_rxfilter(sc); 3092 ALC_UNLOCK(sc); 3093 break; 3094 case SIOCSIFMEDIA: 3095 case SIOCGIFMEDIA: 3096 mii = device_get_softc(sc->alc_miibus); 3097 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3098 break; 3099 case SIOCSIFCAP: 3100 ALC_LOCK(sc); 3101 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3102 if ((mask & IFCAP_TXCSUM) != 0 && 3103 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3104 if_togglecapenable(ifp, IFCAP_TXCSUM); 3105 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3106 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3107 else 3108 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3109 } 3110 if ((mask & IFCAP_TSO4) != 0 && 3111 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3112 if_togglecapenable(ifp, IFCAP_TSO4); 3113 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3114 /* AR81[3567]x has 13 bits MSS field. */ 3115 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3116 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3117 if_sethwassistbits(ifp, 0, CSUM_TSO); 3118 } else 3119 if_sethwassistbits(ifp, CSUM_TSO, 0); 3120 } else 3121 if_sethwassistbits(ifp, 0, CSUM_TSO); 3122 } 3123 if ((mask & IFCAP_WOL_MCAST) != 0 && 3124 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3125 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3126 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3127 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3128 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3129 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3130 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3131 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3132 alc_rxvlan(sc); 3133 } 3134 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3135 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3136 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3137 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3138 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3139 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3140 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3141 if_setcapenablebit(ifp, 0, 3142 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3143 ALC_UNLOCK(sc); 3144 VLAN_CAPABILITIES(ifp); 3145 break; 3146 default: 3147 error = ether_ioctl(ifp, cmd, data); 3148 break; 3149 } 3150 3151 return (error); 3152 } 3153 3154 static void 3155 alc_mac_config(struct alc_softc *sc) 3156 { 3157 struct mii_data *mii; 3158 uint32_t reg; 3159 3160 ALC_LOCK_ASSERT(sc); 3161 3162 mii = device_get_softc(sc->alc_miibus); 3163 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3164 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3165 MAC_CFG_SPEED_MASK); 3166 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3167 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3168 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3169 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3170 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3171 /* Reprogram MAC with resolved speed/duplex. */ 3172 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3173 case IFM_10_T: 3174 case IFM_100_TX: 3175 reg |= MAC_CFG_SPEED_10_100; 3176 break; 3177 case IFM_1000_T: 3178 reg |= MAC_CFG_SPEED_1000; 3179 break; 3180 } 3181 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3182 reg |= MAC_CFG_FULL_DUPLEX; 3183 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3184 reg |= MAC_CFG_TX_FC; 3185 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3186 reg |= MAC_CFG_RX_FC; 3187 } 3188 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3189 } 3190 3191 static void 3192 alc_stats_clear(struct alc_softc *sc) 3193 { 3194 struct smb sb, *smb; 3195 uint32_t *reg; 3196 int i; 3197 3198 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3199 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3200 sc->alc_cdata.alc_smb_map, 3201 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3202 smb = sc->alc_rdata.alc_smb; 3203 /* Update done, clear. */ 3204 smb->updated = 0; 3205 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3206 sc->alc_cdata.alc_smb_map, 3207 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3208 } else { 3209 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3210 reg++) { 3211 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3212 i += sizeof(uint32_t); 3213 } 3214 /* Read Tx statistics. */ 3215 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3216 reg++) { 3217 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3218 i += sizeof(uint32_t); 3219 } 3220 } 3221 } 3222 3223 static void 3224 alc_stats_update(struct alc_softc *sc) 3225 { 3226 struct alc_hw_stats *stat; 3227 struct smb sb, *smb; 3228 if_t ifp; 3229 uint32_t *reg; 3230 int i; 3231 3232 ALC_LOCK_ASSERT(sc); 3233 3234 ifp = sc->alc_ifp; 3235 stat = &sc->alc_stats; 3236 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3237 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3238 sc->alc_cdata.alc_smb_map, 3239 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3240 smb = sc->alc_rdata.alc_smb; 3241 if (smb->updated == 0) 3242 return; 3243 } else { 3244 smb = &sb; 3245 /* Read Rx statistics. */ 3246 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3247 reg++) { 3248 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3249 i += sizeof(uint32_t); 3250 } 3251 /* Read Tx statistics. */ 3252 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3253 reg++) { 3254 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3255 i += sizeof(uint32_t); 3256 } 3257 } 3258 3259 /* Rx stats. */ 3260 stat->rx_frames += smb->rx_frames; 3261 stat->rx_bcast_frames += smb->rx_bcast_frames; 3262 stat->rx_mcast_frames += smb->rx_mcast_frames; 3263 stat->rx_pause_frames += smb->rx_pause_frames; 3264 stat->rx_control_frames += smb->rx_control_frames; 3265 stat->rx_crcerrs += smb->rx_crcerrs; 3266 stat->rx_lenerrs += smb->rx_lenerrs; 3267 stat->rx_bytes += smb->rx_bytes; 3268 stat->rx_runts += smb->rx_runts; 3269 stat->rx_fragments += smb->rx_fragments; 3270 stat->rx_pkts_64 += smb->rx_pkts_64; 3271 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3272 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3273 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3274 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3275 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3276 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3277 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3278 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3279 stat->rx_rrs_errs += smb->rx_rrs_errs; 3280 stat->rx_alignerrs += smb->rx_alignerrs; 3281 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3282 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3283 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3284 3285 /* Tx stats. */ 3286 stat->tx_frames += smb->tx_frames; 3287 stat->tx_bcast_frames += smb->tx_bcast_frames; 3288 stat->tx_mcast_frames += smb->tx_mcast_frames; 3289 stat->tx_pause_frames += smb->tx_pause_frames; 3290 stat->tx_excess_defer += smb->tx_excess_defer; 3291 stat->tx_control_frames += smb->tx_control_frames; 3292 stat->tx_deferred += smb->tx_deferred; 3293 stat->tx_bytes += smb->tx_bytes; 3294 stat->tx_pkts_64 += smb->tx_pkts_64; 3295 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3296 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3297 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3298 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3299 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3300 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3301 stat->tx_single_colls += smb->tx_single_colls; 3302 stat->tx_multi_colls += smb->tx_multi_colls; 3303 stat->tx_late_colls += smb->tx_late_colls; 3304 stat->tx_excess_colls += smb->tx_excess_colls; 3305 stat->tx_underrun += smb->tx_underrun; 3306 stat->tx_desc_underrun += smb->tx_desc_underrun; 3307 stat->tx_lenerrs += smb->tx_lenerrs; 3308 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3309 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3310 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3311 3312 /* Update counters in ifnet. */ 3313 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3314 3315 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3316 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3317 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3318 3319 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3320 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3321 3322 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3323 3324 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3325 smb->rx_crcerrs + smb->rx_lenerrs + 3326 smb->rx_runts + smb->rx_pkts_truncated + 3327 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3328 smb->rx_alignerrs); 3329 3330 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3331 /* Update done, clear. */ 3332 smb->updated = 0; 3333 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3334 sc->alc_cdata.alc_smb_map, 3335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3336 } 3337 } 3338 3339 static int 3340 alc_intr(void *arg) 3341 { 3342 struct alc_softc *sc; 3343 uint32_t status; 3344 3345 sc = (struct alc_softc *)arg; 3346 3347 if (sc->alc_flags & ALC_FLAG_MT) { 3348 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3349 return (FILTER_HANDLED); 3350 } 3351 3352 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3353 if ((status & ALC_INTRS) == 0) 3354 return (FILTER_STRAY); 3355 /* Disable interrupts. */ 3356 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3357 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3358 3359 return (FILTER_HANDLED); 3360 } 3361 3362 static void 3363 alc_int_task(void *arg, int pending) 3364 { 3365 struct alc_softc *sc; 3366 if_t ifp; 3367 uint32_t status; 3368 int more; 3369 3370 sc = (struct alc_softc *)arg; 3371 ifp = sc->alc_ifp; 3372 3373 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3374 ALC_LOCK(sc); 3375 if (sc->alc_morework != 0) { 3376 sc->alc_morework = 0; 3377 status |= INTR_RX_PKT; 3378 } 3379 if ((status & ALC_INTRS) == 0) 3380 goto done; 3381 3382 /* Acknowledge interrupts but still disable interrupts. */ 3383 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3384 3385 more = 0; 3386 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3387 if ((status & INTR_RX_PKT) != 0) { 3388 more = alc_rxintr(sc, sc->alc_process_limit); 3389 if (more == EAGAIN) 3390 sc->alc_morework = 1; 3391 else if (more == EIO) { 3392 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3393 alc_init_locked(sc); 3394 ALC_UNLOCK(sc); 3395 return; 3396 } 3397 } 3398 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3399 INTR_TXQ_TO_RST)) != 0) { 3400 if ((status & INTR_DMA_RD_TO_RST) != 0) 3401 device_printf(sc->alc_dev, 3402 "DMA read error! -- resetting\n"); 3403 if ((status & INTR_DMA_WR_TO_RST) != 0) 3404 device_printf(sc->alc_dev, 3405 "DMA write error! -- resetting\n"); 3406 if ((status & INTR_TXQ_TO_RST) != 0) 3407 device_printf(sc->alc_dev, 3408 "TxQ reset! -- resetting\n"); 3409 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3410 alc_init_locked(sc); 3411 ALC_UNLOCK(sc); 3412 return; 3413 } 3414 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3415 !if_sendq_empty(ifp)) 3416 alc_start_locked(ifp); 3417 } 3418 3419 if (more == EAGAIN || 3420 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3421 ALC_UNLOCK(sc); 3422 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3423 return; 3424 } 3425 3426 done: 3427 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3428 /* Re-enable interrupts if we're running. */ 3429 if (sc->alc_flags & ALC_FLAG_MT) 3430 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3431 else 3432 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3433 } 3434 ALC_UNLOCK(sc); 3435 } 3436 3437 static void 3438 alc_txeof(struct alc_softc *sc) 3439 { 3440 if_t ifp; 3441 struct alc_txdesc *txd; 3442 uint32_t cons, prod; 3443 3444 ALC_LOCK_ASSERT(sc); 3445 3446 ifp = sc->alc_ifp; 3447 3448 if (sc->alc_cdata.alc_tx_cnt == 0) 3449 return; 3450 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3451 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3452 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3453 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3454 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3455 prod = sc->alc_rdata.alc_cmb->cons; 3456 } else { 3457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3458 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3459 else { 3460 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3461 /* Assume we're using normal Tx priority queue. */ 3462 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3463 MBOX_TD_CONS_LO_IDX_SHIFT; 3464 } 3465 } 3466 cons = sc->alc_cdata.alc_tx_cons; 3467 /* 3468 * Go through our Tx list and free mbufs for those 3469 * frames which have been transmitted. 3470 */ 3471 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3472 if (sc->alc_cdata.alc_tx_cnt <= 0) 3473 break; 3474 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3475 sc->alc_cdata.alc_tx_cnt--; 3476 txd = &sc->alc_cdata.alc_txdesc[cons]; 3477 if (txd->tx_m != NULL) { 3478 /* Reclaim transmitted mbufs. */ 3479 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3480 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3481 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3482 txd->tx_dmamap); 3483 m_freem(txd->tx_m); 3484 txd->tx_m = NULL; 3485 } 3486 } 3487 3488 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3489 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3490 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3491 sc->alc_cdata.alc_tx_cons = cons; 3492 /* 3493 * Unarm watchdog timer only when there is no pending 3494 * frames in Tx queue. 3495 */ 3496 if (sc->alc_cdata.alc_tx_cnt == 0) 3497 sc->alc_watchdog_timer = 0; 3498 } 3499 3500 static int 3501 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3502 { 3503 struct mbuf *m; 3504 bus_dma_segment_t segs[1]; 3505 bus_dmamap_t map; 3506 int nsegs; 3507 3508 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3509 if (m == NULL) 3510 return (ENOBUFS); 3511 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3512 #ifndef __NO_STRICT_ALIGNMENT 3513 m_adj(m, sizeof(uint64_t)); 3514 #endif 3515 3516 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3517 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3518 m_freem(m); 3519 return (ENOBUFS); 3520 } 3521 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3522 3523 if (rxd->rx_m != NULL) { 3524 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3525 BUS_DMASYNC_POSTREAD); 3526 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3527 } 3528 map = rxd->rx_dmamap; 3529 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3530 sc->alc_cdata.alc_rx_sparemap = map; 3531 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3532 BUS_DMASYNC_PREREAD); 3533 rxd->rx_m = m; 3534 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3535 return (0); 3536 } 3537 3538 static int 3539 alc_rxintr(struct alc_softc *sc, int count) 3540 { 3541 if_t ifp; 3542 struct rx_rdesc *rrd; 3543 uint32_t nsegs, status; 3544 int rr_cons, prog; 3545 3546 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3547 sc->alc_cdata.alc_rr_ring_map, 3548 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3549 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3550 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3551 rr_cons = sc->alc_cdata.alc_rr_cons; 3552 ifp = sc->alc_ifp; 3553 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3554 if (count-- <= 0) 3555 break; 3556 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3557 status = le32toh(rrd->status); 3558 if ((status & RRD_VALID) == 0) 3559 break; 3560 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3561 if (nsegs == 0) { 3562 /* This should not happen! */ 3563 device_printf(sc->alc_dev, 3564 "unexpected segment count -- resetting\n"); 3565 return (EIO); 3566 } 3567 alc_rxeof(sc, rrd); 3568 /* Clear Rx return status. */ 3569 rrd->status = 0; 3570 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3571 sc->alc_cdata.alc_rx_cons += nsegs; 3572 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3573 prog += nsegs; 3574 } 3575 3576 if (prog > 0) { 3577 /* Update the consumer index. */ 3578 sc->alc_cdata.alc_rr_cons = rr_cons; 3579 /* Sync Rx return descriptors. */ 3580 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3581 sc->alc_cdata.alc_rr_ring_map, 3582 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3583 /* 3584 * Sync updated Rx descriptors such that controller see 3585 * modified buffer addresses. 3586 */ 3587 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3588 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3589 /* 3590 * Let controller know availability of new Rx buffers. 3591 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3592 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3593 * only when Rx buffer pre-fetching is required. In 3594 * addition we already set ALC_RX_RD_FREE_THRESH to 3595 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3596 * it still seems that pre-fetching needs more 3597 * experimentation. 3598 */ 3599 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3600 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3601 (uint16_t)sc->alc_cdata.alc_rx_cons); 3602 else 3603 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3604 sc->alc_cdata.alc_rx_cons); 3605 } 3606 3607 return (count > 0 ? 0 : EAGAIN); 3608 } 3609 3610 #ifndef __NO_STRICT_ALIGNMENT 3611 static struct mbuf * 3612 alc_fixup_rx(if_t ifp, struct mbuf *m) 3613 { 3614 struct mbuf *n; 3615 int i; 3616 uint16_t *src, *dst; 3617 3618 src = mtod(m, uint16_t *); 3619 dst = src - 3; 3620 3621 if (m->m_next == NULL) { 3622 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3623 *dst++ = *src++; 3624 m->m_data -= 6; 3625 return (m); 3626 } 3627 /* 3628 * Append a new mbuf to received mbuf chain and copy ethernet 3629 * header from the mbuf chain. This can save lots of CPU 3630 * cycles for jumbo frame. 3631 */ 3632 MGETHDR(n, M_NOWAIT, MT_DATA); 3633 if (n == NULL) { 3634 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3635 m_freem(m); 3636 return (NULL); 3637 } 3638 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3639 m->m_data += ETHER_HDR_LEN; 3640 m->m_len -= ETHER_HDR_LEN; 3641 n->m_len = ETHER_HDR_LEN; 3642 M_MOVE_PKTHDR(n, m); 3643 n->m_next = m; 3644 return (n); 3645 } 3646 #endif 3647 3648 /* Receive a frame. */ 3649 static void 3650 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3651 { 3652 struct alc_rxdesc *rxd; 3653 if_t ifp; 3654 struct mbuf *mp, *m; 3655 uint32_t rdinfo, status, vtag; 3656 int count, nsegs, rx_cons; 3657 3658 ifp = sc->alc_ifp; 3659 status = le32toh(rrd->status); 3660 rdinfo = le32toh(rrd->rdinfo); 3661 rx_cons = RRD_RD_IDX(rdinfo); 3662 nsegs = RRD_RD_CNT(rdinfo); 3663 3664 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3665 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3666 /* 3667 * We want to pass the following frames to upper 3668 * layer regardless of error status of Rx return 3669 * ring. 3670 * 3671 * o IP/TCP/UDP checksum is bad. 3672 * o frame length and protocol specific length 3673 * does not match. 3674 * 3675 * Force network stack compute checksum for 3676 * errored frames. 3677 */ 3678 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3679 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3680 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3681 return; 3682 } 3683 3684 for (count = 0; count < nsegs; count++, 3685 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3686 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3687 mp = rxd->rx_m; 3688 /* Add a new receive buffer to the ring. */ 3689 if (alc_newbuf(sc, rxd) != 0) { 3690 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3691 /* Reuse Rx buffers. */ 3692 if (sc->alc_cdata.alc_rxhead != NULL) 3693 m_freem(sc->alc_cdata.alc_rxhead); 3694 break; 3695 } 3696 3697 /* 3698 * Assume we've received a full sized frame. 3699 * Actual size is fixed when we encounter the end of 3700 * multi-segmented frame. 3701 */ 3702 mp->m_len = sc->alc_buf_size; 3703 3704 /* Chain received mbufs. */ 3705 if (sc->alc_cdata.alc_rxhead == NULL) { 3706 sc->alc_cdata.alc_rxhead = mp; 3707 sc->alc_cdata.alc_rxtail = mp; 3708 } else { 3709 mp->m_flags &= ~M_PKTHDR; 3710 sc->alc_cdata.alc_rxprev_tail = 3711 sc->alc_cdata.alc_rxtail; 3712 sc->alc_cdata.alc_rxtail->m_next = mp; 3713 sc->alc_cdata.alc_rxtail = mp; 3714 } 3715 3716 if (count == nsegs - 1) { 3717 /* Last desc. for this frame. */ 3718 m = sc->alc_cdata.alc_rxhead; 3719 m->m_flags |= M_PKTHDR; 3720 /* 3721 * It seems that L1C/L2C controller has no way 3722 * to tell hardware to strip CRC bytes. 3723 */ 3724 m->m_pkthdr.len = 3725 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3726 if (nsegs > 1) { 3727 /* Set last mbuf size. */ 3728 mp->m_len = sc->alc_cdata.alc_rxlen - 3729 (nsegs - 1) * sc->alc_buf_size; 3730 /* Remove the CRC bytes in chained mbufs. */ 3731 if (mp->m_len <= ETHER_CRC_LEN) { 3732 sc->alc_cdata.alc_rxtail = 3733 sc->alc_cdata.alc_rxprev_tail; 3734 sc->alc_cdata.alc_rxtail->m_len -= 3735 (ETHER_CRC_LEN - mp->m_len); 3736 sc->alc_cdata.alc_rxtail->m_next = NULL; 3737 m_freem(mp); 3738 } else { 3739 mp->m_len -= ETHER_CRC_LEN; 3740 } 3741 } else 3742 m->m_len = m->m_pkthdr.len; 3743 m->m_pkthdr.rcvif = ifp; 3744 /* 3745 * Due to hardware bugs, Rx checksum offloading 3746 * was intentionally disabled. 3747 */ 3748 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3749 (status & RRD_VLAN_TAG) != 0) { 3750 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3751 m->m_pkthdr.ether_vtag = ntohs(vtag); 3752 m->m_flags |= M_VLANTAG; 3753 } 3754 #ifndef __NO_STRICT_ALIGNMENT 3755 m = alc_fixup_rx(ifp, m); 3756 if (m != NULL) 3757 #endif 3758 { 3759 /* Pass it on. */ 3760 ALC_UNLOCK(sc); 3761 if_input(ifp, m); 3762 ALC_LOCK(sc); 3763 } 3764 } 3765 } 3766 /* Reset mbuf chains. */ 3767 ALC_RXCHAIN_RESET(sc); 3768 } 3769 3770 static void 3771 alc_tick(void *arg) 3772 { 3773 struct alc_softc *sc; 3774 struct mii_data *mii; 3775 3776 sc = (struct alc_softc *)arg; 3777 3778 ALC_LOCK_ASSERT(sc); 3779 3780 mii = device_get_softc(sc->alc_miibus); 3781 mii_tick(mii); 3782 alc_stats_update(sc); 3783 /* 3784 * alc(4) does not rely on Tx completion interrupts to reclaim 3785 * transferred buffers. Instead Tx completion interrupts are 3786 * used to hint for scheduling Tx task. So it's necessary to 3787 * release transmitted buffers by kicking Tx completion 3788 * handler. This limits the maximum reclamation delay to a hz. 3789 */ 3790 alc_txeof(sc); 3791 alc_watchdog(sc); 3792 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3793 } 3794 3795 static void 3796 alc_osc_reset(struct alc_softc *sc) 3797 { 3798 uint32_t reg; 3799 3800 reg = CSR_READ_4(sc, ALC_MISC3); 3801 reg &= ~MISC3_25M_BY_SW; 3802 reg |= MISC3_25M_NOTO_INTNL; 3803 CSR_WRITE_4(sc, ALC_MISC3, reg); 3804 3805 reg = CSR_READ_4(sc, ALC_MISC); 3806 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3807 /* 3808 * Restore over-current protection default value. 3809 * This value could be reset by MAC reset. 3810 */ 3811 reg &= ~MISC_PSW_OCP_MASK; 3812 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3813 reg &= ~MISC_INTNLOSC_OPEN; 3814 CSR_WRITE_4(sc, ALC_MISC, reg); 3815 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3816 reg = CSR_READ_4(sc, ALC_MISC2); 3817 reg &= ~MISC2_CALB_START; 3818 CSR_WRITE_4(sc, ALC_MISC2, reg); 3819 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3820 3821 } else { 3822 reg &= ~MISC_INTNLOSC_OPEN; 3823 /* Disable isolate for revision A devices. */ 3824 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3825 reg &= ~MISC_ISO_ENB; 3826 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3827 CSR_WRITE_4(sc, ALC_MISC, reg); 3828 } 3829 3830 DELAY(20); 3831 } 3832 3833 static void 3834 alc_reset(struct alc_softc *sc) 3835 { 3836 uint32_t pmcfg, reg; 3837 int i; 3838 3839 pmcfg = 0; 3840 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3841 /* Reset workaround. */ 3842 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3843 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3844 (sc->alc_rev & 0x01) != 0) { 3845 /* Disable L0s/L1s before reset. */ 3846 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3847 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3848 != 0) { 3849 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3850 PM_CFG_ASPM_L1_ENB); 3851 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3852 } 3853 } 3854 } 3855 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3856 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3857 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3858 3859 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3860 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3861 DELAY(10); 3862 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3863 break; 3864 } 3865 if (i == 0) 3866 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3867 } 3868 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3869 DELAY(10); 3870 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3871 break; 3872 } 3873 if (i == 0) 3874 device_printf(sc->alc_dev, "master reset timeout!\n"); 3875 3876 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3877 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3878 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3879 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3880 break; 3881 DELAY(10); 3882 } 3883 if (i == 0) 3884 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3885 3886 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3887 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3888 (sc->alc_rev & 0x01) != 0) { 3889 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3890 reg |= MASTER_CLK_SEL_DIS; 3891 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3892 /* Restore L0s/L1s config. */ 3893 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3894 != 0) 3895 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3896 } 3897 3898 alc_osc_reset(sc); 3899 reg = CSR_READ_4(sc, ALC_MISC3); 3900 reg &= ~MISC3_25M_BY_SW; 3901 reg |= MISC3_25M_NOTO_INTNL; 3902 CSR_WRITE_4(sc, ALC_MISC3, reg); 3903 reg = CSR_READ_4(sc, ALC_MISC); 3904 reg &= ~MISC_INTNLOSC_OPEN; 3905 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3906 reg &= ~MISC_ISO_ENB; 3907 CSR_WRITE_4(sc, ALC_MISC, reg); 3908 DELAY(20); 3909 } 3910 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3911 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3912 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3913 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3914 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3915 SERDES_PHY_CLK_SLOWDOWN); 3916 } 3917 3918 static void 3919 alc_init(void *xsc) 3920 { 3921 struct alc_softc *sc; 3922 3923 sc = (struct alc_softc *)xsc; 3924 ALC_LOCK(sc); 3925 alc_init_locked(sc); 3926 ALC_UNLOCK(sc); 3927 } 3928 3929 static void 3930 alc_init_locked(struct alc_softc *sc) 3931 { 3932 if_t ifp; 3933 uint8_t eaddr[ETHER_ADDR_LEN]; 3934 bus_addr_t paddr; 3935 uint32_t reg, rxf_hi, rxf_lo; 3936 3937 ALC_LOCK_ASSERT(sc); 3938 3939 ifp = sc->alc_ifp; 3940 3941 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3942 return; 3943 /* 3944 * Cancel any pending I/O. 3945 */ 3946 alc_stop(sc); 3947 /* 3948 * Reset the chip to a known state. 3949 */ 3950 alc_reset(sc); 3951 3952 /* Initialize Rx descriptors. */ 3953 if (alc_init_rx_ring(sc) != 0) { 3954 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3955 alc_stop(sc); 3956 return; 3957 } 3958 alc_init_rr_ring(sc); 3959 alc_init_tx_ring(sc); 3960 alc_init_cmb(sc); 3961 alc_init_smb(sc); 3962 3963 /* Enable all clocks. */ 3964 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3965 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3966 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3967 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3968 CLK_GATING_RXMAC_ENB); 3969 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3970 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3971 IDLE_DECISN_TIMER_DEFAULT_1MS); 3972 } else 3973 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3974 3975 /* Reprogram the station address. */ 3976 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3977 CSR_WRITE_4(sc, ALC_PAR0, 3978 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3979 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3980 /* 3981 * Clear WOL status and disable all WOL feature as WOL 3982 * would interfere Rx operation under normal environments. 3983 */ 3984 CSR_READ_4(sc, ALC_WOL_CFG); 3985 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3986 /* Set Tx descriptor base addresses. */ 3987 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3988 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3989 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3990 /* We don't use high priority ring. */ 3991 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3992 /* Set Tx descriptor counter. */ 3993 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3994 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3995 /* Set Rx descriptor base addresses. */ 3996 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3997 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3998 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3999 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4000 /* We use one Rx ring. */ 4001 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4002 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4003 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4004 } 4005 /* Set Rx descriptor counter. */ 4006 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4007 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4008 4009 /* 4010 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4011 * if it do not fit the buffer size. Rx return descriptor holds 4012 * a counter that indicates how many fragments were made by the 4013 * hardware. The buffer size should be multiple of 8 bytes. 4014 * Since hardware has limit on the size of buffer size, always 4015 * use the maximum value. 4016 * For strict-alignment architectures make sure to reduce buffer 4017 * size by 8 bytes to make room for alignment fixup. 4018 */ 4019 #ifndef __NO_STRICT_ALIGNMENT 4020 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4021 #else 4022 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4023 #endif 4024 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4025 4026 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4027 /* Set Rx return descriptor base addresses. */ 4028 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4029 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4030 /* We use one Rx return ring. */ 4031 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4032 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4033 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4034 } 4035 /* Set Rx return descriptor counter. */ 4036 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4037 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4038 paddr = sc->alc_rdata.alc_cmb_paddr; 4039 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4040 paddr = sc->alc_rdata.alc_smb_paddr; 4041 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4042 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4043 4044 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4045 /* Reconfigure SRAM - Vendor magic. */ 4046 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4047 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4048 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4049 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4050 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4051 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4052 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4053 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4054 } 4055 4056 /* Tell hardware that we're ready to load DMA blocks. */ 4057 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4058 4059 /* Configure interrupt moderation timer. */ 4060 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4061 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4062 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4063 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4064 /* 4065 * We don't want to automatic interrupt clear as task queue 4066 * for the interrupt should know interrupt status. 4067 */ 4068 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4069 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4070 reg |= MASTER_SA_TIMER_ENB; 4071 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4072 reg |= MASTER_IM_RX_TIMER_ENB; 4073 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4074 ALC_USECS(sc->alc_int_tx_mod) != 0) 4075 reg |= MASTER_IM_TX_TIMER_ENB; 4076 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4077 /* 4078 * Disable interrupt re-trigger timer. We don't want automatic 4079 * re-triggering of un-ACKed interrupts. 4080 */ 4081 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4082 /* Configure CMB. */ 4083 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4084 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4085 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4086 ALC_USECS(sc->alc_int_tx_mod)); 4087 } else { 4088 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4089 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4090 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4091 } else 4092 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4093 } 4094 /* 4095 * Hardware can be configured to issue SMB interrupt based 4096 * on programmed interval. Since there is a callout that is 4097 * invoked for every hz in driver we use that instead of 4098 * relying on periodic SMB interrupt. 4099 */ 4100 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4101 /* Clear MAC statistics. */ 4102 alc_stats_clear(sc); 4103 4104 /* 4105 * Always use maximum frame size that controller can support. 4106 * Otherwise received frames that has larger frame length 4107 * than alc(4) MTU would be silently dropped in hardware. This 4108 * would make path-MTU discovery hard as sender wouldn't get 4109 * any responses from receiver. alc(4) supports 4110 * multi-fragmented frames on Rx path so it has no issue on 4111 * assembling fragmented frames. Using maximum frame size also 4112 * removes the need to reinitialize hardware when interface 4113 * MTU configuration was changed. 4114 * 4115 * Be conservative in what you do, be liberal in what you 4116 * accept from others - RFC 793. 4117 */ 4118 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4119 4120 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4121 /* Disable header split(?) */ 4122 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4123 4124 /* Configure IPG/IFG parameters. */ 4125 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4126 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4127 IPG_IFG_IPGT_MASK) | 4128 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4129 IPG_IFG_MIFG_MASK) | 4130 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4131 IPG_IFG_IPG1_MASK) | 4132 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4133 IPG_IFG_IPG2_MASK)); 4134 /* Set parameters for half-duplex media. */ 4135 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4136 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4137 HDPX_CFG_LCOL_MASK) | 4138 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4139 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4140 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4141 HDPX_CFG_ABEBT_MASK) | 4142 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4143 HDPX_CFG_JAMIPG_MASK)); 4144 } 4145 4146 /* 4147 * Set TSO/checksum offload threshold. For frames that is 4148 * larger than this threshold, hardware wouldn't do 4149 * TSO/checksum offloading. 4150 */ 4151 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4152 TSO_OFFLOAD_THRESH_MASK; 4153 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4154 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4155 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4156 /* Configure TxQ. */ 4157 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4158 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4159 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4160 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4161 reg >>= 1; 4162 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4163 TXQ_CFG_TD_BURST_MASK; 4164 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4165 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4166 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4167 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4168 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4169 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4170 HQTD_CFG_BURST_ENB); 4171 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4172 reg = WRR_PRI_RESTRICT_NONE; 4173 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4174 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4175 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4176 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4177 CSR_WRITE_4(sc, ALC_WRR, reg); 4178 } else { 4179 /* Configure Rx free descriptor pre-fetching. */ 4180 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4181 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4182 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4183 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4184 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4185 } 4186 4187 /* 4188 * Configure flow control parameters. 4189 * XON : 80% of Rx FIFO 4190 * XOFF : 30% of Rx FIFO 4191 */ 4192 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4193 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4194 reg &= SRAM_RX_FIFO_LEN_MASK; 4195 reg *= 8; 4196 if (reg > 8 * 1024) 4197 reg -= RX_FIFO_PAUSE_816X_RSVD; 4198 else 4199 reg -= RX_BUF_SIZE_MAX; 4200 reg /= 8; 4201 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4202 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4203 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4204 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4205 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4206 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4207 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4208 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4209 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4210 rxf_hi = (reg * 8) / 10; 4211 rxf_lo = (reg * 3) / 10; 4212 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4213 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4214 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4215 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4216 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4217 } 4218 4219 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4220 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4221 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4222 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4223 } 4224 4225 /* Configure RxQ. */ 4226 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4227 RXQ_CFG_RD_BURST_MASK; 4228 reg |= RXQ_CFG_RSS_MODE_DIS; 4229 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4230 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4231 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4232 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4233 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4234 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4235 } else { 4236 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4237 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4238 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4239 } 4240 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4241 4242 /* Configure DMA parameters. */ 4243 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4244 reg |= sc->alc_rcb; 4245 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4246 reg |= DMA_CFG_CMB_ENB; 4247 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4248 reg |= DMA_CFG_SMB_ENB; 4249 else 4250 reg |= DMA_CFG_SMB_DIS; 4251 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4252 DMA_CFG_RD_BURST_SHIFT; 4253 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4254 DMA_CFG_WR_BURST_SHIFT; 4255 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4256 DMA_CFG_RD_DELAY_CNT_MASK; 4257 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4258 DMA_CFG_WR_DELAY_CNT_MASK; 4259 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4260 switch (AR816X_REV(sc->alc_rev)) { 4261 case AR816X_REV_A0: 4262 case AR816X_REV_A1: 4263 reg |= DMA_CFG_RD_CHNL_SEL_2; 4264 break; 4265 case AR816X_REV_B0: 4266 /* FALLTHROUGH */ 4267 default: 4268 reg |= DMA_CFG_RD_CHNL_SEL_4; 4269 break; 4270 } 4271 } 4272 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4273 4274 /* 4275 * Configure Tx/Rx MACs. 4276 * - Auto-padding for short frames. 4277 * - Enable CRC generation. 4278 * Actual reconfiguration of MAC for resolved speed/duplex 4279 * is followed after detection of link establishment. 4280 * AR813x/AR815x always does checksum computation regardless 4281 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4282 * have bug in protocol field in Rx return structure so 4283 * these controllers can't handle fragmented frames. Disable 4284 * Rx checksum offloading until there is a newer controller 4285 * that has sane implementation. 4286 */ 4287 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4288 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4289 MAC_CFG_PREAMBLE_MASK); 4290 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4291 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4292 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4293 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4294 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4295 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4296 reg |= MAC_CFG_SPEED_10_100; 4297 else 4298 reg |= MAC_CFG_SPEED_1000; 4299 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4300 4301 /* Set up the receive filter. */ 4302 alc_rxfilter(sc); 4303 alc_rxvlan(sc); 4304 4305 /* Acknowledge all pending interrupts and clear it. */ 4306 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4307 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4308 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4309 4310 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4311 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4312 4313 sc->alc_flags &= ~ALC_FLAG_LINK; 4314 /* Switch to the current media. */ 4315 alc_mediachange_locked(sc); 4316 4317 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4318 } 4319 4320 static void 4321 alc_stop(struct alc_softc *sc) 4322 { 4323 if_t ifp; 4324 struct alc_txdesc *txd; 4325 struct alc_rxdesc *rxd; 4326 uint32_t reg; 4327 int i; 4328 4329 ALC_LOCK_ASSERT(sc); 4330 /* 4331 * Mark the interface down and cancel the watchdog timer. 4332 */ 4333 ifp = sc->alc_ifp; 4334 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4335 sc->alc_flags &= ~ALC_FLAG_LINK; 4336 callout_stop(&sc->alc_tick_ch); 4337 sc->alc_watchdog_timer = 0; 4338 alc_stats_update(sc); 4339 /* Disable interrupts. */ 4340 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4341 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4342 /* Disable DMA. */ 4343 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4344 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4345 reg |= DMA_CFG_SMB_DIS; 4346 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4347 DELAY(1000); 4348 /* Stop Rx/Tx MACs. */ 4349 alc_stop_mac(sc); 4350 /* Disable interrupts which might be touched in taskq handler. */ 4351 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4352 /* Disable L0s/L1s */ 4353 alc_aspm(sc, 0, IFM_UNKNOWN); 4354 /* Reclaim Rx buffers that have been processed. */ 4355 if (sc->alc_cdata.alc_rxhead != NULL) 4356 m_freem(sc->alc_cdata.alc_rxhead); 4357 ALC_RXCHAIN_RESET(sc); 4358 /* 4359 * Free Tx/Rx mbufs still in the queues. 4360 */ 4361 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4362 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4363 if (rxd->rx_m != NULL) { 4364 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4365 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4366 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4367 rxd->rx_dmamap); 4368 m_freem(rxd->rx_m); 4369 rxd->rx_m = NULL; 4370 } 4371 } 4372 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4373 txd = &sc->alc_cdata.alc_txdesc[i]; 4374 if (txd->tx_m != NULL) { 4375 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4376 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4377 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4378 txd->tx_dmamap); 4379 m_freem(txd->tx_m); 4380 txd->tx_m = NULL; 4381 } 4382 } 4383 } 4384 4385 static void 4386 alc_stop_mac(struct alc_softc *sc) 4387 { 4388 uint32_t reg; 4389 int i; 4390 4391 alc_stop_queue(sc); 4392 /* Disable Rx/Tx MAC. */ 4393 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4394 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4395 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4396 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4397 } 4398 for (i = ALC_TIMEOUT; i > 0; i--) { 4399 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4400 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4401 break; 4402 DELAY(10); 4403 } 4404 if (i == 0) 4405 device_printf(sc->alc_dev, 4406 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4407 } 4408 4409 static void 4410 alc_start_queue(struct alc_softc *sc) 4411 { 4412 uint32_t qcfg[] = { 4413 0, 4414 RXQ_CFG_QUEUE0_ENB, 4415 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4416 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4417 RXQ_CFG_ENB 4418 }; 4419 uint32_t cfg; 4420 4421 ALC_LOCK_ASSERT(sc); 4422 4423 /* Enable RxQ. */ 4424 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4425 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4426 cfg &= ~RXQ_CFG_ENB; 4427 cfg |= qcfg[1]; 4428 } else 4429 cfg |= RXQ_CFG_QUEUE0_ENB; 4430 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4431 /* Enable TxQ. */ 4432 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4433 cfg |= TXQ_CFG_ENB; 4434 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4435 } 4436 4437 static void 4438 alc_stop_queue(struct alc_softc *sc) 4439 { 4440 uint32_t reg; 4441 int i; 4442 4443 /* Disable RxQ. */ 4444 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4445 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4446 if ((reg & RXQ_CFG_ENB) != 0) { 4447 reg &= ~RXQ_CFG_ENB; 4448 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4449 } 4450 } else { 4451 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4452 reg &= ~RXQ_CFG_QUEUE0_ENB; 4453 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4454 } 4455 } 4456 /* Disable TxQ. */ 4457 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4458 if ((reg & TXQ_CFG_ENB) != 0) { 4459 reg &= ~TXQ_CFG_ENB; 4460 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4461 } 4462 DELAY(40); 4463 for (i = ALC_TIMEOUT; i > 0; i--) { 4464 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4465 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4466 break; 4467 DELAY(10); 4468 } 4469 if (i == 0) 4470 device_printf(sc->alc_dev, 4471 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4472 } 4473 4474 static void 4475 alc_init_tx_ring(struct alc_softc *sc) 4476 { 4477 struct alc_ring_data *rd; 4478 struct alc_txdesc *txd; 4479 int i; 4480 4481 ALC_LOCK_ASSERT(sc); 4482 4483 sc->alc_cdata.alc_tx_prod = 0; 4484 sc->alc_cdata.alc_tx_cons = 0; 4485 sc->alc_cdata.alc_tx_cnt = 0; 4486 4487 rd = &sc->alc_rdata; 4488 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4489 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4490 txd = &sc->alc_cdata.alc_txdesc[i]; 4491 txd->tx_m = NULL; 4492 } 4493 4494 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4495 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4496 } 4497 4498 static int 4499 alc_init_rx_ring(struct alc_softc *sc) 4500 { 4501 struct alc_ring_data *rd; 4502 struct alc_rxdesc *rxd; 4503 int i; 4504 4505 ALC_LOCK_ASSERT(sc); 4506 4507 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4508 sc->alc_morework = 0; 4509 rd = &sc->alc_rdata; 4510 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4511 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4512 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4513 rxd->rx_m = NULL; 4514 rxd->rx_desc = &rd->alc_rx_ring[i]; 4515 if (alc_newbuf(sc, rxd) != 0) 4516 return (ENOBUFS); 4517 } 4518 4519 /* 4520 * Since controller does not update Rx descriptors, driver 4521 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4522 * is enough to ensure coherence. 4523 */ 4524 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4525 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4526 /* Let controller know availability of new Rx buffers. */ 4527 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4528 4529 return (0); 4530 } 4531 4532 static void 4533 alc_init_rr_ring(struct alc_softc *sc) 4534 { 4535 struct alc_ring_data *rd; 4536 4537 ALC_LOCK_ASSERT(sc); 4538 4539 sc->alc_cdata.alc_rr_cons = 0; 4540 ALC_RXCHAIN_RESET(sc); 4541 4542 rd = &sc->alc_rdata; 4543 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4544 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4545 sc->alc_cdata.alc_rr_ring_map, 4546 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4547 } 4548 4549 static void 4550 alc_init_cmb(struct alc_softc *sc) 4551 { 4552 struct alc_ring_data *rd; 4553 4554 ALC_LOCK_ASSERT(sc); 4555 4556 rd = &sc->alc_rdata; 4557 bzero(rd->alc_cmb, ALC_CMB_SZ); 4558 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4559 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4560 } 4561 4562 static void 4563 alc_init_smb(struct alc_softc *sc) 4564 { 4565 struct alc_ring_data *rd; 4566 4567 ALC_LOCK_ASSERT(sc); 4568 4569 rd = &sc->alc_rdata; 4570 bzero(rd->alc_smb, ALC_SMB_SZ); 4571 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4572 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4573 } 4574 4575 static void 4576 alc_rxvlan(struct alc_softc *sc) 4577 { 4578 if_t ifp; 4579 uint32_t reg; 4580 4581 ALC_LOCK_ASSERT(sc); 4582 4583 ifp = sc->alc_ifp; 4584 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4585 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4586 reg |= MAC_CFG_VLAN_TAG_STRIP; 4587 else 4588 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4589 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4590 } 4591 4592 static u_int 4593 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4594 { 4595 uint32_t *mchash = arg; 4596 uint32_t crc; 4597 4598 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4599 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4600 4601 return (1); 4602 } 4603 4604 static void 4605 alc_rxfilter(struct alc_softc *sc) 4606 { 4607 if_t ifp; 4608 uint32_t mchash[2]; 4609 uint32_t rxcfg; 4610 4611 ALC_LOCK_ASSERT(sc); 4612 4613 ifp = sc->alc_ifp; 4614 4615 bzero(mchash, sizeof(mchash)); 4616 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4617 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4618 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4619 rxcfg |= MAC_CFG_BCAST; 4620 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4621 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4622 rxcfg |= MAC_CFG_PROMISC; 4623 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4624 rxcfg |= MAC_CFG_ALLMULTI; 4625 mchash[0] = 0xFFFFFFFF; 4626 mchash[1] = 0xFFFFFFFF; 4627 goto chipit; 4628 } 4629 4630 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4631 4632 chipit: 4633 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4634 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4635 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4636 } 4637 4638 static int 4639 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4640 { 4641 int error, value; 4642 4643 if (arg1 == NULL) 4644 return (EINVAL); 4645 value = *(int *)arg1; 4646 error = sysctl_handle_int(oidp, &value, 0, req); 4647 if (error || req->newptr == NULL) 4648 return (error); 4649 if (value < low || value > high) 4650 return (EINVAL); 4651 *(int *)arg1 = value; 4652 4653 return (0); 4654 } 4655 4656 static int 4657 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4658 { 4659 return (sysctl_int_range(oidp, arg1, arg2, req, 4660 ALC_PROC_MIN, ALC_PROC_MAX)); 4661 } 4662 4663 static int 4664 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4665 { 4666 4667 return (sysctl_int_range(oidp, arg1, arg2, req, 4668 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4669 } 4670 4671 #ifdef DEBUGNET 4672 static void 4673 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4674 { 4675 struct alc_softc *sc __diagused; 4676 4677 sc = if_getsoftc(ifp); 4678 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4679 4680 *nrxr = ALC_RX_RING_CNT; 4681 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4682 *clsize = MCLBYTES; 4683 } 4684 4685 static void 4686 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4687 { 4688 } 4689 4690 static int 4691 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4692 { 4693 struct alc_softc *sc; 4694 int error; 4695 4696 sc = if_getsoftc(ifp); 4697 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4698 IFF_DRV_RUNNING) 4699 return (EBUSY); 4700 4701 error = alc_encap(sc, &m); 4702 if (error == 0) 4703 alc_start_tx(sc); 4704 return (error); 4705 } 4706 4707 static int 4708 alc_debugnet_poll(if_t ifp, int count) 4709 { 4710 struct alc_softc *sc; 4711 4712 sc = if_getsoftc(ifp); 4713 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4714 IFF_DRV_RUNNING) 4715 return (EBUSY); 4716 4717 alc_txeof(sc); 4718 return (alc_rxintr(sc, count)); 4719 } 4720 #endif /* DEBUGNET */ 4721