1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/atomic.h> 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 static int msix_disable = 0; 95 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98 /* 99 * Devices supported by this driver. 100 */ 101 static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { 0, 0, 0, NULL} 115 }; 116 117 static void alc_aspm(struct alc_softc *, int); 118 static int alc_attach(device_t); 119 static int alc_check_boundary(struct alc_softc *); 120 static int alc_detach(device_t); 121 static void alc_disable_l0s_l1(struct alc_softc *); 122 static int alc_dma_alloc(struct alc_softc *); 123 static void alc_dma_free(struct alc_softc *); 124 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 125 static int alc_encap(struct alc_softc *, struct mbuf **); 126 static struct alc_ident * 127 alc_find_ident(device_t); 128 #ifndef __NO_STRICT_ALIGNMENT 129 static struct mbuf * 130 alc_fixup_rx(struct ifnet *, struct mbuf *); 131 #endif 132 static void alc_get_macaddr(struct alc_softc *); 133 static void alc_init(void *); 134 static void alc_init_cmb(struct alc_softc *); 135 static void alc_init_locked(struct alc_softc *); 136 static void alc_init_rr_ring(struct alc_softc *); 137 static int alc_init_rx_ring(struct alc_softc *); 138 static void alc_init_smb(struct alc_softc *); 139 static void alc_init_tx_ring(struct alc_softc *); 140 static void alc_int_task(void *, int); 141 static int alc_intr(void *); 142 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 143 static void alc_mac_config(struct alc_softc *); 144 static int alc_miibus_readreg(device_t, int, int); 145 static void alc_miibus_statchg(device_t); 146 static int alc_miibus_writereg(device_t, int, int, int); 147 static int alc_mediachange(struct ifnet *); 148 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 149 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 150 static void alc_phy_down(struct alc_softc *); 151 static void alc_phy_reset(struct alc_softc *); 152 static int alc_probe(device_t); 153 static void alc_reset(struct alc_softc *); 154 static int alc_resume(device_t); 155 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 156 static int alc_rxintr(struct alc_softc *, int); 157 static void alc_rxfilter(struct alc_softc *); 158 static void alc_rxvlan(struct alc_softc *); 159 static void alc_setlinkspeed(struct alc_softc *); 160 static void alc_setwol(struct alc_softc *); 161 static int alc_shutdown(device_t); 162 static void alc_start(struct ifnet *); 163 static void alc_start_queue(struct alc_softc *); 164 static void alc_stats_clear(struct alc_softc *); 165 static void alc_stats_update(struct alc_softc *); 166 static void alc_stop(struct alc_softc *); 167 static void alc_stop_mac(struct alc_softc *); 168 static void alc_stop_queue(struct alc_softc *); 169 static int alc_suspend(device_t); 170 static void alc_sysctl_node(struct alc_softc *); 171 static void alc_tick(void *); 172 static void alc_tx_task(void *, int); 173 static void alc_txeof(struct alc_softc *); 174 static void alc_watchdog(struct alc_softc *); 175 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 176 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 177 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 178 179 static device_method_t alc_methods[] = { 180 /* Device interface. */ 181 DEVMETHOD(device_probe, alc_probe), 182 DEVMETHOD(device_attach, alc_attach), 183 DEVMETHOD(device_detach, alc_detach), 184 DEVMETHOD(device_shutdown, alc_shutdown), 185 DEVMETHOD(device_suspend, alc_suspend), 186 DEVMETHOD(device_resume, alc_resume), 187 188 /* MII interface. */ 189 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 190 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 191 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 192 193 { NULL, NULL } 194 }; 195 196 static driver_t alc_driver = { 197 "alc", 198 alc_methods, 199 sizeof(struct alc_softc) 200 }; 201 202 static devclass_t alc_devclass; 203 204 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 205 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 206 207 static struct resource_spec alc_res_spec_mem[] = { 208 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 209 { -1, 0, 0 } 210 }; 211 212 static struct resource_spec alc_irq_spec_legacy[] = { 213 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 214 { -1, 0, 0 } 215 }; 216 217 static struct resource_spec alc_irq_spec_msi[] = { 218 { SYS_RES_IRQ, 1, RF_ACTIVE }, 219 { -1, 0, 0 } 220 }; 221 222 static struct resource_spec alc_irq_spec_msix[] = { 223 { SYS_RES_IRQ, 1, RF_ACTIVE }, 224 { -1, 0, 0 } 225 }; 226 227 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 228 229 static int 230 alc_miibus_readreg(device_t dev, int phy, int reg) 231 { 232 struct alc_softc *sc; 233 uint32_t v; 234 int i; 235 236 sc = device_get_softc(dev); 237 238 if (phy != sc->alc_phyaddr) 239 return (0); 240 241 /* 242 * For AR8132 fast ethernet controller, do not report 1000baseT 243 * capability to mii(4). Even though AR8132 uses the same 244 * model/revision number of F1 gigabit PHY, the PHY has no 245 * ability to establish 1000baseT link. 246 */ 247 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 248 reg == MII_EXTSR) 249 return (0); 250 251 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 252 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 253 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 254 DELAY(5); 255 v = CSR_READ_4(sc, ALC_MDIO); 256 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 257 break; 258 } 259 260 if (i == 0) { 261 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 262 return (0); 263 } 264 265 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 266 } 267 268 static int 269 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 270 { 271 struct alc_softc *sc; 272 uint32_t v; 273 int i; 274 275 sc = device_get_softc(dev); 276 277 if (phy != sc->alc_phyaddr) 278 return (0); 279 280 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 281 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 282 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 283 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 284 DELAY(5); 285 v = CSR_READ_4(sc, ALC_MDIO); 286 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 287 break; 288 } 289 290 if (i == 0) 291 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 292 293 return (0); 294 } 295 296 static void 297 alc_miibus_statchg(device_t dev) 298 { 299 struct alc_softc *sc; 300 struct mii_data *mii; 301 struct ifnet *ifp; 302 uint32_t reg; 303 304 sc = device_get_softc(dev); 305 306 mii = device_get_softc(sc->alc_miibus); 307 ifp = sc->alc_ifp; 308 if (mii == NULL || ifp == NULL || 309 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 310 return; 311 312 sc->alc_flags &= ~ALC_FLAG_LINK; 313 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 314 (IFM_ACTIVE | IFM_AVALID)) { 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_10_T: 317 case IFM_100_TX: 318 sc->alc_flags |= ALC_FLAG_LINK; 319 break; 320 case IFM_1000_T: 321 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 322 sc->alc_flags |= ALC_FLAG_LINK; 323 break; 324 default: 325 break; 326 } 327 } 328 alc_stop_queue(sc); 329 /* Stop Rx/Tx MACs. */ 330 alc_stop_mac(sc); 331 332 /* Program MACs with resolved speed/duplex/flow-control. */ 333 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 334 alc_start_queue(sc); 335 alc_mac_config(sc); 336 /* Re-enable Tx/Rx MACs. */ 337 reg = CSR_READ_4(sc, ALC_MAC_CFG); 338 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 339 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 340 } 341 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 342 } 343 344 static void 345 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 346 { 347 struct alc_softc *sc; 348 struct mii_data *mii; 349 350 sc = ifp->if_softc; 351 ALC_LOCK(sc); 352 if ((ifp->if_flags & IFF_UP) == 0) { 353 ALC_UNLOCK(sc); 354 return; 355 } 356 mii = device_get_softc(sc->alc_miibus); 357 358 mii_pollstat(mii); 359 ALC_UNLOCK(sc); 360 ifmr->ifm_status = mii->mii_media_status; 361 ifmr->ifm_active = mii->mii_media_active; 362 } 363 364 static int 365 alc_mediachange(struct ifnet *ifp) 366 { 367 struct alc_softc *sc; 368 struct mii_data *mii; 369 struct mii_softc *miisc; 370 int error; 371 372 sc = ifp->if_softc; 373 ALC_LOCK(sc); 374 mii = device_get_softc(sc->alc_miibus); 375 if (mii->mii_instance != 0) { 376 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 377 mii_phy_reset(miisc); 378 } 379 error = mii_mediachg(mii); 380 ALC_UNLOCK(sc); 381 382 return (error); 383 } 384 385 static struct alc_ident * 386 alc_find_ident(device_t dev) 387 { 388 struct alc_ident *ident; 389 uint16_t vendor, devid; 390 391 vendor = pci_get_vendor(dev); 392 devid = pci_get_device(dev); 393 for (ident = alc_ident_table; ident->name != NULL; ident++) { 394 if (vendor == ident->vendorid && devid == ident->deviceid) 395 return (ident); 396 } 397 398 return (NULL); 399 } 400 401 static int 402 alc_probe(device_t dev) 403 { 404 struct alc_ident *ident; 405 406 ident = alc_find_ident(dev); 407 if (ident != NULL) { 408 device_set_desc(dev, ident->name); 409 return (BUS_PROBE_DEFAULT); 410 } 411 412 return (ENXIO); 413 } 414 415 static void 416 alc_get_macaddr(struct alc_softc *sc) 417 { 418 uint32_t ea[2], opt; 419 uint16_t val; 420 int eeprom, i; 421 422 eeprom = 0; 423 opt = CSR_READ_4(sc, ALC_OPT_CFG); 424 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 425 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 426 /* 427 * EEPROM found, let TWSI reload EEPROM configuration. 428 * This will set ethernet address of controller. 429 */ 430 eeprom++; 431 switch (sc->alc_ident->deviceid) { 432 case DEVICEID_ATHEROS_AR8131: 433 case DEVICEID_ATHEROS_AR8132: 434 if ((opt & OPT_CFG_CLK_ENB) == 0) { 435 opt |= OPT_CFG_CLK_ENB; 436 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 437 CSR_READ_4(sc, ALC_OPT_CFG); 438 DELAY(1000); 439 } 440 break; 441 case DEVICEID_ATHEROS_AR8151: 442 case DEVICEID_ATHEROS_AR8151_V2: 443 case DEVICEID_ATHEROS_AR8152_B: 444 case DEVICEID_ATHEROS_AR8152_B2: 445 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_ADDR, 0x00); 447 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 448 ALC_MII_DBG_DATA); 449 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_DATA, val & 0xFF7F); 451 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 452 ALC_MII_DBG_ADDR, 0x3B); 453 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_DATA); 455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 456 ALC_MII_DBG_DATA, val | 0x0008); 457 DELAY(20); 458 break; 459 } 460 461 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 462 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 463 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 464 CSR_READ_4(sc, ALC_WOL_CFG); 465 466 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 467 TWSI_CFG_SW_LD_START); 468 for (i = 100; i > 0; i--) { 469 DELAY(1000); 470 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 471 TWSI_CFG_SW_LD_START) == 0) 472 break; 473 } 474 if (i == 0) 475 device_printf(sc->alc_dev, 476 "reloading EEPROM timeout!\n"); 477 } else { 478 if (bootverbose) 479 device_printf(sc->alc_dev, "EEPROM not found!\n"); 480 } 481 if (eeprom != 0) { 482 switch (sc->alc_ident->deviceid) { 483 case DEVICEID_ATHEROS_AR8131: 484 case DEVICEID_ATHEROS_AR8132: 485 if ((opt & OPT_CFG_CLK_ENB) != 0) { 486 opt &= ~OPT_CFG_CLK_ENB; 487 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 488 CSR_READ_4(sc, ALC_OPT_CFG); 489 DELAY(1000); 490 } 491 break; 492 case DEVICEID_ATHEROS_AR8151: 493 case DEVICEID_ATHEROS_AR8151_V2: 494 case DEVICEID_ATHEROS_AR8152_B: 495 case DEVICEID_ATHEROS_AR8152_B2: 496 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_ADDR, 0x00); 498 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 499 ALC_MII_DBG_DATA); 500 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 501 ALC_MII_DBG_DATA, val | 0x0080); 502 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 503 ALC_MII_DBG_ADDR, 0x3B); 504 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 505 ALC_MII_DBG_DATA); 506 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 507 ALC_MII_DBG_DATA, val & 0xFFF7); 508 DELAY(20); 509 break; 510 } 511 } 512 513 ea[0] = CSR_READ_4(sc, ALC_PAR0); 514 ea[1] = CSR_READ_4(sc, ALC_PAR1); 515 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 516 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 517 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 518 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 519 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 520 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 521 } 522 523 static void 524 alc_disable_l0s_l1(struct alc_softc *sc) 525 { 526 uint32_t pmcfg; 527 528 /* Another magic from vendor. */ 529 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 530 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 531 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 532 PM_CFG_SERDES_PD_EX_L1); 533 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 534 PM_CFG_SERDES_L1_ENB; 535 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 536 } 537 538 static void 539 alc_phy_reset(struct alc_softc *sc) 540 { 541 uint16_t data; 542 543 /* Reset magic from Linux. */ 544 CSR_WRITE_2(sc, ALC_GPHY_CFG, 545 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 546 CSR_READ_2(sc, ALC_GPHY_CFG); 547 DELAY(10 * 1000); 548 549 CSR_WRITE_2(sc, ALC_GPHY_CFG, 550 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 551 GPHY_CFG_SEL_ANA_RESET); 552 CSR_READ_2(sc, ALC_GPHY_CFG); 553 DELAY(10 * 1000); 554 555 /* DSP fixup, Vendor magic. */ 556 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 557 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 558 ALC_MII_DBG_ADDR, 0x000A); 559 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 560 ALC_MII_DBG_DATA); 561 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 562 ALC_MII_DBG_DATA, data & 0xDFFF); 563 } 564 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 565 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 566 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 567 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_ADDR, 0x003B); 570 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_DATA); 572 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 573 ALC_MII_DBG_DATA, data & 0xFFF7); 574 DELAY(20 * 1000); 575 } 576 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 577 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 578 ALC_MII_DBG_ADDR, 0x0029); 579 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 580 ALC_MII_DBG_DATA, 0x929D); 581 } 582 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 583 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 584 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 585 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 586 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_ADDR, 0x0029); 588 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_DATA, 0xB6DD); 590 } 591 592 /* Load DSP codes, vendor magic. */ 593 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 594 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 595 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 596 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 597 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 598 ALC_MII_DBG_DATA, data); 599 600 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 601 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 602 ANA_SERDES_EN_LCKDT; 603 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 604 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 605 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 606 ALC_MII_DBG_DATA, data); 607 608 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 609 ANA_LONG_CABLE_TH_100_MASK) | 610 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 611 ANA_SHORT_CABLE_TH_100_SHIFT) | 612 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_DATA, data); 617 618 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 619 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 620 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 621 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 622 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 624 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_DATA, data); 626 627 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 628 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 629 ANA_OEN_125M; 630 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 631 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 632 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 633 ALC_MII_DBG_DATA, data); 634 DELAY(1000); 635 } 636 637 static void 638 alc_phy_down(struct alc_softc *sc) 639 { 640 641 switch (sc->alc_ident->deviceid) { 642 case DEVICEID_ATHEROS_AR8151: 643 case DEVICEID_ATHEROS_AR8151_V2: 644 /* 645 * GPHY power down caused more problems on AR8151 v2.0. 646 * When driver is reloaded after GPHY power down, 647 * accesses to PHY/MAC registers hung the system. Only 648 * cold boot recovered from it. I'm not sure whether 649 * AR8151 v1.0 also requires this one though. I don't 650 * have AR8151 v1.0 controller in hand. 651 * The only option left is to isolate the PHY and 652 * initiates power down the PHY which in turn saves 653 * more power when driver is unloaded. 654 */ 655 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 656 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 657 break; 658 default: 659 /* Force PHY down. */ 660 CSR_WRITE_2(sc, ALC_GPHY_CFG, 661 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 662 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 663 GPHY_CFG_PWDOWN_HW); 664 DELAY(1000); 665 break; 666 } 667 } 668 669 static void 670 alc_aspm(struct alc_softc *sc, int media) 671 { 672 uint32_t pmcfg; 673 uint16_t linkcfg; 674 675 ALC_LOCK_ASSERT(sc); 676 677 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 678 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 679 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 680 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 681 PCIR_EXPRESS_LINK_CTL); 682 else 683 linkcfg = 0; 684 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 685 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 686 pmcfg |= PM_CFG_MAC_ASPM_CHK; 687 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 688 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 689 690 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 691 /* Disable extended sync except AR8152 B v1.0 */ 692 linkcfg &= ~0x80; 693 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 694 sc->alc_rev == ATHEROS_AR8152_B_V10) 695 linkcfg |= 0x80; 696 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 697 linkcfg); 698 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 699 PM_CFG_HOTRST); 700 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 701 PM_CFG_L1_ENTRY_TIMER_SHIFT); 702 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 703 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 704 PM_CFG_PM_REQ_TIMER_SHIFT); 705 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 706 } 707 708 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 709 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 710 pmcfg |= PM_CFG_ASPM_L0S_ENB; 711 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 712 pmcfg |= PM_CFG_ASPM_L1_ENB; 713 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 714 if (sc->alc_ident->deviceid == 715 DEVICEID_ATHEROS_AR8152_B) 716 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 717 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 718 PM_CFG_SERDES_PLL_L1_ENB | 719 PM_CFG_SERDES_BUDS_RX_L1_ENB); 720 pmcfg |= PM_CFG_CLK_SWH_L1; 721 if (media == IFM_100_TX || media == IFM_1000_T) { 722 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 723 switch (sc->alc_ident->deviceid) { 724 case DEVICEID_ATHEROS_AR8152_B: 725 pmcfg |= (7 << 726 PM_CFG_L1_ENTRY_TIMER_SHIFT); 727 break; 728 case DEVICEID_ATHEROS_AR8152_B2: 729 case DEVICEID_ATHEROS_AR8151_V2: 730 pmcfg |= (4 << 731 PM_CFG_L1_ENTRY_TIMER_SHIFT); 732 break; 733 default: 734 pmcfg |= (15 << 735 PM_CFG_L1_ENTRY_TIMER_SHIFT); 736 break; 737 } 738 } 739 } else { 740 pmcfg |= PM_CFG_SERDES_L1_ENB | 741 PM_CFG_SERDES_PLL_L1_ENB | 742 PM_CFG_SERDES_BUDS_RX_L1_ENB; 743 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 744 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 745 } 746 } else { 747 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 748 PM_CFG_SERDES_PLL_L1_ENB); 749 pmcfg |= PM_CFG_CLK_SWH_L1; 750 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 751 pmcfg |= PM_CFG_ASPM_L1_ENB; 752 } 753 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 754 } 755 756 static int 757 alc_attach(device_t dev) 758 { 759 struct alc_softc *sc; 760 struct ifnet *ifp; 761 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 762 uint16_t burst; 763 int base, error, i, msic, msixc, state; 764 uint32_t cap, ctl, val; 765 766 error = 0; 767 sc = device_get_softc(dev); 768 sc->alc_dev = dev; 769 770 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 771 MTX_DEF); 772 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 773 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 774 sc->alc_ident = alc_find_ident(dev); 775 776 /* Map the device. */ 777 pci_enable_busmaster(dev); 778 sc->alc_res_spec = alc_res_spec_mem; 779 sc->alc_irq_spec = alc_irq_spec_legacy; 780 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 781 if (error != 0) { 782 device_printf(dev, "cannot allocate memory resources.\n"); 783 goto fail; 784 } 785 786 /* Set PHY address. */ 787 sc->alc_phyaddr = ALC_PHY_ADDR; 788 789 /* Initialize DMA parameters. */ 790 sc->alc_dma_rd_burst = 0; 791 sc->alc_dma_wr_burst = 0; 792 sc->alc_rcb = DMA_CFG_RCB_64; 793 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 794 sc->alc_flags |= ALC_FLAG_PCIE; 795 sc->alc_expcap = base; 796 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 797 sc->alc_dma_rd_burst = 798 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 799 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 800 if (bootverbose) { 801 device_printf(dev, "Read request size : %u bytes.\n", 802 alc_dma_burst[sc->alc_dma_rd_burst]); 803 device_printf(dev, "TLP payload size : %u bytes.\n", 804 alc_dma_burst[sc->alc_dma_wr_burst]); 805 } 806 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 807 sc->alc_dma_rd_burst = 3; 808 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 809 sc->alc_dma_wr_burst = 3; 810 /* Clear data link and flow-control protocol error. */ 811 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 812 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 813 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 814 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 815 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 816 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 817 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 818 PCIE_PHYMISC_FORCE_RCV_DET); 819 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 820 sc->alc_rev == ATHEROS_AR8152_B_V10) { 821 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 822 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 823 PCIE_PHYMISC2_SERDES_TH_MASK); 824 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 825 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 826 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 827 } 828 /* Disable ASPM L0S and L1. */ 829 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 830 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 831 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 832 if ((ctl & 0x08) != 0) 833 sc->alc_rcb = DMA_CFG_RCB_128; 834 if (bootverbose) 835 device_printf(dev, "RCB %u bytes\n", 836 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 837 state = ctl & 0x03; 838 if (state & 0x01) 839 sc->alc_flags |= ALC_FLAG_L0S; 840 if (state & 0x02) 841 sc->alc_flags |= ALC_FLAG_L1S; 842 if (bootverbose) 843 device_printf(sc->alc_dev, "ASPM %s %s\n", 844 aspm_state[state], 845 state == 0 ? "disabled" : "enabled"); 846 alc_disable_l0s_l1(sc); 847 } else { 848 if (bootverbose) 849 device_printf(sc->alc_dev, 850 "no ASPM support\n"); 851 } 852 } 853 854 /* Reset PHY. */ 855 alc_phy_reset(sc); 856 857 /* Reset the ethernet controller. */ 858 alc_reset(sc); 859 860 /* 861 * One odd thing is AR8132 uses the same PHY hardware(F1 862 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 863 * the PHY supports 1000Mbps but that's not true. The PHY 864 * used in AR8132 can't establish gigabit link even if it 865 * shows the same PHY model/revision number of AR8131. 866 */ 867 switch (sc->alc_ident->deviceid) { 868 case DEVICEID_ATHEROS_AR8152_B: 869 case DEVICEID_ATHEROS_AR8152_B2: 870 sc->alc_flags |= ALC_FLAG_APS; 871 /* FALLTHROUGH */ 872 case DEVICEID_ATHEROS_AR8132: 873 sc->alc_flags |= ALC_FLAG_FASTETHER; 874 break; 875 case DEVICEID_ATHEROS_AR8151: 876 case DEVICEID_ATHEROS_AR8151_V2: 877 sc->alc_flags |= ALC_FLAG_APS; 878 /* FALLTHROUGH */ 879 default: 880 break; 881 } 882 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 883 884 /* 885 * It seems that AR813x/AR815x has silicon bug for SMB. In 886 * addition, Atheros said that enabling SMB wouldn't improve 887 * performance. However I think it's bad to access lots of 888 * registers to extract MAC statistics. 889 */ 890 sc->alc_flags |= ALC_FLAG_SMB_BUG; 891 /* 892 * Don't use Tx CMB. It is known to have silicon bug. 893 */ 894 sc->alc_flags |= ALC_FLAG_CMB_BUG; 895 sc->alc_rev = pci_get_revid(dev); 896 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 897 MASTER_CHIP_REV_SHIFT; 898 if (bootverbose) { 899 device_printf(dev, "PCI device revision : 0x%04x\n", 900 sc->alc_rev); 901 device_printf(dev, "Chip id/revision : 0x%04x\n", 902 sc->alc_chip_rev); 903 } 904 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 905 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 906 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 907 908 /* Allocate IRQ resources. */ 909 msixc = pci_msix_count(dev); 910 msic = pci_msi_count(dev); 911 if (bootverbose) { 912 device_printf(dev, "MSIX count : %d\n", msixc); 913 device_printf(dev, "MSI count : %d\n", msic); 914 } 915 /* Prefer MSIX over MSI. */ 916 if (msix_disable == 0 || msi_disable == 0) { 917 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 918 pci_alloc_msix(dev, &msixc) == 0) { 919 if (msic == ALC_MSIX_MESSAGES) { 920 device_printf(dev, 921 "Using %d MSIX message(s).\n", msixc); 922 sc->alc_flags |= ALC_FLAG_MSIX; 923 sc->alc_irq_spec = alc_irq_spec_msix; 924 } else 925 pci_release_msi(dev); 926 } 927 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 928 msic == ALC_MSI_MESSAGES && 929 pci_alloc_msi(dev, &msic) == 0) { 930 if (msic == ALC_MSI_MESSAGES) { 931 device_printf(dev, 932 "Using %d MSI message(s).\n", msic); 933 sc->alc_flags |= ALC_FLAG_MSI; 934 sc->alc_irq_spec = alc_irq_spec_msi; 935 } else 936 pci_release_msi(dev); 937 } 938 } 939 940 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 941 if (error != 0) { 942 device_printf(dev, "cannot allocate IRQ resources.\n"); 943 goto fail; 944 } 945 946 /* Create device sysctl node. */ 947 alc_sysctl_node(sc); 948 949 if ((error = alc_dma_alloc(sc) != 0)) 950 goto fail; 951 952 /* Load station address. */ 953 alc_get_macaddr(sc); 954 955 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 956 if (ifp == NULL) { 957 device_printf(dev, "cannot allocate ifnet structure.\n"); 958 error = ENXIO; 959 goto fail; 960 } 961 962 ifp->if_softc = sc; 963 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 965 ifp->if_ioctl = alc_ioctl; 966 ifp->if_start = alc_start; 967 ifp->if_init = alc_init; 968 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 969 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 970 IFQ_SET_READY(&ifp->if_snd); 971 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 972 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 973 if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { 974 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 975 sc->alc_flags |= ALC_FLAG_PM; 976 sc->alc_pmcap = base; 977 } 978 ifp->if_capenable = ifp->if_capabilities; 979 980 /* Set up MII bus. */ 981 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 982 alc_mediastatus)) != 0) { 983 device_printf(dev, "no PHY found!\n"); 984 goto fail; 985 } 986 987 ether_ifattach(ifp, sc->alc_eaddr); 988 989 /* VLAN capability setup. */ 990 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 991 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 992 ifp->if_capenable = ifp->if_capabilities; 993 /* 994 * XXX 995 * It seems enabling Tx checksum offloading makes more trouble. 996 * Sometimes the controller does not receive any frames when 997 * Tx checksum offloading is enabled. I'm not sure whether this 998 * is a bug in Tx checksum offloading logic or I got broken 999 * sample boards. To safety, don't enable Tx checksum offloading 1000 * by default but give chance to users to toggle it if they know 1001 * their controllers work without problems. 1002 */ 1003 ifp->if_capenable &= ~IFCAP_TXCSUM; 1004 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1005 1006 /* Tell the upper layer(s) we support long frames. */ 1007 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1008 1009 /* Create local taskq. */ 1010 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1011 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1012 taskqueue_thread_enqueue, &sc->alc_tq); 1013 if (sc->alc_tq == NULL) { 1014 device_printf(dev, "could not create taskqueue.\n"); 1015 ether_ifdetach(ifp); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1020 device_get_nameunit(sc->alc_dev)); 1021 1022 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1023 msic = ALC_MSIX_MESSAGES; 1024 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1025 msic = ALC_MSI_MESSAGES; 1026 else 1027 msic = 1; 1028 for (i = 0; i < msic; i++) { 1029 error = bus_setup_intr(dev, sc->alc_irq[i], 1030 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1031 &sc->alc_intrhand[i]); 1032 if (error != 0) 1033 break; 1034 } 1035 if (error != 0) { 1036 device_printf(dev, "could not set up interrupt handler.\n"); 1037 taskqueue_free(sc->alc_tq); 1038 sc->alc_tq = NULL; 1039 ether_ifdetach(ifp); 1040 goto fail; 1041 } 1042 1043 fail: 1044 if (error != 0) 1045 alc_detach(dev); 1046 1047 return (error); 1048 } 1049 1050 static int 1051 alc_detach(device_t dev) 1052 { 1053 struct alc_softc *sc; 1054 struct ifnet *ifp; 1055 int i, msic; 1056 1057 sc = device_get_softc(dev); 1058 1059 ifp = sc->alc_ifp; 1060 if (device_is_attached(dev)) { 1061 ALC_LOCK(sc); 1062 sc->alc_flags |= ALC_FLAG_DETACH; 1063 alc_stop(sc); 1064 ALC_UNLOCK(sc); 1065 callout_drain(&sc->alc_tick_ch); 1066 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1067 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1068 ether_ifdetach(ifp); 1069 } 1070 1071 if (sc->alc_tq != NULL) { 1072 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1073 taskqueue_free(sc->alc_tq); 1074 sc->alc_tq = NULL; 1075 } 1076 1077 if (sc->alc_miibus != NULL) { 1078 device_delete_child(dev, sc->alc_miibus); 1079 sc->alc_miibus = NULL; 1080 } 1081 bus_generic_detach(dev); 1082 alc_dma_free(sc); 1083 1084 if (ifp != NULL) { 1085 if_free(ifp); 1086 sc->alc_ifp = NULL; 1087 } 1088 1089 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1090 msic = ALC_MSIX_MESSAGES; 1091 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1092 msic = ALC_MSI_MESSAGES; 1093 else 1094 msic = 1; 1095 for (i = 0; i < msic; i++) { 1096 if (sc->alc_intrhand[i] != NULL) { 1097 bus_teardown_intr(dev, sc->alc_irq[i], 1098 sc->alc_intrhand[i]); 1099 sc->alc_intrhand[i] = NULL; 1100 } 1101 } 1102 if (sc->alc_res[0] != NULL) 1103 alc_phy_down(sc); 1104 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1105 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1106 pci_release_msi(dev); 1107 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1108 mtx_destroy(&sc->alc_mtx); 1109 1110 return (0); 1111 } 1112 1113 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1114 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1115 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1116 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1117 1118 static void 1119 alc_sysctl_node(struct alc_softc *sc) 1120 { 1121 struct sysctl_ctx_list *ctx; 1122 struct sysctl_oid_list *child, *parent; 1123 struct sysctl_oid *tree; 1124 struct alc_hw_stats *stats; 1125 int error; 1126 1127 stats = &sc->alc_stats; 1128 ctx = device_get_sysctl_ctx(sc->alc_dev); 1129 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1130 1131 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1132 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1133 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1134 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1135 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1136 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1137 /* Pull in device tunables. */ 1138 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1139 error = resource_int_value(device_get_name(sc->alc_dev), 1140 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1141 if (error == 0) { 1142 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1143 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1144 device_printf(sc->alc_dev, "int_rx_mod value out of " 1145 "range; using default: %d\n", 1146 ALC_IM_RX_TIMER_DEFAULT); 1147 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1148 } 1149 } 1150 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1151 error = resource_int_value(device_get_name(sc->alc_dev), 1152 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1153 if (error == 0) { 1154 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1155 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1156 device_printf(sc->alc_dev, "int_tx_mod value out of " 1157 "range; using default: %d\n", 1158 ALC_IM_TX_TIMER_DEFAULT); 1159 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1160 } 1161 } 1162 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1163 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1164 sysctl_hw_alc_proc_limit, "I", 1165 "max number of Rx events to process"); 1166 /* Pull in device tunables. */ 1167 sc->alc_process_limit = ALC_PROC_DEFAULT; 1168 error = resource_int_value(device_get_name(sc->alc_dev), 1169 device_get_unit(sc->alc_dev), "process_limit", 1170 &sc->alc_process_limit); 1171 if (error == 0) { 1172 if (sc->alc_process_limit < ALC_PROC_MIN || 1173 sc->alc_process_limit > ALC_PROC_MAX) { 1174 device_printf(sc->alc_dev, 1175 "process_limit value out of range; " 1176 "using default: %d\n", ALC_PROC_DEFAULT); 1177 sc->alc_process_limit = ALC_PROC_DEFAULT; 1178 } 1179 } 1180 1181 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1182 NULL, "ALC statistics"); 1183 parent = SYSCTL_CHILDREN(tree); 1184 1185 /* Rx statistics. */ 1186 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1187 NULL, "Rx MAC statistics"); 1188 child = SYSCTL_CHILDREN(tree); 1189 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1190 &stats->rx_frames, "Good frames"); 1191 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1192 &stats->rx_bcast_frames, "Good broadcast frames"); 1193 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1194 &stats->rx_mcast_frames, "Good multicast frames"); 1195 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1196 &stats->rx_pause_frames, "Pause control frames"); 1197 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1198 &stats->rx_control_frames, "Control frames"); 1199 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1200 &stats->rx_crcerrs, "CRC errors"); 1201 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1202 &stats->rx_lenerrs, "Frames with length mismatched"); 1203 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1204 &stats->rx_bytes, "Good octets"); 1205 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1206 &stats->rx_bcast_bytes, "Good broadcast octets"); 1207 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1208 &stats->rx_mcast_bytes, "Good multicast octets"); 1209 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1210 &stats->rx_runts, "Too short frames"); 1211 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1212 &stats->rx_fragments, "Fragmented frames"); 1213 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1214 &stats->rx_pkts_64, "64 bytes frames"); 1215 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1216 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1218 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1219 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1220 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1221 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1222 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1223 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1224 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1225 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1226 &stats->rx_pkts_1519_max, "1519 to max frames"); 1227 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1228 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1229 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1230 &stats->rx_fifo_oflows, "FIFO overflows"); 1231 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1232 &stats->rx_rrs_errs, "Return status write-back errors"); 1233 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1234 &stats->rx_alignerrs, "Alignment errors"); 1235 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1236 &stats->rx_pkts_filtered, 1237 "Frames dropped due to address filtering"); 1238 1239 /* Tx statistics. */ 1240 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1241 NULL, "Tx MAC statistics"); 1242 child = SYSCTL_CHILDREN(tree); 1243 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1244 &stats->tx_frames, "Good frames"); 1245 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1246 &stats->tx_bcast_frames, "Good broadcast frames"); 1247 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1248 &stats->tx_mcast_frames, "Good multicast frames"); 1249 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1250 &stats->tx_pause_frames, "Pause control frames"); 1251 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1252 &stats->tx_control_frames, "Control frames"); 1253 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1254 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1255 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1256 &stats->tx_excess_defer, "Frames with derferrals"); 1257 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1258 &stats->tx_bytes, "Good octets"); 1259 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1260 &stats->tx_bcast_bytes, "Good broadcast octets"); 1261 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1262 &stats->tx_mcast_bytes, "Good multicast octets"); 1263 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1264 &stats->tx_pkts_64, "64 bytes frames"); 1265 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1266 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1267 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1268 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1269 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1270 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1271 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1272 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1273 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1274 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1275 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1276 &stats->tx_pkts_1519_max, "1519 to max frames"); 1277 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1278 &stats->tx_single_colls, "Single collisions"); 1279 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1280 &stats->tx_multi_colls, "Multiple collisions"); 1281 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1282 &stats->tx_late_colls, "Late collisions"); 1283 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1284 &stats->tx_excess_colls, "Excessive collisions"); 1285 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1286 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1287 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1288 &stats->tx_underrun, "FIFO underruns"); 1289 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1290 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1291 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1292 &stats->tx_lenerrs, "Frames with length mismatched"); 1293 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1294 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1295 } 1296 1297 #undef ALC_SYSCTL_STAT_ADD32 1298 #undef ALC_SYSCTL_STAT_ADD64 1299 1300 struct alc_dmamap_arg { 1301 bus_addr_t alc_busaddr; 1302 }; 1303 1304 static void 1305 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1306 { 1307 struct alc_dmamap_arg *ctx; 1308 1309 if (error != 0) 1310 return; 1311 1312 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1313 1314 ctx = (struct alc_dmamap_arg *)arg; 1315 ctx->alc_busaddr = segs[0].ds_addr; 1316 } 1317 1318 /* 1319 * Normal and high Tx descriptors shares single Tx high address. 1320 * Four Rx descriptor/return rings and CMB shares the same Rx 1321 * high address. 1322 */ 1323 static int 1324 alc_check_boundary(struct alc_softc *sc) 1325 { 1326 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1327 1328 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1329 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1330 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1331 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1332 1333 /* 4GB boundary crossing is not allowed. */ 1334 if ((ALC_ADDR_HI(rx_ring_end) != 1335 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1336 (ALC_ADDR_HI(rr_ring_end) != 1337 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1338 (ALC_ADDR_HI(cmb_end) != 1339 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1340 (ALC_ADDR_HI(tx_ring_end) != 1341 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1342 return (EFBIG); 1343 /* 1344 * Make sure Rx return descriptor/Rx descriptor/CMB use 1345 * the same high address. 1346 */ 1347 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1348 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1349 return (EFBIG); 1350 1351 return (0); 1352 } 1353 1354 static int 1355 alc_dma_alloc(struct alc_softc *sc) 1356 { 1357 struct alc_txdesc *txd; 1358 struct alc_rxdesc *rxd; 1359 bus_addr_t lowaddr; 1360 struct alc_dmamap_arg ctx; 1361 int error, i; 1362 1363 lowaddr = BUS_SPACE_MAXADDR; 1364 again: 1365 /* Create parent DMA tag. */ 1366 error = bus_dma_tag_create( 1367 bus_get_dma_tag(sc->alc_dev), /* parent */ 1368 1, 0, /* alignment, boundary */ 1369 lowaddr, /* lowaddr */ 1370 BUS_SPACE_MAXADDR, /* highaddr */ 1371 NULL, NULL, /* filter, filterarg */ 1372 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1373 0, /* nsegments */ 1374 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1375 0, /* flags */ 1376 NULL, NULL, /* lockfunc, lockarg */ 1377 &sc->alc_cdata.alc_parent_tag); 1378 if (error != 0) { 1379 device_printf(sc->alc_dev, 1380 "could not create parent DMA tag.\n"); 1381 goto fail; 1382 } 1383 1384 /* Create DMA tag for Tx descriptor ring. */ 1385 error = bus_dma_tag_create( 1386 sc->alc_cdata.alc_parent_tag, /* parent */ 1387 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1388 BUS_SPACE_MAXADDR, /* lowaddr */ 1389 BUS_SPACE_MAXADDR, /* highaddr */ 1390 NULL, NULL, /* filter, filterarg */ 1391 ALC_TX_RING_SZ, /* maxsize */ 1392 1, /* nsegments */ 1393 ALC_TX_RING_SZ, /* maxsegsize */ 1394 0, /* flags */ 1395 NULL, NULL, /* lockfunc, lockarg */ 1396 &sc->alc_cdata.alc_tx_ring_tag); 1397 if (error != 0) { 1398 device_printf(sc->alc_dev, 1399 "could not create Tx ring DMA tag.\n"); 1400 goto fail; 1401 } 1402 1403 /* Create DMA tag for Rx free descriptor ring. */ 1404 error = bus_dma_tag_create( 1405 sc->alc_cdata.alc_parent_tag, /* parent */ 1406 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1407 BUS_SPACE_MAXADDR, /* lowaddr */ 1408 BUS_SPACE_MAXADDR, /* highaddr */ 1409 NULL, NULL, /* filter, filterarg */ 1410 ALC_RX_RING_SZ, /* maxsize */ 1411 1, /* nsegments */ 1412 ALC_RX_RING_SZ, /* maxsegsize */ 1413 0, /* flags */ 1414 NULL, NULL, /* lockfunc, lockarg */ 1415 &sc->alc_cdata.alc_rx_ring_tag); 1416 if (error != 0) { 1417 device_printf(sc->alc_dev, 1418 "could not create Rx ring DMA tag.\n"); 1419 goto fail; 1420 } 1421 /* Create DMA tag for Rx return descriptor ring. */ 1422 error = bus_dma_tag_create( 1423 sc->alc_cdata.alc_parent_tag, /* parent */ 1424 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1425 BUS_SPACE_MAXADDR, /* lowaddr */ 1426 BUS_SPACE_MAXADDR, /* highaddr */ 1427 NULL, NULL, /* filter, filterarg */ 1428 ALC_RR_RING_SZ, /* maxsize */ 1429 1, /* nsegments */ 1430 ALC_RR_RING_SZ, /* maxsegsize */ 1431 0, /* flags */ 1432 NULL, NULL, /* lockfunc, lockarg */ 1433 &sc->alc_cdata.alc_rr_ring_tag); 1434 if (error != 0) { 1435 device_printf(sc->alc_dev, 1436 "could not create Rx return ring DMA tag.\n"); 1437 goto fail; 1438 } 1439 1440 /* Create DMA tag for coalescing message block. */ 1441 error = bus_dma_tag_create( 1442 sc->alc_cdata.alc_parent_tag, /* parent */ 1443 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1444 BUS_SPACE_MAXADDR, /* lowaddr */ 1445 BUS_SPACE_MAXADDR, /* highaddr */ 1446 NULL, NULL, /* filter, filterarg */ 1447 ALC_CMB_SZ, /* maxsize */ 1448 1, /* nsegments */ 1449 ALC_CMB_SZ, /* maxsegsize */ 1450 0, /* flags */ 1451 NULL, NULL, /* lockfunc, lockarg */ 1452 &sc->alc_cdata.alc_cmb_tag); 1453 if (error != 0) { 1454 device_printf(sc->alc_dev, 1455 "could not create CMB DMA tag.\n"); 1456 goto fail; 1457 } 1458 /* Create DMA tag for status message block. */ 1459 error = bus_dma_tag_create( 1460 sc->alc_cdata.alc_parent_tag, /* parent */ 1461 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1462 BUS_SPACE_MAXADDR, /* lowaddr */ 1463 BUS_SPACE_MAXADDR, /* highaddr */ 1464 NULL, NULL, /* filter, filterarg */ 1465 ALC_SMB_SZ, /* maxsize */ 1466 1, /* nsegments */ 1467 ALC_SMB_SZ, /* maxsegsize */ 1468 0, /* flags */ 1469 NULL, NULL, /* lockfunc, lockarg */ 1470 &sc->alc_cdata.alc_smb_tag); 1471 if (error != 0) { 1472 device_printf(sc->alc_dev, 1473 "could not create SMB DMA tag.\n"); 1474 goto fail; 1475 } 1476 1477 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1478 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1479 (void **)&sc->alc_rdata.alc_tx_ring, 1480 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1481 &sc->alc_cdata.alc_tx_ring_map); 1482 if (error != 0) { 1483 device_printf(sc->alc_dev, 1484 "could not allocate DMA'able memory for Tx ring.\n"); 1485 goto fail; 1486 } 1487 ctx.alc_busaddr = 0; 1488 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1489 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1490 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1491 if (error != 0 || ctx.alc_busaddr == 0) { 1492 device_printf(sc->alc_dev, 1493 "could not load DMA'able memory for Tx ring.\n"); 1494 goto fail; 1495 } 1496 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1497 1498 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1499 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1500 (void **)&sc->alc_rdata.alc_rx_ring, 1501 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1502 &sc->alc_cdata.alc_rx_ring_map); 1503 if (error != 0) { 1504 device_printf(sc->alc_dev, 1505 "could not allocate DMA'able memory for Rx ring.\n"); 1506 goto fail; 1507 } 1508 ctx.alc_busaddr = 0; 1509 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1510 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1511 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1512 if (error != 0 || ctx.alc_busaddr == 0) { 1513 device_printf(sc->alc_dev, 1514 "could not load DMA'able memory for Rx ring.\n"); 1515 goto fail; 1516 } 1517 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1518 1519 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1520 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1521 (void **)&sc->alc_rdata.alc_rr_ring, 1522 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1523 &sc->alc_cdata.alc_rr_ring_map); 1524 if (error != 0) { 1525 device_printf(sc->alc_dev, 1526 "could not allocate DMA'able memory for Rx return ring.\n"); 1527 goto fail; 1528 } 1529 ctx.alc_busaddr = 0; 1530 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1531 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1532 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1533 if (error != 0 || ctx.alc_busaddr == 0) { 1534 device_printf(sc->alc_dev, 1535 "could not load DMA'able memory for Tx ring.\n"); 1536 goto fail; 1537 } 1538 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1539 1540 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1541 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1542 (void **)&sc->alc_rdata.alc_cmb, 1543 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1544 &sc->alc_cdata.alc_cmb_map); 1545 if (error != 0) { 1546 device_printf(sc->alc_dev, 1547 "could not allocate DMA'able memory for CMB.\n"); 1548 goto fail; 1549 } 1550 ctx.alc_busaddr = 0; 1551 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1552 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1553 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1554 if (error != 0 || ctx.alc_busaddr == 0) { 1555 device_printf(sc->alc_dev, 1556 "could not load DMA'able memory for CMB.\n"); 1557 goto fail; 1558 } 1559 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1560 1561 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1562 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1563 (void **)&sc->alc_rdata.alc_smb, 1564 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1565 &sc->alc_cdata.alc_smb_map); 1566 if (error != 0) { 1567 device_printf(sc->alc_dev, 1568 "could not allocate DMA'able memory for SMB.\n"); 1569 goto fail; 1570 } 1571 ctx.alc_busaddr = 0; 1572 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1573 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1574 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1575 if (error != 0 || ctx.alc_busaddr == 0) { 1576 device_printf(sc->alc_dev, 1577 "could not load DMA'able memory for CMB.\n"); 1578 goto fail; 1579 } 1580 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1581 1582 /* Make sure we've not crossed 4GB boundary. */ 1583 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1584 (error = alc_check_boundary(sc)) != 0) { 1585 device_printf(sc->alc_dev, "4GB boundary crossed, " 1586 "switching to 32bit DMA addressing mode.\n"); 1587 alc_dma_free(sc); 1588 /* 1589 * Limit max allowable DMA address space to 32bit 1590 * and try again. 1591 */ 1592 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1593 goto again; 1594 } 1595 1596 /* 1597 * Create Tx buffer parent tag. 1598 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1599 * so it needs separate parent DMA tag as parent DMA address 1600 * space could be restricted to be within 32bit address space 1601 * by 4GB boundary crossing. 1602 */ 1603 error = bus_dma_tag_create( 1604 bus_get_dma_tag(sc->alc_dev), /* parent */ 1605 1, 0, /* alignment, boundary */ 1606 BUS_SPACE_MAXADDR, /* lowaddr */ 1607 BUS_SPACE_MAXADDR, /* highaddr */ 1608 NULL, NULL, /* filter, filterarg */ 1609 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1610 0, /* nsegments */ 1611 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1612 0, /* flags */ 1613 NULL, NULL, /* lockfunc, lockarg */ 1614 &sc->alc_cdata.alc_buffer_tag); 1615 if (error != 0) { 1616 device_printf(sc->alc_dev, 1617 "could not create parent buffer DMA tag.\n"); 1618 goto fail; 1619 } 1620 1621 /* Create DMA tag for Tx buffers. */ 1622 error = bus_dma_tag_create( 1623 sc->alc_cdata.alc_buffer_tag, /* parent */ 1624 1, 0, /* alignment, boundary */ 1625 BUS_SPACE_MAXADDR, /* lowaddr */ 1626 BUS_SPACE_MAXADDR, /* highaddr */ 1627 NULL, NULL, /* filter, filterarg */ 1628 ALC_TSO_MAXSIZE, /* maxsize */ 1629 ALC_MAXTXSEGS, /* nsegments */ 1630 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1631 0, /* flags */ 1632 NULL, NULL, /* lockfunc, lockarg */ 1633 &sc->alc_cdata.alc_tx_tag); 1634 if (error != 0) { 1635 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1636 goto fail; 1637 } 1638 1639 /* Create DMA tag for Rx buffers. */ 1640 error = bus_dma_tag_create( 1641 sc->alc_cdata.alc_buffer_tag, /* parent */ 1642 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1643 BUS_SPACE_MAXADDR, /* lowaddr */ 1644 BUS_SPACE_MAXADDR, /* highaddr */ 1645 NULL, NULL, /* filter, filterarg */ 1646 MCLBYTES, /* maxsize */ 1647 1, /* nsegments */ 1648 MCLBYTES, /* maxsegsize */ 1649 0, /* flags */ 1650 NULL, NULL, /* lockfunc, lockarg */ 1651 &sc->alc_cdata.alc_rx_tag); 1652 if (error != 0) { 1653 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1654 goto fail; 1655 } 1656 /* Create DMA maps for Tx buffers. */ 1657 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1658 txd = &sc->alc_cdata.alc_txdesc[i]; 1659 txd->tx_m = NULL; 1660 txd->tx_dmamap = NULL; 1661 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1662 &txd->tx_dmamap); 1663 if (error != 0) { 1664 device_printf(sc->alc_dev, 1665 "could not create Tx dmamap.\n"); 1666 goto fail; 1667 } 1668 } 1669 /* Create DMA maps for Rx buffers. */ 1670 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1671 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1672 device_printf(sc->alc_dev, 1673 "could not create spare Rx dmamap.\n"); 1674 goto fail; 1675 } 1676 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1677 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1678 rxd->rx_m = NULL; 1679 rxd->rx_dmamap = NULL; 1680 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1681 &rxd->rx_dmamap); 1682 if (error != 0) { 1683 device_printf(sc->alc_dev, 1684 "could not create Rx dmamap.\n"); 1685 goto fail; 1686 } 1687 } 1688 1689 fail: 1690 return (error); 1691 } 1692 1693 static void 1694 alc_dma_free(struct alc_softc *sc) 1695 { 1696 struct alc_txdesc *txd; 1697 struct alc_rxdesc *rxd; 1698 int i; 1699 1700 /* Tx buffers. */ 1701 if (sc->alc_cdata.alc_tx_tag != NULL) { 1702 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1703 txd = &sc->alc_cdata.alc_txdesc[i]; 1704 if (txd->tx_dmamap != NULL) { 1705 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1706 txd->tx_dmamap); 1707 txd->tx_dmamap = NULL; 1708 } 1709 } 1710 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1711 sc->alc_cdata.alc_tx_tag = NULL; 1712 } 1713 /* Rx buffers */ 1714 if (sc->alc_cdata.alc_rx_tag != NULL) { 1715 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1716 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1717 if (rxd->rx_dmamap != NULL) { 1718 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1719 rxd->rx_dmamap); 1720 rxd->rx_dmamap = NULL; 1721 } 1722 } 1723 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1724 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1725 sc->alc_cdata.alc_rx_sparemap); 1726 sc->alc_cdata.alc_rx_sparemap = NULL; 1727 } 1728 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1729 sc->alc_cdata.alc_rx_tag = NULL; 1730 } 1731 /* Tx descriptor ring. */ 1732 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1733 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1734 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1735 sc->alc_cdata.alc_tx_ring_map); 1736 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1737 sc->alc_rdata.alc_tx_ring != NULL) 1738 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1739 sc->alc_rdata.alc_tx_ring, 1740 sc->alc_cdata.alc_tx_ring_map); 1741 sc->alc_rdata.alc_tx_ring = NULL; 1742 sc->alc_cdata.alc_tx_ring_map = NULL; 1743 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1744 sc->alc_cdata.alc_tx_ring_tag = NULL; 1745 } 1746 /* Rx ring. */ 1747 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1748 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1749 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1750 sc->alc_cdata.alc_rx_ring_map); 1751 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1752 sc->alc_rdata.alc_rx_ring != NULL) 1753 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1754 sc->alc_rdata.alc_rx_ring, 1755 sc->alc_cdata.alc_rx_ring_map); 1756 sc->alc_rdata.alc_rx_ring = NULL; 1757 sc->alc_cdata.alc_rx_ring_map = NULL; 1758 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1759 sc->alc_cdata.alc_rx_ring_tag = NULL; 1760 } 1761 /* Rx return ring. */ 1762 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1763 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1764 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1765 sc->alc_cdata.alc_rr_ring_map); 1766 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1767 sc->alc_rdata.alc_rr_ring != NULL) 1768 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1769 sc->alc_rdata.alc_rr_ring, 1770 sc->alc_cdata.alc_rr_ring_map); 1771 sc->alc_rdata.alc_rr_ring = NULL; 1772 sc->alc_cdata.alc_rr_ring_map = NULL; 1773 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1774 sc->alc_cdata.alc_rr_ring_tag = NULL; 1775 } 1776 /* CMB block */ 1777 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1778 if (sc->alc_cdata.alc_cmb_map != NULL) 1779 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1780 sc->alc_cdata.alc_cmb_map); 1781 if (sc->alc_cdata.alc_cmb_map != NULL && 1782 sc->alc_rdata.alc_cmb != NULL) 1783 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1784 sc->alc_rdata.alc_cmb, 1785 sc->alc_cdata.alc_cmb_map); 1786 sc->alc_rdata.alc_cmb = NULL; 1787 sc->alc_cdata.alc_cmb_map = NULL; 1788 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1789 sc->alc_cdata.alc_cmb_tag = NULL; 1790 } 1791 /* SMB block */ 1792 if (sc->alc_cdata.alc_smb_tag != NULL) { 1793 if (sc->alc_cdata.alc_smb_map != NULL) 1794 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1795 sc->alc_cdata.alc_smb_map); 1796 if (sc->alc_cdata.alc_smb_map != NULL && 1797 sc->alc_rdata.alc_smb != NULL) 1798 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1799 sc->alc_rdata.alc_smb, 1800 sc->alc_cdata.alc_smb_map); 1801 sc->alc_rdata.alc_smb = NULL; 1802 sc->alc_cdata.alc_smb_map = NULL; 1803 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1804 sc->alc_cdata.alc_smb_tag = NULL; 1805 } 1806 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1807 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1808 sc->alc_cdata.alc_buffer_tag = NULL; 1809 } 1810 if (sc->alc_cdata.alc_parent_tag != NULL) { 1811 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1812 sc->alc_cdata.alc_parent_tag = NULL; 1813 } 1814 } 1815 1816 static int 1817 alc_shutdown(device_t dev) 1818 { 1819 1820 return (alc_suspend(dev)); 1821 } 1822 1823 /* 1824 * Note, this driver resets the link speed to 10/100Mbps by 1825 * restarting auto-negotiation in suspend/shutdown phase but we 1826 * don't know whether that auto-negotiation would succeed or not 1827 * as driver has no control after powering off/suspend operation. 1828 * If the renegotiation fail WOL may not work. Running at 1Gbps 1829 * will draw more power than 375mA at 3.3V which is specified in 1830 * PCI specification and that would result in complete 1831 * shutdowning power to ethernet controller. 1832 * 1833 * TODO 1834 * Save current negotiated media speed/duplex/flow-control to 1835 * softc and restore the same link again after resuming. PHY 1836 * handling such as power down/resetting to 100Mbps may be better 1837 * handled in suspend method in phy driver. 1838 */ 1839 static void 1840 alc_setlinkspeed(struct alc_softc *sc) 1841 { 1842 struct mii_data *mii; 1843 int aneg, i; 1844 1845 mii = device_get_softc(sc->alc_miibus); 1846 mii_pollstat(mii); 1847 aneg = 0; 1848 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1849 (IFM_ACTIVE | IFM_AVALID)) { 1850 switch IFM_SUBTYPE(mii->mii_media_active) { 1851 case IFM_10_T: 1852 case IFM_100_TX: 1853 return; 1854 case IFM_1000_T: 1855 aneg++; 1856 break; 1857 default: 1858 break; 1859 } 1860 } 1861 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1862 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1863 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1864 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1865 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1866 DELAY(1000); 1867 if (aneg != 0) { 1868 /* 1869 * Poll link state until alc(4) get a 10/100Mbps link. 1870 */ 1871 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1872 mii_pollstat(mii); 1873 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1874 == (IFM_ACTIVE | IFM_AVALID)) { 1875 switch (IFM_SUBTYPE( 1876 mii->mii_media_active)) { 1877 case IFM_10_T: 1878 case IFM_100_TX: 1879 alc_mac_config(sc); 1880 return; 1881 default: 1882 break; 1883 } 1884 } 1885 ALC_UNLOCK(sc); 1886 pause("alclnk", hz); 1887 ALC_LOCK(sc); 1888 } 1889 if (i == MII_ANEGTICKS_GIGE) 1890 device_printf(sc->alc_dev, 1891 "establishing a link failed, WOL may not work!"); 1892 } 1893 /* 1894 * No link, force MAC to have 100Mbps, full-duplex link. 1895 * This is the last resort and may/may not work. 1896 */ 1897 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1898 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1899 alc_mac_config(sc); 1900 } 1901 1902 static void 1903 alc_setwol(struct alc_softc *sc) 1904 { 1905 struct ifnet *ifp; 1906 uint32_t reg, pmcs; 1907 uint16_t pmstat; 1908 1909 ALC_LOCK_ASSERT(sc); 1910 1911 alc_disable_l0s_l1(sc); 1912 ifp = sc->alc_ifp; 1913 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1914 /* Disable WOL. */ 1915 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1916 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1917 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1918 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1919 /* Force PHY power down. */ 1920 alc_phy_down(sc); 1921 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1922 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1923 return; 1924 } 1925 1926 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1927 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1928 alc_setlinkspeed(sc); 1929 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1930 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1931 } 1932 1933 pmcs = 0; 1934 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1935 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1936 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1937 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1938 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1939 MAC_CFG_BCAST); 1940 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1941 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1942 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1943 reg |= MAC_CFG_RX_ENB; 1944 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1945 1946 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1947 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1948 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1949 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1950 /* WOL disabled, PHY power down. */ 1951 alc_phy_down(sc); 1952 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1953 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1954 } 1955 /* Request PME. */ 1956 pmstat = pci_read_config(sc->alc_dev, 1957 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1958 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1959 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1960 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1961 pci_write_config(sc->alc_dev, 1962 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1963 } 1964 1965 static int 1966 alc_suspend(device_t dev) 1967 { 1968 struct alc_softc *sc; 1969 1970 sc = device_get_softc(dev); 1971 1972 ALC_LOCK(sc); 1973 alc_stop(sc); 1974 alc_setwol(sc); 1975 ALC_UNLOCK(sc); 1976 1977 return (0); 1978 } 1979 1980 static int 1981 alc_resume(device_t dev) 1982 { 1983 struct alc_softc *sc; 1984 struct ifnet *ifp; 1985 uint16_t pmstat; 1986 1987 sc = device_get_softc(dev); 1988 1989 ALC_LOCK(sc); 1990 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1991 /* Disable PME and clear PME status. */ 1992 pmstat = pci_read_config(sc->alc_dev, 1993 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1994 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1995 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1996 pci_write_config(sc->alc_dev, 1997 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1998 } 1999 } 2000 /* Reset PHY. */ 2001 alc_phy_reset(sc); 2002 ifp = sc->alc_ifp; 2003 if ((ifp->if_flags & IFF_UP) != 0) { 2004 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2005 alc_init_locked(sc); 2006 } 2007 ALC_UNLOCK(sc); 2008 2009 return (0); 2010 } 2011 2012 static int 2013 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2014 { 2015 struct alc_txdesc *txd, *txd_last; 2016 struct tx_desc *desc; 2017 struct mbuf *m; 2018 struct ip *ip; 2019 struct tcphdr *tcp; 2020 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2021 bus_dmamap_t map; 2022 uint32_t cflags, hdrlen, poff, vtag; 2023 int error, idx, nsegs, prod; 2024 2025 ALC_LOCK_ASSERT(sc); 2026 2027 M_ASSERTPKTHDR((*m_head)); 2028 2029 m = *m_head; 2030 ip = NULL; 2031 tcp = NULL; 2032 poff = 0; 2033 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2034 /* 2035 * AR813x/AR815x requires offset of TCP/UDP header in its 2036 * Tx descriptor to perform Tx checksum offloading. TSO 2037 * also requires TCP header offset and modification of 2038 * IP/TCP header. This kind of operation takes many CPU 2039 * cycles on FreeBSD so fast host CPU is required to get 2040 * smooth TSO performance. 2041 */ 2042 2043 if (M_WRITABLE(m) == 0) { 2044 /* Get a writable copy. */ 2045 m = m_dup(*m_head, M_DONTWAIT); 2046 /* Release original mbufs. */ 2047 m_freem(*m_head); 2048 if (m == NULL) { 2049 *m_head = NULL; 2050 return (ENOBUFS); 2051 } 2052 *m_head = m; 2053 } 2054 2055 m = m_pullup(m, sizeof(struct ether_header) + 2056 sizeof(struct ip)); 2057 if (m == NULL) { 2058 *m_head = NULL; 2059 return (ENOBUFS); 2060 } 2061 ip = (struct ip *)(mtod(m, char *) + 2062 sizeof(struct ether_header)); 2063 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 2064 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2065 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2066 if (m == NULL) { 2067 *m_head = NULL; 2068 return (ENOBUFS); 2069 } 2070 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2071 m = m_pullup(m, poff + (tcp->th_off << 2)); 2072 if (m == NULL) { 2073 *m_head = NULL; 2074 return (ENOBUFS); 2075 } 2076 /* 2077 * Due to strict adherence of Microsoft NDIS 2078 * Large Send specification, hardware expects 2079 * a pseudo TCP checksum inserted by upper 2080 * stack. Unfortunately the pseudo TCP 2081 * checksum that NDIS refers to does not include 2082 * TCP payload length so driver should recompute 2083 * the pseudo checksum here. Hopefully this 2084 * wouldn't be much burden on modern CPUs. 2085 * 2086 * Reset IP checksum and recompute TCP pseudo 2087 * checksum as NDIS specification said. 2088 */ 2089 ip->ip_sum = 0; 2090 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2091 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2092 } 2093 *m_head = m; 2094 } 2095 2096 prod = sc->alc_cdata.alc_tx_prod; 2097 txd = &sc->alc_cdata.alc_txdesc[prod]; 2098 txd_last = txd; 2099 map = txd->tx_dmamap; 2100 2101 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2102 *m_head, txsegs, &nsegs, 0); 2103 if (error == EFBIG) { 2104 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 2105 if (m == NULL) { 2106 m_freem(*m_head); 2107 *m_head = NULL; 2108 return (ENOMEM); 2109 } 2110 *m_head = m; 2111 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2112 *m_head, txsegs, &nsegs, 0); 2113 if (error != 0) { 2114 m_freem(*m_head); 2115 *m_head = NULL; 2116 return (error); 2117 } 2118 } else if (error != 0) 2119 return (error); 2120 if (nsegs == 0) { 2121 m_freem(*m_head); 2122 *m_head = NULL; 2123 return (EIO); 2124 } 2125 2126 /* Check descriptor overrun. */ 2127 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2128 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2129 return (ENOBUFS); 2130 } 2131 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2132 2133 m = *m_head; 2134 cflags = TD_ETHERNET; 2135 vtag = 0; 2136 desc = NULL; 2137 idx = 0; 2138 /* Configure VLAN hardware tag insertion. */ 2139 if ((m->m_flags & M_VLANTAG) != 0) { 2140 vtag = htons(m->m_pkthdr.ether_vtag); 2141 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2142 cflags |= TD_INS_VLAN_TAG; 2143 } 2144 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2145 /* Request TSO and set MSS. */ 2146 cflags |= TD_TSO | TD_TSO_DESCV1; 2147 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2148 TD_MSS_MASK; 2149 /* Set TCP header offset. */ 2150 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2151 TD_TCPHDR_OFFSET_MASK; 2152 /* 2153 * AR813x/AR815x requires the first buffer should 2154 * only hold IP/TCP header data. Payload should 2155 * be handled in other descriptors. 2156 */ 2157 hdrlen = poff + (tcp->th_off << 2); 2158 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2159 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2160 desc->flags = htole32(cflags); 2161 desc->addr = htole64(txsegs[0].ds_addr); 2162 sc->alc_cdata.alc_tx_cnt++; 2163 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2164 if (m->m_len - hdrlen > 0) { 2165 /* Handle remaining payload of the first fragment. */ 2166 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2167 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2168 vtag)); 2169 desc->flags = htole32(cflags); 2170 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2171 sc->alc_cdata.alc_tx_cnt++; 2172 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2173 } 2174 /* Handle remaining fragments. */ 2175 idx = 1; 2176 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2177 /* Configure Tx checksum offload. */ 2178 #ifdef ALC_USE_CUSTOM_CSUM 2179 cflags |= TD_CUSTOM_CSUM; 2180 /* Set checksum start offset. */ 2181 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2182 TD_PLOAD_OFFSET_MASK; 2183 /* Set checksum insertion position of TCP/UDP. */ 2184 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2185 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2186 #else 2187 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2188 cflags |= TD_IPCSUM; 2189 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2190 cflags |= TD_TCPCSUM; 2191 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2192 cflags |= TD_UDPCSUM; 2193 /* Set TCP/UDP header offset. */ 2194 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2195 TD_L4HDR_OFFSET_MASK; 2196 #endif 2197 } 2198 for (; idx < nsegs; idx++) { 2199 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2200 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2201 desc->flags = htole32(cflags); 2202 desc->addr = htole64(txsegs[idx].ds_addr); 2203 sc->alc_cdata.alc_tx_cnt++; 2204 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2205 } 2206 /* Update producer index. */ 2207 sc->alc_cdata.alc_tx_prod = prod; 2208 2209 /* Finally set EOP on the last descriptor. */ 2210 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2211 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2212 desc->flags |= htole32(TD_EOP); 2213 2214 /* Swap dmamap of the first and the last. */ 2215 txd = &sc->alc_cdata.alc_txdesc[prod]; 2216 map = txd_last->tx_dmamap; 2217 txd_last->tx_dmamap = txd->tx_dmamap; 2218 txd->tx_dmamap = map; 2219 txd->tx_m = m; 2220 2221 return (0); 2222 } 2223 2224 static void 2225 alc_tx_task(void *arg, int pending) 2226 { 2227 struct ifnet *ifp; 2228 2229 ifp = (struct ifnet *)arg; 2230 alc_start(ifp); 2231 } 2232 2233 static void 2234 alc_start(struct ifnet *ifp) 2235 { 2236 struct alc_softc *sc; 2237 struct mbuf *m_head; 2238 int enq; 2239 2240 sc = ifp->if_softc; 2241 2242 ALC_LOCK(sc); 2243 2244 /* Reclaim transmitted frames. */ 2245 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2246 alc_txeof(sc); 2247 2248 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2249 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2250 ALC_UNLOCK(sc); 2251 return; 2252 } 2253 2254 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2255 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2256 if (m_head == NULL) 2257 break; 2258 /* 2259 * Pack the data into the transmit ring. If we 2260 * don't have room, set the OACTIVE flag and wait 2261 * for the NIC to drain the ring. 2262 */ 2263 if (alc_encap(sc, &m_head)) { 2264 if (m_head == NULL) 2265 break; 2266 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2267 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2268 break; 2269 } 2270 2271 enq++; 2272 /* 2273 * If there's a BPF listener, bounce a copy of this frame 2274 * to him. 2275 */ 2276 ETHER_BPF_MTAP(ifp, m_head); 2277 } 2278 2279 if (enq > 0) { 2280 /* Sync descriptors. */ 2281 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2282 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2283 /* Kick. Assume we're using normal Tx priority queue. */ 2284 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2285 (sc->alc_cdata.alc_tx_prod << 2286 MBOX_TD_PROD_LO_IDX_SHIFT) & 2287 MBOX_TD_PROD_LO_IDX_MASK); 2288 /* Set a timeout in case the chip goes out to lunch. */ 2289 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2290 } 2291 2292 ALC_UNLOCK(sc); 2293 } 2294 2295 static void 2296 alc_watchdog(struct alc_softc *sc) 2297 { 2298 struct ifnet *ifp; 2299 2300 ALC_LOCK_ASSERT(sc); 2301 2302 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2303 return; 2304 2305 ifp = sc->alc_ifp; 2306 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2307 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2308 ifp->if_oerrors++; 2309 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2310 alc_init_locked(sc); 2311 return; 2312 } 2313 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2314 ifp->if_oerrors++; 2315 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2316 alc_init_locked(sc); 2317 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2318 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2319 } 2320 2321 static int 2322 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2323 { 2324 struct alc_softc *sc; 2325 struct ifreq *ifr; 2326 struct mii_data *mii; 2327 int error, mask; 2328 2329 sc = ifp->if_softc; 2330 ifr = (struct ifreq *)data; 2331 error = 0; 2332 switch (cmd) { 2333 case SIOCSIFMTU: 2334 if (ifr->ifr_mtu < ETHERMIN || 2335 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2336 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2337 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2338 ifr->ifr_mtu > ETHERMTU)) 2339 error = EINVAL; 2340 else if (ifp->if_mtu != ifr->ifr_mtu) { 2341 ALC_LOCK(sc); 2342 ifp->if_mtu = ifr->ifr_mtu; 2343 /* AR813x/AR815x has 13 bits MSS field. */ 2344 if (ifp->if_mtu > ALC_TSO_MTU && 2345 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2346 ifp->if_capenable &= ~IFCAP_TSO4; 2347 ifp->if_hwassist &= ~CSUM_TSO; 2348 VLAN_CAPABILITIES(ifp); 2349 } 2350 ALC_UNLOCK(sc); 2351 } 2352 break; 2353 case SIOCSIFFLAGS: 2354 ALC_LOCK(sc); 2355 if ((ifp->if_flags & IFF_UP) != 0) { 2356 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2357 ((ifp->if_flags ^ sc->alc_if_flags) & 2358 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2359 alc_rxfilter(sc); 2360 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2361 alc_init_locked(sc); 2362 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2363 alc_stop(sc); 2364 sc->alc_if_flags = ifp->if_flags; 2365 ALC_UNLOCK(sc); 2366 break; 2367 case SIOCADDMULTI: 2368 case SIOCDELMULTI: 2369 ALC_LOCK(sc); 2370 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2371 alc_rxfilter(sc); 2372 ALC_UNLOCK(sc); 2373 break; 2374 case SIOCSIFMEDIA: 2375 case SIOCGIFMEDIA: 2376 mii = device_get_softc(sc->alc_miibus); 2377 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2378 break; 2379 case SIOCSIFCAP: 2380 ALC_LOCK(sc); 2381 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2382 if ((mask & IFCAP_TXCSUM) != 0 && 2383 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2384 ifp->if_capenable ^= IFCAP_TXCSUM; 2385 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2386 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2387 else 2388 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2389 } 2390 if ((mask & IFCAP_TSO4) != 0 && 2391 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2392 ifp->if_capenable ^= IFCAP_TSO4; 2393 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2394 /* AR813x/AR815x has 13 bits MSS field. */ 2395 if (ifp->if_mtu > ALC_TSO_MTU) { 2396 ifp->if_capenable &= ~IFCAP_TSO4; 2397 ifp->if_hwassist &= ~CSUM_TSO; 2398 } else 2399 ifp->if_hwassist |= CSUM_TSO; 2400 } else 2401 ifp->if_hwassist &= ~CSUM_TSO; 2402 } 2403 if ((mask & IFCAP_WOL_MCAST) != 0 && 2404 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2405 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2406 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2407 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2408 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2409 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2410 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2411 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2412 alc_rxvlan(sc); 2413 } 2414 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2415 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2416 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2417 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2418 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2419 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2420 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2421 ifp->if_capenable &= 2422 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2423 ALC_UNLOCK(sc); 2424 VLAN_CAPABILITIES(ifp); 2425 break; 2426 default: 2427 error = ether_ioctl(ifp, cmd, data); 2428 break; 2429 } 2430 2431 return (error); 2432 } 2433 2434 static void 2435 alc_mac_config(struct alc_softc *sc) 2436 { 2437 struct mii_data *mii; 2438 uint32_t reg; 2439 2440 ALC_LOCK_ASSERT(sc); 2441 2442 mii = device_get_softc(sc->alc_miibus); 2443 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2444 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2445 MAC_CFG_SPEED_MASK); 2446 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2447 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2448 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2449 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2450 /* Reprogram MAC with resolved speed/duplex. */ 2451 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2452 case IFM_10_T: 2453 case IFM_100_TX: 2454 reg |= MAC_CFG_SPEED_10_100; 2455 break; 2456 case IFM_1000_T: 2457 reg |= MAC_CFG_SPEED_1000; 2458 break; 2459 } 2460 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2461 reg |= MAC_CFG_FULL_DUPLEX; 2462 #ifdef notyet 2463 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2464 reg |= MAC_CFG_TX_FC; 2465 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2466 reg |= MAC_CFG_RX_FC; 2467 #endif 2468 } 2469 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2470 } 2471 2472 static void 2473 alc_stats_clear(struct alc_softc *sc) 2474 { 2475 struct smb sb, *smb; 2476 uint32_t *reg; 2477 int i; 2478 2479 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2480 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2481 sc->alc_cdata.alc_smb_map, 2482 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2483 smb = sc->alc_rdata.alc_smb; 2484 /* Update done, clear. */ 2485 smb->updated = 0; 2486 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2487 sc->alc_cdata.alc_smb_map, 2488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2489 } else { 2490 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2491 reg++) { 2492 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2493 i += sizeof(uint32_t); 2494 } 2495 /* Read Tx statistics. */ 2496 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2497 reg++) { 2498 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2499 i += sizeof(uint32_t); 2500 } 2501 } 2502 } 2503 2504 static void 2505 alc_stats_update(struct alc_softc *sc) 2506 { 2507 struct alc_hw_stats *stat; 2508 struct smb sb, *smb; 2509 struct ifnet *ifp; 2510 uint32_t *reg; 2511 int i; 2512 2513 ALC_LOCK_ASSERT(sc); 2514 2515 ifp = sc->alc_ifp; 2516 stat = &sc->alc_stats; 2517 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2518 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2519 sc->alc_cdata.alc_smb_map, 2520 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2521 smb = sc->alc_rdata.alc_smb; 2522 if (smb->updated == 0) 2523 return; 2524 } else { 2525 smb = &sb; 2526 /* Read Rx statistics. */ 2527 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2528 reg++) { 2529 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2530 i += sizeof(uint32_t); 2531 } 2532 /* Read Tx statistics. */ 2533 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2534 reg++) { 2535 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2536 i += sizeof(uint32_t); 2537 } 2538 } 2539 2540 /* Rx stats. */ 2541 stat->rx_frames += smb->rx_frames; 2542 stat->rx_bcast_frames += smb->rx_bcast_frames; 2543 stat->rx_mcast_frames += smb->rx_mcast_frames; 2544 stat->rx_pause_frames += smb->rx_pause_frames; 2545 stat->rx_control_frames += smb->rx_control_frames; 2546 stat->rx_crcerrs += smb->rx_crcerrs; 2547 stat->rx_lenerrs += smb->rx_lenerrs; 2548 stat->rx_bytes += smb->rx_bytes; 2549 stat->rx_runts += smb->rx_runts; 2550 stat->rx_fragments += smb->rx_fragments; 2551 stat->rx_pkts_64 += smb->rx_pkts_64; 2552 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2553 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2554 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2555 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2556 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2557 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2558 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2559 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2560 stat->rx_rrs_errs += smb->rx_rrs_errs; 2561 stat->rx_alignerrs += smb->rx_alignerrs; 2562 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2563 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2564 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2565 2566 /* Tx stats. */ 2567 stat->tx_frames += smb->tx_frames; 2568 stat->tx_bcast_frames += smb->tx_bcast_frames; 2569 stat->tx_mcast_frames += smb->tx_mcast_frames; 2570 stat->tx_pause_frames += smb->tx_pause_frames; 2571 stat->tx_excess_defer += smb->tx_excess_defer; 2572 stat->tx_control_frames += smb->tx_control_frames; 2573 stat->tx_deferred += smb->tx_deferred; 2574 stat->tx_bytes += smb->tx_bytes; 2575 stat->tx_pkts_64 += smb->tx_pkts_64; 2576 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2577 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2578 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2579 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2580 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2581 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2582 stat->tx_single_colls += smb->tx_single_colls; 2583 stat->tx_multi_colls += smb->tx_multi_colls; 2584 stat->tx_late_colls += smb->tx_late_colls; 2585 stat->tx_excess_colls += smb->tx_excess_colls; 2586 stat->tx_abort += smb->tx_abort; 2587 stat->tx_underrun += smb->tx_underrun; 2588 stat->tx_desc_underrun += smb->tx_desc_underrun; 2589 stat->tx_lenerrs += smb->tx_lenerrs; 2590 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2591 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2592 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2593 2594 /* Update counters in ifnet. */ 2595 ifp->if_opackets += smb->tx_frames; 2596 2597 ifp->if_collisions += smb->tx_single_colls + 2598 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2599 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2600 2601 /* 2602 * XXX 2603 * tx_pkts_truncated counter looks suspicious. It constantly 2604 * increments with no sign of Tx errors. This may indicate 2605 * the counter name is not correct one so I've removed the 2606 * counter in output errors. 2607 */ 2608 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2609 smb->tx_underrun; 2610 2611 ifp->if_ipackets += smb->rx_frames; 2612 2613 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2614 smb->rx_runts + smb->rx_pkts_truncated + 2615 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2616 smb->rx_alignerrs; 2617 2618 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2619 /* Update done, clear. */ 2620 smb->updated = 0; 2621 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2622 sc->alc_cdata.alc_smb_map, 2623 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2624 } 2625 } 2626 2627 static int 2628 alc_intr(void *arg) 2629 { 2630 struct alc_softc *sc; 2631 uint32_t status; 2632 2633 sc = (struct alc_softc *)arg; 2634 2635 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2636 if ((status & ALC_INTRS) == 0) 2637 return (FILTER_STRAY); 2638 /* Disable interrupts. */ 2639 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2640 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2641 2642 return (FILTER_HANDLED); 2643 } 2644 2645 static void 2646 alc_int_task(void *arg, int pending) 2647 { 2648 struct alc_softc *sc; 2649 struct ifnet *ifp; 2650 uint32_t status; 2651 int more; 2652 2653 sc = (struct alc_softc *)arg; 2654 ifp = sc->alc_ifp; 2655 2656 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2657 more = atomic_readandclear_int(&sc->alc_morework); 2658 if (more != 0) 2659 status |= INTR_RX_PKT; 2660 if ((status & ALC_INTRS) == 0) 2661 goto done; 2662 2663 /* Acknowledge interrupts but still disable interrupts. */ 2664 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2665 2666 more = 0; 2667 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2668 if ((status & INTR_RX_PKT) != 0) { 2669 more = alc_rxintr(sc, sc->alc_process_limit); 2670 if (more == EAGAIN) 2671 atomic_set_int(&sc->alc_morework, 1); 2672 else if (more == EIO) { 2673 ALC_LOCK(sc); 2674 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2675 alc_init_locked(sc); 2676 ALC_UNLOCK(sc); 2677 return; 2678 } 2679 } 2680 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2681 INTR_TXQ_TO_RST)) != 0) { 2682 if ((status & INTR_DMA_RD_TO_RST) != 0) 2683 device_printf(sc->alc_dev, 2684 "DMA read error! -- resetting\n"); 2685 if ((status & INTR_DMA_WR_TO_RST) != 0) 2686 device_printf(sc->alc_dev, 2687 "DMA write error! -- resetting\n"); 2688 if ((status & INTR_TXQ_TO_RST) != 0) 2689 device_printf(sc->alc_dev, 2690 "TxQ reset! -- resetting\n"); 2691 ALC_LOCK(sc); 2692 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2693 alc_init_locked(sc); 2694 ALC_UNLOCK(sc); 2695 return; 2696 } 2697 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2698 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2699 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2700 } 2701 2702 if (more == EAGAIN || 2703 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2704 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2705 return; 2706 } 2707 2708 done: 2709 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2710 /* Re-enable interrupts if we're running. */ 2711 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2712 } 2713 } 2714 2715 static void 2716 alc_txeof(struct alc_softc *sc) 2717 { 2718 struct ifnet *ifp; 2719 struct alc_txdesc *txd; 2720 uint32_t cons, prod; 2721 int prog; 2722 2723 ALC_LOCK_ASSERT(sc); 2724 2725 ifp = sc->alc_ifp; 2726 2727 if (sc->alc_cdata.alc_tx_cnt == 0) 2728 return; 2729 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2730 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2731 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2732 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2733 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2734 prod = sc->alc_rdata.alc_cmb->cons; 2735 } else 2736 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2737 /* Assume we're using normal Tx priority queue. */ 2738 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2739 MBOX_TD_CONS_LO_IDX_SHIFT; 2740 cons = sc->alc_cdata.alc_tx_cons; 2741 /* 2742 * Go through our Tx list and free mbufs for those 2743 * frames which have been transmitted. 2744 */ 2745 for (prog = 0; cons != prod; prog++, 2746 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2747 if (sc->alc_cdata.alc_tx_cnt <= 0) 2748 break; 2749 prog++; 2750 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2751 sc->alc_cdata.alc_tx_cnt--; 2752 txd = &sc->alc_cdata.alc_txdesc[cons]; 2753 if (txd->tx_m != NULL) { 2754 /* Reclaim transmitted mbufs. */ 2755 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2756 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2757 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2758 txd->tx_dmamap); 2759 m_freem(txd->tx_m); 2760 txd->tx_m = NULL; 2761 } 2762 } 2763 2764 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2765 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2766 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2767 sc->alc_cdata.alc_tx_cons = cons; 2768 /* 2769 * Unarm watchdog timer only when there is no pending 2770 * frames in Tx queue. 2771 */ 2772 if (sc->alc_cdata.alc_tx_cnt == 0) 2773 sc->alc_watchdog_timer = 0; 2774 } 2775 2776 static int 2777 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2778 { 2779 struct mbuf *m; 2780 bus_dma_segment_t segs[1]; 2781 bus_dmamap_t map; 2782 int nsegs; 2783 2784 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2785 if (m == NULL) 2786 return (ENOBUFS); 2787 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2788 #ifndef __NO_STRICT_ALIGNMENT 2789 m_adj(m, sizeof(uint64_t)); 2790 #endif 2791 2792 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2793 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2794 m_freem(m); 2795 return (ENOBUFS); 2796 } 2797 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2798 2799 if (rxd->rx_m != NULL) { 2800 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2801 BUS_DMASYNC_POSTREAD); 2802 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2803 } 2804 map = rxd->rx_dmamap; 2805 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2806 sc->alc_cdata.alc_rx_sparemap = map; 2807 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2808 BUS_DMASYNC_PREREAD); 2809 rxd->rx_m = m; 2810 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2811 return (0); 2812 } 2813 2814 static int 2815 alc_rxintr(struct alc_softc *sc, int count) 2816 { 2817 struct ifnet *ifp; 2818 struct rx_rdesc *rrd; 2819 uint32_t nsegs, status; 2820 int rr_cons, prog; 2821 2822 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2823 sc->alc_cdata.alc_rr_ring_map, 2824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2825 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2826 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2827 rr_cons = sc->alc_cdata.alc_rr_cons; 2828 ifp = sc->alc_ifp; 2829 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2830 if (count-- <= 0) 2831 break; 2832 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2833 status = le32toh(rrd->status); 2834 if ((status & RRD_VALID) == 0) 2835 break; 2836 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2837 if (nsegs == 0) { 2838 /* This should not happen! */ 2839 device_printf(sc->alc_dev, 2840 "unexpected segment count -- resetting\n"); 2841 return (EIO); 2842 } 2843 alc_rxeof(sc, rrd); 2844 /* Clear Rx return status. */ 2845 rrd->status = 0; 2846 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2847 sc->alc_cdata.alc_rx_cons += nsegs; 2848 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2849 prog += nsegs; 2850 } 2851 2852 if (prog > 0) { 2853 /* Update the consumer index. */ 2854 sc->alc_cdata.alc_rr_cons = rr_cons; 2855 /* Sync Rx return descriptors. */ 2856 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2857 sc->alc_cdata.alc_rr_ring_map, 2858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2859 /* 2860 * Sync updated Rx descriptors such that controller see 2861 * modified buffer addresses. 2862 */ 2863 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2864 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2865 /* 2866 * Let controller know availability of new Rx buffers. 2867 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2868 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2869 * only when Rx buffer pre-fetching is required. In 2870 * addition we already set ALC_RX_RD_FREE_THRESH to 2871 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2872 * it still seems that pre-fetching needs more 2873 * experimentation. 2874 */ 2875 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2876 sc->alc_cdata.alc_rx_cons); 2877 } 2878 2879 return (count > 0 ? 0 : EAGAIN); 2880 } 2881 2882 #ifndef __NO_STRICT_ALIGNMENT 2883 static struct mbuf * 2884 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2885 { 2886 struct mbuf *n; 2887 int i; 2888 uint16_t *src, *dst; 2889 2890 src = mtod(m, uint16_t *); 2891 dst = src - 3; 2892 2893 if (m->m_next == NULL) { 2894 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2895 *dst++ = *src++; 2896 m->m_data -= 6; 2897 return (m); 2898 } 2899 /* 2900 * Append a new mbuf to received mbuf chain and copy ethernet 2901 * header from the mbuf chain. This can save lots of CPU 2902 * cycles for jumbo frame. 2903 */ 2904 MGETHDR(n, M_DONTWAIT, MT_DATA); 2905 if (n == NULL) { 2906 ifp->if_iqdrops++; 2907 m_freem(m); 2908 return (NULL); 2909 } 2910 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2911 m->m_data += ETHER_HDR_LEN; 2912 m->m_len -= ETHER_HDR_LEN; 2913 n->m_len = ETHER_HDR_LEN; 2914 M_MOVE_PKTHDR(n, m); 2915 n->m_next = m; 2916 return (n); 2917 } 2918 #endif 2919 2920 /* Receive a frame. */ 2921 static void 2922 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2923 { 2924 struct alc_rxdesc *rxd; 2925 struct ifnet *ifp; 2926 struct mbuf *mp, *m; 2927 uint32_t rdinfo, status, vtag; 2928 int count, nsegs, rx_cons; 2929 2930 ifp = sc->alc_ifp; 2931 status = le32toh(rrd->status); 2932 rdinfo = le32toh(rrd->rdinfo); 2933 rx_cons = RRD_RD_IDX(rdinfo); 2934 nsegs = RRD_RD_CNT(rdinfo); 2935 2936 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2937 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2938 /* 2939 * We want to pass the following frames to upper 2940 * layer regardless of error status of Rx return 2941 * ring. 2942 * 2943 * o IP/TCP/UDP checksum is bad. 2944 * o frame length and protocol specific length 2945 * does not match. 2946 * 2947 * Force network stack compute checksum for 2948 * errored frames. 2949 */ 2950 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2951 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 2952 RRD_ERR_RUNT) != 0) 2953 return; 2954 } 2955 2956 for (count = 0; count < nsegs; count++, 2957 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2958 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2959 mp = rxd->rx_m; 2960 /* Add a new receive buffer to the ring. */ 2961 if (alc_newbuf(sc, rxd) != 0) { 2962 ifp->if_iqdrops++; 2963 /* Reuse Rx buffers. */ 2964 if (sc->alc_cdata.alc_rxhead != NULL) 2965 m_freem(sc->alc_cdata.alc_rxhead); 2966 break; 2967 } 2968 2969 /* 2970 * Assume we've received a full sized frame. 2971 * Actual size is fixed when we encounter the end of 2972 * multi-segmented frame. 2973 */ 2974 mp->m_len = sc->alc_buf_size; 2975 2976 /* Chain received mbufs. */ 2977 if (sc->alc_cdata.alc_rxhead == NULL) { 2978 sc->alc_cdata.alc_rxhead = mp; 2979 sc->alc_cdata.alc_rxtail = mp; 2980 } else { 2981 mp->m_flags &= ~M_PKTHDR; 2982 sc->alc_cdata.alc_rxprev_tail = 2983 sc->alc_cdata.alc_rxtail; 2984 sc->alc_cdata.alc_rxtail->m_next = mp; 2985 sc->alc_cdata.alc_rxtail = mp; 2986 } 2987 2988 if (count == nsegs - 1) { 2989 /* Last desc. for this frame. */ 2990 m = sc->alc_cdata.alc_rxhead; 2991 m->m_flags |= M_PKTHDR; 2992 /* 2993 * It seems that L1C/L2C controller has no way 2994 * to tell hardware to strip CRC bytes. 2995 */ 2996 m->m_pkthdr.len = 2997 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2998 if (nsegs > 1) { 2999 /* Set last mbuf size. */ 3000 mp->m_len = sc->alc_cdata.alc_rxlen - 3001 (nsegs - 1) * sc->alc_buf_size; 3002 /* Remove the CRC bytes in chained mbufs. */ 3003 if (mp->m_len <= ETHER_CRC_LEN) { 3004 sc->alc_cdata.alc_rxtail = 3005 sc->alc_cdata.alc_rxprev_tail; 3006 sc->alc_cdata.alc_rxtail->m_len -= 3007 (ETHER_CRC_LEN - mp->m_len); 3008 sc->alc_cdata.alc_rxtail->m_next = NULL; 3009 m_freem(mp); 3010 } else { 3011 mp->m_len -= ETHER_CRC_LEN; 3012 } 3013 } else 3014 m->m_len = m->m_pkthdr.len; 3015 m->m_pkthdr.rcvif = ifp; 3016 /* 3017 * Due to hardware bugs, Rx checksum offloading 3018 * was intentionally disabled. 3019 */ 3020 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3021 (status & RRD_VLAN_TAG) != 0) { 3022 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3023 m->m_pkthdr.ether_vtag = ntohs(vtag); 3024 m->m_flags |= M_VLANTAG; 3025 } 3026 #ifndef __NO_STRICT_ALIGNMENT 3027 m = alc_fixup_rx(ifp, m); 3028 if (m != NULL) 3029 #endif 3030 { 3031 /* Pass it on. */ 3032 (*ifp->if_input)(ifp, m); 3033 } 3034 } 3035 } 3036 /* Reset mbuf chains. */ 3037 ALC_RXCHAIN_RESET(sc); 3038 } 3039 3040 static void 3041 alc_tick(void *arg) 3042 { 3043 struct alc_softc *sc; 3044 struct mii_data *mii; 3045 3046 sc = (struct alc_softc *)arg; 3047 3048 ALC_LOCK_ASSERT(sc); 3049 3050 mii = device_get_softc(sc->alc_miibus); 3051 mii_tick(mii); 3052 alc_stats_update(sc); 3053 /* 3054 * alc(4) does not rely on Tx completion interrupts to reclaim 3055 * transferred buffers. Instead Tx completion interrupts are 3056 * used to hint for scheduling Tx task. So it's necessary to 3057 * release transmitted buffers by kicking Tx completion 3058 * handler. This limits the maximum reclamation delay to a hz. 3059 */ 3060 alc_txeof(sc); 3061 alc_watchdog(sc); 3062 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3063 } 3064 3065 static void 3066 alc_reset(struct alc_softc *sc) 3067 { 3068 uint32_t reg; 3069 int i; 3070 3071 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3072 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3073 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3074 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3075 DELAY(10); 3076 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3077 break; 3078 } 3079 if (i == 0) 3080 device_printf(sc->alc_dev, "master reset timeout!\n"); 3081 3082 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3083 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3084 break; 3085 DELAY(10); 3086 } 3087 3088 if (i == 0) 3089 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3090 } 3091 3092 static void 3093 alc_init(void *xsc) 3094 { 3095 struct alc_softc *sc; 3096 3097 sc = (struct alc_softc *)xsc; 3098 ALC_LOCK(sc); 3099 alc_init_locked(sc); 3100 ALC_UNLOCK(sc); 3101 } 3102 3103 static void 3104 alc_init_locked(struct alc_softc *sc) 3105 { 3106 struct ifnet *ifp; 3107 struct mii_data *mii; 3108 uint8_t eaddr[ETHER_ADDR_LEN]; 3109 bus_addr_t paddr; 3110 uint32_t reg, rxf_hi, rxf_lo; 3111 3112 ALC_LOCK_ASSERT(sc); 3113 3114 ifp = sc->alc_ifp; 3115 mii = device_get_softc(sc->alc_miibus); 3116 3117 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3118 return; 3119 /* 3120 * Cancel any pending I/O. 3121 */ 3122 alc_stop(sc); 3123 /* 3124 * Reset the chip to a known state. 3125 */ 3126 alc_reset(sc); 3127 3128 /* Initialize Rx descriptors. */ 3129 if (alc_init_rx_ring(sc) != 0) { 3130 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3131 alc_stop(sc); 3132 return; 3133 } 3134 alc_init_rr_ring(sc); 3135 alc_init_tx_ring(sc); 3136 alc_init_cmb(sc); 3137 alc_init_smb(sc); 3138 3139 /* Reprogram the station address. */ 3140 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3141 CSR_WRITE_4(sc, ALC_PAR0, 3142 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3143 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3144 /* 3145 * Clear WOL status and disable all WOL feature as WOL 3146 * would interfere Rx operation under normal environments. 3147 */ 3148 CSR_READ_4(sc, ALC_WOL_CFG); 3149 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3150 /* Set Tx descriptor base addresses. */ 3151 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3152 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3153 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3154 /* We don't use high priority ring. */ 3155 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3156 /* Set Tx descriptor counter. */ 3157 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3158 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3159 /* Set Rx descriptor base addresses. */ 3160 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3161 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3162 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3163 /* We use one Rx ring. */ 3164 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3165 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3166 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3167 /* Set Rx descriptor counter. */ 3168 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3169 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3170 3171 /* 3172 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3173 * if it do not fit the buffer size. Rx return descriptor holds 3174 * a counter that indicates how many fragments were made by the 3175 * hardware. The buffer size should be multiple of 8 bytes. 3176 * Since hardware has limit on the size of buffer size, always 3177 * use the maximum value. 3178 * For strict-alignment architectures make sure to reduce buffer 3179 * size by 8 bytes to make room for alignment fixup. 3180 */ 3181 #ifndef __NO_STRICT_ALIGNMENT 3182 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3183 #else 3184 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3185 #endif 3186 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3187 3188 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3189 /* Set Rx return descriptor base addresses. */ 3190 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3191 /* We use one Rx return ring. */ 3192 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3193 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3194 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3195 /* Set Rx return descriptor counter. */ 3196 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3197 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3198 paddr = sc->alc_rdata.alc_cmb_paddr; 3199 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3200 paddr = sc->alc_rdata.alc_smb_paddr; 3201 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3202 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3203 3204 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3205 /* Reconfigure SRAM - Vendor magic. */ 3206 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3207 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3208 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3209 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3210 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3211 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3212 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3213 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3214 } 3215 3216 /* Tell hardware that we're ready to load DMA blocks. */ 3217 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3218 3219 /* Configure interrupt moderation timer. */ 3220 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3221 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3222 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3223 /* 3224 * We don't want to automatic interrupt clear as task queue 3225 * for the interrupt should know interrupt status. 3226 */ 3227 reg = MASTER_SA_TIMER_ENB; 3228 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3229 reg |= MASTER_IM_RX_TIMER_ENB; 3230 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3231 reg |= MASTER_IM_TX_TIMER_ENB; 3232 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3233 /* 3234 * Disable interrupt re-trigger timer. We don't want automatic 3235 * re-triggering of un-ACKed interrupts. 3236 */ 3237 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3238 /* Configure CMB. */ 3239 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3240 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3241 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3242 } else 3243 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3244 /* 3245 * Hardware can be configured to issue SMB interrupt based 3246 * on programmed interval. Since there is a callout that is 3247 * invoked for every hz in driver we use that instead of 3248 * relying on periodic SMB interrupt. 3249 */ 3250 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3251 /* Clear MAC statistics. */ 3252 alc_stats_clear(sc); 3253 3254 /* 3255 * Always use maximum frame size that controller can support. 3256 * Otherwise received frames that has larger frame length 3257 * than alc(4) MTU would be silently dropped in hardware. This 3258 * would make path-MTU discovery hard as sender wouldn't get 3259 * any responses from receiver. alc(4) supports 3260 * multi-fragmented frames on Rx path so it has no issue on 3261 * assembling fragmented frames. Using maximum frame size also 3262 * removes the need to reinitialize hardware when interface 3263 * MTU configuration was changed. 3264 * 3265 * Be conservative in what you do, be liberal in what you 3266 * accept from others - RFC 793. 3267 */ 3268 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3269 3270 /* Disable header split(?) */ 3271 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3272 3273 /* Configure IPG/IFG parameters. */ 3274 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3275 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3276 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3277 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3278 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3279 /* Set parameters for half-duplex media. */ 3280 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3281 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3282 HDPX_CFG_LCOL_MASK) | 3283 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3284 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3285 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3286 HDPX_CFG_ABEBT_MASK) | 3287 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3288 HDPX_CFG_JAMIPG_MASK)); 3289 /* 3290 * Set TSO/checksum offload threshold. For frames that is 3291 * larger than this threshold, hardware wouldn't do 3292 * TSO/checksum offloading. 3293 */ 3294 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3295 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3296 TSO_OFFLOAD_THRESH_MASK); 3297 /* Configure TxQ. */ 3298 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3299 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3300 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3301 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3302 reg >>= 1; 3303 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3304 TXQ_CFG_TD_BURST_MASK; 3305 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3306 3307 /* Configure Rx free descriptor pre-fetching. */ 3308 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3309 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3310 RX_RD_FREE_THRESH_HI_MASK) | 3311 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3312 RX_RD_FREE_THRESH_LO_MASK)); 3313 3314 /* 3315 * Configure flow control parameters. 3316 * XON : 80% of Rx FIFO 3317 * XOFF : 30% of Rx FIFO 3318 */ 3319 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3320 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3321 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3322 rxf_hi = (reg * 8) / 10; 3323 rxf_lo = (reg * 3) / 10; 3324 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3325 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3326 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3327 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3328 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3329 } 3330 3331 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3332 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3333 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3334 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3335 SERDES_PHY_CLK_SLOWDOWN); 3336 3337 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3338 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3339 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3340 3341 /* Configure RxQ. */ 3342 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3343 RXQ_CFG_RD_BURST_MASK; 3344 reg |= RXQ_CFG_RSS_MODE_DIS; 3345 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3346 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3347 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3348 3349 /* Configure DMA parameters. */ 3350 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3351 reg |= sc->alc_rcb; 3352 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3353 reg |= DMA_CFG_CMB_ENB; 3354 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3355 reg |= DMA_CFG_SMB_ENB; 3356 else 3357 reg |= DMA_CFG_SMB_DIS; 3358 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3359 DMA_CFG_RD_BURST_SHIFT; 3360 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3361 DMA_CFG_WR_BURST_SHIFT; 3362 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3363 DMA_CFG_RD_DELAY_CNT_MASK; 3364 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3365 DMA_CFG_WR_DELAY_CNT_MASK; 3366 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3367 3368 /* 3369 * Configure Tx/Rx MACs. 3370 * - Auto-padding for short frames. 3371 * - Enable CRC generation. 3372 * Actual reconfiguration of MAC for resolved speed/duplex 3373 * is followed after detection of link establishment. 3374 * AR813x/AR815x always does checksum computation regardless 3375 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3376 * have bug in protocol field in Rx return structure so 3377 * these controllers can't handle fragmented frames. Disable 3378 * Rx checksum offloading until there is a newer controller 3379 * that has sane implementation. 3380 */ 3381 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3382 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3383 MAC_CFG_PREAMBLE_MASK); 3384 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3385 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3386 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3387 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3388 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3389 reg |= MAC_CFG_SPEED_10_100; 3390 else 3391 reg |= MAC_CFG_SPEED_1000; 3392 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3393 3394 /* Set up the receive filter. */ 3395 alc_rxfilter(sc); 3396 alc_rxvlan(sc); 3397 3398 /* Acknowledge all pending interrupts and clear it. */ 3399 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3400 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3401 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3402 3403 sc->alc_flags &= ~ALC_FLAG_LINK; 3404 /* Switch to the current media. */ 3405 mii_mediachg(mii); 3406 3407 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3408 3409 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3410 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3411 } 3412 3413 static void 3414 alc_stop(struct alc_softc *sc) 3415 { 3416 struct ifnet *ifp; 3417 struct alc_txdesc *txd; 3418 struct alc_rxdesc *rxd; 3419 uint32_t reg; 3420 int i; 3421 3422 ALC_LOCK_ASSERT(sc); 3423 /* 3424 * Mark the interface down and cancel the watchdog timer. 3425 */ 3426 ifp = sc->alc_ifp; 3427 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3428 sc->alc_flags &= ~ALC_FLAG_LINK; 3429 callout_stop(&sc->alc_tick_ch); 3430 sc->alc_watchdog_timer = 0; 3431 alc_stats_update(sc); 3432 /* Disable interrupts. */ 3433 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3434 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3435 alc_stop_queue(sc); 3436 /* Disable DMA. */ 3437 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3438 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3439 reg |= DMA_CFG_SMB_DIS; 3440 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3441 DELAY(1000); 3442 /* Stop Rx/Tx MACs. */ 3443 alc_stop_mac(sc); 3444 /* Disable interrupts which might be touched in taskq handler. */ 3445 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3446 3447 /* Reclaim Rx buffers that have been processed. */ 3448 if (sc->alc_cdata.alc_rxhead != NULL) 3449 m_freem(sc->alc_cdata.alc_rxhead); 3450 ALC_RXCHAIN_RESET(sc); 3451 /* 3452 * Free Tx/Rx mbufs still in the queues. 3453 */ 3454 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3455 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3456 if (rxd->rx_m != NULL) { 3457 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3458 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3459 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3460 rxd->rx_dmamap); 3461 m_freem(rxd->rx_m); 3462 rxd->rx_m = NULL; 3463 } 3464 } 3465 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3466 txd = &sc->alc_cdata.alc_txdesc[i]; 3467 if (txd->tx_m != NULL) { 3468 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3469 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3470 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3471 txd->tx_dmamap); 3472 m_freem(txd->tx_m); 3473 txd->tx_m = NULL; 3474 } 3475 } 3476 } 3477 3478 static void 3479 alc_stop_mac(struct alc_softc *sc) 3480 { 3481 uint32_t reg; 3482 int i; 3483 3484 ALC_LOCK_ASSERT(sc); 3485 3486 /* Disable Rx/Tx MAC. */ 3487 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3488 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3489 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3490 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3491 } 3492 for (i = ALC_TIMEOUT; i > 0; i--) { 3493 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3494 if (reg == 0) 3495 break; 3496 DELAY(10); 3497 } 3498 if (i == 0) 3499 device_printf(sc->alc_dev, 3500 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3501 } 3502 3503 static void 3504 alc_start_queue(struct alc_softc *sc) 3505 { 3506 uint32_t qcfg[] = { 3507 0, 3508 RXQ_CFG_QUEUE0_ENB, 3509 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3510 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3511 RXQ_CFG_ENB 3512 }; 3513 uint32_t cfg; 3514 3515 ALC_LOCK_ASSERT(sc); 3516 3517 /* Enable RxQ. */ 3518 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3519 cfg &= ~RXQ_CFG_ENB; 3520 cfg |= qcfg[1]; 3521 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3522 /* Enable TxQ. */ 3523 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3524 cfg |= TXQ_CFG_ENB; 3525 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3526 } 3527 3528 static void 3529 alc_stop_queue(struct alc_softc *sc) 3530 { 3531 uint32_t reg; 3532 int i; 3533 3534 ALC_LOCK_ASSERT(sc); 3535 3536 /* Disable RxQ. */ 3537 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3538 if ((reg & RXQ_CFG_ENB) != 0) { 3539 reg &= ~RXQ_CFG_ENB; 3540 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3541 } 3542 /* Disable TxQ. */ 3543 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3544 if ((reg & TXQ_CFG_ENB) == 0) { 3545 reg &= ~TXQ_CFG_ENB; 3546 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3547 } 3548 for (i = ALC_TIMEOUT; i > 0; i--) { 3549 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3550 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3551 break; 3552 DELAY(10); 3553 } 3554 if (i == 0) 3555 device_printf(sc->alc_dev, 3556 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3557 } 3558 3559 static void 3560 alc_init_tx_ring(struct alc_softc *sc) 3561 { 3562 struct alc_ring_data *rd; 3563 struct alc_txdesc *txd; 3564 int i; 3565 3566 ALC_LOCK_ASSERT(sc); 3567 3568 sc->alc_cdata.alc_tx_prod = 0; 3569 sc->alc_cdata.alc_tx_cons = 0; 3570 sc->alc_cdata.alc_tx_cnt = 0; 3571 3572 rd = &sc->alc_rdata; 3573 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3574 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3575 txd = &sc->alc_cdata.alc_txdesc[i]; 3576 txd->tx_m = NULL; 3577 } 3578 3579 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3580 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3581 } 3582 3583 static int 3584 alc_init_rx_ring(struct alc_softc *sc) 3585 { 3586 struct alc_ring_data *rd; 3587 struct alc_rxdesc *rxd; 3588 int i; 3589 3590 ALC_LOCK_ASSERT(sc); 3591 3592 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3593 sc->alc_morework = 0; 3594 rd = &sc->alc_rdata; 3595 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3596 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3597 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3598 rxd->rx_m = NULL; 3599 rxd->rx_desc = &rd->alc_rx_ring[i]; 3600 if (alc_newbuf(sc, rxd) != 0) 3601 return (ENOBUFS); 3602 } 3603 3604 /* 3605 * Since controller does not update Rx descriptors, driver 3606 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3607 * is enough to ensure coherence. 3608 */ 3609 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3610 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3611 /* Let controller know availability of new Rx buffers. */ 3612 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3613 3614 return (0); 3615 } 3616 3617 static void 3618 alc_init_rr_ring(struct alc_softc *sc) 3619 { 3620 struct alc_ring_data *rd; 3621 3622 ALC_LOCK_ASSERT(sc); 3623 3624 sc->alc_cdata.alc_rr_cons = 0; 3625 ALC_RXCHAIN_RESET(sc); 3626 3627 rd = &sc->alc_rdata; 3628 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3629 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3630 sc->alc_cdata.alc_rr_ring_map, 3631 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3632 } 3633 3634 static void 3635 alc_init_cmb(struct alc_softc *sc) 3636 { 3637 struct alc_ring_data *rd; 3638 3639 ALC_LOCK_ASSERT(sc); 3640 3641 rd = &sc->alc_rdata; 3642 bzero(rd->alc_cmb, ALC_CMB_SZ); 3643 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3645 } 3646 3647 static void 3648 alc_init_smb(struct alc_softc *sc) 3649 { 3650 struct alc_ring_data *rd; 3651 3652 ALC_LOCK_ASSERT(sc); 3653 3654 rd = &sc->alc_rdata; 3655 bzero(rd->alc_smb, ALC_SMB_SZ); 3656 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3658 } 3659 3660 static void 3661 alc_rxvlan(struct alc_softc *sc) 3662 { 3663 struct ifnet *ifp; 3664 uint32_t reg; 3665 3666 ALC_LOCK_ASSERT(sc); 3667 3668 ifp = sc->alc_ifp; 3669 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3670 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3671 reg |= MAC_CFG_VLAN_TAG_STRIP; 3672 else 3673 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3674 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3675 } 3676 3677 static void 3678 alc_rxfilter(struct alc_softc *sc) 3679 { 3680 struct ifnet *ifp; 3681 struct ifmultiaddr *ifma; 3682 uint32_t crc; 3683 uint32_t mchash[2]; 3684 uint32_t rxcfg; 3685 3686 ALC_LOCK_ASSERT(sc); 3687 3688 ifp = sc->alc_ifp; 3689 3690 bzero(mchash, sizeof(mchash)); 3691 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3692 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3693 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3694 rxcfg |= MAC_CFG_BCAST; 3695 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3696 if ((ifp->if_flags & IFF_PROMISC) != 0) 3697 rxcfg |= MAC_CFG_PROMISC; 3698 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3699 rxcfg |= MAC_CFG_ALLMULTI; 3700 mchash[0] = 0xFFFFFFFF; 3701 mchash[1] = 0xFFFFFFFF; 3702 goto chipit; 3703 } 3704 3705 if_maddr_rlock(ifp); 3706 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3707 if (ifma->ifma_addr->sa_family != AF_LINK) 3708 continue; 3709 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3710 ifma->ifma_addr), ETHER_ADDR_LEN); 3711 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3712 } 3713 if_maddr_runlock(ifp); 3714 3715 chipit: 3716 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3717 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3718 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3719 } 3720 3721 static int 3722 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3723 { 3724 int error, value; 3725 3726 if (arg1 == NULL) 3727 return (EINVAL); 3728 value = *(int *)arg1; 3729 error = sysctl_handle_int(oidp, &value, 0, req); 3730 if (error || req->newptr == NULL) 3731 return (error); 3732 if (value < low || value > high) 3733 return (EINVAL); 3734 *(int *)arg1 = value; 3735 3736 return (0); 3737 } 3738 3739 static int 3740 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3741 { 3742 return (sysctl_int_range(oidp, arg1, arg2, req, 3743 ALC_PROC_MIN, ALC_PROC_MAX)); 3744 } 3745 3746 static int 3747 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3748 { 3749 3750 return (sysctl_int_range(oidp, arg1, arg2, req, 3751 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3752 } 3753