1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/debugnet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_llc.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 73 #include <machine/bus.h> 74 #include <machine/in_cksum.h> 75 76 #include <dev/alc/if_alcreg.h> 77 #include <dev/alc/if_alcvar.h> 78 79 /* "device miibus" required. See GENERIC if you get errors here. */ 80 #include "miibus_if.h" 81 #undef ALC_USE_CUSTOM_CSUM 82 83 #ifdef ALC_USE_CUSTOM_CSUM 84 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 85 #else 86 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 87 #endif 88 89 MODULE_DEPEND(alc, pci, 1, 1, 1); 90 MODULE_DEPEND(alc, ether, 1, 1, 1); 91 MODULE_DEPEND(alc, miibus, 1, 1, 1); 92 93 /* Tunables. */ 94 static int msi_disable = 0; 95 static int msix_disable = 0; 96 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 97 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 98 99 /* 100 * Devices supported by this driver. 101 */ 102 static struct alc_ident alc_ident_table[] = { 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 104 "Atheros AR8131 PCIe Gigabit Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 106 "Atheros AR8132 PCIe Fast Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 108 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 110 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 112 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 114 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 116 "Atheros AR8161 PCIe Gigabit Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 118 "Atheros AR8162 PCIe Fast Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 120 "Atheros AR8171 PCIe Gigabit Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 122 "Atheros AR8172 PCIe Fast Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 124 "Killer E2200 Gigabit Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 126 "Killer E2400 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 128 "Killer E2500 Gigabit Ethernet" }, 129 { 0, 0, 0, NULL} 130 }; 131 132 static void alc_aspm(struct alc_softc *, int, int); 133 static void alc_aspm_813x(struct alc_softc *, int); 134 static void alc_aspm_816x(struct alc_softc *, int); 135 static int alc_attach(device_t); 136 static int alc_check_boundary(struct alc_softc *); 137 static void alc_config_msi(struct alc_softc *); 138 static int alc_detach(device_t); 139 static void alc_disable_l0s_l1(struct alc_softc *); 140 static int alc_dma_alloc(struct alc_softc *); 141 static void alc_dma_free(struct alc_softc *); 142 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 143 static void alc_dsp_fixup(struct alc_softc *, int); 144 static int alc_encap(struct alc_softc *, struct mbuf **); 145 static struct alc_ident * 146 alc_find_ident(device_t); 147 #ifndef __NO_STRICT_ALIGNMENT 148 static struct mbuf * 149 alc_fixup_rx(if_t, struct mbuf *); 150 #endif 151 static void alc_get_macaddr(struct alc_softc *); 152 static void alc_get_macaddr_813x(struct alc_softc *); 153 static void alc_get_macaddr_816x(struct alc_softc *); 154 static void alc_get_macaddr_par(struct alc_softc *); 155 static void alc_init(void *); 156 static void alc_init_cmb(struct alc_softc *); 157 static void alc_init_locked(struct alc_softc *); 158 static void alc_init_rr_ring(struct alc_softc *); 159 static int alc_init_rx_ring(struct alc_softc *); 160 static void alc_init_smb(struct alc_softc *); 161 static void alc_init_tx_ring(struct alc_softc *); 162 static void alc_int_task(void *, int); 163 static int alc_intr(void *); 164 static int alc_ioctl(if_t, u_long, caddr_t); 165 static void alc_mac_config(struct alc_softc *); 166 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 167 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 168 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 169 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 170 static int alc_miibus_readreg(device_t, int, int); 171 static void alc_miibus_statchg(device_t); 172 static int alc_miibus_writereg(device_t, int, int, int); 173 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 174 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 175 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 176 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 177 static int alc_mediachange(if_t); 178 static int alc_mediachange_locked(struct alc_softc *); 179 static void alc_mediastatus(if_t, struct ifmediareq *); 180 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 181 static void alc_osc_reset(struct alc_softc *); 182 static void alc_phy_down(struct alc_softc *); 183 static void alc_phy_reset(struct alc_softc *); 184 static void alc_phy_reset_813x(struct alc_softc *); 185 static void alc_phy_reset_816x(struct alc_softc *); 186 static int alc_probe(device_t); 187 static void alc_reset(struct alc_softc *); 188 static int alc_resume(device_t); 189 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 190 static int alc_rxintr(struct alc_softc *, int); 191 static void alc_rxfilter(struct alc_softc *); 192 static void alc_rxvlan(struct alc_softc *); 193 static void alc_setlinkspeed(struct alc_softc *); 194 static void alc_setwol(struct alc_softc *); 195 static void alc_setwol_813x(struct alc_softc *); 196 static void alc_setwol_816x(struct alc_softc *); 197 static int alc_shutdown(device_t); 198 static void alc_start(if_t); 199 static void alc_start_locked(if_t); 200 static void alc_start_queue(struct alc_softc *); 201 static void alc_start_tx(struct alc_softc *); 202 static void alc_stats_clear(struct alc_softc *); 203 static void alc_stats_update(struct alc_softc *); 204 static void alc_stop(struct alc_softc *); 205 static void alc_stop_mac(struct alc_softc *); 206 static void alc_stop_queue(struct alc_softc *); 207 static int alc_suspend(device_t); 208 static void alc_sysctl_node(struct alc_softc *); 209 static void alc_tick(void *); 210 static void alc_txeof(struct alc_softc *); 211 static void alc_watchdog(struct alc_softc *); 212 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 213 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 214 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 215 216 DEBUGNET_DEFINE(alc); 217 218 static device_method_t alc_methods[] = { 219 /* Device interface. */ 220 DEVMETHOD(device_probe, alc_probe), 221 DEVMETHOD(device_attach, alc_attach), 222 DEVMETHOD(device_detach, alc_detach), 223 DEVMETHOD(device_shutdown, alc_shutdown), 224 DEVMETHOD(device_suspend, alc_suspend), 225 DEVMETHOD(device_resume, alc_resume), 226 227 /* MII interface. */ 228 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 229 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 230 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 231 232 DEVMETHOD_END 233 }; 234 235 static driver_t alc_driver = { 236 "alc", 237 alc_methods, 238 sizeof(struct alc_softc) 239 }; 240 241 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 242 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 243 nitems(alc_ident_table) - 1); 244 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 245 246 static struct resource_spec alc_res_spec_mem[] = { 247 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 248 { -1, 0, 0 } 249 }; 250 251 static struct resource_spec alc_irq_spec_legacy[] = { 252 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 253 { -1, 0, 0 } 254 }; 255 256 static struct resource_spec alc_irq_spec_msi[] = { 257 { SYS_RES_IRQ, 1, RF_ACTIVE }, 258 { -1, 0, 0 } 259 }; 260 261 static struct resource_spec alc_irq_spec_msix[] = { 262 { SYS_RES_IRQ, 1, RF_ACTIVE }, 263 { -1, 0, 0 } 264 }; 265 266 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 267 268 static int 269 alc_miibus_readreg(device_t dev, int phy, int reg) 270 { 271 struct alc_softc *sc; 272 int v; 273 274 sc = device_get_softc(dev); 275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 276 v = alc_mii_readreg_816x(sc, phy, reg); 277 else 278 v = alc_mii_readreg_813x(sc, phy, reg); 279 return (v); 280 } 281 282 static uint32_t 283 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 284 { 285 uint32_t v; 286 int i; 287 288 /* 289 * For AR8132 fast ethernet controller, do not report 1000baseT 290 * capability to mii(4). Even though AR8132 uses the same 291 * model/revision number of F1 gigabit PHY, the PHY has no 292 * ability to establish 1000baseT link. 293 */ 294 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 295 reg == MII_EXTSR) 296 return (0); 297 298 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 299 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 300 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 301 DELAY(5); 302 v = CSR_READ_4(sc, ALC_MDIO); 303 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 304 break; 305 } 306 307 if (i == 0) { 308 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 309 return (0); 310 } 311 312 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 313 } 314 315 static uint32_t 316 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 317 { 318 uint32_t clk, v; 319 int i; 320 321 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 322 clk = MDIO_CLK_25_128; 323 else 324 clk = MDIO_CLK_25_4; 325 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 326 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 327 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 328 DELAY(5); 329 v = CSR_READ_4(sc, ALC_MDIO); 330 if ((v & MDIO_OP_BUSY) == 0) 331 break; 332 } 333 334 if (i == 0) { 335 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 336 return (0); 337 } 338 339 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 340 } 341 342 static int 343 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 344 { 345 struct alc_softc *sc; 346 int v; 347 348 sc = device_get_softc(dev); 349 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 350 v = alc_mii_writereg_816x(sc, phy, reg, val); 351 else 352 v = alc_mii_writereg_813x(sc, phy, reg, val); 353 return (v); 354 } 355 356 static uint32_t 357 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 358 { 359 uint32_t v; 360 int i; 361 362 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 363 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 364 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 365 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 366 DELAY(5); 367 v = CSR_READ_4(sc, ALC_MDIO); 368 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 369 break; 370 } 371 372 if (i == 0) 373 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 374 375 return (0); 376 } 377 378 static uint32_t 379 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 380 { 381 uint32_t clk, v; 382 int i; 383 384 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 385 clk = MDIO_CLK_25_128; 386 else 387 clk = MDIO_CLK_25_4; 388 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 389 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 390 MDIO_SUP_PREAMBLE | clk); 391 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 392 DELAY(5); 393 v = CSR_READ_4(sc, ALC_MDIO); 394 if ((v & MDIO_OP_BUSY) == 0) 395 break; 396 } 397 398 if (i == 0) 399 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 400 401 return (0); 402 } 403 404 static void 405 alc_miibus_statchg(device_t dev) 406 { 407 struct alc_softc *sc; 408 struct mii_data *mii; 409 if_t ifp; 410 uint32_t reg; 411 412 sc = device_get_softc(dev); 413 414 mii = device_get_softc(sc->alc_miibus); 415 ifp = sc->alc_ifp; 416 if (mii == NULL || ifp == NULL || 417 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 418 return; 419 420 sc->alc_flags &= ~ALC_FLAG_LINK; 421 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 422 (IFM_ACTIVE | IFM_AVALID)) { 423 switch (IFM_SUBTYPE(mii->mii_media_active)) { 424 case IFM_10_T: 425 case IFM_100_TX: 426 sc->alc_flags |= ALC_FLAG_LINK; 427 break; 428 case IFM_1000_T: 429 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 430 sc->alc_flags |= ALC_FLAG_LINK; 431 break; 432 default: 433 break; 434 } 435 } 436 /* Stop Rx/Tx MACs. */ 437 alc_stop_mac(sc); 438 439 /* Program MACs with resolved speed/duplex/flow-control. */ 440 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 441 alc_start_queue(sc); 442 alc_mac_config(sc); 443 /* Re-enable Tx/Rx MACs. */ 444 reg = CSR_READ_4(sc, ALC_MAC_CFG); 445 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 446 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 447 } 448 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 449 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 450 } 451 452 static uint32_t 453 alc_miidbg_readreg(struct alc_softc *sc, int reg) 454 { 455 456 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 457 reg); 458 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 459 ALC_MII_DBG_DATA)); 460 } 461 462 static uint32_t 463 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 464 { 465 466 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 467 reg); 468 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 469 ALC_MII_DBG_DATA, val)); 470 } 471 472 static uint32_t 473 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 474 { 475 uint32_t clk, v; 476 int i; 477 478 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 479 EXT_MDIO_DEVADDR(devaddr)); 480 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 481 clk = MDIO_CLK_25_128; 482 else 483 clk = MDIO_CLK_25_4; 484 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 485 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 486 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 487 DELAY(5); 488 v = CSR_READ_4(sc, ALC_MDIO); 489 if ((v & MDIO_OP_BUSY) == 0) 490 break; 491 } 492 493 if (i == 0) { 494 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 495 devaddr, reg); 496 return (0); 497 } 498 499 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 500 } 501 502 static uint32_t 503 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 504 { 505 uint32_t clk, v; 506 int i; 507 508 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 509 EXT_MDIO_DEVADDR(devaddr)); 510 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 511 clk = MDIO_CLK_25_128; 512 else 513 clk = MDIO_CLK_25_4; 514 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 515 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 516 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 517 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 518 DELAY(5); 519 v = CSR_READ_4(sc, ALC_MDIO); 520 if ((v & MDIO_OP_BUSY) == 0) 521 break; 522 } 523 524 if (i == 0) 525 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 526 devaddr, reg); 527 528 return (0); 529 } 530 531 static void 532 alc_dsp_fixup(struct alc_softc *sc, int media) 533 { 534 uint16_t agc, len, val; 535 536 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 537 return; 538 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 539 return; 540 541 /* 542 * Vendor PHY magic. 543 * 1000BT/AZ, wrong cable length 544 */ 545 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 546 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 547 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 548 EXT_CLDCTL6_CAB_LEN_MASK; 549 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 550 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 551 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 552 agc > DBG_AGC_LONG1G_LIMT) || 553 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 554 agc > DBG_AGC_LONG1G_LIMT)) { 555 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 556 DBG_AZ_ANADECT_LONG); 557 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 558 MII_EXT_ANEG_AFE); 559 val |= ANEG_AFEE_10BT_100M_TH; 560 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 561 val); 562 } else { 563 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 564 DBG_AZ_ANADECT_DEFAULT); 565 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 566 MII_EXT_ANEG_AFE); 567 val &= ~ANEG_AFEE_10BT_100M_TH; 568 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 569 val); 570 } 571 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 572 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 573 if (media == IFM_1000_T) { 574 /* 575 * Giga link threshold, raise the tolerance of 576 * noise 50%. 577 */ 578 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 579 val &= ~DBG_MSE20DB_TH_MASK; 580 val |= (DBG_MSE20DB_TH_HI << 581 DBG_MSE20DB_TH_SHIFT); 582 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 583 } else if (media == IFM_100_TX) 584 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 585 DBG_MSE16DB_UP); 586 } 587 } else { 588 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 589 val &= ~ANEG_AFEE_10BT_100M_TH; 590 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 591 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 592 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 593 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 594 DBG_MSE16DB_DOWN); 595 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 596 val &= ~DBG_MSE20DB_TH_MASK; 597 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 598 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 599 } 600 } 601 } 602 603 static void 604 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 605 { 606 struct alc_softc *sc; 607 struct mii_data *mii; 608 609 sc = if_getsoftc(ifp); 610 ALC_LOCK(sc); 611 if ((if_getflags(ifp) & IFF_UP) == 0) { 612 ALC_UNLOCK(sc); 613 return; 614 } 615 mii = device_get_softc(sc->alc_miibus); 616 617 mii_pollstat(mii); 618 ifmr->ifm_status = mii->mii_media_status; 619 ifmr->ifm_active = mii->mii_media_active; 620 ALC_UNLOCK(sc); 621 } 622 623 static int 624 alc_mediachange(if_t ifp) 625 { 626 struct alc_softc *sc; 627 int error; 628 629 sc = if_getsoftc(ifp); 630 ALC_LOCK(sc); 631 error = alc_mediachange_locked(sc); 632 ALC_UNLOCK(sc); 633 634 return (error); 635 } 636 637 static int 638 alc_mediachange_locked(struct alc_softc *sc) 639 { 640 struct mii_data *mii; 641 struct mii_softc *miisc; 642 int error; 643 644 ALC_LOCK_ASSERT(sc); 645 646 mii = device_get_softc(sc->alc_miibus); 647 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 648 PHY_RESET(miisc); 649 error = mii_mediachg(mii); 650 651 return (error); 652 } 653 654 static struct alc_ident * 655 alc_find_ident(device_t dev) 656 { 657 struct alc_ident *ident; 658 uint16_t vendor, devid; 659 660 vendor = pci_get_vendor(dev); 661 devid = pci_get_device(dev); 662 for (ident = alc_ident_table; ident->name != NULL; ident++) { 663 if (vendor == ident->vendorid && devid == ident->deviceid) 664 return (ident); 665 } 666 667 return (NULL); 668 } 669 670 static int 671 alc_probe(device_t dev) 672 { 673 struct alc_ident *ident; 674 675 ident = alc_find_ident(dev); 676 if (ident != NULL) { 677 device_set_desc(dev, ident->name); 678 return (BUS_PROBE_DEFAULT); 679 } 680 681 return (ENXIO); 682 } 683 684 static void 685 alc_get_macaddr(struct alc_softc *sc) 686 { 687 688 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 689 alc_get_macaddr_816x(sc); 690 else 691 alc_get_macaddr_813x(sc); 692 } 693 694 static void 695 alc_get_macaddr_813x(struct alc_softc *sc) 696 { 697 uint32_t opt; 698 uint16_t val; 699 int eeprom, i; 700 701 eeprom = 0; 702 opt = CSR_READ_4(sc, ALC_OPT_CFG); 703 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 704 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 705 /* 706 * EEPROM found, let TWSI reload EEPROM configuration. 707 * This will set ethernet address of controller. 708 */ 709 eeprom++; 710 switch (sc->alc_ident->deviceid) { 711 case DEVICEID_ATHEROS_AR8131: 712 case DEVICEID_ATHEROS_AR8132: 713 if ((opt & OPT_CFG_CLK_ENB) == 0) { 714 opt |= OPT_CFG_CLK_ENB; 715 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 716 CSR_READ_4(sc, ALC_OPT_CFG); 717 DELAY(1000); 718 } 719 break; 720 case DEVICEID_ATHEROS_AR8151: 721 case DEVICEID_ATHEROS_AR8151_V2: 722 case DEVICEID_ATHEROS_AR8152_B: 723 case DEVICEID_ATHEROS_AR8152_B2: 724 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 725 ALC_MII_DBG_ADDR, 0x00); 726 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_DATA); 728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA, val & 0xFF7F); 730 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_ADDR, 0x3B); 732 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_DATA); 734 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_DATA, val | 0x0008); 736 DELAY(20); 737 break; 738 } 739 740 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 741 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 742 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 743 CSR_READ_4(sc, ALC_WOL_CFG); 744 745 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 746 TWSI_CFG_SW_LD_START); 747 for (i = 100; i > 0; i--) { 748 DELAY(1000); 749 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 750 TWSI_CFG_SW_LD_START) == 0) 751 break; 752 } 753 if (i == 0) 754 device_printf(sc->alc_dev, 755 "reloading EEPROM timeout!\n"); 756 } else { 757 if (bootverbose) 758 device_printf(sc->alc_dev, "EEPROM not found!\n"); 759 } 760 if (eeprom != 0) { 761 switch (sc->alc_ident->deviceid) { 762 case DEVICEID_ATHEROS_AR8131: 763 case DEVICEID_ATHEROS_AR8132: 764 if ((opt & OPT_CFG_CLK_ENB) != 0) { 765 opt &= ~OPT_CFG_CLK_ENB; 766 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 767 CSR_READ_4(sc, ALC_OPT_CFG); 768 DELAY(1000); 769 } 770 break; 771 case DEVICEID_ATHEROS_AR8151: 772 case DEVICEID_ATHEROS_AR8151_V2: 773 case DEVICEID_ATHEROS_AR8152_B: 774 case DEVICEID_ATHEROS_AR8152_B2: 775 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 776 ALC_MII_DBG_ADDR, 0x00); 777 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_DATA); 779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA, val | 0x0080); 781 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_ADDR, 0x3B); 783 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_DATA); 785 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_DATA, val & 0xFFF7); 787 DELAY(20); 788 break; 789 } 790 } 791 792 alc_get_macaddr_par(sc); 793 } 794 795 static void 796 alc_get_macaddr_816x(struct alc_softc *sc) 797 { 798 uint32_t reg; 799 int i, reloaded; 800 801 reloaded = 0; 802 /* Try to reload station address via TWSI. */ 803 for (i = 100; i > 0; i--) { 804 reg = CSR_READ_4(sc, ALC_SLD); 805 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 806 break; 807 DELAY(1000); 808 } 809 if (i != 0) { 810 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 811 for (i = 100; i > 0; i--) { 812 DELAY(1000); 813 reg = CSR_READ_4(sc, ALC_SLD); 814 if ((reg & SLD_START) == 0) 815 break; 816 } 817 if (i != 0) 818 reloaded++; 819 else if (bootverbose) 820 device_printf(sc->alc_dev, 821 "reloading station address via TWSI timed out!\n"); 822 } 823 824 /* Try to reload station address from EEPROM or FLASH. */ 825 if (reloaded == 0) { 826 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 827 if ((reg & (EEPROM_LD_EEPROM_EXIST | 828 EEPROM_LD_FLASH_EXIST)) != 0) { 829 for (i = 100; i > 0; i--) { 830 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 831 if ((reg & (EEPROM_LD_PROGRESS | 832 EEPROM_LD_START)) == 0) 833 break; 834 DELAY(1000); 835 } 836 if (i != 0) { 837 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 838 EEPROM_LD_START); 839 for (i = 100; i > 0; i--) { 840 DELAY(1000); 841 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 842 if ((reg & EEPROM_LD_START) == 0) 843 break; 844 } 845 } else if (bootverbose) 846 device_printf(sc->alc_dev, 847 "reloading EEPROM/FLASH timed out!\n"); 848 } 849 } 850 851 alc_get_macaddr_par(sc); 852 } 853 854 static void 855 alc_get_macaddr_par(struct alc_softc *sc) 856 { 857 uint32_t ea[2]; 858 859 ea[0] = CSR_READ_4(sc, ALC_PAR0); 860 ea[1] = CSR_READ_4(sc, ALC_PAR1); 861 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 862 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 863 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 864 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 865 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 866 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 867 } 868 869 static void 870 alc_disable_l0s_l1(struct alc_softc *sc) 871 { 872 uint32_t pmcfg; 873 874 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 875 /* Another magic from vendor. */ 876 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 877 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 878 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 879 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 880 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 881 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 882 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 883 } 884 } 885 886 static void 887 alc_phy_reset(struct alc_softc *sc) 888 { 889 890 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 891 alc_phy_reset_816x(sc); 892 else 893 alc_phy_reset_813x(sc); 894 } 895 896 static void 897 alc_phy_reset_813x(struct alc_softc *sc) 898 { 899 uint16_t data; 900 901 /* Reset magic from Linux. */ 902 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 903 CSR_READ_2(sc, ALC_GPHY_CFG); 904 DELAY(10 * 1000); 905 906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 907 GPHY_CFG_SEL_ANA_RESET); 908 CSR_READ_2(sc, ALC_GPHY_CFG); 909 DELAY(10 * 1000); 910 911 /* DSP fixup, Vendor magic. */ 912 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 913 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 914 ALC_MII_DBG_ADDR, 0x000A); 915 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_DATA); 917 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA, data & 0xDFFF); 919 } 920 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 921 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 922 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 923 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 924 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 925 ALC_MII_DBG_ADDR, 0x003B); 926 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_DATA); 928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_DATA, data & 0xFFF7); 930 DELAY(20 * 1000); 931 } 932 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_ADDR, 0x0029); 935 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 936 ALC_MII_DBG_DATA, 0x929D); 937 } 938 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 939 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 940 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 941 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 942 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 943 ALC_MII_DBG_ADDR, 0x0029); 944 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 945 ALC_MII_DBG_DATA, 0xB6DD); 946 } 947 948 /* Load DSP codes, vendor magic. */ 949 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 950 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 951 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 952 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_DATA, data); 955 956 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 957 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 958 ANA_SERDES_EN_LCKDT; 959 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 960 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 961 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 962 ALC_MII_DBG_DATA, data); 963 964 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 965 ANA_LONG_CABLE_TH_100_MASK) | 966 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 967 ANA_SHORT_CABLE_TH_100_SHIFT) | 968 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 969 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 970 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 971 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 972 ALC_MII_DBG_DATA, data); 973 974 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 975 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 976 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 977 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 978 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 979 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 980 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 981 ALC_MII_DBG_DATA, data); 982 983 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 984 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 985 ANA_OEN_125M; 986 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 987 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 988 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 989 ALC_MII_DBG_DATA, data); 990 DELAY(1000); 991 992 /* Disable hibernation. */ 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 994 0x0029); 995 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 996 ALC_MII_DBG_DATA); 997 data &= ~0x8000; 998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 999 data); 1000 1001 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1002 0x000B); 1003 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1004 ALC_MII_DBG_DATA); 1005 data &= ~0x8000; 1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1007 data); 1008 } 1009 1010 static void 1011 alc_phy_reset_816x(struct alc_softc *sc) 1012 { 1013 uint32_t val; 1014 1015 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1016 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1017 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1018 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1019 val |= GPHY_CFG_SEL_ANA_RESET; 1020 #ifdef notyet 1021 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1022 #else 1023 /* Disable PHY hibernation. */ 1024 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1025 #endif 1026 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1027 DELAY(10); 1028 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1029 DELAY(800); 1030 1031 /* Vendor PHY magic. */ 1032 #ifdef notyet 1033 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1034 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1035 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1036 EXT_VDRVBIAS_DEFAULT); 1037 #else 1038 /* Disable PHY hibernation. */ 1039 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1040 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1041 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1042 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1043 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1044 #endif 1045 1046 /* XXX Disable EEE. */ 1047 val = CSR_READ_4(sc, ALC_LPI_CTL); 1048 val &= ~LPI_CTL_ENB; 1049 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1050 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1051 1052 /* PHY power saving. */ 1053 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1054 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1055 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1056 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1057 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1058 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1059 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1060 1061 /* RTL8139C, 120m issue. */ 1062 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1063 ANEG_NLP78_120M_DEFAULT); 1064 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1065 ANEG_S3DIG10_DEFAULT); 1066 1067 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1068 /* Turn off half amplitude. */ 1069 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1070 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1071 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1072 /* Turn off Green feature. */ 1073 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1074 val |= DBG_GREENCFG2_BP_GREEN; 1075 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1076 /* Turn off half bias. */ 1077 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1078 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1079 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1080 } 1081 } 1082 1083 static void 1084 alc_phy_down(struct alc_softc *sc) 1085 { 1086 uint32_t gphy; 1087 1088 switch (sc->alc_ident->deviceid) { 1089 case DEVICEID_ATHEROS_AR8161: 1090 case DEVICEID_ATHEROS_E2200: 1091 case DEVICEID_ATHEROS_E2400: 1092 case DEVICEID_ATHEROS_E2500: 1093 case DEVICEID_ATHEROS_AR8162: 1094 case DEVICEID_ATHEROS_AR8171: 1095 case DEVICEID_ATHEROS_AR8172: 1096 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1097 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1098 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1099 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1100 GPHY_CFG_SEL_ANA_RESET; 1101 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1102 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1103 break; 1104 case DEVICEID_ATHEROS_AR8151: 1105 case DEVICEID_ATHEROS_AR8151_V2: 1106 case DEVICEID_ATHEROS_AR8152_B: 1107 case DEVICEID_ATHEROS_AR8152_B2: 1108 /* 1109 * GPHY power down caused more problems on AR8151 v2.0. 1110 * When driver is reloaded after GPHY power down, 1111 * accesses to PHY/MAC registers hung the system. Only 1112 * cold boot recovered from it. I'm not sure whether 1113 * AR8151 v1.0 also requires this one though. I don't 1114 * have AR8151 v1.0 controller in hand. 1115 * The only option left is to isolate the PHY and 1116 * initiates power down the PHY which in turn saves 1117 * more power when driver is unloaded. 1118 */ 1119 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1120 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1121 break; 1122 default: 1123 /* Force PHY down. */ 1124 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1125 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1126 GPHY_CFG_PWDOWN_HW); 1127 DELAY(1000); 1128 break; 1129 } 1130 } 1131 1132 static void 1133 alc_aspm(struct alc_softc *sc, int init, int media) 1134 { 1135 1136 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1137 alc_aspm_816x(sc, init); 1138 else 1139 alc_aspm_813x(sc, media); 1140 } 1141 1142 static void 1143 alc_aspm_813x(struct alc_softc *sc, int media) 1144 { 1145 uint32_t pmcfg; 1146 uint16_t linkcfg; 1147 1148 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1149 return; 1150 1151 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1152 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1153 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1154 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1155 PCIER_LINK_CTL); 1156 else 1157 linkcfg = 0; 1158 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1159 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1160 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1161 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1162 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1163 1164 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1165 /* Disable extended sync except AR8152 B v1.0 */ 1166 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1167 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1168 sc->alc_rev == ATHEROS_AR8152_B_V10) 1169 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1170 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1171 linkcfg); 1172 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1173 PM_CFG_HOTRST); 1174 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1175 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1176 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1177 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1178 PM_CFG_PM_REQ_TIMER_SHIFT); 1179 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1180 } 1181 1182 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1183 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1184 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1185 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1186 pmcfg |= PM_CFG_ASPM_L1_ENB; 1187 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1188 if (sc->alc_ident->deviceid == 1189 DEVICEID_ATHEROS_AR8152_B) 1190 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1191 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1192 PM_CFG_SERDES_PLL_L1_ENB | 1193 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1194 pmcfg |= PM_CFG_CLK_SWH_L1; 1195 if (media == IFM_100_TX || media == IFM_1000_T) { 1196 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1197 switch (sc->alc_ident->deviceid) { 1198 case DEVICEID_ATHEROS_AR8152_B: 1199 pmcfg |= (7 << 1200 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1201 break; 1202 case DEVICEID_ATHEROS_AR8152_B2: 1203 case DEVICEID_ATHEROS_AR8151_V2: 1204 pmcfg |= (4 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 default: 1208 pmcfg |= (15 << 1209 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1210 break; 1211 } 1212 } 1213 } else { 1214 pmcfg |= PM_CFG_SERDES_L1_ENB | 1215 PM_CFG_SERDES_PLL_L1_ENB | 1216 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1217 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1218 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1219 } 1220 } else { 1221 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1222 PM_CFG_SERDES_PLL_L1_ENB); 1223 pmcfg |= PM_CFG_CLK_SWH_L1; 1224 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1225 pmcfg |= PM_CFG_ASPM_L1_ENB; 1226 } 1227 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1228 } 1229 1230 static void 1231 alc_aspm_816x(struct alc_softc *sc, int init) 1232 { 1233 uint32_t pmcfg; 1234 1235 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1236 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1237 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1238 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1239 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1240 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1241 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1242 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1243 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1244 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1245 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1246 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1247 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1248 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1249 (sc->alc_rev & 0x01) != 0) 1250 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1251 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1252 /* Link up, enable both L0s, L1s. */ 1253 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1254 PM_CFG_MAC_ASPM_CHK; 1255 } else { 1256 if (init != 0) 1257 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1258 PM_CFG_MAC_ASPM_CHK; 1259 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1260 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1261 } 1262 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1263 } 1264 1265 static void 1266 alc_init_pcie(struct alc_softc *sc) 1267 { 1268 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1269 uint32_t cap, ctl, val; 1270 int state; 1271 1272 /* Clear data link and flow-control protocol error. */ 1273 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1274 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1275 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1276 1277 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1278 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1279 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1280 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1281 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1282 PCIE_PHYMISC_FORCE_RCV_DET); 1283 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1284 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1285 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1286 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1287 PCIE_PHYMISC2_SERDES_TH_MASK); 1288 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1289 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1290 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1291 } 1292 /* Disable ASPM L0S and L1. */ 1293 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1294 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1295 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1296 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1297 sc->alc_rcb = DMA_CFG_RCB_128; 1298 if (bootverbose) 1299 device_printf(sc->alc_dev, "RCB %u bytes\n", 1300 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1301 state = ctl & PCIEM_LINK_CTL_ASPMC; 1302 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1303 sc->alc_flags |= ALC_FLAG_L0S; 1304 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1305 sc->alc_flags |= ALC_FLAG_L1S; 1306 if (bootverbose) 1307 device_printf(sc->alc_dev, "ASPM %s %s\n", 1308 aspm_state[state], 1309 state == 0 ? "disabled" : "enabled"); 1310 alc_disable_l0s_l1(sc); 1311 } else { 1312 if (bootverbose) 1313 device_printf(sc->alc_dev, 1314 "no ASPM support\n"); 1315 } 1316 } else { 1317 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1318 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1319 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1320 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1321 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1322 (sc->alc_rev & 0x01) != 0) { 1323 if ((val & MASTER_WAKEN_25M) == 0 || 1324 (val & MASTER_CLK_SEL_DIS) == 0) { 1325 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1326 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1327 } 1328 } else { 1329 if ((val & MASTER_WAKEN_25M) == 0 || 1330 (val & MASTER_CLK_SEL_DIS) != 0) { 1331 val |= MASTER_WAKEN_25M; 1332 val &= ~MASTER_CLK_SEL_DIS; 1333 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1334 } 1335 } 1336 } 1337 alc_aspm(sc, 1, IFM_UNKNOWN); 1338 } 1339 1340 static void 1341 alc_config_msi(struct alc_softc *sc) 1342 { 1343 uint32_t ctl, mod; 1344 1345 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1346 /* 1347 * It seems interrupt moderation is controlled by 1348 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1349 * Driver uses RX interrupt moderation parameter to 1350 * program ALC_MSI_RETRANS_TIMER register. 1351 */ 1352 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1353 ctl &= ~MSI_RETRANS_TIMER_MASK; 1354 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1355 mod = ALC_USECS(sc->alc_int_rx_mod); 1356 if (mod == 0) 1357 mod = 1; 1358 ctl |= mod; 1359 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1360 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1361 MSI_RETRANS_MASK_SEL_STD); 1362 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1363 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1364 MSI_RETRANS_MASK_SEL_LINE); 1365 else 1366 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1367 } 1368 } 1369 1370 static int 1371 alc_attach(device_t dev) 1372 { 1373 struct alc_softc *sc; 1374 if_t ifp; 1375 int base, error, i, msic, msixc; 1376 uint16_t burst; 1377 1378 error = 0; 1379 sc = device_get_softc(dev); 1380 sc->alc_dev = dev; 1381 sc->alc_rev = pci_get_revid(dev); 1382 1383 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1384 MTX_DEF); 1385 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1386 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1387 sc->alc_ident = alc_find_ident(dev); 1388 1389 /* Map the device. */ 1390 pci_enable_busmaster(dev); 1391 sc->alc_res_spec = alc_res_spec_mem; 1392 sc->alc_irq_spec = alc_irq_spec_legacy; 1393 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1394 if (error != 0) { 1395 device_printf(dev, "cannot allocate memory resources.\n"); 1396 goto fail; 1397 } 1398 1399 /* Set PHY address. */ 1400 sc->alc_phyaddr = ALC_PHY_ADDR; 1401 1402 /* 1403 * One odd thing is AR8132 uses the same PHY hardware(F1 1404 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1405 * the PHY supports 1000Mbps but that's not true. The PHY 1406 * used in AR8132 can't establish gigabit link even if it 1407 * shows the same PHY model/revision number of AR8131. 1408 */ 1409 switch (sc->alc_ident->deviceid) { 1410 case DEVICEID_ATHEROS_E2200: 1411 case DEVICEID_ATHEROS_E2400: 1412 case DEVICEID_ATHEROS_E2500: 1413 sc->alc_flags |= ALC_FLAG_E2X00; 1414 /* FALLTHROUGH */ 1415 case DEVICEID_ATHEROS_AR8161: 1416 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1417 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1418 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1419 /* FALLTHROUGH */ 1420 case DEVICEID_ATHEROS_AR8171: 1421 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1422 break; 1423 case DEVICEID_ATHEROS_AR8162: 1424 case DEVICEID_ATHEROS_AR8172: 1425 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1426 break; 1427 case DEVICEID_ATHEROS_AR8152_B: 1428 case DEVICEID_ATHEROS_AR8152_B2: 1429 sc->alc_flags |= ALC_FLAG_APS; 1430 /* FALLTHROUGH */ 1431 case DEVICEID_ATHEROS_AR8132: 1432 sc->alc_flags |= ALC_FLAG_FASTETHER; 1433 break; 1434 case DEVICEID_ATHEROS_AR8151: 1435 case DEVICEID_ATHEROS_AR8151_V2: 1436 sc->alc_flags |= ALC_FLAG_APS; 1437 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1438 sc->alc_flags |= ALC_FLAG_MT; 1439 /* FALLTHROUGH */ 1440 default: 1441 break; 1442 } 1443 sc->alc_flags |= ALC_FLAG_JUMBO; 1444 1445 /* 1446 * It seems that AR813x/AR815x has silicon bug for SMB. In 1447 * addition, Atheros said that enabling SMB wouldn't improve 1448 * performance. However I think it's bad to access lots of 1449 * registers to extract MAC statistics. 1450 */ 1451 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1452 /* 1453 * Don't use Tx CMB. It is known to have silicon bug. 1454 */ 1455 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1456 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1457 MASTER_CHIP_REV_SHIFT; 1458 if (bootverbose) { 1459 device_printf(dev, "PCI device revision : 0x%04x\n", 1460 sc->alc_rev); 1461 device_printf(dev, "Chip id/revision : 0x%04x\n", 1462 sc->alc_chip_rev); 1463 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1464 device_printf(dev, "AR816x revision : 0x%x\n", 1465 AR816X_REV(sc->alc_rev)); 1466 } 1467 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1468 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1469 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1470 1471 /* Initialize DMA parameters. */ 1472 sc->alc_dma_rd_burst = 0; 1473 sc->alc_dma_wr_burst = 0; 1474 sc->alc_rcb = DMA_CFG_RCB_64; 1475 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1476 sc->alc_flags |= ALC_FLAG_PCIE; 1477 sc->alc_expcap = base; 1478 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1479 sc->alc_dma_rd_burst = 1480 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1481 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1482 if (bootverbose) { 1483 device_printf(dev, "Read request size : %u bytes.\n", 1484 alc_dma_burst[sc->alc_dma_rd_burst]); 1485 device_printf(dev, "TLP payload size : %u bytes.\n", 1486 alc_dma_burst[sc->alc_dma_wr_burst]); 1487 } 1488 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1489 sc->alc_dma_rd_burst = 3; 1490 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1491 sc->alc_dma_wr_burst = 3; 1492 /* 1493 * Force maximum payload size to 128 bytes for 1494 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1495 * Otherwise it triggers DMA write error. 1496 */ 1497 if ((sc->alc_flags & 1498 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1499 sc->alc_dma_wr_burst = 0; 1500 alc_init_pcie(sc); 1501 } 1502 1503 /* Reset PHY. */ 1504 alc_phy_reset(sc); 1505 1506 /* Reset the ethernet controller. */ 1507 alc_stop_mac(sc); 1508 alc_reset(sc); 1509 1510 /* Allocate IRQ resources. */ 1511 msixc = pci_msix_count(dev); 1512 msic = pci_msi_count(dev); 1513 if (bootverbose) { 1514 device_printf(dev, "MSIX count : %d\n", msixc); 1515 device_printf(dev, "MSI count : %d\n", msic); 1516 } 1517 if (msixc > 1) 1518 msixc = 1; 1519 if (msic > 1) 1520 msic = 1; 1521 /* 1522 * Prefer MSIX over MSI. 1523 * AR816x controller has a silicon bug that MSI interrupt 1524 * does not assert if PCIM_CMD_INTxDIS bit of command 1525 * register is set. pci(4) was taught to handle that case. 1526 */ 1527 if (msix_disable == 0 || msi_disable == 0) { 1528 if (msix_disable == 0 && msixc > 0 && 1529 pci_alloc_msix(dev, &msixc) == 0) { 1530 if (msic == 1) { 1531 device_printf(dev, 1532 "Using %d MSIX message(s).\n", msixc); 1533 sc->alc_flags |= ALC_FLAG_MSIX; 1534 sc->alc_irq_spec = alc_irq_spec_msix; 1535 } else 1536 pci_release_msi(dev); 1537 } 1538 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1539 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1540 if (msic == 1) { 1541 device_printf(dev, 1542 "Using %d MSI message(s).\n", msic); 1543 sc->alc_flags |= ALC_FLAG_MSI; 1544 sc->alc_irq_spec = alc_irq_spec_msi; 1545 } else 1546 pci_release_msi(dev); 1547 } 1548 } 1549 1550 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1551 if (error != 0) { 1552 device_printf(dev, "cannot allocate IRQ resources.\n"); 1553 goto fail; 1554 } 1555 1556 /* Create device sysctl node. */ 1557 alc_sysctl_node(sc); 1558 1559 if ((error = alc_dma_alloc(sc)) != 0) 1560 goto fail; 1561 1562 /* Load station address. */ 1563 alc_get_macaddr(sc); 1564 1565 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1566 if (ifp == NULL) { 1567 device_printf(dev, "cannot allocate ifnet structure.\n"); 1568 error = ENXIO; 1569 goto fail; 1570 } 1571 1572 if_setsoftc(ifp, sc); 1573 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1574 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1575 if_setioctlfn(ifp, alc_ioctl); 1576 if_setstartfn(ifp, alc_start); 1577 if_setinitfn(ifp, alc_init); 1578 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1579 if_setsendqready(ifp); 1580 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1581 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1582 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1583 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1584 sc->alc_flags |= ALC_FLAG_PM; 1585 sc->alc_pmcap = base; 1586 } 1587 if_setcapenable(ifp, if_getcapabilities(ifp)); 1588 1589 /* Set up MII bus. */ 1590 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1591 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1592 MIIF_DOPAUSE); 1593 if (error != 0) { 1594 device_printf(dev, "attaching PHYs failed\n"); 1595 goto fail; 1596 } 1597 1598 ether_ifattach(ifp, sc->alc_eaddr); 1599 1600 /* VLAN capability setup. */ 1601 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1602 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1603 if_setcapenable(ifp, if_getcapabilities(ifp)); 1604 /* 1605 * XXX 1606 * It seems enabling Tx checksum offloading makes more trouble. 1607 * Sometimes the controller does not receive any frames when 1608 * Tx checksum offloading is enabled. I'm not sure whether this 1609 * is a bug in Tx checksum offloading logic or I got broken 1610 * sample boards. To safety, don't enable Tx checksum offloading 1611 * by default but give chance to users to toggle it if they know 1612 * their controllers work without problems. 1613 * Fortunately, Tx checksum offloading for AR816x family 1614 * seems to work. 1615 */ 1616 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1617 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1618 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1619 } 1620 1621 /* Tell the upper layer(s) we support long frames. */ 1622 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1623 1624 /* Create local taskq. */ 1625 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1626 taskqueue_thread_enqueue, &sc->alc_tq); 1627 if (sc->alc_tq == NULL) { 1628 device_printf(dev, "could not create taskqueue.\n"); 1629 ether_ifdetach(ifp); 1630 error = ENXIO; 1631 goto fail; 1632 } 1633 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1634 device_get_nameunit(sc->alc_dev)); 1635 1636 alc_config_msi(sc); 1637 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1638 msic = ALC_MSIX_MESSAGES; 1639 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1640 msic = ALC_MSI_MESSAGES; 1641 else 1642 msic = 1; 1643 for (i = 0; i < msic; i++) { 1644 error = bus_setup_intr(dev, sc->alc_irq[i], 1645 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1646 &sc->alc_intrhand[i]); 1647 if (error != 0) 1648 break; 1649 } 1650 if (error != 0) { 1651 device_printf(dev, "could not set up interrupt handler.\n"); 1652 taskqueue_free(sc->alc_tq); 1653 sc->alc_tq = NULL; 1654 ether_ifdetach(ifp); 1655 goto fail; 1656 } 1657 1658 /* Attach driver debugnet methods. */ 1659 DEBUGNET_SET(ifp, alc); 1660 1661 fail: 1662 if (error != 0) 1663 alc_detach(dev); 1664 1665 return (error); 1666 } 1667 1668 static int 1669 alc_detach(device_t dev) 1670 { 1671 struct alc_softc *sc; 1672 if_t ifp; 1673 int i, msic; 1674 1675 sc = device_get_softc(dev); 1676 1677 ifp = sc->alc_ifp; 1678 if (device_is_attached(dev)) { 1679 ether_ifdetach(ifp); 1680 ALC_LOCK(sc); 1681 alc_stop(sc); 1682 ALC_UNLOCK(sc); 1683 callout_drain(&sc->alc_tick_ch); 1684 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1685 } 1686 1687 if (sc->alc_tq != NULL) { 1688 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1689 taskqueue_free(sc->alc_tq); 1690 sc->alc_tq = NULL; 1691 } 1692 1693 if (sc->alc_miibus != NULL) { 1694 device_delete_child(dev, sc->alc_miibus); 1695 sc->alc_miibus = NULL; 1696 } 1697 bus_generic_detach(dev); 1698 alc_dma_free(sc); 1699 1700 if (ifp != NULL) { 1701 if_free(ifp); 1702 sc->alc_ifp = NULL; 1703 } 1704 1705 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1706 msic = ALC_MSIX_MESSAGES; 1707 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1708 msic = ALC_MSI_MESSAGES; 1709 else 1710 msic = 1; 1711 for (i = 0; i < msic; i++) { 1712 if (sc->alc_intrhand[i] != NULL) { 1713 bus_teardown_intr(dev, sc->alc_irq[i], 1714 sc->alc_intrhand[i]); 1715 sc->alc_intrhand[i] = NULL; 1716 } 1717 } 1718 if (sc->alc_res[0] != NULL) 1719 alc_phy_down(sc); 1720 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1721 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1722 pci_release_msi(dev); 1723 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1724 mtx_destroy(&sc->alc_mtx); 1725 1726 return (0); 1727 } 1728 1729 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1730 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1731 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1732 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1733 1734 static void 1735 alc_sysctl_node(struct alc_softc *sc) 1736 { 1737 struct sysctl_ctx_list *ctx; 1738 struct sysctl_oid_list *child, *parent; 1739 struct sysctl_oid *tree; 1740 struct alc_hw_stats *stats; 1741 int error; 1742 1743 stats = &sc->alc_stats; 1744 ctx = device_get_sysctl_ctx(sc->alc_dev); 1745 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1746 1747 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1748 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1749 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1750 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1751 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1752 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1753 /* Pull in device tunables. */ 1754 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1755 error = resource_int_value(device_get_name(sc->alc_dev), 1756 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1757 if (error == 0) { 1758 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1759 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1760 device_printf(sc->alc_dev, "int_rx_mod value out of " 1761 "range; using default: %d\n", 1762 ALC_IM_RX_TIMER_DEFAULT); 1763 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1764 } 1765 } 1766 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1767 error = resource_int_value(device_get_name(sc->alc_dev), 1768 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1769 if (error == 0) { 1770 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1771 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1772 device_printf(sc->alc_dev, "int_tx_mod value out of " 1773 "range; using default: %d\n", 1774 ALC_IM_TX_TIMER_DEFAULT); 1775 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1776 } 1777 } 1778 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1779 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1780 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1781 "max number of Rx events to process"); 1782 /* Pull in device tunables. */ 1783 sc->alc_process_limit = ALC_PROC_DEFAULT; 1784 error = resource_int_value(device_get_name(sc->alc_dev), 1785 device_get_unit(sc->alc_dev), "process_limit", 1786 &sc->alc_process_limit); 1787 if (error == 0) { 1788 if (sc->alc_process_limit < ALC_PROC_MIN || 1789 sc->alc_process_limit > ALC_PROC_MAX) { 1790 device_printf(sc->alc_dev, 1791 "process_limit value out of range; " 1792 "using default: %d\n", ALC_PROC_DEFAULT); 1793 sc->alc_process_limit = ALC_PROC_DEFAULT; 1794 } 1795 } 1796 1797 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1798 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1799 parent = SYSCTL_CHILDREN(tree); 1800 1801 /* Rx statistics. */ 1802 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1803 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1804 child = SYSCTL_CHILDREN(tree); 1805 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1806 &stats->rx_frames, "Good frames"); 1807 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1808 &stats->rx_bcast_frames, "Good broadcast frames"); 1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1810 &stats->rx_mcast_frames, "Good multicast frames"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1812 &stats->rx_pause_frames, "Pause control frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1814 &stats->rx_control_frames, "Control frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1816 &stats->rx_crcerrs, "CRC errors"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1818 &stats->rx_lenerrs, "Frames with length mismatched"); 1819 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1820 &stats->rx_bytes, "Good octets"); 1821 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1822 &stats->rx_bcast_bytes, "Good broadcast octets"); 1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1824 &stats->rx_mcast_bytes, "Good multicast octets"); 1825 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1826 &stats->rx_runts, "Too short frames"); 1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1828 &stats->rx_fragments, "Fragmented frames"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1830 &stats->rx_pkts_64, "64 bytes frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1832 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1834 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1836 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1838 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1840 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1842 &stats->rx_pkts_1519_max, "1519 to max frames"); 1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1844 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1846 &stats->rx_fifo_oflows, "FIFO overflows"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1848 &stats->rx_rrs_errs, "Return status write-back errors"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1850 &stats->rx_alignerrs, "Alignment errors"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1852 &stats->rx_pkts_filtered, 1853 "Frames dropped due to address filtering"); 1854 1855 /* Tx statistics. */ 1856 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1857 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1858 child = SYSCTL_CHILDREN(tree); 1859 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1860 &stats->tx_frames, "Good frames"); 1861 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1862 &stats->tx_bcast_frames, "Good broadcast frames"); 1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1864 &stats->tx_mcast_frames, "Good multicast frames"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1866 &stats->tx_pause_frames, "Pause control frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1868 &stats->tx_control_frames, "Control frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1870 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1872 &stats->tx_excess_defer, "Frames with derferrals"); 1873 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1874 &stats->tx_bytes, "Good octets"); 1875 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1876 &stats->tx_bcast_bytes, "Good broadcast octets"); 1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1878 &stats->tx_mcast_bytes, "Good multicast octets"); 1879 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1880 &stats->tx_pkts_64, "64 bytes frames"); 1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1882 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1884 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1886 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1888 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1890 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1892 &stats->tx_pkts_1519_max, "1519 to max frames"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1894 &stats->tx_single_colls, "Single collisions"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1896 &stats->tx_multi_colls, "Multiple collisions"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1898 &stats->tx_late_colls, "Late collisions"); 1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1900 &stats->tx_excess_colls, "Excessive collisions"); 1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1902 &stats->tx_underrun, "FIFO underruns"); 1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1904 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1906 &stats->tx_lenerrs, "Frames with length mismatched"); 1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1908 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1909 } 1910 1911 #undef ALC_SYSCTL_STAT_ADD32 1912 #undef ALC_SYSCTL_STAT_ADD64 1913 1914 struct alc_dmamap_arg { 1915 bus_addr_t alc_busaddr; 1916 }; 1917 1918 static void 1919 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1920 { 1921 struct alc_dmamap_arg *ctx; 1922 1923 if (error != 0) 1924 return; 1925 1926 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1927 1928 ctx = (struct alc_dmamap_arg *)arg; 1929 ctx->alc_busaddr = segs[0].ds_addr; 1930 } 1931 1932 /* 1933 * Normal and high Tx descriptors shares single Tx high address. 1934 * Four Rx descriptor/return rings and CMB shares the same Rx 1935 * high address. 1936 */ 1937 static int 1938 alc_check_boundary(struct alc_softc *sc) 1939 { 1940 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1941 1942 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1943 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1944 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1945 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1946 1947 /* 4GB boundary crossing is not allowed. */ 1948 if ((ALC_ADDR_HI(rx_ring_end) != 1949 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1950 (ALC_ADDR_HI(rr_ring_end) != 1951 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1952 (ALC_ADDR_HI(cmb_end) != 1953 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1954 (ALC_ADDR_HI(tx_ring_end) != 1955 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1956 return (EFBIG); 1957 /* 1958 * Make sure Rx return descriptor/Rx descriptor/CMB use 1959 * the same high address. 1960 */ 1961 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1962 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1963 return (EFBIG); 1964 1965 return (0); 1966 } 1967 1968 static int 1969 alc_dma_alloc(struct alc_softc *sc) 1970 { 1971 struct alc_txdesc *txd; 1972 struct alc_rxdesc *rxd; 1973 bus_addr_t lowaddr; 1974 struct alc_dmamap_arg ctx; 1975 int error, i; 1976 1977 lowaddr = BUS_SPACE_MAXADDR; 1978 if (sc->alc_flags & ALC_FLAG_MT) 1979 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1980 again: 1981 /* Create parent DMA tag. */ 1982 error = bus_dma_tag_create( 1983 bus_get_dma_tag(sc->alc_dev), /* parent */ 1984 1, 0, /* alignment, boundary */ 1985 lowaddr, /* lowaddr */ 1986 BUS_SPACE_MAXADDR, /* highaddr */ 1987 NULL, NULL, /* filter, filterarg */ 1988 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1989 0, /* nsegments */ 1990 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1991 0, /* flags */ 1992 NULL, NULL, /* lockfunc, lockarg */ 1993 &sc->alc_cdata.alc_parent_tag); 1994 if (error != 0) { 1995 device_printf(sc->alc_dev, 1996 "could not create parent DMA tag.\n"); 1997 goto fail; 1998 } 1999 2000 /* Create DMA tag for Tx descriptor ring. */ 2001 error = bus_dma_tag_create( 2002 sc->alc_cdata.alc_parent_tag, /* parent */ 2003 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2004 BUS_SPACE_MAXADDR, /* lowaddr */ 2005 BUS_SPACE_MAXADDR, /* highaddr */ 2006 NULL, NULL, /* filter, filterarg */ 2007 ALC_TX_RING_SZ, /* maxsize */ 2008 1, /* nsegments */ 2009 ALC_TX_RING_SZ, /* maxsegsize */ 2010 0, /* flags */ 2011 NULL, NULL, /* lockfunc, lockarg */ 2012 &sc->alc_cdata.alc_tx_ring_tag); 2013 if (error != 0) { 2014 device_printf(sc->alc_dev, 2015 "could not create Tx ring DMA tag.\n"); 2016 goto fail; 2017 } 2018 2019 /* Create DMA tag for Rx free descriptor ring. */ 2020 error = bus_dma_tag_create( 2021 sc->alc_cdata.alc_parent_tag, /* parent */ 2022 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2023 BUS_SPACE_MAXADDR, /* lowaddr */ 2024 BUS_SPACE_MAXADDR, /* highaddr */ 2025 NULL, NULL, /* filter, filterarg */ 2026 ALC_RX_RING_SZ, /* maxsize */ 2027 1, /* nsegments */ 2028 ALC_RX_RING_SZ, /* maxsegsize */ 2029 0, /* flags */ 2030 NULL, NULL, /* lockfunc, lockarg */ 2031 &sc->alc_cdata.alc_rx_ring_tag); 2032 if (error != 0) { 2033 device_printf(sc->alc_dev, 2034 "could not create Rx ring DMA tag.\n"); 2035 goto fail; 2036 } 2037 /* Create DMA tag for Rx return descriptor ring. */ 2038 error = bus_dma_tag_create( 2039 sc->alc_cdata.alc_parent_tag, /* parent */ 2040 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2041 BUS_SPACE_MAXADDR, /* lowaddr */ 2042 BUS_SPACE_MAXADDR, /* highaddr */ 2043 NULL, NULL, /* filter, filterarg */ 2044 ALC_RR_RING_SZ, /* maxsize */ 2045 1, /* nsegments */ 2046 ALC_RR_RING_SZ, /* maxsegsize */ 2047 0, /* flags */ 2048 NULL, NULL, /* lockfunc, lockarg */ 2049 &sc->alc_cdata.alc_rr_ring_tag); 2050 if (error != 0) { 2051 device_printf(sc->alc_dev, 2052 "could not create Rx return ring DMA tag.\n"); 2053 goto fail; 2054 } 2055 2056 /* Create DMA tag for coalescing message block. */ 2057 error = bus_dma_tag_create( 2058 sc->alc_cdata.alc_parent_tag, /* parent */ 2059 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2060 BUS_SPACE_MAXADDR, /* lowaddr */ 2061 BUS_SPACE_MAXADDR, /* highaddr */ 2062 NULL, NULL, /* filter, filterarg */ 2063 ALC_CMB_SZ, /* maxsize */ 2064 1, /* nsegments */ 2065 ALC_CMB_SZ, /* maxsegsize */ 2066 0, /* flags */ 2067 NULL, NULL, /* lockfunc, lockarg */ 2068 &sc->alc_cdata.alc_cmb_tag); 2069 if (error != 0) { 2070 device_printf(sc->alc_dev, 2071 "could not create CMB DMA tag.\n"); 2072 goto fail; 2073 } 2074 /* Create DMA tag for status message block. */ 2075 error = bus_dma_tag_create( 2076 sc->alc_cdata.alc_parent_tag, /* parent */ 2077 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2078 BUS_SPACE_MAXADDR, /* lowaddr */ 2079 BUS_SPACE_MAXADDR, /* highaddr */ 2080 NULL, NULL, /* filter, filterarg */ 2081 ALC_SMB_SZ, /* maxsize */ 2082 1, /* nsegments */ 2083 ALC_SMB_SZ, /* maxsegsize */ 2084 0, /* flags */ 2085 NULL, NULL, /* lockfunc, lockarg */ 2086 &sc->alc_cdata.alc_smb_tag); 2087 if (error != 0) { 2088 device_printf(sc->alc_dev, 2089 "could not create SMB DMA tag.\n"); 2090 goto fail; 2091 } 2092 2093 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2094 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2095 (void **)&sc->alc_rdata.alc_tx_ring, 2096 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2097 &sc->alc_cdata.alc_tx_ring_map); 2098 if (error != 0) { 2099 device_printf(sc->alc_dev, 2100 "could not allocate DMA'able memory for Tx ring.\n"); 2101 goto fail; 2102 } 2103 ctx.alc_busaddr = 0; 2104 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2105 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2106 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2107 if (error != 0 || ctx.alc_busaddr == 0) { 2108 device_printf(sc->alc_dev, 2109 "could not load DMA'able memory for Tx ring.\n"); 2110 goto fail; 2111 } 2112 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2113 2114 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2115 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2116 (void **)&sc->alc_rdata.alc_rx_ring, 2117 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2118 &sc->alc_cdata.alc_rx_ring_map); 2119 if (error != 0) { 2120 device_printf(sc->alc_dev, 2121 "could not allocate DMA'able memory for Rx ring.\n"); 2122 goto fail; 2123 } 2124 ctx.alc_busaddr = 0; 2125 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2126 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2127 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2128 if (error != 0 || ctx.alc_busaddr == 0) { 2129 device_printf(sc->alc_dev, 2130 "could not load DMA'able memory for Rx ring.\n"); 2131 goto fail; 2132 } 2133 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2134 2135 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2136 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2137 (void **)&sc->alc_rdata.alc_rr_ring, 2138 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2139 &sc->alc_cdata.alc_rr_ring_map); 2140 if (error != 0) { 2141 device_printf(sc->alc_dev, 2142 "could not allocate DMA'able memory for Rx return ring.\n"); 2143 goto fail; 2144 } 2145 ctx.alc_busaddr = 0; 2146 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2147 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2148 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2149 if (error != 0 || ctx.alc_busaddr == 0) { 2150 device_printf(sc->alc_dev, 2151 "could not load DMA'able memory for Tx ring.\n"); 2152 goto fail; 2153 } 2154 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2155 2156 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2157 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2158 (void **)&sc->alc_rdata.alc_cmb, 2159 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2160 &sc->alc_cdata.alc_cmb_map); 2161 if (error != 0) { 2162 device_printf(sc->alc_dev, 2163 "could not allocate DMA'able memory for CMB.\n"); 2164 goto fail; 2165 } 2166 ctx.alc_busaddr = 0; 2167 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2168 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2169 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2170 if (error != 0 || ctx.alc_busaddr == 0) { 2171 device_printf(sc->alc_dev, 2172 "could not load DMA'able memory for CMB.\n"); 2173 goto fail; 2174 } 2175 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2176 2177 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2178 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2179 (void **)&sc->alc_rdata.alc_smb, 2180 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2181 &sc->alc_cdata.alc_smb_map); 2182 if (error != 0) { 2183 device_printf(sc->alc_dev, 2184 "could not allocate DMA'able memory for SMB.\n"); 2185 goto fail; 2186 } 2187 ctx.alc_busaddr = 0; 2188 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2189 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2190 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2191 if (error != 0 || ctx.alc_busaddr == 0) { 2192 device_printf(sc->alc_dev, 2193 "could not load DMA'able memory for CMB.\n"); 2194 goto fail; 2195 } 2196 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2197 2198 /* Make sure we've not crossed 4GB boundary. */ 2199 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2200 (error = alc_check_boundary(sc)) != 0) { 2201 device_printf(sc->alc_dev, "4GB boundary crossed, " 2202 "switching to 32bit DMA addressing mode.\n"); 2203 alc_dma_free(sc); 2204 /* 2205 * Limit max allowable DMA address space to 32bit 2206 * and try again. 2207 */ 2208 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2209 goto again; 2210 } 2211 2212 /* 2213 * Create Tx buffer parent tag. 2214 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2215 * so it needs separate parent DMA tag as parent DMA address 2216 * space could be restricted to be within 32bit address space 2217 * by 4GB boundary crossing. 2218 */ 2219 error = bus_dma_tag_create( 2220 bus_get_dma_tag(sc->alc_dev), /* parent */ 2221 1, 0, /* alignment, boundary */ 2222 lowaddr, /* lowaddr */ 2223 BUS_SPACE_MAXADDR, /* highaddr */ 2224 NULL, NULL, /* filter, filterarg */ 2225 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2226 0, /* nsegments */ 2227 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2228 0, /* flags */ 2229 NULL, NULL, /* lockfunc, lockarg */ 2230 &sc->alc_cdata.alc_buffer_tag); 2231 if (error != 0) { 2232 device_printf(sc->alc_dev, 2233 "could not create parent buffer DMA tag.\n"); 2234 goto fail; 2235 } 2236 2237 /* Create DMA tag for Tx buffers. */ 2238 error = bus_dma_tag_create( 2239 sc->alc_cdata.alc_buffer_tag, /* parent */ 2240 1, 0, /* alignment, boundary */ 2241 BUS_SPACE_MAXADDR, /* lowaddr */ 2242 BUS_SPACE_MAXADDR, /* highaddr */ 2243 NULL, NULL, /* filter, filterarg */ 2244 ALC_TSO_MAXSIZE, /* maxsize */ 2245 ALC_MAXTXSEGS, /* nsegments */ 2246 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2247 0, /* flags */ 2248 NULL, NULL, /* lockfunc, lockarg */ 2249 &sc->alc_cdata.alc_tx_tag); 2250 if (error != 0) { 2251 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2252 goto fail; 2253 } 2254 2255 /* Create DMA tag for Rx buffers. */ 2256 error = bus_dma_tag_create( 2257 sc->alc_cdata.alc_buffer_tag, /* parent */ 2258 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2259 BUS_SPACE_MAXADDR, /* lowaddr */ 2260 BUS_SPACE_MAXADDR, /* highaddr */ 2261 NULL, NULL, /* filter, filterarg */ 2262 MCLBYTES, /* maxsize */ 2263 1, /* nsegments */ 2264 MCLBYTES, /* maxsegsize */ 2265 0, /* flags */ 2266 NULL, NULL, /* lockfunc, lockarg */ 2267 &sc->alc_cdata.alc_rx_tag); 2268 if (error != 0) { 2269 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2270 goto fail; 2271 } 2272 /* Create DMA maps for Tx buffers. */ 2273 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2274 txd = &sc->alc_cdata.alc_txdesc[i]; 2275 txd->tx_m = NULL; 2276 txd->tx_dmamap = NULL; 2277 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2278 &txd->tx_dmamap); 2279 if (error != 0) { 2280 device_printf(sc->alc_dev, 2281 "could not create Tx dmamap.\n"); 2282 goto fail; 2283 } 2284 } 2285 /* Create DMA maps for Rx buffers. */ 2286 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2287 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2288 device_printf(sc->alc_dev, 2289 "could not create spare Rx dmamap.\n"); 2290 goto fail; 2291 } 2292 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2293 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2294 rxd->rx_m = NULL; 2295 rxd->rx_dmamap = NULL; 2296 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2297 &rxd->rx_dmamap); 2298 if (error != 0) { 2299 device_printf(sc->alc_dev, 2300 "could not create Rx dmamap.\n"); 2301 goto fail; 2302 } 2303 } 2304 2305 fail: 2306 return (error); 2307 } 2308 2309 static void 2310 alc_dma_free(struct alc_softc *sc) 2311 { 2312 struct alc_txdesc *txd; 2313 struct alc_rxdesc *rxd; 2314 int i; 2315 2316 /* Tx buffers. */ 2317 if (sc->alc_cdata.alc_tx_tag != NULL) { 2318 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2319 txd = &sc->alc_cdata.alc_txdesc[i]; 2320 if (txd->tx_dmamap != NULL) { 2321 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2322 txd->tx_dmamap); 2323 txd->tx_dmamap = NULL; 2324 } 2325 } 2326 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2327 sc->alc_cdata.alc_tx_tag = NULL; 2328 } 2329 /* Rx buffers */ 2330 if (sc->alc_cdata.alc_rx_tag != NULL) { 2331 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2332 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2333 if (rxd->rx_dmamap != NULL) { 2334 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2335 rxd->rx_dmamap); 2336 rxd->rx_dmamap = NULL; 2337 } 2338 } 2339 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2340 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2341 sc->alc_cdata.alc_rx_sparemap); 2342 sc->alc_cdata.alc_rx_sparemap = NULL; 2343 } 2344 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2345 sc->alc_cdata.alc_rx_tag = NULL; 2346 } 2347 /* Tx descriptor ring. */ 2348 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2349 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2350 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2351 sc->alc_cdata.alc_tx_ring_map); 2352 if (sc->alc_rdata.alc_tx_ring != NULL) 2353 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2354 sc->alc_rdata.alc_tx_ring, 2355 sc->alc_cdata.alc_tx_ring_map); 2356 sc->alc_rdata.alc_tx_ring_paddr = 0; 2357 sc->alc_rdata.alc_tx_ring = NULL; 2358 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2359 sc->alc_cdata.alc_tx_ring_tag = NULL; 2360 } 2361 /* Rx ring. */ 2362 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2363 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2364 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2365 sc->alc_cdata.alc_rx_ring_map); 2366 if (sc->alc_rdata.alc_rx_ring != NULL) 2367 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2368 sc->alc_rdata.alc_rx_ring, 2369 sc->alc_cdata.alc_rx_ring_map); 2370 sc->alc_rdata.alc_rx_ring_paddr = 0; 2371 sc->alc_rdata.alc_rx_ring = NULL; 2372 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2373 sc->alc_cdata.alc_rx_ring_tag = NULL; 2374 } 2375 /* Rx return ring. */ 2376 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2377 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2378 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2379 sc->alc_cdata.alc_rr_ring_map); 2380 if (sc->alc_rdata.alc_rr_ring != NULL) 2381 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2382 sc->alc_rdata.alc_rr_ring, 2383 sc->alc_cdata.alc_rr_ring_map); 2384 sc->alc_rdata.alc_rr_ring_paddr = 0; 2385 sc->alc_rdata.alc_rr_ring = NULL; 2386 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2387 sc->alc_cdata.alc_rr_ring_tag = NULL; 2388 } 2389 /* CMB block */ 2390 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2391 if (sc->alc_rdata.alc_cmb_paddr != 0) 2392 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2393 sc->alc_cdata.alc_cmb_map); 2394 if (sc->alc_rdata.alc_cmb != NULL) 2395 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2396 sc->alc_rdata.alc_cmb, 2397 sc->alc_cdata.alc_cmb_map); 2398 sc->alc_rdata.alc_cmb_paddr = 0; 2399 sc->alc_rdata.alc_cmb = NULL; 2400 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2401 sc->alc_cdata.alc_cmb_tag = NULL; 2402 } 2403 /* SMB block */ 2404 if (sc->alc_cdata.alc_smb_tag != NULL) { 2405 if (sc->alc_rdata.alc_smb_paddr != 0) 2406 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2407 sc->alc_cdata.alc_smb_map); 2408 if (sc->alc_rdata.alc_smb != NULL) 2409 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2410 sc->alc_rdata.alc_smb, 2411 sc->alc_cdata.alc_smb_map); 2412 sc->alc_rdata.alc_smb_paddr = 0; 2413 sc->alc_rdata.alc_smb = NULL; 2414 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2415 sc->alc_cdata.alc_smb_tag = NULL; 2416 } 2417 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2418 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2419 sc->alc_cdata.alc_buffer_tag = NULL; 2420 } 2421 if (sc->alc_cdata.alc_parent_tag != NULL) { 2422 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2423 sc->alc_cdata.alc_parent_tag = NULL; 2424 } 2425 } 2426 2427 static int 2428 alc_shutdown(device_t dev) 2429 { 2430 2431 return (alc_suspend(dev)); 2432 } 2433 2434 /* 2435 * Note, this driver resets the link speed to 10/100Mbps by 2436 * restarting auto-negotiation in suspend/shutdown phase but we 2437 * don't know whether that auto-negotiation would succeed or not 2438 * as driver has no control after powering off/suspend operation. 2439 * If the renegotiation fail WOL may not work. Running at 1Gbps 2440 * will draw more power than 375mA at 3.3V which is specified in 2441 * PCI specification and that would result in complete 2442 * shutdowning power to ethernet controller. 2443 * 2444 * TODO 2445 * Save current negotiated media speed/duplex/flow-control to 2446 * softc and restore the same link again after resuming. PHY 2447 * handling such as power down/resetting to 100Mbps may be better 2448 * handled in suspend method in phy driver. 2449 */ 2450 static void 2451 alc_setlinkspeed(struct alc_softc *sc) 2452 { 2453 struct mii_data *mii; 2454 int aneg, i; 2455 2456 mii = device_get_softc(sc->alc_miibus); 2457 mii_pollstat(mii); 2458 aneg = 0; 2459 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2460 (IFM_ACTIVE | IFM_AVALID)) { 2461 switch IFM_SUBTYPE(mii->mii_media_active) { 2462 case IFM_10_T: 2463 case IFM_100_TX: 2464 return; 2465 case IFM_1000_T: 2466 aneg++; 2467 break; 2468 default: 2469 break; 2470 } 2471 } 2472 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2473 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2474 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2475 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2476 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2477 DELAY(1000); 2478 if (aneg != 0) { 2479 /* 2480 * Poll link state until alc(4) get a 10/100Mbps link. 2481 */ 2482 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2483 mii_pollstat(mii); 2484 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2485 == (IFM_ACTIVE | IFM_AVALID)) { 2486 switch (IFM_SUBTYPE( 2487 mii->mii_media_active)) { 2488 case IFM_10_T: 2489 case IFM_100_TX: 2490 alc_mac_config(sc); 2491 return; 2492 default: 2493 break; 2494 } 2495 } 2496 ALC_UNLOCK(sc); 2497 pause("alclnk", hz); 2498 ALC_LOCK(sc); 2499 } 2500 if (i == MII_ANEGTICKS_GIGE) 2501 device_printf(sc->alc_dev, 2502 "establishing a link failed, WOL may not work!"); 2503 } 2504 /* 2505 * No link, force MAC to have 100Mbps, full-duplex link. 2506 * This is the last resort and may/may not work. 2507 */ 2508 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2509 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2510 alc_mac_config(sc); 2511 } 2512 2513 static void 2514 alc_setwol(struct alc_softc *sc) 2515 { 2516 2517 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2518 alc_setwol_816x(sc); 2519 else 2520 alc_setwol_813x(sc); 2521 } 2522 2523 static void 2524 alc_setwol_813x(struct alc_softc *sc) 2525 { 2526 if_t ifp; 2527 uint32_t reg, pmcs; 2528 uint16_t pmstat; 2529 2530 ALC_LOCK_ASSERT(sc); 2531 2532 alc_disable_l0s_l1(sc); 2533 ifp = sc->alc_ifp; 2534 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2535 /* Disable WOL. */ 2536 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2537 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2538 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2539 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2540 /* Force PHY power down. */ 2541 alc_phy_down(sc); 2542 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2543 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2544 return; 2545 } 2546 2547 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2548 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2549 alc_setlinkspeed(sc); 2550 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2551 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2552 } 2553 2554 pmcs = 0; 2555 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2556 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2557 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2558 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2559 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2560 MAC_CFG_BCAST); 2561 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2562 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2563 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2564 reg |= MAC_CFG_RX_ENB; 2565 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2566 2567 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2568 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2569 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2570 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2571 /* WOL disabled, PHY power down. */ 2572 alc_phy_down(sc); 2573 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2574 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2575 } 2576 /* Request PME. */ 2577 pmstat = pci_read_config(sc->alc_dev, 2578 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2579 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2580 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2581 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2582 pci_write_config(sc->alc_dev, 2583 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2584 } 2585 2586 static void 2587 alc_setwol_816x(struct alc_softc *sc) 2588 { 2589 if_t ifp; 2590 uint32_t gphy, mac, master, pmcs, reg; 2591 uint16_t pmstat; 2592 2593 ALC_LOCK_ASSERT(sc); 2594 2595 ifp = sc->alc_ifp; 2596 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2597 master &= ~MASTER_CLK_SEL_DIS; 2598 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2599 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2600 GPHY_CFG_PHY_PLL_ON); 2601 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2602 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2603 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2604 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2605 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2606 } else { 2607 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2608 gphy |= GPHY_CFG_EXT_RESET; 2609 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2610 alc_setlinkspeed(sc); 2611 } 2612 pmcs = 0; 2613 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2614 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2615 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2616 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2617 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2618 MAC_CFG_BCAST); 2619 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2620 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2621 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2622 mac |= MAC_CFG_RX_ENB; 2623 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2624 ANEG_S3DIG10_SL); 2625 } 2626 2627 /* Enable OSC. */ 2628 reg = CSR_READ_4(sc, ALC_MISC); 2629 reg &= ~MISC_INTNLOSC_OPEN; 2630 CSR_WRITE_4(sc, ALC_MISC, reg); 2631 reg |= MISC_INTNLOSC_OPEN; 2632 CSR_WRITE_4(sc, ALC_MISC, reg); 2633 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2634 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2635 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2636 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2637 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2638 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2639 2640 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2641 /* Request PME. */ 2642 pmstat = pci_read_config(sc->alc_dev, 2643 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2644 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2645 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2646 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2647 pci_write_config(sc->alc_dev, 2648 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2649 } 2650 } 2651 2652 static int 2653 alc_suspend(device_t dev) 2654 { 2655 struct alc_softc *sc; 2656 2657 sc = device_get_softc(dev); 2658 2659 ALC_LOCK(sc); 2660 alc_stop(sc); 2661 alc_setwol(sc); 2662 ALC_UNLOCK(sc); 2663 2664 return (0); 2665 } 2666 2667 static int 2668 alc_resume(device_t dev) 2669 { 2670 struct alc_softc *sc; 2671 if_t ifp; 2672 uint16_t pmstat; 2673 2674 sc = device_get_softc(dev); 2675 2676 ALC_LOCK(sc); 2677 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2678 /* Disable PME and clear PME status. */ 2679 pmstat = pci_read_config(sc->alc_dev, 2680 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2681 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2682 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2683 pci_write_config(sc->alc_dev, 2684 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2685 } 2686 } 2687 /* Reset PHY. */ 2688 alc_phy_reset(sc); 2689 ifp = sc->alc_ifp; 2690 if ((if_getflags(ifp) & IFF_UP) != 0) { 2691 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2692 alc_init_locked(sc); 2693 } 2694 ALC_UNLOCK(sc); 2695 2696 return (0); 2697 } 2698 2699 static int 2700 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2701 { 2702 struct alc_txdesc *txd, *txd_last; 2703 struct tx_desc *desc; 2704 struct mbuf *m; 2705 struct ip *ip; 2706 struct tcphdr *tcp; 2707 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2708 bus_dmamap_t map; 2709 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2710 int error, idx, nsegs, prod; 2711 2712 ALC_LOCK_ASSERT(sc); 2713 2714 M_ASSERTPKTHDR((*m_head)); 2715 2716 m = *m_head; 2717 ip = NULL; 2718 tcp = NULL; 2719 ip_off = poff = 0; 2720 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2721 /* 2722 * AR81[3567]x requires offset of TCP/UDP header in its 2723 * Tx descriptor to perform Tx checksum offloading. TSO 2724 * also requires TCP header offset and modification of 2725 * IP/TCP header. This kind of operation takes many CPU 2726 * cycles on FreeBSD so fast host CPU is required to get 2727 * smooth TSO performance. 2728 */ 2729 struct ether_header *eh; 2730 2731 if (M_WRITABLE(m) == 0) { 2732 /* Get a writable copy. */ 2733 m = m_dup(*m_head, M_NOWAIT); 2734 /* Release original mbufs. */ 2735 m_freem(*m_head); 2736 if (m == NULL) { 2737 *m_head = NULL; 2738 return (ENOBUFS); 2739 } 2740 *m_head = m; 2741 } 2742 2743 ip_off = sizeof(struct ether_header); 2744 m = m_pullup(m, ip_off); 2745 if (m == NULL) { 2746 *m_head = NULL; 2747 return (ENOBUFS); 2748 } 2749 eh = mtod(m, struct ether_header *); 2750 /* 2751 * Check if hardware VLAN insertion is off. 2752 * Additional check for LLC/SNAP frame? 2753 */ 2754 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2755 ip_off = sizeof(struct ether_vlan_header); 2756 m = m_pullup(m, ip_off); 2757 if (m == NULL) { 2758 *m_head = NULL; 2759 return (ENOBUFS); 2760 } 2761 } 2762 m = m_pullup(m, ip_off + sizeof(struct ip)); 2763 if (m == NULL) { 2764 *m_head = NULL; 2765 return (ENOBUFS); 2766 } 2767 ip = (struct ip *)(mtod(m, char *) + ip_off); 2768 poff = ip_off + (ip->ip_hl << 2); 2769 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2770 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2771 if (m == NULL) { 2772 *m_head = NULL; 2773 return (ENOBUFS); 2774 } 2775 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2776 m = m_pullup(m, poff + (tcp->th_off << 2)); 2777 if (m == NULL) { 2778 *m_head = NULL; 2779 return (ENOBUFS); 2780 } 2781 /* 2782 * Due to strict adherence of Microsoft NDIS 2783 * Large Send specification, hardware expects 2784 * a pseudo TCP checksum inserted by upper 2785 * stack. Unfortunately the pseudo TCP 2786 * checksum that NDIS refers to does not include 2787 * TCP payload length so driver should recompute 2788 * the pseudo checksum here. Hopefully this 2789 * wouldn't be much burden on modern CPUs. 2790 * 2791 * Reset IP checksum and recompute TCP pseudo 2792 * checksum as NDIS specification said. 2793 */ 2794 ip = (struct ip *)(mtod(m, char *) + ip_off); 2795 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2796 ip->ip_sum = 0; 2797 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2798 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2799 } 2800 *m_head = m; 2801 } 2802 2803 prod = sc->alc_cdata.alc_tx_prod; 2804 txd = &sc->alc_cdata.alc_txdesc[prod]; 2805 txd_last = txd; 2806 map = txd->tx_dmamap; 2807 2808 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2809 *m_head, txsegs, &nsegs, 0); 2810 if (error == EFBIG) { 2811 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2812 if (m == NULL) { 2813 m_freem(*m_head); 2814 *m_head = NULL; 2815 return (ENOMEM); 2816 } 2817 *m_head = m; 2818 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2819 *m_head, txsegs, &nsegs, 0); 2820 if (error != 0) { 2821 m_freem(*m_head); 2822 *m_head = NULL; 2823 return (error); 2824 } 2825 } else if (error != 0) 2826 return (error); 2827 if (nsegs == 0) { 2828 m_freem(*m_head); 2829 *m_head = NULL; 2830 return (EIO); 2831 } 2832 2833 /* Check descriptor overrun. */ 2834 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2835 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2836 return (ENOBUFS); 2837 } 2838 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2839 2840 m = *m_head; 2841 cflags = TD_ETHERNET; 2842 vtag = 0; 2843 desc = NULL; 2844 idx = 0; 2845 /* Configure VLAN hardware tag insertion. */ 2846 if ((m->m_flags & M_VLANTAG) != 0) { 2847 vtag = htons(m->m_pkthdr.ether_vtag); 2848 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2849 cflags |= TD_INS_VLAN_TAG; 2850 } 2851 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2852 /* Request TSO and set MSS. */ 2853 cflags |= TD_TSO | TD_TSO_DESCV1; 2854 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2855 TD_MSS_MASK; 2856 /* Set TCP header offset. */ 2857 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2858 TD_TCPHDR_OFFSET_MASK; 2859 /* 2860 * AR81[3567]x requires the first buffer should 2861 * only hold IP/TCP header data. Payload should 2862 * be handled in other descriptors. 2863 */ 2864 hdrlen = poff + (tcp->th_off << 2); 2865 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2866 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2867 desc->flags = htole32(cflags); 2868 desc->addr = htole64(txsegs[0].ds_addr); 2869 sc->alc_cdata.alc_tx_cnt++; 2870 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2871 if (m->m_len - hdrlen > 0) { 2872 /* Handle remaining payload of the first fragment. */ 2873 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2874 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2875 vtag)); 2876 desc->flags = htole32(cflags); 2877 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2878 sc->alc_cdata.alc_tx_cnt++; 2879 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2880 } 2881 /* Handle remaining fragments. */ 2882 idx = 1; 2883 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2884 /* Configure Tx checksum offload. */ 2885 #ifdef ALC_USE_CUSTOM_CSUM 2886 cflags |= TD_CUSTOM_CSUM; 2887 /* Set checksum start offset. */ 2888 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2889 TD_PLOAD_OFFSET_MASK; 2890 /* Set checksum insertion position of TCP/UDP. */ 2891 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2892 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2893 #else 2894 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2895 cflags |= TD_IPCSUM; 2896 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2897 cflags |= TD_TCPCSUM; 2898 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2899 cflags |= TD_UDPCSUM; 2900 /* Set TCP/UDP header offset. */ 2901 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2902 TD_L4HDR_OFFSET_MASK; 2903 #endif 2904 } 2905 for (; idx < nsegs; idx++) { 2906 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2907 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2908 desc->flags = htole32(cflags); 2909 desc->addr = htole64(txsegs[idx].ds_addr); 2910 sc->alc_cdata.alc_tx_cnt++; 2911 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2912 } 2913 /* Update producer index. */ 2914 sc->alc_cdata.alc_tx_prod = prod; 2915 2916 /* Finally set EOP on the last descriptor. */ 2917 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2918 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2919 desc->flags |= htole32(TD_EOP); 2920 2921 /* Swap dmamap of the first and the last. */ 2922 txd = &sc->alc_cdata.alc_txdesc[prod]; 2923 map = txd_last->tx_dmamap; 2924 txd_last->tx_dmamap = txd->tx_dmamap; 2925 txd->tx_dmamap = map; 2926 txd->tx_m = m; 2927 2928 return (0); 2929 } 2930 2931 static void 2932 alc_start(if_t ifp) 2933 { 2934 struct alc_softc *sc; 2935 2936 sc = if_getsoftc(ifp); 2937 ALC_LOCK(sc); 2938 alc_start_locked(ifp); 2939 ALC_UNLOCK(sc); 2940 } 2941 2942 static void 2943 alc_start_locked(if_t ifp) 2944 { 2945 struct alc_softc *sc; 2946 struct mbuf *m_head; 2947 int enq; 2948 2949 sc = if_getsoftc(ifp); 2950 2951 ALC_LOCK_ASSERT(sc); 2952 2953 /* Reclaim transmitted frames. */ 2954 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2955 alc_txeof(sc); 2956 2957 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2958 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2959 return; 2960 2961 for (enq = 0; !if_sendq_empty(ifp); ) { 2962 m_head = if_dequeue(ifp); 2963 if (m_head == NULL) 2964 break; 2965 /* 2966 * Pack the data into the transmit ring. If we 2967 * don't have room, set the OACTIVE flag and wait 2968 * for the NIC to drain the ring. 2969 */ 2970 if (alc_encap(sc, &m_head)) { 2971 if (m_head == NULL) 2972 break; 2973 if_sendq_prepend(ifp, m_head); 2974 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2975 break; 2976 } 2977 2978 enq++; 2979 /* 2980 * If there's a BPF listener, bounce a copy of this frame 2981 * to him. 2982 */ 2983 ETHER_BPF_MTAP(ifp, m_head); 2984 } 2985 2986 if (enq > 0) 2987 alc_start_tx(sc); 2988 } 2989 2990 static void 2991 alc_start_tx(struct alc_softc *sc) 2992 { 2993 2994 /* Sync descriptors. */ 2995 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2996 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2997 /* Kick. Assume we're using normal Tx priority queue. */ 2998 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2999 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3000 (uint16_t)sc->alc_cdata.alc_tx_prod); 3001 else 3002 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3003 (sc->alc_cdata.alc_tx_prod << 3004 MBOX_TD_PROD_LO_IDX_SHIFT) & 3005 MBOX_TD_PROD_LO_IDX_MASK); 3006 /* Set a timeout in case the chip goes out to lunch. */ 3007 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3008 } 3009 3010 static void 3011 alc_watchdog(struct alc_softc *sc) 3012 { 3013 if_t ifp; 3014 3015 ALC_LOCK_ASSERT(sc); 3016 3017 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3018 return; 3019 3020 ifp = sc->alc_ifp; 3021 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3022 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3023 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3024 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3025 alc_init_locked(sc); 3026 return; 3027 } 3028 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3029 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3030 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3031 alc_init_locked(sc); 3032 if (!if_sendq_empty(ifp)) 3033 alc_start_locked(ifp); 3034 } 3035 3036 static int 3037 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3038 { 3039 struct alc_softc *sc; 3040 struct ifreq *ifr; 3041 struct mii_data *mii; 3042 int error, mask; 3043 3044 sc = if_getsoftc(ifp); 3045 ifr = (struct ifreq *)data; 3046 error = 0; 3047 switch (cmd) { 3048 case SIOCSIFMTU: 3049 if (ifr->ifr_mtu < ETHERMIN || 3050 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3051 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3052 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3053 ifr->ifr_mtu > ETHERMTU)) 3054 error = EINVAL; 3055 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3056 ALC_LOCK(sc); 3057 if_setmtu(ifp, ifr->ifr_mtu); 3058 /* AR81[3567]x has 13 bits MSS field. */ 3059 if (if_getmtu(ifp) > ALC_TSO_MTU && 3060 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3061 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3062 if_sethwassistbits(ifp, 0, CSUM_TSO); 3063 VLAN_CAPABILITIES(ifp); 3064 } 3065 ALC_UNLOCK(sc); 3066 } 3067 break; 3068 case SIOCSIFFLAGS: 3069 ALC_LOCK(sc); 3070 if ((if_getflags(ifp) & IFF_UP) != 0) { 3071 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3072 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3073 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3074 alc_rxfilter(sc); 3075 else 3076 alc_init_locked(sc); 3077 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3078 alc_stop(sc); 3079 sc->alc_if_flags = if_getflags(ifp); 3080 ALC_UNLOCK(sc); 3081 break; 3082 case SIOCADDMULTI: 3083 case SIOCDELMULTI: 3084 ALC_LOCK(sc); 3085 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3086 alc_rxfilter(sc); 3087 ALC_UNLOCK(sc); 3088 break; 3089 case SIOCSIFMEDIA: 3090 case SIOCGIFMEDIA: 3091 mii = device_get_softc(sc->alc_miibus); 3092 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3093 break; 3094 case SIOCSIFCAP: 3095 ALC_LOCK(sc); 3096 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3097 if ((mask & IFCAP_TXCSUM) != 0 && 3098 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3099 if_togglecapenable(ifp, IFCAP_TXCSUM); 3100 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3101 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3102 else 3103 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3104 } 3105 if ((mask & IFCAP_TSO4) != 0 && 3106 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3107 if_togglecapenable(ifp, IFCAP_TSO4); 3108 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3109 /* AR81[3567]x has 13 bits MSS field. */ 3110 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3111 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3112 if_sethwassistbits(ifp, 0, CSUM_TSO); 3113 } else 3114 if_sethwassistbits(ifp, CSUM_TSO, 0); 3115 } else 3116 if_sethwassistbits(ifp, 0, CSUM_TSO); 3117 } 3118 if ((mask & IFCAP_WOL_MCAST) != 0 && 3119 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3120 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3121 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3122 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3123 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3124 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3125 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3126 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3127 alc_rxvlan(sc); 3128 } 3129 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3130 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3131 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3132 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3133 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3134 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3135 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3136 if_setcapenablebit(ifp, 0, 3137 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3138 ALC_UNLOCK(sc); 3139 VLAN_CAPABILITIES(ifp); 3140 break; 3141 default: 3142 error = ether_ioctl(ifp, cmd, data); 3143 break; 3144 } 3145 3146 return (error); 3147 } 3148 3149 static void 3150 alc_mac_config(struct alc_softc *sc) 3151 { 3152 struct mii_data *mii; 3153 uint32_t reg; 3154 3155 ALC_LOCK_ASSERT(sc); 3156 3157 mii = device_get_softc(sc->alc_miibus); 3158 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3159 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3160 MAC_CFG_SPEED_MASK); 3161 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3162 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3163 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3165 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3166 /* Reprogram MAC with resolved speed/duplex. */ 3167 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3168 case IFM_10_T: 3169 case IFM_100_TX: 3170 reg |= MAC_CFG_SPEED_10_100; 3171 break; 3172 case IFM_1000_T: 3173 reg |= MAC_CFG_SPEED_1000; 3174 break; 3175 } 3176 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3177 reg |= MAC_CFG_FULL_DUPLEX; 3178 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3179 reg |= MAC_CFG_TX_FC; 3180 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3181 reg |= MAC_CFG_RX_FC; 3182 } 3183 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3184 } 3185 3186 static void 3187 alc_stats_clear(struct alc_softc *sc) 3188 { 3189 struct smb sb, *smb; 3190 uint32_t *reg; 3191 int i; 3192 3193 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3194 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3195 sc->alc_cdata.alc_smb_map, 3196 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3197 smb = sc->alc_rdata.alc_smb; 3198 /* Update done, clear. */ 3199 smb->updated = 0; 3200 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3201 sc->alc_cdata.alc_smb_map, 3202 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3203 } else { 3204 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3205 reg++) { 3206 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3207 i += sizeof(uint32_t); 3208 } 3209 /* Read Tx statistics. */ 3210 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3211 reg++) { 3212 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3213 i += sizeof(uint32_t); 3214 } 3215 } 3216 } 3217 3218 static void 3219 alc_stats_update(struct alc_softc *sc) 3220 { 3221 struct alc_hw_stats *stat; 3222 struct smb sb, *smb; 3223 if_t ifp; 3224 uint32_t *reg; 3225 int i; 3226 3227 ALC_LOCK_ASSERT(sc); 3228 3229 ifp = sc->alc_ifp; 3230 stat = &sc->alc_stats; 3231 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3232 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3233 sc->alc_cdata.alc_smb_map, 3234 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3235 smb = sc->alc_rdata.alc_smb; 3236 if (smb->updated == 0) 3237 return; 3238 } else { 3239 smb = &sb; 3240 /* Read Rx statistics. */ 3241 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3242 reg++) { 3243 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3244 i += sizeof(uint32_t); 3245 } 3246 /* Read Tx statistics. */ 3247 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3248 reg++) { 3249 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3250 i += sizeof(uint32_t); 3251 } 3252 } 3253 3254 /* Rx stats. */ 3255 stat->rx_frames += smb->rx_frames; 3256 stat->rx_bcast_frames += smb->rx_bcast_frames; 3257 stat->rx_mcast_frames += smb->rx_mcast_frames; 3258 stat->rx_pause_frames += smb->rx_pause_frames; 3259 stat->rx_control_frames += smb->rx_control_frames; 3260 stat->rx_crcerrs += smb->rx_crcerrs; 3261 stat->rx_lenerrs += smb->rx_lenerrs; 3262 stat->rx_bytes += smb->rx_bytes; 3263 stat->rx_runts += smb->rx_runts; 3264 stat->rx_fragments += smb->rx_fragments; 3265 stat->rx_pkts_64 += smb->rx_pkts_64; 3266 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3267 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3268 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3269 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3270 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3271 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3272 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3273 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3274 stat->rx_rrs_errs += smb->rx_rrs_errs; 3275 stat->rx_alignerrs += smb->rx_alignerrs; 3276 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3277 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3278 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3279 3280 /* Tx stats. */ 3281 stat->tx_frames += smb->tx_frames; 3282 stat->tx_bcast_frames += smb->tx_bcast_frames; 3283 stat->tx_mcast_frames += smb->tx_mcast_frames; 3284 stat->tx_pause_frames += smb->tx_pause_frames; 3285 stat->tx_excess_defer += smb->tx_excess_defer; 3286 stat->tx_control_frames += smb->tx_control_frames; 3287 stat->tx_deferred += smb->tx_deferred; 3288 stat->tx_bytes += smb->tx_bytes; 3289 stat->tx_pkts_64 += smb->tx_pkts_64; 3290 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3291 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3292 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3293 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3294 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3295 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3296 stat->tx_single_colls += smb->tx_single_colls; 3297 stat->tx_multi_colls += smb->tx_multi_colls; 3298 stat->tx_late_colls += smb->tx_late_colls; 3299 stat->tx_excess_colls += smb->tx_excess_colls; 3300 stat->tx_underrun += smb->tx_underrun; 3301 stat->tx_desc_underrun += smb->tx_desc_underrun; 3302 stat->tx_lenerrs += smb->tx_lenerrs; 3303 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3304 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3305 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3306 3307 /* Update counters in ifnet. */ 3308 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3309 3310 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3311 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3312 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3313 3314 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3315 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3316 3317 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3318 3319 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3320 smb->rx_crcerrs + smb->rx_lenerrs + 3321 smb->rx_runts + smb->rx_pkts_truncated + 3322 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3323 smb->rx_alignerrs); 3324 3325 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3326 /* Update done, clear. */ 3327 smb->updated = 0; 3328 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3329 sc->alc_cdata.alc_smb_map, 3330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3331 } 3332 } 3333 3334 static int 3335 alc_intr(void *arg) 3336 { 3337 struct alc_softc *sc; 3338 uint32_t status; 3339 3340 sc = (struct alc_softc *)arg; 3341 3342 if (sc->alc_flags & ALC_FLAG_MT) { 3343 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3344 return (FILTER_HANDLED); 3345 } 3346 3347 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3348 if ((status & ALC_INTRS) == 0) 3349 return (FILTER_STRAY); 3350 /* Disable interrupts. */ 3351 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3352 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3353 3354 return (FILTER_HANDLED); 3355 } 3356 3357 static void 3358 alc_int_task(void *arg, int pending) 3359 { 3360 struct alc_softc *sc; 3361 if_t ifp; 3362 uint32_t status; 3363 int more; 3364 3365 sc = (struct alc_softc *)arg; 3366 ifp = sc->alc_ifp; 3367 3368 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3369 ALC_LOCK(sc); 3370 if (sc->alc_morework != 0) { 3371 sc->alc_morework = 0; 3372 status |= INTR_RX_PKT; 3373 } 3374 if ((status & ALC_INTRS) == 0) 3375 goto done; 3376 3377 /* Acknowledge interrupts but still disable interrupts. */ 3378 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3379 3380 more = 0; 3381 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3382 if ((status & INTR_RX_PKT) != 0) { 3383 more = alc_rxintr(sc, sc->alc_process_limit); 3384 if (more == EAGAIN) 3385 sc->alc_morework = 1; 3386 else if (more == EIO) { 3387 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3388 alc_init_locked(sc); 3389 ALC_UNLOCK(sc); 3390 return; 3391 } 3392 } 3393 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3394 INTR_TXQ_TO_RST)) != 0) { 3395 if ((status & INTR_DMA_RD_TO_RST) != 0) 3396 device_printf(sc->alc_dev, 3397 "DMA read error! -- resetting\n"); 3398 if ((status & INTR_DMA_WR_TO_RST) != 0) 3399 device_printf(sc->alc_dev, 3400 "DMA write error! -- resetting\n"); 3401 if ((status & INTR_TXQ_TO_RST) != 0) 3402 device_printf(sc->alc_dev, 3403 "TxQ reset! -- resetting\n"); 3404 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3405 alc_init_locked(sc); 3406 ALC_UNLOCK(sc); 3407 return; 3408 } 3409 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3410 !if_sendq_empty(ifp)) 3411 alc_start_locked(ifp); 3412 } 3413 3414 if (more == EAGAIN || 3415 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3416 ALC_UNLOCK(sc); 3417 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3418 return; 3419 } 3420 3421 done: 3422 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3423 /* Re-enable interrupts if we're running. */ 3424 if (sc->alc_flags & ALC_FLAG_MT) 3425 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3426 else 3427 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3428 } 3429 ALC_UNLOCK(sc); 3430 } 3431 3432 static void 3433 alc_txeof(struct alc_softc *sc) 3434 { 3435 if_t ifp; 3436 struct alc_txdesc *txd; 3437 uint32_t cons, prod; 3438 3439 ALC_LOCK_ASSERT(sc); 3440 3441 ifp = sc->alc_ifp; 3442 3443 if (sc->alc_cdata.alc_tx_cnt == 0) 3444 return; 3445 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3446 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3447 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3448 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3449 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3450 prod = sc->alc_rdata.alc_cmb->cons; 3451 } else { 3452 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3453 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3454 else { 3455 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3456 /* Assume we're using normal Tx priority queue. */ 3457 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3458 MBOX_TD_CONS_LO_IDX_SHIFT; 3459 } 3460 } 3461 cons = sc->alc_cdata.alc_tx_cons; 3462 /* 3463 * Go through our Tx list and free mbufs for those 3464 * frames which have been transmitted. 3465 */ 3466 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3467 if (sc->alc_cdata.alc_tx_cnt <= 0) 3468 break; 3469 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3470 sc->alc_cdata.alc_tx_cnt--; 3471 txd = &sc->alc_cdata.alc_txdesc[cons]; 3472 if (txd->tx_m != NULL) { 3473 /* Reclaim transmitted mbufs. */ 3474 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3475 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3476 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3477 txd->tx_dmamap); 3478 m_freem(txd->tx_m); 3479 txd->tx_m = NULL; 3480 } 3481 } 3482 3483 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3484 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3485 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3486 sc->alc_cdata.alc_tx_cons = cons; 3487 /* 3488 * Unarm watchdog timer only when there is no pending 3489 * frames in Tx queue. 3490 */ 3491 if (sc->alc_cdata.alc_tx_cnt == 0) 3492 sc->alc_watchdog_timer = 0; 3493 } 3494 3495 static int 3496 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3497 { 3498 struct mbuf *m; 3499 bus_dma_segment_t segs[1]; 3500 bus_dmamap_t map; 3501 int nsegs; 3502 3503 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3504 if (m == NULL) 3505 return (ENOBUFS); 3506 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3507 #ifndef __NO_STRICT_ALIGNMENT 3508 m_adj(m, sizeof(uint64_t)); 3509 #endif 3510 3511 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3512 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3513 m_freem(m); 3514 return (ENOBUFS); 3515 } 3516 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3517 3518 if (rxd->rx_m != NULL) { 3519 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3520 BUS_DMASYNC_POSTREAD); 3521 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3522 } 3523 map = rxd->rx_dmamap; 3524 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3525 sc->alc_cdata.alc_rx_sparemap = map; 3526 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3527 BUS_DMASYNC_PREREAD); 3528 rxd->rx_m = m; 3529 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3530 return (0); 3531 } 3532 3533 static int 3534 alc_rxintr(struct alc_softc *sc, int count) 3535 { 3536 if_t ifp; 3537 struct rx_rdesc *rrd; 3538 uint32_t nsegs, status; 3539 int rr_cons, prog; 3540 3541 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3542 sc->alc_cdata.alc_rr_ring_map, 3543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3544 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3545 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3546 rr_cons = sc->alc_cdata.alc_rr_cons; 3547 ifp = sc->alc_ifp; 3548 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3549 if (count-- <= 0) 3550 break; 3551 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3552 status = le32toh(rrd->status); 3553 if ((status & RRD_VALID) == 0) 3554 break; 3555 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3556 if (nsegs == 0) { 3557 /* This should not happen! */ 3558 device_printf(sc->alc_dev, 3559 "unexpected segment count -- resetting\n"); 3560 return (EIO); 3561 } 3562 alc_rxeof(sc, rrd); 3563 /* Clear Rx return status. */ 3564 rrd->status = 0; 3565 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3566 sc->alc_cdata.alc_rx_cons += nsegs; 3567 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3568 prog += nsegs; 3569 } 3570 3571 if (prog > 0) { 3572 /* Update the consumer index. */ 3573 sc->alc_cdata.alc_rr_cons = rr_cons; 3574 /* Sync Rx return descriptors. */ 3575 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3576 sc->alc_cdata.alc_rr_ring_map, 3577 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3578 /* 3579 * Sync updated Rx descriptors such that controller see 3580 * modified buffer addresses. 3581 */ 3582 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3583 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3584 /* 3585 * Let controller know availability of new Rx buffers. 3586 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3587 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3588 * only when Rx buffer pre-fetching is required. In 3589 * addition we already set ALC_RX_RD_FREE_THRESH to 3590 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3591 * it still seems that pre-fetching needs more 3592 * experimentation. 3593 */ 3594 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3595 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3596 (uint16_t)sc->alc_cdata.alc_rx_cons); 3597 else 3598 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3599 sc->alc_cdata.alc_rx_cons); 3600 } 3601 3602 return (count > 0 ? 0 : EAGAIN); 3603 } 3604 3605 #ifndef __NO_STRICT_ALIGNMENT 3606 static struct mbuf * 3607 alc_fixup_rx(if_t ifp, struct mbuf *m) 3608 { 3609 struct mbuf *n; 3610 int i; 3611 uint16_t *src, *dst; 3612 3613 src = mtod(m, uint16_t *); 3614 dst = src - 3; 3615 3616 if (m->m_next == NULL) { 3617 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3618 *dst++ = *src++; 3619 m->m_data -= 6; 3620 return (m); 3621 } 3622 /* 3623 * Append a new mbuf to received mbuf chain and copy ethernet 3624 * header from the mbuf chain. This can save lots of CPU 3625 * cycles for jumbo frame. 3626 */ 3627 MGETHDR(n, M_NOWAIT, MT_DATA); 3628 if (n == NULL) { 3629 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3630 m_freem(m); 3631 return (NULL); 3632 } 3633 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3634 m->m_data += ETHER_HDR_LEN; 3635 m->m_len -= ETHER_HDR_LEN; 3636 n->m_len = ETHER_HDR_LEN; 3637 M_MOVE_PKTHDR(n, m); 3638 n->m_next = m; 3639 return (n); 3640 } 3641 #endif 3642 3643 /* Receive a frame. */ 3644 static void 3645 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3646 { 3647 struct alc_rxdesc *rxd; 3648 if_t ifp; 3649 struct mbuf *mp, *m; 3650 uint32_t rdinfo, status, vtag; 3651 int count, nsegs, rx_cons; 3652 3653 ifp = sc->alc_ifp; 3654 status = le32toh(rrd->status); 3655 rdinfo = le32toh(rrd->rdinfo); 3656 rx_cons = RRD_RD_IDX(rdinfo); 3657 nsegs = RRD_RD_CNT(rdinfo); 3658 3659 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3660 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3661 /* 3662 * We want to pass the following frames to upper 3663 * layer regardless of error status of Rx return 3664 * ring. 3665 * 3666 * o IP/TCP/UDP checksum is bad. 3667 * o frame length and protocol specific length 3668 * does not match. 3669 * 3670 * Force network stack compute checksum for 3671 * errored frames. 3672 */ 3673 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3674 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3675 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3676 return; 3677 } 3678 3679 for (count = 0; count < nsegs; count++, 3680 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3681 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3682 mp = rxd->rx_m; 3683 /* Add a new receive buffer to the ring. */ 3684 if (alc_newbuf(sc, rxd) != 0) { 3685 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3686 /* Reuse Rx buffers. */ 3687 if (sc->alc_cdata.alc_rxhead != NULL) 3688 m_freem(sc->alc_cdata.alc_rxhead); 3689 break; 3690 } 3691 3692 /* 3693 * Assume we've received a full sized frame. 3694 * Actual size is fixed when we encounter the end of 3695 * multi-segmented frame. 3696 */ 3697 mp->m_len = sc->alc_buf_size; 3698 3699 /* Chain received mbufs. */ 3700 if (sc->alc_cdata.alc_rxhead == NULL) { 3701 sc->alc_cdata.alc_rxhead = mp; 3702 sc->alc_cdata.alc_rxtail = mp; 3703 } else { 3704 mp->m_flags &= ~M_PKTHDR; 3705 sc->alc_cdata.alc_rxprev_tail = 3706 sc->alc_cdata.alc_rxtail; 3707 sc->alc_cdata.alc_rxtail->m_next = mp; 3708 sc->alc_cdata.alc_rxtail = mp; 3709 } 3710 3711 if (count == nsegs - 1) { 3712 /* Last desc. for this frame. */ 3713 m = sc->alc_cdata.alc_rxhead; 3714 m->m_flags |= M_PKTHDR; 3715 /* 3716 * It seems that L1C/L2C controller has no way 3717 * to tell hardware to strip CRC bytes. 3718 */ 3719 m->m_pkthdr.len = 3720 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3721 if (nsegs > 1) { 3722 /* Set last mbuf size. */ 3723 mp->m_len = sc->alc_cdata.alc_rxlen - 3724 (nsegs - 1) * sc->alc_buf_size; 3725 /* Remove the CRC bytes in chained mbufs. */ 3726 if (mp->m_len <= ETHER_CRC_LEN) { 3727 sc->alc_cdata.alc_rxtail = 3728 sc->alc_cdata.alc_rxprev_tail; 3729 sc->alc_cdata.alc_rxtail->m_len -= 3730 (ETHER_CRC_LEN - mp->m_len); 3731 sc->alc_cdata.alc_rxtail->m_next = NULL; 3732 m_freem(mp); 3733 } else { 3734 mp->m_len -= ETHER_CRC_LEN; 3735 } 3736 } else 3737 m->m_len = m->m_pkthdr.len; 3738 m->m_pkthdr.rcvif = ifp; 3739 /* 3740 * Due to hardware bugs, Rx checksum offloading 3741 * was intentionally disabled. 3742 */ 3743 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3744 (status & RRD_VLAN_TAG) != 0) { 3745 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3746 m->m_pkthdr.ether_vtag = ntohs(vtag); 3747 m->m_flags |= M_VLANTAG; 3748 } 3749 #ifndef __NO_STRICT_ALIGNMENT 3750 m = alc_fixup_rx(ifp, m); 3751 if (m != NULL) 3752 #endif 3753 { 3754 /* Pass it on. */ 3755 ALC_UNLOCK(sc); 3756 if_input(ifp, m); 3757 ALC_LOCK(sc); 3758 } 3759 } 3760 } 3761 /* Reset mbuf chains. */ 3762 ALC_RXCHAIN_RESET(sc); 3763 } 3764 3765 static void 3766 alc_tick(void *arg) 3767 { 3768 struct alc_softc *sc; 3769 struct mii_data *mii; 3770 3771 sc = (struct alc_softc *)arg; 3772 3773 ALC_LOCK_ASSERT(sc); 3774 3775 mii = device_get_softc(sc->alc_miibus); 3776 mii_tick(mii); 3777 alc_stats_update(sc); 3778 /* 3779 * alc(4) does not rely on Tx completion interrupts to reclaim 3780 * transferred buffers. Instead Tx completion interrupts are 3781 * used to hint for scheduling Tx task. So it's necessary to 3782 * release transmitted buffers by kicking Tx completion 3783 * handler. This limits the maximum reclamation delay to a hz. 3784 */ 3785 alc_txeof(sc); 3786 alc_watchdog(sc); 3787 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3788 } 3789 3790 static void 3791 alc_osc_reset(struct alc_softc *sc) 3792 { 3793 uint32_t reg; 3794 3795 reg = CSR_READ_4(sc, ALC_MISC3); 3796 reg &= ~MISC3_25M_BY_SW; 3797 reg |= MISC3_25M_NOTO_INTNL; 3798 CSR_WRITE_4(sc, ALC_MISC3, reg); 3799 3800 reg = CSR_READ_4(sc, ALC_MISC); 3801 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3802 /* 3803 * Restore over-current protection default value. 3804 * This value could be reset by MAC reset. 3805 */ 3806 reg &= ~MISC_PSW_OCP_MASK; 3807 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3808 reg &= ~MISC_INTNLOSC_OPEN; 3809 CSR_WRITE_4(sc, ALC_MISC, reg); 3810 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3811 reg = CSR_READ_4(sc, ALC_MISC2); 3812 reg &= ~MISC2_CALB_START; 3813 CSR_WRITE_4(sc, ALC_MISC2, reg); 3814 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3815 3816 } else { 3817 reg &= ~MISC_INTNLOSC_OPEN; 3818 /* Disable isolate for revision A devices. */ 3819 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3820 reg &= ~MISC_ISO_ENB; 3821 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3822 CSR_WRITE_4(sc, ALC_MISC, reg); 3823 } 3824 3825 DELAY(20); 3826 } 3827 3828 static void 3829 alc_reset(struct alc_softc *sc) 3830 { 3831 uint32_t pmcfg, reg; 3832 int i; 3833 3834 pmcfg = 0; 3835 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3836 /* Reset workaround. */ 3837 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3838 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3839 (sc->alc_rev & 0x01) != 0) { 3840 /* Disable L0s/L1s before reset. */ 3841 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3842 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3843 != 0) { 3844 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3845 PM_CFG_ASPM_L1_ENB); 3846 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3847 } 3848 } 3849 } 3850 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3851 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3852 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3853 3854 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3855 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3856 DELAY(10); 3857 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3858 break; 3859 } 3860 if (i == 0) 3861 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3862 } 3863 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3864 DELAY(10); 3865 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3866 break; 3867 } 3868 if (i == 0) 3869 device_printf(sc->alc_dev, "master reset timeout!\n"); 3870 3871 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3872 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3873 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3874 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3875 break; 3876 DELAY(10); 3877 } 3878 if (i == 0) 3879 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3880 3881 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3882 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3883 (sc->alc_rev & 0x01) != 0) { 3884 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3885 reg |= MASTER_CLK_SEL_DIS; 3886 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3887 /* Restore L0s/L1s config. */ 3888 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3889 != 0) 3890 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3891 } 3892 3893 alc_osc_reset(sc); 3894 reg = CSR_READ_4(sc, ALC_MISC3); 3895 reg &= ~MISC3_25M_BY_SW; 3896 reg |= MISC3_25M_NOTO_INTNL; 3897 CSR_WRITE_4(sc, ALC_MISC3, reg); 3898 reg = CSR_READ_4(sc, ALC_MISC); 3899 reg &= ~MISC_INTNLOSC_OPEN; 3900 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3901 reg &= ~MISC_ISO_ENB; 3902 CSR_WRITE_4(sc, ALC_MISC, reg); 3903 DELAY(20); 3904 } 3905 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3906 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3907 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3908 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3909 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3910 SERDES_PHY_CLK_SLOWDOWN); 3911 } 3912 3913 static void 3914 alc_init(void *xsc) 3915 { 3916 struct alc_softc *sc; 3917 3918 sc = (struct alc_softc *)xsc; 3919 ALC_LOCK(sc); 3920 alc_init_locked(sc); 3921 ALC_UNLOCK(sc); 3922 } 3923 3924 static void 3925 alc_init_locked(struct alc_softc *sc) 3926 { 3927 if_t ifp; 3928 uint8_t eaddr[ETHER_ADDR_LEN]; 3929 bus_addr_t paddr; 3930 uint32_t reg, rxf_hi, rxf_lo; 3931 3932 ALC_LOCK_ASSERT(sc); 3933 3934 ifp = sc->alc_ifp; 3935 3936 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3937 return; 3938 /* 3939 * Cancel any pending I/O. 3940 */ 3941 alc_stop(sc); 3942 /* 3943 * Reset the chip to a known state. 3944 */ 3945 alc_reset(sc); 3946 3947 /* Initialize Rx descriptors. */ 3948 if (alc_init_rx_ring(sc) != 0) { 3949 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3950 alc_stop(sc); 3951 return; 3952 } 3953 alc_init_rr_ring(sc); 3954 alc_init_tx_ring(sc); 3955 alc_init_cmb(sc); 3956 alc_init_smb(sc); 3957 3958 /* Enable all clocks. */ 3959 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3960 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3961 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3962 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3963 CLK_GATING_RXMAC_ENB); 3964 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3965 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3966 IDLE_DECISN_TIMER_DEFAULT_1MS); 3967 } else 3968 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3969 3970 /* Reprogram the station address. */ 3971 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3972 CSR_WRITE_4(sc, ALC_PAR0, 3973 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3974 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3975 /* 3976 * Clear WOL status and disable all WOL feature as WOL 3977 * would interfere Rx operation under normal environments. 3978 */ 3979 CSR_READ_4(sc, ALC_WOL_CFG); 3980 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3981 /* Set Tx descriptor base addresses. */ 3982 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3983 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3984 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3985 /* We don't use high priority ring. */ 3986 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3987 /* Set Tx descriptor counter. */ 3988 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3989 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3990 /* Set Rx descriptor base addresses. */ 3991 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3992 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3993 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3994 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3995 /* We use one Rx ring. */ 3996 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3997 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3998 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3999 } 4000 /* Set Rx descriptor counter. */ 4001 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4002 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4003 4004 /* 4005 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4006 * if it do not fit the buffer size. Rx return descriptor holds 4007 * a counter that indicates how many fragments were made by the 4008 * hardware. The buffer size should be multiple of 8 bytes. 4009 * Since hardware has limit on the size of buffer size, always 4010 * use the maximum value. 4011 * For strict-alignment architectures make sure to reduce buffer 4012 * size by 8 bytes to make room for alignment fixup. 4013 */ 4014 #ifndef __NO_STRICT_ALIGNMENT 4015 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4016 #else 4017 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4018 #endif 4019 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4020 4021 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4022 /* Set Rx return descriptor base addresses. */ 4023 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4024 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4025 /* We use one Rx return ring. */ 4026 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4027 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4028 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4029 } 4030 /* Set Rx return descriptor counter. */ 4031 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4032 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4033 paddr = sc->alc_rdata.alc_cmb_paddr; 4034 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4035 paddr = sc->alc_rdata.alc_smb_paddr; 4036 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4037 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4038 4039 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4040 /* Reconfigure SRAM - Vendor magic. */ 4041 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4042 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4043 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4044 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4045 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4046 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4047 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4048 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4049 } 4050 4051 /* Tell hardware that we're ready to load DMA blocks. */ 4052 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4053 4054 /* Configure interrupt moderation timer. */ 4055 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4056 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4057 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4058 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4059 /* 4060 * We don't want to automatic interrupt clear as task queue 4061 * for the interrupt should know interrupt status. 4062 */ 4063 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4064 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4065 reg |= MASTER_SA_TIMER_ENB; 4066 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4067 reg |= MASTER_IM_RX_TIMER_ENB; 4068 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4069 ALC_USECS(sc->alc_int_tx_mod) != 0) 4070 reg |= MASTER_IM_TX_TIMER_ENB; 4071 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4072 /* 4073 * Disable interrupt re-trigger timer. We don't want automatic 4074 * re-triggering of un-ACKed interrupts. 4075 */ 4076 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4077 /* Configure CMB. */ 4078 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4079 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4080 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4081 ALC_USECS(sc->alc_int_tx_mod)); 4082 } else { 4083 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4084 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4085 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4086 } else 4087 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4088 } 4089 /* 4090 * Hardware can be configured to issue SMB interrupt based 4091 * on programmed interval. Since there is a callout that is 4092 * invoked for every hz in driver we use that instead of 4093 * relying on periodic SMB interrupt. 4094 */ 4095 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4096 /* Clear MAC statistics. */ 4097 alc_stats_clear(sc); 4098 4099 /* 4100 * Always use maximum frame size that controller can support. 4101 * Otherwise received frames that has larger frame length 4102 * than alc(4) MTU would be silently dropped in hardware. This 4103 * would make path-MTU discovery hard as sender wouldn't get 4104 * any responses from receiver. alc(4) supports 4105 * multi-fragmented frames on Rx path so it has no issue on 4106 * assembling fragmented frames. Using maximum frame size also 4107 * removes the need to reinitialize hardware when interface 4108 * MTU configuration was changed. 4109 * 4110 * Be conservative in what you do, be liberal in what you 4111 * accept from others - RFC 793. 4112 */ 4113 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4114 4115 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4116 /* Disable header split(?) */ 4117 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4118 4119 /* Configure IPG/IFG parameters. */ 4120 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4121 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4122 IPG_IFG_IPGT_MASK) | 4123 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4124 IPG_IFG_MIFG_MASK) | 4125 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4126 IPG_IFG_IPG1_MASK) | 4127 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4128 IPG_IFG_IPG2_MASK)); 4129 /* Set parameters for half-duplex media. */ 4130 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4131 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4132 HDPX_CFG_LCOL_MASK) | 4133 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4134 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4135 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4136 HDPX_CFG_ABEBT_MASK) | 4137 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4138 HDPX_CFG_JAMIPG_MASK)); 4139 } 4140 4141 /* 4142 * Set TSO/checksum offload threshold. For frames that is 4143 * larger than this threshold, hardware wouldn't do 4144 * TSO/checksum offloading. 4145 */ 4146 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4147 TSO_OFFLOAD_THRESH_MASK; 4148 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4149 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4150 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4151 /* Configure TxQ. */ 4152 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4153 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4154 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4155 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4156 reg >>= 1; 4157 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4158 TXQ_CFG_TD_BURST_MASK; 4159 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4160 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4161 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4162 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4163 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4164 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4165 HQTD_CFG_BURST_ENB); 4166 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4167 reg = WRR_PRI_RESTRICT_NONE; 4168 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4169 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4170 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4171 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4172 CSR_WRITE_4(sc, ALC_WRR, reg); 4173 } else { 4174 /* Configure Rx free descriptor pre-fetching. */ 4175 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4176 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4177 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4178 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4179 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4180 } 4181 4182 /* 4183 * Configure flow control parameters. 4184 * XON : 80% of Rx FIFO 4185 * XOFF : 30% of Rx FIFO 4186 */ 4187 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4188 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4189 reg &= SRAM_RX_FIFO_LEN_MASK; 4190 reg *= 8; 4191 if (reg > 8 * 1024) 4192 reg -= RX_FIFO_PAUSE_816X_RSVD; 4193 else 4194 reg -= RX_BUF_SIZE_MAX; 4195 reg /= 8; 4196 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4197 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4198 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4199 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4200 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4201 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4202 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4203 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4204 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4205 rxf_hi = (reg * 8) / 10; 4206 rxf_lo = (reg * 3) / 10; 4207 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4208 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4209 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4210 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4211 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4212 } 4213 4214 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4215 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4216 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4217 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4218 } 4219 4220 /* Configure RxQ. */ 4221 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4222 RXQ_CFG_RD_BURST_MASK; 4223 reg |= RXQ_CFG_RSS_MODE_DIS; 4224 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4225 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4226 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4227 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4228 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4229 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4230 } else { 4231 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4232 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4233 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4234 } 4235 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4236 4237 /* Configure DMA parameters. */ 4238 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4239 reg |= sc->alc_rcb; 4240 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4241 reg |= DMA_CFG_CMB_ENB; 4242 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4243 reg |= DMA_CFG_SMB_ENB; 4244 else 4245 reg |= DMA_CFG_SMB_DIS; 4246 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4247 DMA_CFG_RD_BURST_SHIFT; 4248 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4249 DMA_CFG_WR_BURST_SHIFT; 4250 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4251 DMA_CFG_RD_DELAY_CNT_MASK; 4252 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4253 DMA_CFG_WR_DELAY_CNT_MASK; 4254 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4255 switch (AR816X_REV(sc->alc_rev)) { 4256 case AR816X_REV_A0: 4257 case AR816X_REV_A1: 4258 reg |= DMA_CFG_RD_CHNL_SEL_2; 4259 break; 4260 case AR816X_REV_B0: 4261 /* FALLTHROUGH */ 4262 default: 4263 reg |= DMA_CFG_RD_CHNL_SEL_4; 4264 break; 4265 } 4266 } 4267 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4268 4269 /* 4270 * Configure Tx/Rx MACs. 4271 * - Auto-padding for short frames. 4272 * - Enable CRC generation. 4273 * Actual reconfiguration of MAC for resolved speed/duplex 4274 * is followed after detection of link establishment. 4275 * AR813x/AR815x always does checksum computation regardless 4276 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4277 * have bug in protocol field in Rx return structure so 4278 * these controllers can't handle fragmented frames. Disable 4279 * Rx checksum offloading until there is a newer controller 4280 * that has sane implementation. 4281 */ 4282 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4283 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4284 MAC_CFG_PREAMBLE_MASK); 4285 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4286 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4287 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4288 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4289 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4290 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4291 reg |= MAC_CFG_SPEED_10_100; 4292 else 4293 reg |= MAC_CFG_SPEED_1000; 4294 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4295 4296 /* Set up the receive filter. */ 4297 alc_rxfilter(sc); 4298 alc_rxvlan(sc); 4299 4300 /* Acknowledge all pending interrupts and clear it. */ 4301 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4302 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4303 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4304 4305 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4306 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4307 4308 sc->alc_flags &= ~ALC_FLAG_LINK; 4309 /* Switch to the current media. */ 4310 alc_mediachange_locked(sc); 4311 4312 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4313 } 4314 4315 static void 4316 alc_stop(struct alc_softc *sc) 4317 { 4318 if_t ifp; 4319 struct alc_txdesc *txd; 4320 struct alc_rxdesc *rxd; 4321 uint32_t reg; 4322 int i; 4323 4324 ALC_LOCK_ASSERT(sc); 4325 /* 4326 * Mark the interface down and cancel the watchdog timer. 4327 */ 4328 ifp = sc->alc_ifp; 4329 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4330 sc->alc_flags &= ~ALC_FLAG_LINK; 4331 callout_stop(&sc->alc_tick_ch); 4332 sc->alc_watchdog_timer = 0; 4333 alc_stats_update(sc); 4334 /* Disable interrupts. */ 4335 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4336 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4337 /* Disable DMA. */ 4338 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4339 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4340 reg |= DMA_CFG_SMB_DIS; 4341 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4342 DELAY(1000); 4343 /* Stop Rx/Tx MACs. */ 4344 alc_stop_mac(sc); 4345 /* Disable interrupts which might be touched in taskq handler. */ 4346 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4347 /* Disable L0s/L1s */ 4348 alc_aspm(sc, 0, IFM_UNKNOWN); 4349 /* Reclaim Rx buffers that have been processed. */ 4350 if (sc->alc_cdata.alc_rxhead != NULL) 4351 m_freem(sc->alc_cdata.alc_rxhead); 4352 ALC_RXCHAIN_RESET(sc); 4353 /* 4354 * Free Tx/Rx mbufs still in the queues. 4355 */ 4356 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4357 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4358 if (rxd->rx_m != NULL) { 4359 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4360 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4361 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4362 rxd->rx_dmamap); 4363 m_freem(rxd->rx_m); 4364 rxd->rx_m = NULL; 4365 } 4366 } 4367 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4368 txd = &sc->alc_cdata.alc_txdesc[i]; 4369 if (txd->tx_m != NULL) { 4370 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4371 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4372 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4373 txd->tx_dmamap); 4374 m_freem(txd->tx_m); 4375 txd->tx_m = NULL; 4376 } 4377 } 4378 } 4379 4380 static void 4381 alc_stop_mac(struct alc_softc *sc) 4382 { 4383 uint32_t reg; 4384 int i; 4385 4386 alc_stop_queue(sc); 4387 /* Disable Rx/Tx MAC. */ 4388 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4389 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4390 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4391 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4392 } 4393 for (i = ALC_TIMEOUT; i > 0; i--) { 4394 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4395 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4396 break; 4397 DELAY(10); 4398 } 4399 if (i == 0) 4400 device_printf(sc->alc_dev, 4401 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4402 } 4403 4404 static void 4405 alc_start_queue(struct alc_softc *sc) 4406 { 4407 uint32_t qcfg[] = { 4408 0, 4409 RXQ_CFG_QUEUE0_ENB, 4410 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4411 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4412 RXQ_CFG_ENB 4413 }; 4414 uint32_t cfg; 4415 4416 ALC_LOCK_ASSERT(sc); 4417 4418 /* Enable RxQ. */ 4419 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4420 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4421 cfg &= ~RXQ_CFG_ENB; 4422 cfg |= qcfg[1]; 4423 } else 4424 cfg |= RXQ_CFG_QUEUE0_ENB; 4425 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4426 /* Enable TxQ. */ 4427 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4428 cfg |= TXQ_CFG_ENB; 4429 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4430 } 4431 4432 static void 4433 alc_stop_queue(struct alc_softc *sc) 4434 { 4435 uint32_t reg; 4436 int i; 4437 4438 /* Disable RxQ. */ 4439 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4440 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4441 if ((reg & RXQ_CFG_ENB) != 0) { 4442 reg &= ~RXQ_CFG_ENB; 4443 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4444 } 4445 } else { 4446 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4447 reg &= ~RXQ_CFG_QUEUE0_ENB; 4448 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4449 } 4450 } 4451 /* Disable TxQ. */ 4452 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4453 if ((reg & TXQ_CFG_ENB) != 0) { 4454 reg &= ~TXQ_CFG_ENB; 4455 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4456 } 4457 DELAY(40); 4458 for (i = ALC_TIMEOUT; i > 0; i--) { 4459 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4460 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4461 break; 4462 DELAY(10); 4463 } 4464 if (i == 0) 4465 device_printf(sc->alc_dev, 4466 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4467 } 4468 4469 static void 4470 alc_init_tx_ring(struct alc_softc *sc) 4471 { 4472 struct alc_ring_data *rd; 4473 struct alc_txdesc *txd; 4474 int i; 4475 4476 ALC_LOCK_ASSERT(sc); 4477 4478 sc->alc_cdata.alc_tx_prod = 0; 4479 sc->alc_cdata.alc_tx_cons = 0; 4480 sc->alc_cdata.alc_tx_cnt = 0; 4481 4482 rd = &sc->alc_rdata; 4483 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4484 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4485 txd = &sc->alc_cdata.alc_txdesc[i]; 4486 txd->tx_m = NULL; 4487 } 4488 4489 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4490 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4491 } 4492 4493 static int 4494 alc_init_rx_ring(struct alc_softc *sc) 4495 { 4496 struct alc_ring_data *rd; 4497 struct alc_rxdesc *rxd; 4498 int i; 4499 4500 ALC_LOCK_ASSERT(sc); 4501 4502 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4503 sc->alc_morework = 0; 4504 rd = &sc->alc_rdata; 4505 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4506 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4507 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4508 rxd->rx_m = NULL; 4509 rxd->rx_desc = &rd->alc_rx_ring[i]; 4510 if (alc_newbuf(sc, rxd) != 0) 4511 return (ENOBUFS); 4512 } 4513 4514 /* 4515 * Since controller does not update Rx descriptors, driver 4516 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4517 * is enough to ensure coherence. 4518 */ 4519 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4520 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4521 /* Let controller know availability of new Rx buffers. */ 4522 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4523 4524 return (0); 4525 } 4526 4527 static void 4528 alc_init_rr_ring(struct alc_softc *sc) 4529 { 4530 struct alc_ring_data *rd; 4531 4532 ALC_LOCK_ASSERT(sc); 4533 4534 sc->alc_cdata.alc_rr_cons = 0; 4535 ALC_RXCHAIN_RESET(sc); 4536 4537 rd = &sc->alc_rdata; 4538 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4539 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4540 sc->alc_cdata.alc_rr_ring_map, 4541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4542 } 4543 4544 static void 4545 alc_init_cmb(struct alc_softc *sc) 4546 { 4547 struct alc_ring_data *rd; 4548 4549 ALC_LOCK_ASSERT(sc); 4550 4551 rd = &sc->alc_rdata; 4552 bzero(rd->alc_cmb, ALC_CMB_SZ); 4553 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4555 } 4556 4557 static void 4558 alc_init_smb(struct alc_softc *sc) 4559 { 4560 struct alc_ring_data *rd; 4561 4562 ALC_LOCK_ASSERT(sc); 4563 4564 rd = &sc->alc_rdata; 4565 bzero(rd->alc_smb, ALC_SMB_SZ); 4566 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4568 } 4569 4570 static void 4571 alc_rxvlan(struct alc_softc *sc) 4572 { 4573 if_t ifp; 4574 uint32_t reg; 4575 4576 ALC_LOCK_ASSERT(sc); 4577 4578 ifp = sc->alc_ifp; 4579 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4580 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4581 reg |= MAC_CFG_VLAN_TAG_STRIP; 4582 else 4583 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4584 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4585 } 4586 4587 static u_int 4588 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4589 { 4590 uint32_t *mchash = arg; 4591 uint32_t crc; 4592 4593 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4594 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4595 4596 return (1); 4597 } 4598 4599 static void 4600 alc_rxfilter(struct alc_softc *sc) 4601 { 4602 if_t ifp; 4603 uint32_t mchash[2]; 4604 uint32_t rxcfg; 4605 4606 ALC_LOCK_ASSERT(sc); 4607 4608 ifp = sc->alc_ifp; 4609 4610 bzero(mchash, sizeof(mchash)); 4611 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4612 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4613 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4614 rxcfg |= MAC_CFG_BCAST; 4615 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4616 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4617 rxcfg |= MAC_CFG_PROMISC; 4618 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4619 rxcfg |= MAC_CFG_ALLMULTI; 4620 mchash[0] = 0xFFFFFFFF; 4621 mchash[1] = 0xFFFFFFFF; 4622 goto chipit; 4623 } 4624 4625 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4626 4627 chipit: 4628 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4629 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4630 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4631 } 4632 4633 static int 4634 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4635 { 4636 int error, value; 4637 4638 if (arg1 == NULL) 4639 return (EINVAL); 4640 value = *(int *)arg1; 4641 error = sysctl_handle_int(oidp, &value, 0, req); 4642 if (error || req->newptr == NULL) 4643 return (error); 4644 if (value < low || value > high) 4645 return (EINVAL); 4646 *(int *)arg1 = value; 4647 4648 return (0); 4649 } 4650 4651 static int 4652 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4653 { 4654 return (sysctl_int_range(oidp, arg1, arg2, req, 4655 ALC_PROC_MIN, ALC_PROC_MAX)); 4656 } 4657 4658 static int 4659 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4660 { 4661 4662 return (sysctl_int_range(oidp, arg1, arg2, req, 4663 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4664 } 4665 4666 #ifdef DEBUGNET 4667 static void 4668 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4669 { 4670 struct alc_softc *sc __diagused; 4671 4672 sc = if_getsoftc(ifp); 4673 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4674 4675 *nrxr = ALC_RX_RING_CNT; 4676 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4677 *clsize = MCLBYTES; 4678 } 4679 4680 static void 4681 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4682 { 4683 } 4684 4685 static int 4686 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4687 { 4688 struct alc_softc *sc; 4689 int error; 4690 4691 sc = if_getsoftc(ifp); 4692 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4693 IFF_DRV_RUNNING) 4694 return (EBUSY); 4695 4696 error = alc_encap(sc, &m); 4697 if (error == 0) 4698 alc_start_tx(sc); 4699 return (error); 4700 } 4701 4702 static int 4703 alc_debugnet_poll(if_t ifp, int count) 4704 { 4705 struct alc_softc *sc; 4706 4707 sc = if_getsoftc(ifp); 4708 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4709 IFF_DRV_RUNNING) 4710 return (EBUSY); 4711 4712 alc_txeof(sc); 4713 return (alc_rxintr(sc, count)); 4714 } 4715 #endif /* DEBUGNET */ 4716