1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/bus.h> 72 #include <machine/in_cksum.h> 73 74 #include <dev/alc/if_alcreg.h> 75 #include <dev/alc/if_alcvar.h> 76 77 /* "device miibus" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 #undef ALC_USE_CUSTOM_CSUM 80 81 #ifdef ALC_USE_CUSTOM_CSUM 82 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 #else 84 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 #endif 86 87 MODULE_DEPEND(alc, pci, 1, 1, 1); 88 MODULE_DEPEND(alc, ether, 1, 1, 1); 89 MODULE_DEPEND(alc, miibus, 1, 1, 1); 90 91 /* Tunables. */ 92 static int msi_disable = 0; 93 static int msix_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96 97 /* 98 * Devices supported by this driver. 99 */ 100 static struct alc_ident alc_ident_table[] = { 101 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102 "Atheros AR8131 PCIe Gigabit Ethernet" }, 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 104 "Atheros AR8132 PCIe Fast Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 106 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 108 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 110 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 112 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 113 { 0, 0, 0, NULL} 114 }; 115 116 static void alc_aspm(struct alc_softc *, int); 117 static int alc_attach(device_t); 118 static int alc_check_boundary(struct alc_softc *); 119 static int alc_detach(device_t); 120 static void alc_disable_l0s_l1(struct alc_softc *); 121 static int alc_dma_alloc(struct alc_softc *); 122 static void alc_dma_free(struct alc_softc *); 123 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 124 static int alc_encap(struct alc_softc *, struct mbuf **); 125 static struct alc_ident * 126 alc_find_ident(device_t); 127 #ifndef __NO_STRICT_ALIGNMENT 128 static struct mbuf * 129 alc_fixup_rx(struct ifnet *, struct mbuf *); 130 #endif 131 static void alc_get_macaddr(struct alc_softc *); 132 static void alc_init(void *); 133 static void alc_init_cmb(struct alc_softc *); 134 static void alc_init_locked(struct alc_softc *); 135 static void alc_init_rr_ring(struct alc_softc *); 136 static int alc_init_rx_ring(struct alc_softc *); 137 static void alc_init_smb(struct alc_softc *); 138 static void alc_init_tx_ring(struct alc_softc *); 139 static void alc_int_task(void *, int); 140 static int alc_intr(void *); 141 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 142 static void alc_mac_config(struct alc_softc *); 143 static int alc_miibus_readreg(device_t, int, int); 144 static void alc_miibus_statchg(device_t); 145 static int alc_miibus_writereg(device_t, int, int, int); 146 static int alc_mediachange(struct ifnet *); 147 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 148 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 149 static void alc_phy_down(struct alc_softc *); 150 static void alc_phy_reset(struct alc_softc *); 151 static int alc_probe(device_t); 152 static void alc_reset(struct alc_softc *); 153 static int alc_resume(device_t); 154 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 155 static int alc_rxintr(struct alc_softc *, int); 156 static void alc_rxfilter(struct alc_softc *); 157 static void alc_rxvlan(struct alc_softc *); 158 static void alc_setlinkspeed(struct alc_softc *); 159 static void alc_setwol(struct alc_softc *); 160 static int alc_shutdown(device_t); 161 static void alc_start(struct ifnet *); 162 static void alc_start_locked(struct ifnet *); 163 static void alc_start_queue(struct alc_softc *); 164 static void alc_stats_clear(struct alc_softc *); 165 static void alc_stats_update(struct alc_softc *); 166 static void alc_stop(struct alc_softc *); 167 static void alc_stop_mac(struct alc_softc *); 168 static void alc_stop_queue(struct alc_softc *); 169 static int alc_suspend(device_t); 170 static void alc_sysctl_node(struct alc_softc *); 171 static void alc_tick(void *); 172 static void alc_txeof(struct alc_softc *); 173 static void alc_watchdog(struct alc_softc *); 174 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 175 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 176 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 177 178 static device_method_t alc_methods[] = { 179 /* Device interface. */ 180 DEVMETHOD(device_probe, alc_probe), 181 DEVMETHOD(device_attach, alc_attach), 182 DEVMETHOD(device_detach, alc_detach), 183 DEVMETHOD(device_shutdown, alc_shutdown), 184 DEVMETHOD(device_suspend, alc_suspend), 185 DEVMETHOD(device_resume, alc_resume), 186 187 /* MII interface. */ 188 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 189 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 190 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 191 192 { NULL, NULL } 193 }; 194 195 static driver_t alc_driver = { 196 "alc", 197 alc_methods, 198 sizeof(struct alc_softc) 199 }; 200 201 static devclass_t alc_devclass; 202 203 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 204 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 205 206 static struct resource_spec alc_res_spec_mem[] = { 207 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 208 { -1, 0, 0 } 209 }; 210 211 static struct resource_spec alc_irq_spec_legacy[] = { 212 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 213 { -1, 0, 0 } 214 }; 215 216 static struct resource_spec alc_irq_spec_msi[] = { 217 { SYS_RES_IRQ, 1, RF_ACTIVE }, 218 { -1, 0, 0 } 219 }; 220 221 static struct resource_spec alc_irq_spec_msix[] = { 222 { SYS_RES_IRQ, 1, RF_ACTIVE }, 223 { -1, 0, 0 } 224 }; 225 226 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 227 228 static int 229 alc_miibus_readreg(device_t dev, int phy, int reg) 230 { 231 struct alc_softc *sc; 232 uint32_t v; 233 int i; 234 235 sc = device_get_softc(dev); 236 237 /* 238 * For AR8132 fast ethernet controller, do not report 1000baseT 239 * capability to mii(4). Even though AR8132 uses the same 240 * model/revision number of F1 gigabit PHY, the PHY has no 241 * ability to establish 1000baseT link. 242 */ 243 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 244 reg == MII_EXTSR) 245 return (0); 246 247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALC_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) { 257 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262 } 263 264 static int 265 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266 { 267 struct alc_softc *sc; 268 uint32_t v; 269 int i; 270 271 sc = device_get_softc(dev); 272 273 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277 DELAY(5); 278 v = CSR_READ_4(sc, ALC_MDIO); 279 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280 break; 281 } 282 283 if (i == 0) 284 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285 286 return (0); 287 } 288 289 static void 290 alc_miibus_statchg(device_t dev) 291 { 292 struct alc_softc *sc; 293 struct mii_data *mii; 294 struct ifnet *ifp; 295 uint32_t reg; 296 297 sc = device_get_softc(dev); 298 299 mii = device_get_softc(sc->alc_miibus); 300 ifp = sc->alc_ifp; 301 if (mii == NULL || ifp == NULL || 302 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303 return; 304 305 sc->alc_flags &= ~ALC_FLAG_LINK; 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 sc->alc_flags |= ALC_FLAG_LINK; 312 break; 313 case IFM_1000_T: 314 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315 sc->alc_flags |= ALC_FLAG_LINK; 316 break; 317 default: 318 break; 319 } 320 } 321 alc_stop_queue(sc); 322 /* Stop Rx/Tx MACs. */ 323 alc_stop_mac(sc); 324 325 /* Program MACs with resolved speed/duplex/flow-control. */ 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327 alc_start_queue(sc); 328 alc_mac_config(sc); 329 /* Re-enable Tx/Rx MACs. */ 330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 331 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 333 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 334 } 335 } 336 337 static void 338 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339 { 340 struct alc_softc *sc; 341 struct mii_data *mii; 342 343 sc = ifp->if_softc; 344 ALC_LOCK(sc); 345 if ((ifp->if_flags & IFF_UP) == 0) { 346 ALC_UNLOCK(sc); 347 return; 348 } 349 mii = device_get_softc(sc->alc_miibus); 350 351 mii_pollstat(mii); 352 ALC_UNLOCK(sc); 353 ifmr->ifm_status = mii->mii_media_status; 354 ifmr->ifm_active = mii->mii_media_active; 355 } 356 357 static int 358 alc_mediachange(struct ifnet *ifp) 359 { 360 struct alc_softc *sc; 361 struct mii_data *mii; 362 struct mii_softc *miisc; 363 int error; 364 365 sc = ifp->if_softc; 366 ALC_LOCK(sc); 367 mii = device_get_softc(sc->alc_miibus); 368 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 369 PHY_RESET(miisc); 370 error = mii_mediachg(mii); 371 ALC_UNLOCK(sc); 372 373 return (error); 374 } 375 376 static struct alc_ident * 377 alc_find_ident(device_t dev) 378 { 379 struct alc_ident *ident; 380 uint16_t vendor, devid; 381 382 vendor = pci_get_vendor(dev); 383 devid = pci_get_device(dev); 384 for (ident = alc_ident_table; ident->name != NULL; ident++) { 385 if (vendor == ident->vendorid && devid == ident->deviceid) 386 return (ident); 387 } 388 389 return (NULL); 390 } 391 392 static int 393 alc_probe(device_t dev) 394 { 395 struct alc_ident *ident; 396 397 ident = alc_find_ident(dev); 398 if (ident != NULL) { 399 device_set_desc(dev, ident->name); 400 return (BUS_PROBE_DEFAULT); 401 } 402 403 return (ENXIO); 404 } 405 406 static void 407 alc_get_macaddr(struct alc_softc *sc) 408 { 409 uint32_t ea[2], opt; 410 uint16_t val; 411 int eeprom, i; 412 413 eeprom = 0; 414 opt = CSR_READ_4(sc, ALC_OPT_CFG); 415 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 416 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 417 /* 418 * EEPROM found, let TWSI reload EEPROM configuration. 419 * This will set ethernet address of controller. 420 */ 421 eeprom++; 422 switch (sc->alc_ident->deviceid) { 423 case DEVICEID_ATHEROS_AR8131: 424 case DEVICEID_ATHEROS_AR8132: 425 if ((opt & OPT_CFG_CLK_ENB) == 0) { 426 opt |= OPT_CFG_CLK_ENB; 427 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 428 CSR_READ_4(sc, ALC_OPT_CFG); 429 DELAY(1000); 430 } 431 break; 432 case DEVICEID_ATHEROS_AR8151: 433 case DEVICEID_ATHEROS_AR8151_V2: 434 case DEVICEID_ATHEROS_AR8152_B: 435 case DEVICEID_ATHEROS_AR8152_B2: 436 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_ADDR, 0x00); 438 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 439 ALC_MII_DBG_DATA); 440 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 441 ALC_MII_DBG_DATA, val & 0xFF7F); 442 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 443 ALC_MII_DBG_ADDR, 0x3B); 444 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 445 ALC_MII_DBG_DATA); 446 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 447 ALC_MII_DBG_DATA, val | 0x0008); 448 DELAY(20); 449 break; 450 } 451 452 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 453 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 454 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 455 CSR_READ_4(sc, ALC_WOL_CFG); 456 457 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 458 TWSI_CFG_SW_LD_START); 459 for (i = 100; i > 0; i--) { 460 DELAY(1000); 461 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 462 TWSI_CFG_SW_LD_START) == 0) 463 break; 464 } 465 if (i == 0) 466 device_printf(sc->alc_dev, 467 "reloading EEPROM timeout!\n"); 468 } else { 469 if (bootverbose) 470 device_printf(sc->alc_dev, "EEPROM not found!\n"); 471 } 472 if (eeprom != 0) { 473 switch (sc->alc_ident->deviceid) { 474 case DEVICEID_ATHEROS_AR8131: 475 case DEVICEID_ATHEROS_AR8132: 476 if ((opt & OPT_CFG_CLK_ENB) != 0) { 477 opt &= ~OPT_CFG_CLK_ENB; 478 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 479 CSR_READ_4(sc, ALC_OPT_CFG); 480 DELAY(1000); 481 } 482 break; 483 case DEVICEID_ATHEROS_AR8151: 484 case DEVICEID_ATHEROS_AR8151_V2: 485 case DEVICEID_ATHEROS_AR8152_B: 486 case DEVICEID_ATHEROS_AR8152_B2: 487 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_ADDR, 0x00); 489 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 490 ALC_MII_DBG_DATA); 491 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 492 ALC_MII_DBG_DATA, val | 0x0080); 493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 494 ALC_MII_DBG_ADDR, 0x3B); 495 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_DATA); 497 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA, val & 0xFFF7); 499 DELAY(20); 500 break; 501 } 502 } 503 504 ea[0] = CSR_READ_4(sc, ALC_PAR0); 505 ea[1] = CSR_READ_4(sc, ALC_PAR1); 506 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 507 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 508 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 509 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 510 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 511 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 512 } 513 514 static void 515 alc_disable_l0s_l1(struct alc_softc *sc) 516 { 517 uint32_t pmcfg; 518 519 /* Another magic from vendor. */ 520 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 521 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 522 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 523 PM_CFG_SERDES_PD_EX_L1); 524 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 525 PM_CFG_SERDES_L1_ENB; 526 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 527 } 528 529 static void 530 alc_phy_reset(struct alc_softc *sc) 531 { 532 uint16_t data; 533 534 /* Reset magic from Linux. */ 535 CSR_WRITE_2(sc, ALC_GPHY_CFG, 536 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 537 CSR_READ_2(sc, ALC_GPHY_CFG); 538 DELAY(10 * 1000); 539 540 CSR_WRITE_2(sc, ALC_GPHY_CFG, 541 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 542 GPHY_CFG_SEL_ANA_RESET); 543 CSR_READ_2(sc, ALC_GPHY_CFG); 544 DELAY(10 * 1000); 545 546 /* DSP fixup, Vendor magic. */ 547 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 548 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 549 ALC_MII_DBG_ADDR, 0x000A); 550 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 551 ALC_MII_DBG_DATA); 552 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 553 ALC_MII_DBG_DATA, data & 0xDFFF); 554 } 555 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 556 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 557 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 558 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 559 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 560 ALC_MII_DBG_ADDR, 0x003B); 561 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 562 ALC_MII_DBG_DATA); 563 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 564 ALC_MII_DBG_DATA, data & 0xFFF7); 565 DELAY(20 * 1000); 566 } 567 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_ADDR, 0x0029); 570 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_DATA, 0x929D); 572 } 573 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 574 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 575 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 576 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 577 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 578 ALC_MII_DBG_ADDR, 0x0029); 579 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 580 ALC_MII_DBG_DATA, 0xB6DD); 581 } 582 583 /* Load DSP codes, vendor magic. */ 584 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 585 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 586 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 588 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_DATA, data); 590 591 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 592 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 593 ANA_SERDES_EN_LCKDT; 594 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 595 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 596 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 597 ALC_MII_DBG_DATA, data); 598 599 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 600 ANA_LONG_CABLE_TH_100_MASK) | 601 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 602 ANA_SHORT_CABLE_TH_100_SHIFT) | 603 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 604 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 605 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 606 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 607 ALC_MII_DBG_DATA, data); 608 609 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 610 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 611 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 612 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_DATA, data); 617 618 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 619 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 620 ANA_OEN_125M; 621 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 623 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_DATA, data); 625 DELAY(1000); 626 } 627 628 static void 629 alc_phy_down(struct alc_softc *sc) 630 { 631 632 switch (sc->alc_ident->deviceid) { 633 case DEVICEID_ATHEROS_AR8151: 634 case DEVICEID_ATHEROS_AR8151_V2: 635 /* 636 * GPHY power down caused more problems on AR8151 v2.0. 637 * When driver is reloaded after GPHY power down, 638 * accesses to PHY/MAC registers hung the system. Only 639 * cold boot recovered from it. I'm not sure whether 640 * AR8151 v1.0 also requires this one though. I don't 641 * have AR8151 v1.0 controller in hand. 642 * The only option left is to isolate the PHY and 643 * initiates power down the PHY which in turn saves 644 * more power when driver is unloaded. 645 */ 646 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 647 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 648 break; 649 default: 650 /* Force PHY down. */ 651 CSR_WRITE_2(sc, ALC_GPHY_CFG, 652 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 653 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 654 GPHY_CFG_PWDOWN_HW); 655 DELAY(1000); 656 break; 657 } 658 } 659 660 static void 661 alc_aspm(struct alc_softc *sc, int media) 662 { 663 uint32_t pmcfg; 664 uint16_t linkcfg; 665 666 ALC_LOCK_ASSERT(sc); 667 668 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 669 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 670 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 671 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 672 PCIR_EXPRESS_LINK_CTL); 673 else 674 linkcfg = 0; 675 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 676 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 677 pmcfg |= PM_CFG_MAC_ASPM_CHK; 678 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 679 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 680 681 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 682 /* Disable extended sync except AR8152 B v1.0 */ 683 linkcfg &= ~0x80; 684 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 685 sc->alc_rev == ATHEROS_AR8152_B_V10) 686 linkcfg |= 0x80; 687 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 688 linkcfg); 689 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 690 PM_CFG_HOTRST); 691 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 692 PM_CFG_L1_ENTRY_TIMER_SHIFT); 693 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 694 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 695 PM_CFG_PM_REQ_TIMER_SHIFT); 696 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 697 } 698 699 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 700 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 701 pmcfg |= PM_CFG_ASPM_L0S_ENB; 702 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 703 pmcfg |= PM_CFG_ASPM_L1_ENB; 704 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 705 if (sc->alc_ident->deviceid == 706 DEVICEID_ATHEROS_AR8152_B) 707 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 708 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 709 PM_CFG_SERDES_PLL_L1_ENB | 710 PM_CFG_SERDES_BUDS_RX_L1_ENB); 711 pmcfg |= PM_CFG_CLK_SWH_L1; 712 if (media == IFM_100_TX || media == IFM_1000_T) { 713 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 714 switch (sc->alc_ident->deviceid) { 715 case DEVICEID_ATHEROS_AR8152_B: 716 pmcfg |= (7 << 717 PM_CFG_L1_ENTRY_TIMER_SHIFT); 718 break; 719 case DEVICEID_ATHEROS_AR8152_B2: 720 case DEVICEID_ATHEROS_AR8151_V2: 721 pmcfg |= (4 << 722 PM_CFG_L1_ENTRY_TIMER_SHIFT); 723 break; 724 default: 725 pmcfg |= (15 << 726 PM_CFG_L1_ENTRY_TIMER_SHIFT); 727 break; 728 } 729 } 730 } else { 731 pmcfg |= PM_CFG_SERDES_L1_ENB | 732 PM_CFG_SERDES_PLL_L1_ENB | 733 PM_CFG_SERDES_BUDS_RX_L1_ENB; 734 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 735 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 736 } 737 } else { 738 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 739 PM_CFG_SERDES_PLL_L1_ENB); 740 pmcfg |= PM_CFG_CLK_SWH_L1; 741 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 742 pmcfg |= PM_CFG_ASPM_L1_ENB; 743 } 744 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 745 } 746 747 static int 748 alc_attach(device_t dev) 749 { 750 struct alc_softc *sc; 751 struct ifnet *ifp; 752 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 753 uint16_t burst; 754 int base, error, i, msic, msixc, state; 755 uint32_t cap, ctl, val; 756 757 error = 0; 758 sc = device_get_softc(dev); 759 sc->alc_dev = dev; 760 761 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 762 MTX_DEF); 763 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 764 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 765 sc->alc_ident = alc_find_ident(dev); 766 767 /* Map the device. */ 768 pci_enable_busmaster(dev); 769 sc->alc_res_spec = alc_res_spec_mem; 770 sc->alc_irq_spec = alc_irq_spec_legacy; 771 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 772 if (error != 0) { 773 device_printf(dev, "cannot allocate memory resources.\n"); 774 goto fail; 775 } 776 777 /* Set PHY address. */ 778 sc->alc_phyaddr = ALC_PHY_ADDR; 779 780 /* Initialize DMA parameters. */ 781 sc->alc_dma_rd_burst = 0; 782 sc->alc_dma_wr_burst = 0; 783 sc->alc_rcb = DMA_CFG_RCB_64; 784 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 785 sc->alc_flags |= ALC_FLAG_PCIE; 786 sc->alc_expcap = base; 787 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 788 sc->alc_dma_rd_burst = 789 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 790 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 791 if (bootverbose) { 792 device_printf(dev, "Read request size : %u bytes.\n", 793 alc_dma_burst[sc->alc_dma_rd_burst]); 794 device_printf(dev, "TLP payload size : %u bytes.\n", 795 alc_dma_burst[sc->alc_dma_wr_burst]); 796 } 797 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 798 sc->alc_dma_rd_burst = 3; 799 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 800 sc->alc_dma_wr_burst = 3; 801 /* Clear data link and flow-control protocol error. */ 802 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 803 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 804 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 805 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 806 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 807 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 808 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 809 PCIE_PHYMISC_FORCE_RCV_DET); 810 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 811 pci_get_revid(dev) == ATHEROS_AR8152_B_V10) { 812 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 813 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 814 PCIE_PHYMISC2_SERDES_TH_MASK); 815 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 816 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 817 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 818 } 819 /* Disable ASPM L0S and L1. */ 820 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 821 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 822 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 823 if ((ctl & 0x08) != 0) 824 sc->alc_rcb = DMA_CFG_RCB_128; 825 if (bootverbose) 826 device_printf(dev, "RCB %u bytes\n", 827 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 828 state = ctl & 0x03; 829 if (state & 0x01) 830 sc->alc_flags |= ALC_FLAG_L0S; 831 if (state & 0x02) 832 sc->alc_flags |= ALC_FLAG_L1S; 833 if (bootverbose) 834 device_printf(sc->alc_dev, "ASPM %s %s\n", 835 aspm_state[state], 836 state == 0 ? "disabled" : "enabled"); 837 alc_disable_l0s_l1(sc); 838 } else { 839 if (bootverbose) 840 device_printf(sc->alc_dev, 841 "no ASPM support\n"); 842 } 843 } 844 845 /* Reset PHY. */ 846 alc_phy_reset(sc); 847 848 /* Reset the ethernet controller. */ 849 alc_reset(sc); 850 851 /* 852 * One odd thing is AR8132 uses the same PHY hardware(F1 853 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 854 * the PHY supports 1000Mbps but that's not true. The PHY 855 * used in AR8132 can't establish gigabit link even if it 856 * shows the same PHY model/revision number of AR8131. 857 */ 858 switch (sc->alc_ident->deviceid) { 859 case DEVICEID_ATHEROS_AR8152_B: 860 case DEVICEID_ATHEROS_AR8152_B2: 861 sc->alc_flags |= ALC_FLAG_APS; 862 /* FALLTHROUGH */ 863 case DEVICEID_ATHEROS_AR8132: 864 sc->alc_flags |= ALC_FLAG_FASTETHER; 865 break; 866 case DEVICEID_ATHEROS_AR8151: 867 case DEVICEID_ATHEROS_AR8151_V2: 868 sc->alc_flags |= ALC_FLAG_APS; 869 /* FALLTHROUGH */ 870 default: 871 break; 872 } 873 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 874 875 /* 876 * It seems that AR813x/AR815x has silicon bug for SMB. In 877 * addition, Atheros said that enabling SMB wouldn't improve 878 * performance. However I think it's bad to access lots of 879 * registers to extract MAC statistics. 880 */ 881 sc->alc_flags |= ALC_FLAG_SMB_BUG; 882 /* 883 * Don't use Tx CMB. It is known to have silicon bug. 884 */ 885 sc->alc_flags |= ALC_FLAG_CMB_BUG; 886 sc->alc_rev = pci_get_revid(dev); 887 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 888 MASTER_CHIP_REV_SHIFT; 889 if (bootverbose) { 890 device_printf(dev, "PCI device revision : 0x%04x\n", 891 sc->alc_rev); 892 device_printf(dev, "Chip id/revision : 0x%04x\n", 893 sc->alc_chip_rev); 894 } 895 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 896 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 897 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 898 899 /* Allocate IRQ resources. */ 900 msixc = pci_msix_count(dev); 901 msic = pci_msi_count(dev); 902 if (bootverbose) { 903 device_printf(dev, "MSIX count : %d\n", msixc); 904 device_printf(dev, "MSI count : %d\n", msic); 905 } 906 /* Prefer MSIX over MSI. */ 907 if (msix_disable == 0 || msi_disable == 0) { 908 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 909 pci_alloc_msix(dev, &msixc) == 0) { 910 if (msic == ALC_MSIX_MESSAGES) { 911 device_printf(dev, 912 "Using %d MSIX message(s).\n", msixc); 913 sc->alc_flags |= ALC_FLAG_MSIX; 914 sc->alc_irq_spec = alc_irq_spec_msix; 915 } else 916 pci_release_msi(dev); 917 } 918 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 919 msic == ALC_MSI_MESSAGES && 920 pci_alloc_msi(dev, &msic) == 0) { 921 if (msic == ALC_MSI_MESSAGES) { 922 device_printf(dev, 923 "Using %d MSI message(s).\n", msic); 924 sc->alc_flags |= ALC_FLAG_MSI; 925 sc->alc_irq_spec = alc_irq_spec_msi; 926 } else 927 pci_release_msi(dev); 928 } 929 } 930 931 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 932 if (error != 0) { 933 device_printf(dev, "cannot allocate IRQ resources.\n"); 934 goto fail; 935 } 936 937 /* Create device sysctl node. */ 938 alc_sysctl_node(sc); 939 940 if ((error = alc_dma_alloc(sc) != 0)) 941 goto fail; 942 943 /* Load station address. */ 944 alc_get_macaddr(sc); 945 946 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 947 if (ifp == NULL) { 948 device_printf(dev, "cannot allocate ifnet structure.\n"); 949 error = ENXIO; 950 goto fail; 951 } 952 953 ifp->if_softc = sc; 954 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 955 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 956 ifp->if_ioctl = alc_ioctl; 957 ifp->if_start = alc_start; 958 ifp->if_init = alc_init; 959 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 960 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 961 IFQ_SET_READY(&ifp->if_snd); 962 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 963 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 964 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 965 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 966 sc->alc_flags |= ALC_FLAG_PM; 967 sc->alc_pmcap = base; 968 } 969 ifp->if_capenable = ifp->if_capabilities; 970 971 /* Set up MII bus. */ 972 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 973 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 974 MIIF_DOPAUSE); 975 if (error != 0) { 976 device_printf(dev, "attaching PHYs failed\n"); 977 goto fail; 978 } 979 980 ether_ifattach(ifp, sc->alc_eaddr); 981 982 /* VLAN capability setup. */ 983 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 984 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 985 ifp->if_capenable = ifp->if_capabilities; 986 /* 987 * XXX 988 * It seems enabling Tx checksum offloading makes more trouble. 989 * Sometimes the controller does not receive any frames when 990 * Tx checksum offloading is enabled. I'm not sure whether this 991 * is a bug in Tx checksum offloading logic or I got broken 992 * sample boards. To safety, don't enable Tx checksum offloading 993 * by default but give chance to users to toggle it if they know 994 * their controllers work without problems. 995 */ 996 ifp->if_capenable &= ~IFCAP_TXCSUM; 997 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 998 999 /* Tell the upper layer(s) we support long frames. */ 1000 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1001 1002 /* Create local taskq. */ 1003 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1004 taskqueue_thread_enqueue, &sc->alc_tq); 1005 if (sc->alc_tq == NULL) { 1006 device_printf(dev, "could not create taskqueue.\n"); 1007 ether_ifdetach(ifp); 1008 error = ENXIO; 1009 goto fail; 1010 } 1011 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1012 device_get_nameunit(sc->alc_dev)); 1013 1014 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1015 msic = ALC_MSIX_MESSAGES; 1016 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1017 msic = ALC_MSI_MESSAGES; 1018 else 1019 msic = 1; 1020 for (i = 0; i < msic; i++) { 1021 error = bus_setup_intr(dev, sc->alc_irq[i], 1022 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1023 &sc->alc_intrhand[i]); 1024 if (error != 0) 1025 break; 1026 } 1027 if (error != 0) { 1028 device_printf(dev, "could not set up interrupt handler.\n"); 1029 taskqueue_free(sc->alc_tq); 1030 sc->alc_tq = NULL; 1031 ether_ifdetach(ifp); 1032 goto fail; 1033 } 1034 1035 fail: 1036 if (error != 0) 1037 alc_detach(dev); 1038 1039 return (error); 1040 } 1041 1042 static int 1043 alc_detach(device_t dev) 1044 { 1045 struct alc_softc *sc; 1046 struct ifnet *ifp; 1047 int i, msic; 1048 1049 sc = device_get_softc(dev); 1050 1051 ifp = sc->alc_ifp; 1052 if (device_is_attached(dev)) { 1053 ether_ifdetach(ifp); 1054 ALC_LOCK(sc); 1055 alc_stop(sc); 1056 ALC_UNLOCK(sc); 1057 callout_drain(&sc->alc_tick_ch); 1058 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1059 } 1060 1061 if (sc->alc_tq != NULL) { 1062 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1063 taskqueue_free(sc->alc_tq); 1064 sc->alc_tq = NULL; 1065 } 1066 1067 if (sc->alc_miibus != NULL) { 1068 device_delete_child(dev, sc->alc_miibus); 1069 sc->alc_miibus = NULL; 1070 } 1071 bus_generic_detach(dev); 1072 alc_dma_free(sc); 1073 1074 if (ifp != NULL) { 1075 if_free(ifp); 1076 sc->alc_ifp = NULL; 1077 } 1078 1079 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1080 msic = ALC_MSIX_MESSAGES; 1081 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1082 msic = ALC_MSI_MESSAGES; 1083 else 1084 msic = 1; 1085 for (i = 0; i < msic; i++) { 1086 if (sc->alc_intrhand[i] != NULL) { 1087 bus_teardown_intr(dev, sc->alc_irq[i], 1088 sc->alc_intrhand[i]); 1089 sc->alc_intrhand[i] = NULL; 1090 } 1091 } 1092 if (sc->alc_res[0] != NULL) 1093 alc_phy_down(sc); 1094 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1095 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1096 pci_release_msi(dev); 1097 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1098 mtx_destroy(&sc->alc_mtx); 1099 1100 return (0); 1101 } 1102 1103 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1104 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1105 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1106 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1107 1108 static void 1109 alc_sysctl_node(struct alc_softc *sc) 1110 { 1111 struct sysctl_ctx_list *ctx; 1112 struct sysctl_oid_list *child, *parent; 1113 struct sysctl_oid *tree; 1114 struct alc_hw_stats *stats; 1115 int error; 1116 1117 stats = &sc->alc_stats; 1118 ctx = device_get_sysctl_ctx(sc->alc_dev); 1119 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1120 1121 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1122 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1123 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1124 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1125 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1126 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1127 /* Pull in device tunables. */ 1128 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1129 error = resource_int_value(device_get_name(sc->alc_dev), 1130 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1131 if (error == 0) { 1132 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1133 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1134 device_printf(sc->alc_dev, "int_rx_mod value out of " 1135 "range; using default: %d\n", 1136 ALC_IM_RX_TIMER_DEFAULT); 1137 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1138 } 1139 } 1140 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1141 error = resource_int_value(device_get_name(sc->alc_dev), 1142 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1143 if (error == 0) { 1144 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1145 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1146 device_printf(sc->alc_dev, "int_tx_mod value out of " 1147 "range; using default: %d\n", 1148 ALC_IM_TX_TIMER_DEFAULT); 1149 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1150 } 1151 } 1152 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1153 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1154 sysctl_hw_alc_proc_limit, "I", 1155 "max number of Rx events to process"); 1156 /* Pull in device tunables. */ 1157 sc->alc_process_limit = ALC_PROC_DEFAULT; 1158 error = resource_int_value(device_get_name(sc->alc_dev), 1159 device_get_unit(sc->alc_dev), "process_limit", 1160 &sc->alc_process_limit); 1161 if (error == 0) { 1162 if (sc->alc_process_limit < ALC_PROC_MIN || 1163 sc->alc_process_limit > ALC_PROC_MAX) { 1164 device_printf(sc->alc_dev, 1165 "process_limit value out of range; " 1166 "using default: %d\n", ALC_PROC_DEFAULT); 1167 sc->alc_process_limit = ALC_PROC_DEFAULT; 1168 } 1169 } 1170 1171 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1172 NULL, "ALC statistics"); 1173 parent = SYSCTL_CHILDREN(tree); 1174 1175 /* Rx statistics. */ 1176 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1177 NULL, "Rx MAC statistics"); 1178 child = SYSCTL_CHILDREN(tree); 1179 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1180 &stats->rx_frames, "Good frames"); 1181 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1182 &stats->rx_bcast_frames, "Good broadcast frames"); 1183 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1184 &stats->rx_mcast_frames, "Good multicast frames"); 1185 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1186 &stats->rx_pause_frames, "Pause control frames"); 1187 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1188 &stats->rx_control_frames, "Control frames"); 1189 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1190 &stats->rx_crcerrs, "CRC errors"); 1191 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1192 &stats->rx_lenerrs, "Frames with length mismatched"); 1193 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1194 &stats->rx_bytes, "Good octets"); 1195 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1196 &stats->rx_bcast_bytes, "Good broadcast octets"); 1197 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1198 &stats->rx_mcast_bytes, "Good multicast octets"); 1199 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1200 &stats->rx_runts, "Too short frames"); 1201 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1202 &stats->rx_fragments, "Fragmented frames"); 1203 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1204 &stats->rx_pkts_64, "64 bytes frames"); 1205 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1206 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1207 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1208 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1209 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1210 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1211 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1212 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1213 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1214 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1215 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1216 &stats->rx_pkts_1519_max, "1519 to max frames"); 1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1218 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1219 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1220 &stats->rx_fifo_oflows, "FIFO overflows"); 1221 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1222 &stats->rx_rrs_errs, "Return status write-back errors"); 1223 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1224 &stats->rx_alignerrs, "Alignment errors"); 1225 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1226 &stats->rx_pkts_filtered, 1227 "Frames dropped due to address filtering"); 1228 1229 /* Tx statistics. */ 1230 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1231 NULL, "Tx MAC statistics"); 1232 child = SYSCTL_CHILDREN(tree); 1233 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1234 &stats->tx_frames, "Good frames"); 1235 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1236 &stats->tx_bcast_frames, "Good broadcast frames"); 1237 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1238 &stats->tx_mcast_frames, "Good multicast frames"); 1239 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1240 &stats->tx_pause_frames, "Pause control frames"); 1241 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1242 &stats->tx_control_frames, "Control frames"); 1243 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1244 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1245 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1246 &stats->tx_excess_defer, "Frames with derferrals"); 1247 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1248 &stats->tx_bytes, "Good octets"); 1249 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1250 &stats->tx_bcast_bytes, "Good broadcast octets"); 1251 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1252 &stats->tx_mcast_bytes, "Good multicast octets"); 1253 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1254 &stats->tx_pkts_64, "64 bytes frames"); 1255 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1256 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1257 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1258 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1259 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1260 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1261 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1262 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1263 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1264 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1265 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1266 &stats->tx_pkts_1519_max, "1519 to max frames"); 1267 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1268 &stats->tx_single_colls, "Single collisions"); 1269 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1270 &stats->tx_multi_colls, "Multiple collisions"); 1271 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1272 &stats->tx_late_colls, "Late collisions"); 1273 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1274 &stats->tx_excess_colls, "Excessive collisions"); 1275 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1276 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1277 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1278 &stats->tx_underrun, "FIFO underruns"); 1279 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1280 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1281 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1282 &stats->tx_lenerrs, "Frames with length mismatched"); 1283 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1284 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1285 } 1286 1287 #undef ALC_SYSCTL_STAT_ADD32 1288 #undef ALC_SYSCTL_STAT_ADD64 1289 1290 struct alc_dmamap_arg { 1291 bus_addr_t alc_busaddr; 1292 }; 1293 1294 static void 1295 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1296 { 1297 struct alc_dmamap_arg *ctx; 1298 1299 if (error != 0) 1300 return; 1301 1302 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1303 1304 ctx = (struct alc_dmamap_arg *)arg; 1305 ctx->alc_busaddr = segs[0].ds_addr; 1306 } 1307 1308 /* 1309 * Normal and high Tx descriptors shares single Tx high address. 1310 * Four Rx descriptor/return rings and CMB shares the same Rx 1311 * high address. 1312 */ 1313 static int 1314 alc_check_boundary(struct alc_softc *sc) 1315 { 1316 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1317 1318 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1319 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1320 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1321 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1322 1323 /* 4GB boundary crossing is not allowed. */ 1324 if ((ALC_ADDR_HI(rx_ring_end) != 1325 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1326 (ALC_ADDR_HI(rr_ring_end) != 1327 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1328 (ALC_ADDR_HI(cmb_end) != 1329 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1330 (ALC_ADDR_HI(tx_ring_end) != 1331 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1332 return (EFBIG); 1333 /* 1334 * Make sure Rx return descriptor/Rx descriptor/CMB use 1335 * the same high address. 1336 */ 1337 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1338 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1339 return (EFBIG); 1340 1341 return (0); 1342 } 1343 1344 static int 1345 alc_dma_alloc(struct alc_softc *sc) 1346 { 1347 struct alc_txdesc *txd; 1348 struct alc_rxdesc *rxd; 1349 bus_addr_t lowaddr; 1350 struct alc_dmamap_arg ctx; 1351 int error, i; 1352 1353 lowaddr = BUS_SPACE_MAXADDR; 1354 again: 1355 /* Create parent DMA tag. */ 1356 error = bus_dma_tag_create( 1357 bus_get_dma_tag(sc->alc_dev), /* parent */ 1358 1, 0, /* alignment, boundary */ 1359 lowaddr, /* lowaddr */ 1360 BUS_SPACE_MAXADDR, /* highaddr */ 1361 NULL, NULL, /* filter, filterarg */ 1362 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1363 0, /* nsegments */ 1364 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1365 0, /* flags */ 1366 NULL, NULL, /* lockfunc, lockarg */ 1367 &sc->alc_cdata.alc_parent_tag); 1368 if (error != 0) { 1369 device_printf(sc->alc_dev, 1370 "could not create parent DMA tag.\n"); 1371 goto fail; 1372 } 1373 1374 /* Create DMA tag for Tx descriptor ring. */ 1375 error = bus_dma_tag_create( 1376 sc->alc_cdata.alc_parent_tag, /* parent */ 1377 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1378 BUS_SPACE_MAXADDR, /* lowaddr */ 1379 BUS_SPACE_MAXADDR, /* highaddr */ 1380 NULL, NULL, /* filter, filterarg */ 1381 ALC_TX_RING_SZ, /* maxsize */ 1382 1, /* nsegments */ 1383 ALC_TX_RING_SZ, /* maxsegsize */ 1384 0, /* flags */ 1385 NULL, NULL, /* lockfunc, lockarg */ 1386 &sc->alc_cdata.alc_tx_ring_tag); 1387 if (error != 0) { 1388 device_printf(sc->alc_dev, 1389 "could not create Tx ring DMA tag.\n"); 1390 goto fail; 1391 } 1392 1393 /* Create DMA tag for Rx free descriptor ring. */ 1394 error = bus_dma_tag_create( 1395 sc->alc_cdata.alc_parent_tag, /* parent */ 1396 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1397 BUS_SPACE_MAXADDR, /* lowaddr */ 1398 BUS_SPACE_MAXADDR, /* highaddr */ 1399 NULL, NULL, /* filter, filterarg */ 1400 ALC_RX_RING_SZ, /* maxsize */ 1401 1, /* nsegments */ 1402 ALC_RX_RING_SZ, /* maxsegsize */ 1403 0, /* flags */ 1404 NULL, NULL, /* lockfunc, lockarg */ 1405 &sc->alc_cdata.alc_rx_ring_tag); 1406 if (error != 0) { 1407 device_printf(sc->alc_dev, 1408 "could not create Rx ring DMA tag.\n"); 1409 goto fail; 1410 } 1411 /* Create DMA tag for Rx return descriptor ring. */ 1412 error = bus_dma_tag_create( 1413 sc->alc_cdata.alc_parent_tag, /* parent */ 1414 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1415 BUS_SPACE_MAXADDR, /* lowaddr */ 1416 BUS_SPACE_MAXADDR, /* highaddr */ 1417 NULL, NULL, /* filter, filterarg */ 1418 ALC_RR_RING_SZ, /* maxsize */ 1419 1, /* nsegments */ 1420 ALC_RR_RING_SZ, /* maxsegsize */ 1421 0, /* flags */ 1422 NULL, NULL, /* lockfunc, lockarg */ 1423 &sc->alc_cdata.alc_rr_ring_tag); 1424 if (error != 0) { 1425 device_printf(sc->alc_dev, 1426 "could not create Rx return ring DMA tag.\n"); 1427 goto fail; 1428 } 1429 1430 /* Create DMA tag for coalescing message block. */ 1431 error = bus_dma_tag_create( 1432 sc->alc_cdata.alc_parent_tag, /* parent */ 1433 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1434 BUS_SPACE_MAXADDR, /* lowaddr */ 1435 BUS_SPACE_MAXADDR, /* highaddr */ 1436 NULL, NULL, /* filter, filterarg */ 1437 ALC_CMB_SZ, /* maxsize */ 1438 1, /* nsegments */ 1439 ALC_CMB_SZ, /* maxsegsize */ 1440 0, /* flags */ 1441 NULL, NULL, /* lockfunc, lockarg */ 1442 &sc->alc_cdata.alc_cmb_tag); 1443 if (error != 0) { 1444 device_printf(sc->alc_dev, 1445 "could not create CMB DMA tag.\n"); 1446 goto fail; 1447 } 1448 /* Create DMA tag for status message block. */ 1449 error = bus_dma_tag_create( 1450 sc->alc_cdata.alc_parent_tag, /* parent */ 1451 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1452 BUS_SPACE_MAXADDR, /* lowaddr */ 1453 BUS_SPACE_MAXADDR, /* highaddr */ 1454 NULL, NULL, /* filter, filterarg */ 1455 ALC_SMB_SZ, /* maxsize */ 1456 1, /* nsegments */ 1457 ALC_SMB_SZ, /* maxsegsize */ 1458 0, /* flags */ 1459 NULL, NULL, /* lockfunc, lockarg */ 1460 &sc->alc_cdata.alc_smb_tag); 1461 if (error != 0) { 1462 device_printf(sc->alc_dev, 1463 "could not create SMB DMA tag.\n"); 1464 goto fail; 1465 } 1466 1467 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1468 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1469 (void **)&sc->alc_rdata.alc_tx_ring, 1470 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1471 &sc->alc_cdata.alc_tx_ring_map); 1472 if (error != 0) { 1473 device_printf(sc->alc_dev, 1474 "could not allocate DMA'able memory for Tx ring.\n"); 1475 goto fail; 1476 } 1477 ctx.alc_busaddr = 0; 1478 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1479 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1480 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1481 if (error != 0 || ctx.alc_busaddr == 0) { 1482 device_printf(sc->alc_dev, 1483 "could not load DMA'able memory for Tx ring.\n"); 1484 goto fail; 1485 } 1486 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1487 1488 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1489 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1490 (void **)&sc->alc_rdata.alc_rx_ring, 1491 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1492 &sc->alc_cdata.alc_rx_ring_map); 1493 if (error != 0) { 1494 device_printf(sc->alc_dev, 1495 "could not allocate DMA'able memory for Rx ring.\n"); 1496 goto fail; 1497 } 1498 ctx.alc_busaddr = 0; 1499 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1500 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1501 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1502 if (error != 0 || ctx.alc_busaddr == 0) { 1503 device_printf(sc->alc_dev, 1504 "could not load DMA'able memory for Rx ring.\n"); 1505 goto fail; 1506 } 1507 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1508 1509 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1510 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1511 (void **)&sc->alc_rdata.alc_rr_ring, 1512 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1513 &sc->alc_cdata.alc_rr_ring_map); 1514 if (error != 0) { 1515 device_printf(sc->alc_dev, 1516 "could not allocate DMA'able memory for Rx return ring.\n"); 1517 goto fail; 1518 } 1519 ctx.alc_busaddr = 0; 1520 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1521 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1522 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1523 if (error != 0 || ctx.alc_busaddr == 0) { 1524 device_printf(sc->alc_dev, 1525 "could not load DMA'able memory for Tx ring.\n"); 1526 goto fail; 1527 } 1528 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1529 1530 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1531 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1532 (void **)&sc->alc_rdata.alc_cmb, 1533 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1534 &sc->alc_cdata.alc_cmb_map); 1535 if (error != 0) { 1536 device_printf(sc->alc_dev, 1537 "could not allocate DMA'able memory for CMB.\n"); 1538 goto fail; 1539 } 1540 ctx.alc_busaddr = 0; 1541 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1542 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1543 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1544 if (error != 0 || ctx.alc_busaddr == 0) { 1545 device_printf(sc->alc_dev, 1546 "could not load DMA'able memory for CMB.\n"); 1547 goto fail; 1548 } 1549 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1550 1551 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1552 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1553 (void **)&sc->alc_rdata.alc_smb, 1554 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1555 &sc->alc_cdata.alc_smb_map); 1556 if (error != 0) { 1557 device_printf(sc->alc_dev, 1558 "could not allocate DMA'able memory for SMB.\n"); 1559 goto fail; 1560 } 1561 ctx.alc_busaddr = 0; 1562 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1563 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1564 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1565 if (error != 0 || ctx.alc_busaddr == 0) { 1566 device_printf(sc->alc_dev, 1567 "could not load DMA'able memory for CMB.\n"); 1568 goto fail; 1569 } 1570 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1571 1572 /* Make sure we've not crossed 4GB boundary. */ 1573 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1574 (error = alc_check_boundary(sc)) != 0) { 1575 device_printf(sc->alc_dev, "4GB boundary crossed, " 1576 "switching to 32bit DMA addressing mode.\n"); 1577 alc_dma_free(sc); 1578 /* 1579 * Limit max allowable DMA address space to 32bit 1580 * and try again. 1581 */ 1582 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1583 goto again; 1584 } 1585 1586 /* 1587 * Create Tx buffer parent tag. 1588 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1589 * so it needs separate parent DMA tag as parent DMA address 1590 * space could be restricted to be within 32bit address space 1591 * by 4GB boundary crossing. 1592 */ 1593 error = bus_dma_tag_create( 1594 bus_get_dma_tag(sc->alc_dev), /* parent */ 1595 1, 0, /* alignment, boundary */ 1596 BUS_SPACE_MAXADDR, /* lowaddr */ 1597 BUS_SPACE_MAXADDR, /* highaddr */ 1598 NULL, NULL, /* filter, filterarg */ 1599 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1600 0, /* nsegments */ 1601 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1602 0, /* flags */ 1603 NULL, NULL, /* lockfunc, lockarg */ 1604 &sc->alc_cdata.alc_buffer_tag); 1605 if (error != 0) { 1606 device_printf(sc->alc_dev, 1607 "could not create parent buffer DMA tag.\n"); 1608 goto fail; 1609 } 1610 1611 /* Create DMA tag for Tx buffers. */ 1612 error = bus_dma_tag_create( 1613 sc->alc_cdata.alc_buffer_tag, /* parent */ 1614 1, 0, /* alignment, boundary */ 1615 BUS_SPACE_MAXADDR, /* lowaddr */ 1616 BUS_SPACE_MAXADDR, /* highaddr */ 1617 NULL, NULL, /* filter, filterarg */ 1618 ALC_TSO_MAXSIZE, /* maxsize */ 1619 ALC_MAXTXSEGS, /* nsegments */ 1620 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1621 0, /* flags */ 1622 NULL, NULL, /* lockfunc, lockarg */ 1623 &sc->alc_cdata.alc_tx_tag); 1624 if (error != 0) { 1625 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1626 goto fail; 1627 } 1628 1629 /* Create DMA tag for Rx buffers. */ 1630 error = bus_dma_tag_create( 1631 sc->alc_cdata.alc_buffer_tag, /* parent */ 1632 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1633 BUS_SPACE_MAXADDR, /* lowaddr */ 1634 BUS_SPACE_MAXADDR, /* highaddr */ 1635 NULL, NULL, /* filter, filterarg */ 1636 MCLBYTES, /* maxsize */ 1637 1, /* nsegments */ 1638 MCLBYTES, /* maxsegsize */ 1639 0, /* flags */ 1640 NULL, NULL, /* lockfunc, lockarg */ 1641 &sc->alc_cdata.alc_rx_tag); 1642 if (error != 0) { 1643 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1644 goto fail; 1645 } 1646 /* Create DMA maps for Tx buffers. */ 1647 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1648 txd = &sc->alc_cdata.alc_txdesc[i]; 1649 txd->tx_m = NULL; 1650 txd->tx_dmamap = NULL; 1651 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1652 &txd->tx_dmamap); 1653 if (error != 0) { 1654 device_printf(sc->alc_dev, 1655 "could not create Tx dmamap.\n"); 1656 goto fail; 1657 } 1658 } 1659 /* Create DMA maps for Rx buffers. */ 1660 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1661 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1662 device_printf(sc->alc_dev, 1663 "could not create spare Rx dmamap.\n"); 1664 goto fail; 1665 } 1666 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1667 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1668 rxd->rx_m = NULL; 1669 rxd->rx_dmamap = NULL; 1670 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1671 &rxd->rx_dmamap); 1672 if (error != 0) { 1673 device_printf(sc->alc_dev, 1674 "could not create Rx dmamap.\n"); 1675 goto fail; 1676 } 1677 } 1678 1679 fail: 1680 return (error); 1681 } 1682 1683 static void 1684 alc_dma_free(struct alc_softc *sc) 1685 { 1686 struct alc_txdesc *txd; 1687 struct alc_rxdesc *rxd; 1688 int i; 1689 1690 /* Tx buffers. */ 1691 if (sc->alc_cdata.alc_tx_tag != NULL) { 1692 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1693 txd = &sc->alc_cdata.alc_txdesc[i]; 1694 if (txd->tx_dmamap != NULL) { 1695 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1696 txd->tx_dmamap); 1697 txd->tx_dmamap = NULL; 1698 } 1699 } 1700 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1701 sc->alc_cdata.alc_tx_tag = NULL; 1702 } 1703 /* Rx buffers */ 1704 if (sc->alc_cdata.alc_rx_tag != NULL) { 1705 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1706 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1707 if (rxd->rx_dmamap != NULL) { 1708 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1709 rxd->rx_dmamap); 1710 rxd->rx_dmamap = NULL; 1711 } 1712 } 1713 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1714 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1715 sc->alc_cdata.alc_rx_sparemap); 1716 sc->alc_cdata.alc_rx_sparemap = NULL; 1717 } 1718 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1719 sc->alc_cdata.alc_rx_tag = NULL; 1720 } 1721 /* Tx descriptor ring. */ 1722 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1723 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1724 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1725 sc->alc_cdata.alc_tx_ring_map); 1726 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1727 sc->alc_rdata.alc_tx_ring != NULL) 1728 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1729 sc->alc_rdata.alc_tx_ring, 1730 sc->alc_cdata.alc_tx_ring_map); 1731 sc->alc_rdata.alc_tx_ring = NULL; 1732 sc->alc_cdata.alc_tx_ring_map = NULL; 1733 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1734 sc->alc_cdata.alc_tx_ring_tag = NULL; 1735 } 1736 /* Rx ring. */ 1737 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1738 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1739 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1740 sc->alc_cdata.alc_rx_ring_map); 1741 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1742 sc->alc_rdata.alc_rx_ring != NULL) 1743 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1744 sc->alc_rdata.alc_rx_ring, 1745 sc->alc_cdata.alc_rx_ring_map); 1746 sc->alc_rdata.alc_rx_ring = NULL; 1747 sc->alc_cdata.alc_rx_ring_map = NULL; 1748 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1749 sc->alc_cdata.alc_rx_ring_tag = NULL; 1750 } 1751 /* Rx return ring. */ 1752 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1753 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1754 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1755 sc->alc_cdata.alc_rr_ring_map); 1756 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1757 sc->alc_rdata.alc_rr_ring != NULL) 1758 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1759 sc->alc_rdata.alc_rr_ring, 1760 sc->alc_cdata.alc_rr_ring_map); 1761 sc->alc_rdata.alc_rr_ring = NULL; 1762 sc->alc_cdata.alc_rr_ring_map = NULL; 1763 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1764 sc->alc_cdata.alc_rr_ring_tag = NULL; 1765 } 1766 /* CMB block */ 1767 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1768 if (sc->alc_cdata.alc_cmb_map != NULL) 1769 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1770 sc->alc_cdata.alc_cmb_map); 1771 if (sc->alc_cdata.alc_cmb_map != NULL && 1772 sc->alc_rdata.alc_cmb != NULL) 1773 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1774 sc->alc_rdata.alc_cmb, 1775 sc->alc_cdata.alc_cmb_map); 1776 sc->alc_rdata.alc_cmb = NULL; 1777 sc->alc_cdata.alc_cmb_map = NULL; 1778 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1779 sc->alc_cdata.alc_cmb_tag = NULL; 1780 } 1781 /* SMB block */ 1782 if (sc->alc_cdata.alc_smb_tag != NULL) { 1783 if (sc->alc_cdata.alc_smb_map != NULL) 1784 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1785 sc->alc_cdata.alc_smb_map); 1786 if (sc->alc_cdata.alc_smb_map != NULL && 1787 sc->alc_rdata.alc_smb != NULL) 1788 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1789 sc->alc_rdata.alc_smb, 1790 sc->alc_cdata.alc_smb_map); 1791 sc->alc_rdata.alc_smb = NULL; 1792 sc->alc_cdata.alc_smb_map = NULL; 1793 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1794 sc->alc_cdata.alc_smb_tag = NULL; 1795 } 1796 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1797 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1798 sc->alc_cdata.alc_buffer_tag = NULL; 1799 } 1800 if (sc->alc_cdata.alc_parent_tag != NULL) { 1801 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1802 sc->alc_cdata.alc_parent_tag = NULL; 1803 } 1804 } 1805 1806 static int 1807 alc_shutdown(device_t dev) 1808 { 1809 1810 return (alc_suspend(dev)); 1811 } 1812 1813 /* 1814 * Note, this driver resets the link speed to 10/100Mbps by 1815 * restarting auto-negotiation in suspend/shutdown phase but we 1816 * don't know whether that auto-negotiation would succeed or not 1817 * as driver has no control after powering off/suspend operation. 1818 * If the renegotiation fail WOL may not work. Running at 1Gbps 1819 * will draw more power than 375mA at 3.3V which is specified in 1820 * PCI specification and that would result in complete 1821 * shutdowning power to ethernet controller. 1822 * 1823 * TODO 1824 * Save current negotiated media speed/duplex/flow-control to 1825 * softc and restore the same link again after resuming. PHY 1826 * handling such as power down/resetting to 100Mbps may be better 1827 * handled in suspend method in phy driver. 1828 */ 1829 static void 1830 alc_setlinkspeed(struct alc_softc *sc) 1831 { 1832 struct mii_data *mii; 1833 int aneg, i; 1834 1835 mii = device_get_softc(sc->alc_miibus); 1836 mii_pollstat(mii); 1837 aneg = 0; 1838 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1839 (IFM_ACTIVE | IFM_AVALID)) { 1840 switch IFM_SUBTYPE(mii->mii_media_active) { 1841 case IFM_10_T: 1842 case IFM_100_TX: 1843 return; 1844 case IFM_1000_T: 1845 aneg++; 1846 break; 1847 default: 1848 break; 1849 } 1850 } 1851 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1852 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1853 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1854 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1855 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1856 DELAY(1000); 1857 if (aneg != 0) { 1858 /* 1859 * Poll link state until alc(4) get a 10/100Mbps link. 1860 */ 1861 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1862 mii_pollstat(mii); 1863 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1864 == (IFM_ACTIVE | IFM_AVALID)) { 1865 switch (IFM_SUBTYPE( 1866 mii->mii_media_active)) { 1867 case IFM_10_T: 1868 case IFM_100_TX: 1869 alc_mac_config(sc); 1870 return; 1871 default: 1872 break; 1873 } 1874 } 1875 ALC_UNLOCK(sc); 1876 pause("alclnk", hz); 1877 ALC_LOCK(sc); 1878 } 1879 if (i == MII_ANEGTICKS_GIGE) 1880 device_printf(sc->alc_dev, 1881 "establishing a link failed, WOL may not work!"); 1882 } 1883 /* 1884 * No link, force MAC to have 100Mbps, full-duplex link. 1885 * This is the last resort and may/may not work. 1886 */ 1887 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1888 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1889 alc_mac_config(sc); 1890 } 1891 1892 static void 1893 alc_setwol(struct alc_softc *sc) 1894 { 1895 struct ifnet *ifp; 1896 uint32_t reg, pmcs; 1897 uint16_t pmstat; 1898 1899 ALC_LOCK_ASSERT(sc); 1900 1901 alc_disable_l0s_l1(sc); 1902 ifp = sc->alc_ifp; 1903 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1904 /* Disable WOL. */ 1905 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1906 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1907 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1908 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1909 /* Force PHY power down. */ 1910 alc_phy_down(sc); 1911 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1912 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1913 return; 1914 } 1915 1916 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1917 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1918 alc_setlinkspeed(sc); 1919 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1920 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1921 } 1922 1923 pmcs = 0; 1924 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1925 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1926 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1927 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1928 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1929 MAC_CFG_BCAST); 1930 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1931 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1932 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1933 reg |= MAC_CFG_RX_ENB; 1934 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1935 1936 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1937 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1938 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1939 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1940 /* WOL disabled, PHY power down. */ 1941 alc_phy_down(sc); 1942 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1943 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1944 } 1945 /* Request PME. */ 1946 pmstat = pci_read_config(sc->alc_dev, 1947 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1948 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1949 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1950 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1951 pci_write_config(sc->alc_dev, 1952 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1953 } 1954 1955 static int 1956 alc_suspend(device_t dev) 1957 { 1958 struct alc_softc *sc; 1959 1960 sc = device_get_softc(dev); 1961 1962 ALC_LOCK(sc); 1963 alc_stop(sc); 1964 alc_setwol(sc); 1965 ALC_UNLOCK(sc); 1966 1967 return (0); 1968 } 1969 1970 static int 1971 alc_resume(device_t dev) 1972 { 1973 struct alc_softc *sc; 1974 struct ifnet *ifp; 1975 uint16_t pmstat; 1976 1977 sc = device_get_softc(dev); 1978 1979 ALC_LOCK(sc); 1980 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1981 /* Disable PME and clear PME status. */ 1982 pmstat = pci_read_config(sc->alc_dev, 1983 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1984 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1985 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1986 pci_write_config(sc->alc_dev, 1987 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1988 } 1989 } 1990 /* Reset PHY. */ 1991 alc_phy_reset(sc); 1992 ifp = sc->alc_ifp; 1993 if ((ifp->if_flags & IFF_UP) != 0) { 1994 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1995 alc_init_locked(sc); 1996 } 1997 ALC_UNLOCK(sc); 1998 1999 return (0); 2000 } 2001 2002 static int 2003 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2004 { 2005 struct alc_txdesc *txd, *txd_last; 2006 struct tx_desc *desc; 2007 struct mbuf *m; 2008 struct ip *ip; 2009 struct tcphdr *tcp; 2010 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2011 bus_dmamap_t map; 2012 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2013 int error, idx, nsegs, prod; 2014 2015 ALC_LOCK_ASSERT(sc); 2016 2017 M_ASSERTPKTHDR((*m_head)); 2018 2019 m = *m_head; 2020 ip = NULL; 2021 tcp = NULL; 2022 ip_off = poff = 0; 2023 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2024 /* 2025 * AR813x/AR815x requires offset of TCP/UDP header in its 2026 * Tx descriptor to perform Tx checksum offloading. TSO 2027 * also requires TCP header offset and modification of 2028 * IP/TCP header. This kind of operation takes many CPU 2029 * cycles on FreeBSD so fast host CPU is required to get 2030 * smooth TSO performance. 2031 */ 2032 struct ether_header *eh; 2033 2034 if (M_WRITABLE(m) == 0) { 2035 /* Get a writable copy. */ 2036 m = m_dup(*m_head, M_DONTWAIT); 2037 /* Release original mbufs. */ 2038 m_freem(*m_head); 2039 if (m == NULL) { 2040 *m_head = NULL; 2041 return (ENOBUFS); 2042 } 2043 *m_head = m; 2044 } 2045 2046 ip_off = sizeof(struct ether_header); 2047 m = m_pullup(m, ip_off); 2048 if (m == NULL) { 2049 *m_head = NULL; 2050 return (ENOBUFS); 2051 } 2052 eh = mtod(m, struct ether_header *); 2053 /* 2054 * Check if hardware VLAN insertion is off. 2055 * Additional check for LLC/SNAP frame? 2056 */ 2057 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2058 ip_off = sizeof(struct ether_vlan_header); 2059 m = m_pullup(m, ip_off); 2060 if (m == NULL) { 2061 *m_head = NULL; 2062 return (ENOBUFS); 2063 } 2064 } 2065 m = m_pullup(m, ip_off + sizeof(struct ip)); 2066 if (m == NULL) { 2067 *m_head = NULL; 2068 return (ENOBUFS); 2069 } 2070 ip = (struct ip *)(mtod(m, char *) + ip_off); 2071 poff = ip_off + (ip->ip_hl << 2); 2072 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2073 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2074 if (m == NULL) { 2075 *m_head = NULL; 2076 return (ENOBUFS); 2077 } 2078 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2079 m = m_pullup(m, poff + (tcp->th_off << 2)); 2080 if (m == NULL) { 2081 *m_head = NULL; 2082 return (ENOBUFS); 2083 } 2084 /* 2085 * Due to strict adherence of Microsoft NDIS 2086 * Large Send specification, hardware expects 2087 * a pseudo TCP checksum inserted by upper 2088 * stack. Unfortunately the pseudo TCP 2089 * checksum that NDIS refers to does not include 2090 * TCP payload length so driver should recompute 2091 * the pseudo checksum here. Hopefully this 2092 * wouldn't be much burden on modern CPUs. 2093 * 2094 * Reset IP checksum and recompute TCP pseudo 2095 * checksum as NDIS specification said. 2096 */ 2097 ip = (struct ip *)(mtod(m, char *) + ip_off); 2098 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2099 ip->ip_sum = 0; 2100 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2101 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2102 } 2103 *m_head = m; 2104 } 2105 2106 prod = sc->alc_cdata.alc_tx_prod; 2107 txd = &sc->alc_cdata.alc_txdesc[prod]; 2108 txd_last = txd; 2109 map = txd->tx_dmamap; 2110 2111 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2112 *m_head, txsegs, &nsegs, 0); 2113 if (error == EFBIG) { 2114 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 2115 if (m == NULL) { 2116 m_freem(*m_head); 2117 *m_head = NULL; 2118 return (ENOMEM); 2119 } 2120 *m_head = m; 2121 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2122 *m_head, txsegs, &nsegs, 0); 2123 if (error != 0) { 2124 m_freem(*m_head); 2125 *m_head = NULL; 2126 return (error); 2127 } 2128 } else if (error != 0) 2129 return (error); 2130 if (nsegs == 0) { 2131 m_freem(*m_head); 2132 *m_head = NULL; 2133 return (EIO); 2134 } 2135 2136 /* Check descriptor overrun. */ 2137 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2138 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2139 return (ENOBUFS); 2140 } 2141 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2142 2143 m = *m_head; 2144 cflags = TD_ETHERNET; 2145 vtag = 0; 2146 desc = NULL; 2147 idx = 0; 2148 /* Configure VLAN hardware tag insertion. */ 2149 if ((m->m_flags & M_VLANTAG) != 0) { 2150 vtag = htons(m->m_pkthdr.ether_vtag); 2151 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2152 cflags |= TD_INS_VLAN_TAG; 2153 } 2154 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2155 /* Request TSO and set MSS. */ 2156 cflags |= TD_TSO | TD_TSO_DESCV1; 2157 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2158 TD_MSS_MASK; 2159 /* Set TCP header offset. */ 2160 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2161 TD_TCPHDR_OFFSET_MASK; 2162 /* 2163 * AR813x/AR815x requires the first buffer should 2164 * only hold IP/TCP header data. Payload should 2165 * be handled in other descriptors. 2166 */ 2167 hdrlen = poff + (tcp->th_off << 2); 2168 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2169 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2170 desc->flags = htole32(cflags); 2171 desc->addr = htole64(txsegs[0].ds_addr); 2172 sc->alc_cdata.alc_tx_cnt++; 2173 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2174 if (m->m_len - hdrlen > 0) { 2175 /* Handle remaining payload of the first fragment. */ 2176 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2177 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2178 vtag)); 2179 desc->flags = htole32(cflags); 2180 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2181 sc->alc_cdata.alc_tx_cnt++; 2182 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2183 } 2184 /* Handle remaining fragments. */ 2185 idx = 1; 2186 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2187 /* Configure Tx checksum offload. */ 2188 #ifdef ALC_USE_CUSTOM_CSUM 2189 cflags |= TD_CUSTOM_CSUM; 2190 /* Set checksum start offset. */ 2191 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2192 TD_PLOAD_OFFSET_MASK; 2193 /* Set checksum insertion position of TCP/UDP. */ 2194 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2195 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2196 #else 2197 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2198 cflags |= TD_IPCSUM; 2199 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2200 cflags |= TD_TCPCSUM; 2201 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2202 cflags |= TD_UDPCSUM; 2203 /* Set TCP/UDP header offset. */ 2204 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2205 TD_L4HDR_OFFSET_MASK; 2206 #endif 2207 } 2208 for (; idx < nsegs; idx++) { 2209 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2210 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2211 desc->flags = htole32(cflags); 2212 desc->addr = htole64(txsegs[idx].ds_addr); 2213 sc->alc_cdata.alc_tx_cnt++; 2214 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2215 } 2216 /* Update producer index. */ 2217 sc->alc_cdata.alc_tx_prod = prod; 2218 2219 /* Finally set EOP on the last descriptor. */ 2220 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2221 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2222 desc->flags |= htole32(TD_EOP); 2223 2224 /* Swap dmamap of the first and the last. */ 2225 txd = &sc->alc_cdata.alc_txdesc[prod]; 2226 map = txd_last->tx_dmamap; 2227 txd_last->tx_dmamap = txd->tx_dmamap; 2228 txd->tx_dmamap = map; 2229 txd->tx_m = m; 2230 2231 return (0); 2232 } 2233 2234 static void 2235 alc_start(struct ifnet *ifp) 2236 { 2237 struct alc_softc *sc; 2238 2239 sc = ifp->if_softc; 2240 ALC_LOCK(sc); 2241 alc_start_locked(ifp); 2242 ALC_UNLOCK(sc); 2243 } 2244 2245 static void 2246 alc_start_locked(struct ifnet *ifp) 2247 { 2248 struct alc_softc *sc; 2249 struct mbuf *m_head; 2250 int enq; 2251 2252 sc = ifp->if_softc; 2253 2254 ALC_LOCK_ASSERT(sc); 2255 2256 /* Reclaim transmitted frames. */ 2257 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2258 alc_txeof(sc); 2259 2260 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2261 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2262 return; 2263 2264 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2265 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2266 if (m_head == NULL) 2267 break; 2268 /* 2269 * Pack the data into the transmit ring. If we 2270 * don't have room, set the OACTIVE flag and wait 2271 * for the NIC to drain the ring. 2272 */ 2273 if (alc_encap(sc, &m_head)) { 2274 if (m_head == NULL) 2275 break; 2276 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2277 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2278 break; 2279 } 2280 2281 enq++; 2282 /* 2283 * If there's a BPF listener, bounce a copy of this frame 2284 * to him. 2285 */ 2286 ETHER_BPF_MTAP(ifp, m_head); 2287 } 2288 2289 if (enq > 0) { 2290 /* Sync descriptors. */ 2291 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2292 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2293 /* Kick. Assume we're using normal Tx priority queue. */ 2294 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2295 (sc->alc_cdata.alc_tx_prod << 2296 MBOX_TD_PROD_LO_IDX_SHIFT) & 2297 MBOX_TD_PROD_LO_IDX_MASK); 2298 /* Set a timeout in case the chip goes out to lunch. */ 2299 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2300 } 2301 } 2302 2303 static void 2304 alc_watchdog(struct alc_softc *sc) 2305 { 2306 struct ifnet *ifp; 2307 2308 ALC_LOCK_ASSERT(sc); 2309 2310 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2311 return; 2312 2313 ifp = sc->alc_ifp; 2314 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2315 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2316 ifp->if_oerrors++; 2317 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2318 alc_init_locked(sc); 2319 return; 2320 } 2321 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2322 ifp->if_oerrors++; 2323 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2324 alc_init_locked(sc); 2325 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2326 alc_start_locked(ifp); 2327 } 2328 2329 static int 2330 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2331 { 2332 struct alc_softc *sc; 2333 struct ifreq *ifr; 2334 struct mii_data *mii; 2335 int error, mask; 2336 2337 sc = ifp->if_softc; 2338 ifr = (struct ifreq *)data; 2339 error = 0; 2340 switch (cmd) { 2341 case SIOCSIFMTU: 2342 if (ifr->ifr_mtu < ETHERMIN || 2343 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2344 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2345 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2346 ifr->ifr_mtu > ETHERMTU)) 2347 error = EINVAL; 2348 else if (ifp->if_mtu != ifr->ifr_mtu) { 2349 ALC_LOCK(sc); 2350 ifp->if_mtu = ifr->ifr_mtu; 2351 /* AR813x/AR815x has 13 bits MSS field. */ 2352 if (ifp->if_mtu > ALC_TSO_MTU && 2353 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2354 ifp->if_capenable &= ~IFCAP_TSO4; 2355 ifp->if_hwassist &= ~CSUM_TSO; 2356 VLAN_CAPABILITIES(ifp); 2357 } 2358 ALC_UNLOCK(sc); 2359 } 2360 break; 2361 case SIOCSIFFLAGS: 2362 ALC_LOCK(sc); 2363 if ((ifp->if_flags & IFF_UP) != 0) { 2364 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2365 ((ifp->if_flags ^ sc->alc_if_flags) & 2366 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2367 alc_rxfilter(sc); 2368 else 2369 alc_init_locked(sc); 2370 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2371 alc_stop(sc); 2372 sc->alc_if_flags = ifp->if_flags; 2373 ALC_UNLOCK(sc); 2374 break; 2375 case SIOCADDMULTI: 2376 case SIOCDELMULTI: 2377 ALC_LOCK(sc); 2378 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2379 alc_rxfilter(sc); 2380 ALC_UNLOCK(sc); 2381 break; 2382 case SIOCSIFMEDIA: 2383 case SIOCGIFMEDIA: 2384 mii = device_get_softc(sc->alc_miibus); 2385 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2386 break; 2387 case SIOCSIFCAP: 2388 ALC_LOCK(sc); 2389 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2390 if ((mask & IFCAP_TXCSUM) != 0 && 2391 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2392 ifp->if_capenable ^= IFCAP_TXCSUM; 2393 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2394 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2395 else 2396 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2397 } 2398 if ((mask & IFCAP_TSO4) != 0 && 2399 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2400 ifp->if_capenable ^= IFCAP_TSO4; 2401 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2402 /* AR813x/AR815x has 13 bits MSS field. */ 2403 if (ifp->if_mtu > ALC_TSO_MTU) { 2404 ifp->if_capenable &= ~IFCAP_TSO4; 2405 ifp->if_hwassist &= ~CSUM_TSO; 2406 } else 2407 ifp->if_hwassist |= CSUM_TSO; 2408 } else 2409 ifp->if_hwassist &= ~CSUM_TSO; 2410 } 2411 if ((mask & IFCAP_WOL_MCAST) != 0 && 2412 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2413 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2414 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2415 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2416 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2417 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2418 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2419 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2420 alc_rxvlan(sc); 2421 } 2422 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2423 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2424 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2425 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2426 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2427 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2428 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2429 ifp->if_capenable &= 2430 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2431 ALC_UNLOCK(sc); 2432 VLAN_CAPABILITIES(ifp); 2433 break; 2434 default: 2435 error = ether_ioctl(ifp, cmd, data); 2436 break; 2437 } 2438 2439 return (error); 2440 } 2441 2442 static void 2443 alc_mac_config(struct alc_softc *sc) 2444 { 2445 struct mii_data *mii; 2446 uint32_t reg; 2447 2448 ALC_LOCK_ASSERT(sc); 2449 2450 mii = device_get_softc(sc->alc_miibus); 2451 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2452 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2453 MAC_CFG_SPEED_MASK); 2454 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2455 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2456 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2457 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2458 /* Reprogram MAC with resolved speed/duplex. */ 2459 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2460 case IFM_10_T: 2461 case IFM_100_TX: 2462 reg |= MAC_CFG_SPEED_10_100; 2463 break; 2464 case IFM_1000_T: 2465 reg |= MAC_CFG_SPEED_1000; 2466 break; 2467 } 2468 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2469 reg |= MAC_CFG_FULL_DUPLEX; 2470 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2471 reg |= MAC_CFG_TX_FC; 2472 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2473 reg |= MAC_CFG_RX_FC; 2474 } 2475 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2476 } 2477 2478 static void 2479 alc_stats_clear(struct alc_softc *sc) 2480 { 2481 struct smb sb, *smb; 2482 uint32_t *reg; 2483 int i; 2484 2485 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2486 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2487 sc->alc_cdata.alc_smb_map, 2488 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2489 smb = sc->alc_rdata.alc_smb; 2490 /* Update done, clear. */ 2491 smb->updated = 0; 2492 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2493 sc->alc_cdata.alc_smb_map, 2494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2495 } else { 2496 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2497 reg++) { 2498 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2499 i += sizeof(uint32_t); 2500 } 2501 /* Read Tx statistics. */ 2502 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2503 reg++) { 2504 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2505 i += sizeof(uint32_t); 2506 } 2507 } 2508 } 2509 2510 static void 2511 alc_stats_update(struct alc_softc *sc) 2512 { 2513 struct alc_hw_stats *stat; 2514 struct smb sb, *smb; 2515 struct ifnet *ifp; 2516 uint32_t *reg; 2517 int i; 2518 2519 ALC_LOCK_ASSERT(sc); 2520 2521 ifp = sc->alc_ifp; 2522 stat = &sc->alc_stats; 2523 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2524 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2525 sc->alc_cdata.alc_smb_map, 2526 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2527 smb = sc->alc_rdata.alc_smb; 2528 if (smb->updated == 0) 2529 return; 2530 } else { 2531 smb = &sb; 2532 /* Read Rx statistics. */ 2533 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2534 reg++) { 2535 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2536 i += sizeof(uint32_t); 2537 } 2538 /* Read Tx statistics. */ 2539 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2540 reg++) { 2541 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2542 i += sizeof(uint32_t); 2543 } 2544 } 2545 2546 /* Rx stats. */ 2547 stat->rx_frames += smb->rx_frames; 2548 stat->rx_bcast_frames += smb->rx_bcast_frames; 2549 stat->rx_mcast_frames += smb->rx_mcast_frames; 2550 stat->rx_pause_frames += smb->rx_pause_frames; 2551 stat->rx_control_frames += smb->rx_control_frames; 2552 stat->rx_crcerrs += smb->rx_crcerrs; 2553 stat->rx_lenerrs += smb->rx_lenerrs; 2554 stat->rx_bytes += smb->rx_bytes; 2555 stat->rx_runts += smb->rx_runts; 2556 stat->rx_fragments += smb->rx_fragments; 2557 stat->rx_pkts_64 += smb->rx_pkts_64; 2558 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2559 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2560 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2561 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2562 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2563 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2564 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2565 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2566 stat->rx_rrs_errs += smb->rx_rrs_errs; 2567 stat->rx_alignerrs += smb->rx_alignerrs; 2568 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2569 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2570 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2571 2572 /* Tx stats. */ 2573 stat->tx_frames += smb->tx_frames; 2574 stat->tx_bcast_frames += smb->tx_bcast_frames; 2575 stat->tx_mcast_frames += smb->tx_mcast_frames; 2576 stat->tx_pause_frames += smb->tx_pause_frames; 2577 stat->tx_excess_defer += smb->tx_excess_defer; 2578 stat->tx_control_frames += smb->tx_control_frames; 2579 stat->tx_deferred += smb->tx_deferred; 2580 stat->tx_bytes += smb->tx_bytes; 2581 stat->tx_pkts_64 += smb->tx_pkts_64; 2582 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2583 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2584 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2585 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2586 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2587 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2588 stat->tx_single_colls += smb->tx_single_colls; 2589 stat->tx_multi_colls += smb->tx_multi_colls; 2590 stat->tx_late_colls += smb->tx_late_colls; 2591 stat->tx_excess_colls += smb->tx_excess_colls; 2592 stat->tx_abort += smb->tx_abort; 2593 stat->tx_underrun += smb->tx_underrun; 2594 stat->tx_desc_underrun += smb->tx_desc_underrun; 2595 stat->tx_lenerrs += smb->tx_lenerrs; 2596 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2597 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2598 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2599 2600 /* Update counters in ifnet. */ 2601 ifp->if_opackets += smb->tx_frames; 2602 2603 ifp->if_collisions += smb->tx_single_colls + 2604 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2605 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2606 2607 /* 2608 * XXX 2609 * tx_pkts_truncated counter looks suspicious. It constantly 2610 * increments with no sign of Tx errors. This may indicate 2611 * the counter name is not correct one so I've removed the 2612 * counter in output errors. 2613 */ 2614 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2615 smb->tx_underrun; 2616 2617 ifp->if_ipackets += smb->rx_frames; 2618 2619 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2620 smb->rx_runts + smb->rx_pkts_truncated + 2621 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2622 smb->rx_alignerrs; 2623 2624 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2625 /* Update done, clear. */ 2626 smb->updated = 0; 2627 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2628 sc->alc_cdata.alc_smb_map, 2629 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2630 } 2631 } 2632 2633 static int 2634 alc_intr(void *arg) 2635 { 2636 struct alc_softc *sc; 2637 uint32_t status; 2638 2639 sc = (struct alc_softc *)arg; 2640 2641 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2642 if ((status & ALC_INTRS) == 0) 2643 return (FILTER_STRAY); 2644 /* Disable interrupts. */ 2645 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2646 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2647 2648 return (FILTER_HANDLED); 2649 } 2650 2651 static void 2652 alc_int_task(void *arg, int pending) 2653 { 2654 struct alc_softc *sc; 2655 struct ifnet *ifp; 2656 uint32_t status; 2657 int more; 2658 2659 sc = (struct alc_softc *)arg; 2660 ifp = sc->alc_ifp; 2661 2662 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2663 ALC_LOCK(sc); 2664 if (sc->alc_morework != 0) { 2665 sc->alc_morework = 0; 2666 status |= INTR_RX_PKT; 2667 } 2668 if ((status & ALC_INTRS) == 0) 2669 goto done; 2670 2671 /* Acknowledge interrupts but still disable interrupts. */ 2672 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2673 2674 more = 0; 2675 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2676 if ((status & INTR_RX_PKT) != 0) { 2677 more = alc_rxintr(sc, sc->alc_process_limit); 2678 if (more == EAGAIN) 2679 sc->alc_morework = 1; 2680 else if (more == EIO) { 2681 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2682 alc_init_locked(sc); 2683 ALC_UNLOCK(sc); 2684 return; 2685 } 2686 } 2687 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2688 INTR_TXQ_TO_RST)) != 0) { 2689 if ((status & INTR_DMA_RD_TO_RST) != 0) 2690 device_printf(sc->alc_dev, 2691 "DMA read error! -- resetting\n"); 2692 if ((status & INTR_DMA_WR_TO_RST) != 0) 2693 device_printf(sc->alc_dev, 2694 "DMA write error! -- resetting\n"); 2695 if ((status & INTR_TXQ_TO_RST) != 0) 2696 device_printf(sc->alc_dev, 2697 "TxQ reset! -- resetting\n"); 2698 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2699 alc_init_locked(sc); 2700 ALC_UNLOCK(sc); 2701 return; 2702 } 2703 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2704 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2705 alc_start_locked(ifp); 2706 } 2707 2708 if (more == EAGAIN || 2709 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2710 ALC_UNLOCK(sc); 2711 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2712 return; 2713 } 2714 2715 done: 2716 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2717 /* Re-enable interrupts if we're running. */ 2718 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2719 } 2720 ALC_UNLOCK(sc); 2721 } 2722 2723 static void 2724 alc_txeof(struct alc_softc *sc) 2725 { 2726 struct ifnet *ifp; 2727 struct alc_txdesc *txd; 2728 uint32_t cons, prod; 2729 int prog; 2730 2731 ALC_LOCK_ASSERT(sc); 2732 2733 ifp = sc->alc_ifp; 2734 2735 if (sc->alc_cdata.alc_tx_cnt == 0) 2736 return; 2737 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2738 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2739 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2740 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2741 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2742 prod = sc->alc_rdata.alc_cmb->cons; 2743 } else 2744 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2745 /* Assume we're using normal Tx priority queue. */ 2746 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2747 MBOX_TD_CONS_LO_IDX_SHIFT; 2748 cons = sc->alc_cdata.alc_tx_cons; 2749 /* 2750 * Go through our Tx list and free mbufs for those 2751 * frames which have been transmitted. 2752 */ 2753 for (prog = 0; cons != prod; prog++, 2754 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2755 if (sc->alc_cdata.alc_tx_cnt <= 0) 2756 break; 2757 prog++; 2758 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2759 sc->alc_cdata.alc_tx_cnt--; 2760 txd = &sc->alc_cdata.alc_txdesc[cons]; 2761 if (txd->tx_m != NULL) { 2762 /* Reclaim transmitted mbufs. */ 2763 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2764 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2765 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2766 txd->tx_dmamap); 2767 m_freem(txd->tx_m); 2768 txd->tx_m = NULL; 2769 } 2770 } 2771 2772 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2773 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2774 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2775 sc->alc_cdata.alc_tx_cons = cons; 2776 /* 2777 * Unarm watchdog timer only when there is no pending 2778 * frames in Tx queue. 2779 */ 2780 if (sc->alc_cdata.alc_tx_cnt == 0) 2781 sc->alc_watchdog_timer = 0; 2782 } 2783 2784 static int 2785 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2786 { 2787 struct mbuf *m; 2788 bus_dma_segment_t segs[1]; 2789 bus_dmamap_t map; 2790 int nsegs; 2791 2792 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2793 if (m == NULL) 2794 return (ENOBUFS); 2795 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2796 #ifndef __NO_STRICT_ALIGNMENT 2797 m_adj(m, sizeof(uint64_t)); 2798 #endif 2799 2800 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2801 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2802 m_freem(m); 2803 return (ENOBUFS); 2804 } 2805 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2806 2807 if (rxd->rx_m != NULL) { 2808 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2809 BUS_DMASYNC_POSTREAD); 2810 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2811 } 2812 map = rxd->rx_dmamap; 2813 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2814 sc->alc_cdata.alc_rx_sparemap = map; 2815 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2816 BUS_DMASYNC_PREREAD); 2817 rxd->rx_m = m; 2818 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2819 return (0); 2820 } 2821 2822 static int 2823 alc_rxintr(struct alc_softc *sc, int count) 2824 { 2825 struct ifnet *ifp; 2826 struct rx_rdesc *rrd; 2827 uint32_t nsegs, status; 2828 int rr_cons, prog; 2829 2830 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2831 sc->alc_cdata.alc_rr_ring_map, 2832 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2833 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2834 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2835 rr_cons = sc->alc_cdata.alc_rr_cons; 2836 ifp = sc->alc_ifp; 2837 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2838 if (count-- <= 0) 2839 break; 2840 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2841 status = le32toh(rrd->status); 2842 if ((status & RRD_VALID) == 0) 2843 break; 2844 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2845 if (nsegs == 0) { 2846 /* This should not happen! */ 2847 device_printf(sc->alc_dev, 2848 "unexpected segment count -- resetting\n"); 2849 return (EIO); 2850 } 2851 alc_rxeof(sc, rrd); 2852 /* Clear Rx return status. */ 2853 rrd->status = 0; 2854 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2855 sc->alc_cdata.alc_rx_cons += nsegs; 2856 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2857 prog += nsegs; 2858 } 2859 2860 if (prog > 0) { 2861 /* Update the consumer index. */ 2862 sc->alc_cdata.alc_rr_cons = rr_cons; 2863 /* Sync Rx return descriptors. */ 2864 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2865 sc->alc_cdata.alc_rr_ring_map, 2866 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2867 /* 2868 * Sync updated Rx descriptors such that controller see 2869 * modified buffer addresses. 2870 */ 2871 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2872 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2873 /* 2874 * Let controller know availability of new Rx buffers. 2875 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2876 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2877 * only when Rx buffer pre-fetching is required. In 2878 * addition we already set ALC_RX_RD_FREE_THRESH to 2879 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2880 * it still seems that pre-fetching needs more 2881 * experimentation. 2882 */ 2883 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2884 sc->alc_cdata.alc_rx_cons); 2885 } 2886 2887 return (count > 0 ? 0 : EAGAIN); 2888 } 2889 2890 #ifndef __NO_STRICT_ALIGNMENT 2891 static struct mbuf * 2892 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2893 { 2894 struct mbuf *n; 2895 int i; 2896 uint16_t *src, *dst; 2897 2898 src = mtod(m, uint16_t *); 2899 dst = src - 3; 2900 2901 if (m->m_next == NULL) { 2902 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2903 *dst++ = *src++; 2904 m->m_data -= 6; 2905 return (m); 2906 } 2907 /* 2908 * Append a new mbuf to received mbuf chain and copy ethernet 2909 * header from the mbuf chain. This can save lots of CPU 2910 * cycles for jumbo frame. 2911 */ 2912 MGETHDR(n, M_DONTWAIT, MT_DATA); 2913 if (n == NULL) { 2914 ifp->if_iqdrops++; 2915 m_freem(m); 2916 return (NULL); 2917 } 2918 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2919 m->m_data += ETHER_HDR_LEN; 2920 m->m_len -= ETHER_HDR_LEN; 2921 n->m_len = ETHER_HDR_LEN; 2922 M_MOVE_PKTHDR(n, m); 2923 n->m_next = m; 2924 return (n); 2925 } 2926 #endif 2927 2928 /* Receive a frame. */ 2929 static void 2930 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2931 { 2932 struct alc_rxdesc *rxd; 2933 struct ifnet *ifp; 2934 struct mbuf *mp, *m; 2935 uint32_t rdinfo, status, vtag; 2936 int count, nsegs, rx_cons; 2937 2938 ifp = sc->alc_ifp; 2939 status = le32toh(rrd->status); 2940 rdinfo = le32toh(rrd->rdinfo); 2941 rx_cons = RRD_RD_IDX(rdinfo); 2942 nsegs = RRD_RD_CNT(rdinfo); 2943 2944 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2945 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2946 /* 2947 * We want to pass the following frames to upper 2948 * layer regardless of error status of Rx return 2949 * ring. 2950 * 2951 * o IP/TCP/UDP checksum is bad. 2952 * o frame length and protocol specific length 2953 * does not match. 2954 * 2955 * Force network stack compute checksum for 2956 * errored frames. 2957 */ 2958 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2959 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2960 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2961 return; 2962 } 2963 2964 for (count = 0; count < nsegs; count++, 2965 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2966 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2967 mp = rxd->rx_m; 2968 /* Add a new receive buffer to the ring. */ 2969 if (alc_newbuf(sc, rxd) != 0) { 2970 ifp->if_iqdrops++; 2971 /* Reuse Rx buffers. */ 2972 if (sc->alc_cdata.alc_rxhead != NULL) 2973 m_freem(sc->alc_cdata.alc_rxhead); 2974 break; 2975 } 2976 2977 /* 2978 * Assume we've received a full sized frame. 2979 * Actual size is fixed when we encounter the end of 2980 * multi-segmented frame. 2981 */ 2982 mp->m_len = sc->alc_buf_size; 2983 2984 /* Chain received mbufs. */ 2985 if (sc->alc_cdata.alc_rxhead == NULL) { 2986 sc->alc_cdata.alc_rxhead = mp; 2987 sc->alc_cdata.alc_rxtail = mp; 2988 } else { 2989 mp->m_flags &= ~M_PKTHDR; 2990 sc->alc_cdata.alc_rxprev_tail = 2991 sc->alc_cdata.alc_rxtail; 2992 sc->alc_cdata.alc_rxtail->m_next = mp; 2993 sc->alc_cdata.alc_rxtail = mp; 2994 } 2995 2996 if (count == nsegs - 1) { 2997 /* Last desc. for this frame. */ 2998 m = sc->alc_cdata.alc_rxhead; 2999 m->m_flags |= M_PKTHDR; 3000 /* 3001 * It seems that L1C/L2C controller has no way 3002 * to tell hardware to strip CRC bytes. 3003 */ 3004 m->m_pkthdr.len = 3005 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3006 if (nsegs > 1) { 3007 /* Set last mbuf size. */ 3008 mp->m_len = sc->alc_cdata.alc_rxlen - 3009 (nsegs - 1) * sc->alc_buf_size; 3010 /* Remove the CRC bytes in chained mbufs. */ 3011 if (mp->m_len <= ETHER_CRC_LEN) { 3012 sc->alc_cdata.alc_rxtail = 3013 sc->alc_cdata.alc_rxprev_tail; 3014 sc->alc_cdata.alc_rxtail->m_len -= 3015 (ETHER_CRC_LEN - mp->m_len); 3016 sc->alc_cdata.alc_rxtail->m_next = NULL; 3017 m_freem(mp); 3018 } else { 3019 mp->m_len -= ETHER_CRC_LEN; 3020 } 3021 } else 3022 m->m_len = m->m_pkthdr.len; 3023 m->m_pkthdr.rcvif = ifp; 3024 /* 3025 * Due to hardware bugs, Rx checksum offloading 3026 * was intentionally disabled. 3027 */ 3028 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3029 (status & RRD_VLAN_TAG) != 0) { 3030 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3031 m->m_pkthdr.ether_vtag = ntohs(vtag); 3032 m->m_flags |= M_VLANTAG; 3033 } 3034 #ifndef __NO_STRICT_ALIGNMENT 3035 m = alc_fixup_rx(ifp, m); 3036 if (m != NULL) 3037 #endif 3038 { 3039 /* Pass it on. */ 3040 ALC_UNLOCK(sc); 3041 (*ifp->if_input)(ifp, m); 3042 ALC_LOCK(sc); 3043 } 3044 } 3045 } 3046 /* Reset mbuf chains. */ 3047 ALC_RXCHAIN_RESET(sc); 3048 } 3049 3050 static void 3051 alc_tick(void *arg) 3052 { 3053 struct alc_softc *sc; 3054 struct mii_data *mii; 3055 3056 sc = (struct alc_softc *)arg; 3057 3058 ALC_LOCK_ASSERT(sc); 3059 3060 mii = device_get_softc(sc->alc_miibus); 3061 mii_tick(mii); 3062 alc_stats_update(sc); 3063 /* 3064 * alc(4) does not rely on Tx completion interrupts to reclaim 3065 * transferred buffers. Instead Tx completion interrupts are 3066 * used to hint for scheduling Tx task. So it's necessary to 3067 * release transmitted buffers by kicking Tx completion 3068 * handler. This limits the maximum reclamation delay to a hz. 3069 */ 3070 alc_txeof(sc); 3071 alc_watchdog(sc); 3072 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3073 } 3074 3075 static void 3076 alc_reset(struct alc_softc *sc) 3077 { 3078 uint32_t reg; 3079 int i; 3080 3081 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3082 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3083 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3084 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3085 DELAY(10); 3086 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3087 break; 3088 } 3089 if (i == 0) 3090 device_printf(sc->alc_dev, "master reset timeout!\n"); 3091 3092 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3093 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3094 break; 3095 DELAY(10); 3096 } 3097 3098 if (i == 0) 3099 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3100 } 3101 3102 static void 3103 alc_init(void *xsc) 3104 { 3105 struct alc_softc *sc; 3106 3107 sc = (struct alc_softc *)xsc; 3108 ALC_LOCK(sc); 3109 alc_init_locked(sc); 3110 ALC_UNLOCK(sc); 3111 } 3112 3113 static void 3114 alc_init_locked(struct alc_softc *sc) 3115 { 3116 struct ifnet *ifp; 3117 struct mii_data *mii; 3118 uint8_t eaddr[ETHER_ADDR_LEN]; 3119 bus_addr_t paddr; 3120 uint32_t reg, rxf_hi, rxf_lo; 3121 3122 ALC_LOCK_ASSERT(sc); 3123 3124 ifp = sc->alc_ifp; 3125 mii = device_get_softc(sc->alc_miibus); 3126 3127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3128 return; 3129 /* 3130 * Cancel any pending I/O. 3131 */ 3132 alc_stop(sc); 3133 /* 3134 * Reset the chip to a known state. 3135 */ 3136 alc_reset(sc); 3137 3138 /* Initialize Rx descriptors. */ 3139 if (alc_init_rx_ring(sc) != 0) { 3140 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3141 alc_stop(sc); 3142 return; 3143 } 3144 alc_init_rr_ring(sc); 3145 alc_init_tx_ring(sc); 3146 alc_init_cmb(sc); 3147 alc_init_smb(sc); 3148 3149 /* Enable all clocks. */ 3150 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3151 3152 /* Reprogram the station address. */ 3153 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3154 CSR_WRITE_4(sc, ALC_PAR0, 3155 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3156 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3157 /* 3158 * Clear WOL status and disable all WOL feature as WOL 3159 * would interfere Rx operation under normal environments. 3160 */ 3161 CSR_READ_4(sc, ALC_WOL_CFG); 3162 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3163 /* Set Tx descriptor base addresses. */ 3164 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3165 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3166 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3167 /* We don't use high priority ring. */ 3168 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3169 /* Set Tx descriptor counter. */ 3170 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3171 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3172 /* Set Rx descriptor base addresses. */ 3173 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3174 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3175 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3176 /* We use one Rx ring. */ 3177 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3178 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3179 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3180 /* Set Rx descriptor counter. */ 3181 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3182 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3183 3184 /* 3185 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3186 * if it do not fit the buffer size. Rx return descriptor holds 3187 * a counter that indicates how many fragments were made by the 3188 * hardware. The buffer size should be multiple of 8 bytes. 3189 * Since hardware has limit on the size of buffer size, always 3190 * use the maximum value. 3191 * For strict-alignment architectures make sure to reduce buffer 3192 * size by 8 bytes to make room for alignment fixup. 3193 */ 3194 #ifndef __NO_STRICT_ALIGNMENT 3195 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3196 #else 3197 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3198 #endif 3199 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3200 3201 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3202 /* Set Rx return descriptor base addresses. */ 3203 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3204 /* We use one Rx return ring. */ 3205 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3206 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3207 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3208 /* Set Rx return descriptor counter. */ 3209 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3210 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3211 paddr = sc->alc_rdata.alc_cmb_paddr; 3212 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3213 paddr = sc->alc_rdata.alc_smb_paddr; 3214 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3215 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3216 3217 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3218 /* Reconfigure SRAM - Vendor magic. */ 3219 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3220 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3221 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3222 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3223 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3224 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3225 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3226 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3227 } 3228 3229 /* Tell hardware that we're ready to load DMA blocks. */ 3230 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3231 3232 /* Configure interrupt moderation timer. */ 3233 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3234 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3235 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3236 /* 3237 * We don't want to automatic interrupt clear as task queue 3238 * for the interrupt should know interrupt status. 3239 */ 3240 reg = MASTER_SA_TIMER_ENB; 3241 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3242 reg |= MASTER_IM_RX_TIMER_ENB; 3243 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3244 reg |= MASTER_IM_TX_TIMER_ENB; 3245 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3246 /* 3247 * Disable interrupt re-trigger timer. We don't want automatic 3248 * re-triggering of un-ACKed interrupts. 3249 */ 3250 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3251 /* Configure CMB. */ 3252 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3253 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3254 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3255 } else 3256 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3257 /* 3258 * Hardware can be configured to issue SMB interrupt based 3259 * on programmed interval. Since there is a callout that is 3260 * invoked for every hz in driver we use that instead of 3261 * relying on periodic SMB interrupt. 3262 */ 3263 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3264 /* Clear MAC statistics. */ 3265 alc_stats_clear(sc); 3266 3267 /* 3268 * Always use maximum frame size that controller can support. 3269 * Otherwise received frames that has larger frame length 3270 * than alc(4) MTU would be silently dropped in hardware. This 3271 * would make path-MTU discovery hard as sender wouldn't get 3272 * any responses from receiver. alc(4) supports 3273 * multi-fragmented frames on Rx path so it has no issue on 3274 * assembling fragmented frames. Using maximum frame size also 3275 * removes the need to reinitialize hardware when interface 3276 * MTU configuration was changed. 3277 * 3278 * Be conservative in what you do, be liberal in what you 3279 * accept from others - RFC 793. 3280 */ 3281 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3282 3283 /* Disable header split(?) */ 3284 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3285 3286 /* Configure IPG/IFG parameters. */ 3287 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3288 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3289 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3290 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3291 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3292 /* Set parameters for half-duplex media. */ 3293 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3294 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3295 HDPX_CFG_LCOL_MASK) | 3296 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3297 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3298 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3299 HDPX_CFG_ABEBT_MASK) | 3300 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3301 HDPX_CFG_JAMIPG_MASK)); 3302 /* 3303 * Set TSO/checksum offload threshold. For frames that is 3304 * larger than this threshold, hardware wouldn't do 3305 * TSO/checksum offloading. 3306 */ 3307 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3308 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3309 TSO_OFFLOAD_THRESH_MASK); 3310 /* Configure TxQ. */ 3311 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3312 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3313 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3314 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3315 reg >>= 1; 3316 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3317 TXQ_CFG_TD_BURST_MASK; 3318 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3319 3320 /* Configure Rx free descriptor pre-fetching. */ 3321 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3322 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3323 RX_RD_FREE_THRESH_HI_MASK) | 3324 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3325 RX_RD_FREE_THRESH_LO_MASK)); 3326 3327 /* 3328 * Configure flow control parameters. 3329 * XON : 80% of Rx FIFO 3330 * XOFF : 30% of Rx FIFO 3331 */ 3332 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3333 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3334 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3335 rxf_hi = (reg * 8) / 10; 3336 rxf_lo = (reg * 3) / 10; 3337 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3338 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3339 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3340 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3341 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3342 } 3343 3344 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3345 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3346 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3347 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3348 SERDES_PHY_CLK_SLOWDOWN); 3349 3350 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3351 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3352 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3353 3354 /* Configure RxQ. */ 3355 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3356 RXQ_CFG_RD_BURST_MASK; 3357 reg |= RXQ_CFG_RSS_MODE_DIS; 3358 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3359 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3360 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3361 3362 /* Configure DMA parameters. */ 3363 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3364 reg |= sc->alc_rcb; 3365 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3366 reg |= DMA_CFG_CMB_ENB; 3367 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3368 reg |= DMA_CFG_SMB_ENB; 3369 else 3370 reg |= DMA_CFG_SMB_DIS; 3371 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3372 DMA_CFG_RD_BURST_SHIFT; 3373 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3374 DMA_CFG_WR_BURST_SHIFT; 3375 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3376 DMA_CFG_RD_DELAY_CNT_MASK; 3377 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3378 DMA_CFG_WR_DELAY_CNT_MASK; 3379 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3380 3381 /* 3382 * Configure Tx/Rx MACs. 3383 * - Auto-padding for short frames. 3384 * - Enable CRC generation. 3385 * Actual reconfiguration of MAC for resolved speed/duplex 3386 * is followed after detection of link establishment. 3387 * AR813x/AR815x always does checksum computation regardless 3388 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3389 * have bug in protocol field in Rx return structure so 3390 * these controllers can't handle fragmented frames. Disable 3391 * Rx checksum offloading until there is a newer controller 3392 * that has sane implementation. 3393 */ 3394 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3395 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3396 MAC_CFG_PREAMBLE_MASK); 3397 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3398 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3399 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3400 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3401 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3402 reg |= MAC_CFG_SPEED_10_100; 3403 else 3404 reg |= MAC_CFG_SPEED_1000; 3405 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3406 3407 /* Set up the receive filter. */ 3408 alc_rxfilter(sc); 3409 alc_rxvlan(sc); 3410 3411 /* Acknowledge all pending interrupts and clear it. */ 3412 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3413 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3414 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3415 3416 sc->alc_flags &= ~ALC_FLAG_LINK; 3417 /* Switch to the current media. */ 3418 mii_mediachg(mii); 3419 3420 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3421 3422 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3423 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3424 } 3425 3426 static void 3427 alc_stop(struct alc_softc *sc) 3428 { 3429 struct ifnet *ifp; 3430 struct alc_txdesc *txd; 3431 struct alc_rxdesc *rxd; 3432 uint32_t reg; 3433 int i; 3434 3435 ALC_LOCK_ASSERT(sc); 3436 /* 3437 * Mark the interface down and cancel the watchdog timer. 3438 */ 3439 ifp = sc->alc_ifp; 3440 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3441 sc->alc_flags &= ~ALC_FLAG_LINK; 3442 callout_stop(&sc->alc_tick_ch); 3443 sc->alc_watchdog_timer = 0; 3444 alc_stats_update(sc); 3445 /* Disable interrupts. */ 3446 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3447 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3448 alc_stop_queue(sc); 3449 /* Disable DMA. */ 3450 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3451 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3452 reg |= DMA_CFG_SMB_DIS; 3453 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3454 DELAY(1000); 3455 /* Stop Rx/Tx MACs. */ 3456 alc_stop_mac(sc); 3457 /* Disable interrupts which might be touched in taskq handler. */ 3458 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3459 3460 /* Reclaim Rx buffers that have been processed. */ 3461 if (sc->alc_cdata.alc_rxhead != NULL) 3462 m_freem(sc->alc_cdata.alc_rxhead); 3463 ALC_RXCHAIN_RESET(sc); 3464 /* 3465 * Free Tx/Rx mbufs still in the queues. 3466 */ 3467 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3468 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3469 if (rxd->rx_m != NULL) { 3470 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3471 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3472 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3473 rxd->rx_dmamap); 3474 m_freem(rxd->rx_m); 3475 rxd->rx_m = NULL; 3476 } 3477 } 3478 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3479 txd = &sc->alc_cdata.alc_txdesc[i]; 3480 if (txd->tx_m != NULL) { 3481 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3482 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3483 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3484 txd->tx_dmamap); 3485 m_freem(txd->tx_m); 3486 txd->tx_m = NULL; 3487 } 3488 } 3489 } 3490 3491 static void 3492 alc_stop_mac(struct alc_softc *sc) 3493 { 3494 uint32_t reg; 3495 int i; 3496 3497 ALC_LOCK_ASSERT(sc); 3498 3499 /* Disable Rx/Tx MAC. */ 3500 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3501 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3502 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3503 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3504 } 3505 for (i = ALC_TIMEOUT; i > 0; i--) { 3506 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3507 if (reg == 0) 3508 break; 3509 DELAY(10); 3510 } 3511 if (i == 0) 3512 device_printf(sc->alc_dev, 3513 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3514 } 3515 3516 static void 3517 alc_start_queue(struct alc_softc *sc) 3518 { 3519 uint32_t qcfg[] = { 3520 0, 3521 RXQ_CFG_QUEUE0_ENB, 3522 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3523 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3524 RXQ_CFG_ENB 3525 }; 3526 uint32_t cfg; 3527 3528 ALC_LOCK_ASSERT(sc); 3529 3530 /* Enable RxQ. */ 3531 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3532 cfg &= ~RXQ_CFG_ENB; 3533 cfg |= qcfg[1]; 3534 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3535 /* Enable TxQ. */ 3536 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3537 cfg |= TXQ_CFG_ENB; 3538 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3539 } 3540 3541 static void 3542 alc_stop_queue(struct alc_softc *sc) 3543 { 3544 uint32_t reg; 3545 int i; 3546 3547 ALC_LOCK_ASSERT(sc); 3548 3549 /* Disable RxQ. */ 3550 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3551 if ((reg & RXQ_CFG_ENB) != 0) { 3552 reg &= ~RXQ_CFG_ENB; 3553 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3554 } 3555 /* Disable TxQ. */ 3556 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3557 if ((reg & TXQ_CFG_ENB) != 0) { 3558 reg &= ~TXQ_CFG_ENB; 3559 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3560 } 3561 for (i = ALC_TIMEOUT; i > 0; i--) { 3562 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3563 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3564 break; 3565 DELAY(10); 3566 } 3567 if (i == 0) 3568 device_printf(sc->alc_dev, 3569 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3570 } 3571 3572 static void 3573 alc_init_tx_ring(struct alc_softc *sc) 3574 { 3575 struct alc_ring_data *rd; 3576 struct alc_txdesc *txd; 3577 int i; 3578 3579 ALC_LOCK_ASSERT(sc); 3580 3581 sc->alc_cdata.alc_tx_prod = 0; 3582 sc->alc_cdata.alc_tx_cons = 0; 3583 sc->alc_cdata.alc_tx_cnt = 0; 3584 3585 rd = &sc->alc_rdata; 3586 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3587 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3588 txd = &sc->alc_cdata.alc_txdesc[i]; 3589 txd->tx_m = NULL; 3590 } 3591 3592 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3593 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3594 } 3595 3596 static int 3597 alc_init_rx_ring(struct alc_softc *sc) 3598 { 3599 struct alc_ring_data *rd; 3600 struct alc_rxdesc *rxd; 3601 int i; 3602 3603 ALC_LOCK_ASSERT(sc); 3604 3605 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3606 sc->alc_morework = 0; 3607 rd = &sc->alc_rdata; 3608 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3609 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3610 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3611 rxd->rx_m = NULL; 3612 rxd->rx_desc = &rd->alc_rx_ring[i]; 3613 if (alc_newbuf(sc, rxd) != 0) 3614 return (ENOBUFS); 3615 } 3616 3617 /* 3618 * Since controller does not update Rx descriptors, driver 3619 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3620 * is enough to ensure coherence. 3621 */ 3622 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3623 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3624 /* Let controller know availability of new Rx buffers. */ 3625 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3626 3627 return (0); 3628 } 3629 3630 static void 3631 alc_init_rr_ring(struct alc_softc *sc) 3632 { 3633 struct alc_ring_data *rd; 3634 3635 ALC_LOCK_ASSERT(sc); 3636 3637 sc->alc_cdata.alc_rr_cons = 0; 3638 ALC_RXCHAIN_RESET(sc); 3639 3640 rd = &sc->alc_rdata; 3641 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3642 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3643 sc->alc_cdata.alc_rr_ring_map, 3644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3645 } 3646 3647 static void 3648 alc_init_cmb(struct alc_softc *sc) 3649 { 3650 struct alc_ring_data *rd; 3651 3652 ALC_LOCK_ASSERT(sc); 3653 3654 rd = &sc->alc_rdata; 3655 bzero(rd->alc_cmb, ALC_CMB_SZ); 3656 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3658 } 3659 3660 static void 3661 alc_init_smb(struct alc_softc *sc) 3662 { 3663 struct alc_ring_data *rd; 3664 3665 ALC_LOCK_ASSERT(sc); 3666 3667 rd = &sc->alc_rdata; 3668 bzero(rd->alc_smb, ALC_SMB_SZ); 3669 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3670 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3671 } 3672 3673 static void 3674 alc_rxvlan(struct alc_softc *sc) 3675 { 3676 struct ifnet *ifp; 3677 uint32_t reg; 3678 3679 ALC_LOCK_ASSERT(sc); 3680 3681 ifp = sc->alc_ifp; 3682 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3683 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3684 reg |= MAC_CFG_VLAN_TAG_STRIP; 3685 else 3686 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3687 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3688 } 3689 3690 static void 3691 alc_rxfilter(struct alc_softc *sc) 3692 { 3693 struct ifnet *ifp; 3694 struct ifmultiaddr *ifma; 3695 uint32_t crc; 3696 uint32_t mchash[2]; 3697 uint32_t rxcfg; 3698 3699 ALC_LOCK_ASSERT(sc); 3700 3701 ifp = sc->alc_ifp; 3702 3703 bzero(mchash, sizeof(mchash)); 3704 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3705 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3706 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3707 rxcfg |= MAC_CFG_BCAST; 3708 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3709 if ((ifp->if_flags & IFF_PROMISC) != 0) 3710 rxcfg |= MAC_CFG_PROMISC; 3711 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3712 rxcfg |= MAC_CFG_ALLMULTI; 3713 mchash[0] = 0xFFFFFFFF; 3714 mchash[1] = 0xFFFFFFFF; 3715 goto chipit; 3716 } 3717 3718 if_maddr_rlock(ifp); 3719 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3720 if (ifma->ifma_addr->sa_family != AF_LINK) 3721 continue; 3722 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3723 ifma->ifma_addr), ETHER_ADDR_LEN); 3724 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3725 } 3726 if_maddr_runlock(ifp); 3727 3728 chipit: 3729 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3730 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3731 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3732 } 3733 3734 static int 3735 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3736 { 3737 int error, value; 3738 3739 if (arg1 == NULL) 3740 return (EINVAL); 3741 value = *(int *)arg1; 3742 error = sysctl_handle_int(oidp, &value, 0, req); 3743 if (error || req->newptr == NULL) 3744 return (error); 3745 if (value < low || value > high) 3746 return (EINVAL); 3747 *(int *)arg1 = value; 3748 3749 return (0); 3750 } 3751 3752 static int 3753 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3754 { 3755 return (sysctl_int_range(oidp, arg1, arg2, req, 3756 ALC_PROC_MIN, ALC_PROC_MAX)); 3757 } 3758 3759 static int 3760 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3761 { 3762 3763 return (sysctl_int_range(oidp, arg1, arg2, req, 3764 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3765 } 3766