1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 static int msix_disable = 0; 95 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98 /* 99 * Devices supported by this driver. 100 */ 101 static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 115 "Atheros AR8161 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 117 "Atheros AR8162 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 119 "Atheros AR8171 PCIe Gigabit Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 121 "Atheros AR8172 PCIe Fast Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 123 "Killer E2200 Gigabit Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 125 "Killer E2400 Gigabit Ethernet" }, 126 { 0, 0, 0, NULL} 127 }; 128 129 static void alc_aspm(struct alc_softc *, int, int); 130 static void alc_aspm_813x(struct alc_softc *, int); 131 static void alc_aspm_816x(struct alc_softc *, int); 132 static int alc_attach(device_t); 133 static int alc_check_boundary(struct alc_softc *); 134 static void alc_config_msi(struct alc_softc *); 135 static int alc_detach(device_t); 136 static void alc_disable_l0s_l1(struct alc_softc *); 137 static int alc_dma_alloc(struct alc_softc *); 138 static void alc_dma_free(struct alc_softc *); 139 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 140 static void alc_dsp_fixup(struct alc_softc *, int); 141 static int alc_encap(struct alc_softc *, struct mbuf **); 142 static struct alc_ident * 143 alc_find_ident(device_t); 144 #ifndef __NO_STRICT_ALIGNMENT 145 static struct mbuf * 146 alc_fixup_rx(struct ifnet *, struct mbuf *); 147 #endif 148 static void alc_get_macaddr(struct alc_softc *); 149 static void alc_get_macaddr_813x(struct alc_softc *); 150 static void alc_get_macaddr_816x(struct alc_softc *); 151 static void alc_get_macaddr_par(struct alc_softc *); 152 static void alc_init(void *); 153 static void alc_init_cmb(struct alc_softc *); 154 static void alc_init_locked(struct alc_softc *); 155 static void alc_init_rr_ring(struct alc_softc *); 156 static int alc_init_rx_ring(struct alc_softc *); 157 static void alc_init_smb(struct alc_softc *); 158 static void alc_init_tx_ring(struct alc_softc *); 159 static void alc_int_task(void *, int); 160 static int alc_intr(void *); 161 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 162 static void alc_mac_config(struct alc_softc *); 163 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 164 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 165 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 166 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 167 static int alc_miibus_readreg(device_t, int, int); 168 static void alc_miibus_statchg(device_t); 169 static int alc_miibus_writereg(device_t, int, int, int); 170 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 171 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 172 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 173 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 174 static int alc_mediachange(struct ifnet *); 175 static int alc_mediachange_locked(struct alc_softc *); 176 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 177 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 178 static void alc_osc_reset(struct alc_softc *); 179 static void alc_phy_down(struct alc_softc *); 180 static void alc_phy_reset(struct alc_softc *); 181 static void alc_phy_reset_813x(struct alc_softc *); 182 static void alc_phy_reset_816x(struct alc_softc *); 183 static int alc_probe(device_t); 184 static void alc_reset(struct alc_softc *); 185 static int alc_resume(device_t); 186 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 187 static int alc_rxintr(struct alc_softc *, int); 188 static void alc_rxfilter(struct alc_softc *); 189 static void alc_rxvlan(struct alc_softc *); 190 static void alc_setlinkspeed(struct alc_softc *); 191 static void alc_setwol(struct alc_softc *); 192 static void alc_setwol_813x(struct alc_softc *); 193 static void alc_setwol_816x(struct alc_softc *); 194 static int alc_shutdown(device_t); 195 static void alc_start(struct ifnet *); 196 static void alc_start_locked(struct ifnet *); 197 static void alc_start_queue(struct alc_softc *); 198 static void alc_stats_clear(struct alc_softc *); 199 static void alc_stats_update(struct alc_softc *); 200 static void alc_stop(struct alc_softc *); 201 static void alc_stop_mac(struct alc_softc *); 202 static void alc_stop_queue(struct alc_softc *); 203 static int alc_suspend(device_t); 204 static void alc_sysctl_node(struct alc_softc *); 205 static void alc_tick(void *); 206 static void alc_txeof(struct alc_softc *); 207 static void alc_watchdog(struct alc_softc *); 208 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 209 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 210 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 211 212 static device_method_t alc_methods[] = { 213 /* Device interface. */ 214 DEVMETHOD(device_probe, alc_probe), 215 DEVMETHOD(device_attach, alc_attach), 216 DEVMETHOD(device_detach, alc_detach), 217 DEVMETHOD(device_shutdown, alc_shutdown), 218 DEVMETHOD(device_suspend, alc_suspend), 219 DEVMETHOD(device_resume, alc_resume), 220 221 /* MII interface. */ 222 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 223 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 224 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 225 226 { NULL, NULL } 227 }; 228 229 static driver_t alc_driver = { 230 "alc", 231 alc_methods, 232 sizeof(struct alc_softc) 233 }; 234 235 static devclass_t alc_devclass; 236 237 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 238 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 239 240 static struct resource_spec alc_res_spec_mem[] = { 241 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 242 { -1, 0, 0 } 243 }; 244 245 static struct resource_spec alc_irq_spec_legacy[] = { 246 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 247 { -1, 0, 0 } 248 }; 249 250 static struct resource_spec alc_irq_spec_msi[] = { 251 { SYS_RES_IRQ, 1, RF_ACTIVE }, 252 { -1, 0, 0 } 253 }; 254 255 static struct resource_spec alc_irq_spec_msix[] = { 256 { SYS_RES_IRQ, 1, RF_ACTIVE }, 257 { -1, 0, 0 } 258 }; 259 260 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 261 262 static int 263 alc_miibus_readreg(device_t dev, int phy, int reg) 264 { 265 struct alc_softc *sc; 266 int v; 267 268 sc = device_get_softc(dev); 269 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 270 v = alc_mii_readreg_816x(sc, phy, reg); 271 else 272 v = alc_mii_readreg_813x(sc, phy, reg); 273 return (v); 274 } 275 276 static uint32_t 277 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 278 { 279 uint32_t v; 280 int i; 281 282 /* 283 * For AR8132 fast ethernet controller, do not report 1000baseT 284 * capability to mii(4). Even though AR8132 uses the same 285 * model/revision number of F1 gigabit PHY, the PHY has no 286 * ability to establish 1000baseT link. 287 */ 288 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 289 reg == MII_EXTSR) 290 return (0); 291 292 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 293 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 294 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 295 DELAY(5); 296 v = CSR_READ_4(sc, ALC_MDIO); 297 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 298 break; 299 } 300 301 if (i == 0) { 302 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 303 return (0); 304 } 305 306 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 307 } 308 309 static uint32_t 310 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 311 { 312 uint32_t clk, v; 313 int i; 314 315 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 316 clk = MDIO_CLK_25_128; 317 else 318 clk = MDIO_CLK_25_4; 319 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 320 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 321 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 322 DELAY(5); 323 v = CSR_READ_4(sc, ALC_MDIO); 324 if ((v & MDIO_OP_BUSY) == 0) 325 break; 326 } 327 328 if (i == 0) { 329 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 330 return (0); 331 } 332 333 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 334 } 335 336 static int 337 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 338 { 339 struct alc_softc *sc; 340 int v; 341 342 sc = device_get_softc(dev); 343 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 344 v = alc_mii_writereg_816x(sc, phy, reg, val); 345 else 346 v = alc_mii_writereg_813x(sc, phy, reg, val); 347 return (v); 348 } 349 350 static uint32_t 351 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 352 { 353 uint32_t v; 354 int i; 355 356 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 357 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 358 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 359 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 360 DELAY(5); 361 v = CSR_READ_4(sc, ALC_MDIO); 362 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 363 break; 364 } 365 366 if (i == 0) 367 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 368 369 return (0); 370 } 371 372 static uint32_t 373 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 374 { 375 uint32_t clk, v; 376 int i; 377 378 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 379 clk = MDIO_CLK_25_128; 380 else 381 clk = MDIO_CLK_25_4; 382 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 383 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 384 MDIO_SUP_PREAMBLE | clk); 385 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 386 DELAY(5); 387 v = CSR_READ_4(sc, ALC_MDIO); 388 if ((v & MDIO_OP_BUSY) == 0) 389 break; 390 } 391 392 if (i == 0) 393 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 394 395 return (0); 396 } 397 398 static void 399 alc_miibus_statchg(device_t dev) 400 { 401 struct alc_softc *sc; 402 struct mii_data *mii; 403 struct ifnet *ifp; 404 uint32_t reg; 405 406 sc = device_get_softc(dev); 407 408 mii = device_get_softc(sc->alc_miibus); 409 ifp = sc->alc_ifp; 410 if (mii == NULL || ifp == NULL || 411 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 412 return; 413 414 sc->alc_flags &= ~ALC_FLAG_LINK; 415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 416 (IFM_ACTIVE | IFM_AVALID)) { 417 switch (IFM_SUBTYPE(mii->mii_media_active)) { 418 case IFM_10_T: 419 case IFM_100_TX: 420 sc->alc_flags |= ALC_FLAG_LINK; 421 break; 422 case IFM_1000_T: 423 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 424 sc->alc_flags |= ALC_FLAG_LINK; 425 break; 426 default: 427 break; 428 } 429 } 430 /* Stop Rx/Tx MACs. */ 431 alc_stop_mac(sc); 432 433 /* Program MACs with resolved speed/duplex/flow-control. */ 434 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 435 alc_start_queue(sc); 436 alc_mac_config(sc); 437 /* Re-enable Tx/Rx MACs. */ 438 reg = CSR_READ_4(sc, ALC_MAC_CFG); 439 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 440 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 441 } 442 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 443 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 444 } 445 446 static uint32_t 447 alc_miidbg_readreg(struct alc_softc *sc, int reg) 448 { 449 450 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 451 reg); 452 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 453 ALC_MII_DBG_DATA)); 454 } 455 456 static uint32_t 457 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 458 { 459 460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 461 reg); 462 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA, val)); 464 } 465 466 static uint32_t 467 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 468 { 469 uint32_t clk, v; 470 int i; 471 472 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 473 EXT_MDIO_DEVADDR(devaddr)); 474 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 475 clk = MDIO_CLK_25_128; 476 else 477 clk = MDIO_CLK_25_4; 478 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 479 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 480 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 481 DELAY(5); 482 v = CSR_READ_4(sc, ALC_MDIO); 483 if ((v & MDIO_OP_BUSY) == 0) 484 break; 485 } 486 487 if (i == 0) { 488 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 489 devaddr, reg); 490 return (0); 491 } 492 493 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 494 } 495 496 static uint32_t 497 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 498 { 499 uint32_t clk, v; 500 int i; 501 502 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 503 EXT_MDIO_DEVADDR(devaddr)); 504 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 505 clk = MDIO_CLK_25_128; 506 else 507 clk = MDIO_CLK_25_4; 508 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 509 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 510 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 511 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 512 DELAY(5); 513 v = CSR_READ_4(sc, ALC_MDIO); 514 if ((v & MDIO_OP_BUSY) == 0) 515 break; 516 } 517 518 if (i == 0) 519 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 520 devaddr, reg); 521 522 return (0); 523 } 524 525 static void 526 alc_dsp_fixup(struct alc_softc *sc, int media) 527 { 528 uint16_t agc, len, val; 529 530 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 531 return; 532 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 533 return; 534 535 /* 536 * Vendor PHY magic. 537 * 1000BT/AZ, wrong cable length 538 */ 539 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 540 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 541 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 542 EXT_CLDCTL6_CAB_LEN_MASK; 543 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 544 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 545 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 546 agc > DBG_AGC_LONG1G_LIMT) || 547 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 548 agc > DBG_AGC_LONG1G_LIMT)) { 549 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 550 DBG_AZ_ANADECT_LONG); 551 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 552 MII_EXT_ANEG_AFE); 553 val |= ANEG_AFEE_10BT_100M_TH; 554 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 555 val); 556 } else { 557 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 558 DBG_AZ_ANADECT_DEFAULT); 559 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 560 MII_EXT_ANEG_AFE); 561 val &= ~ANEG_AFEE_10BT_100M_TH; 562 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 563 val); 564 } 565 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 566 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 567 if (media == IFM_1000_T) { 568 /* 569 * Giga link threshold, raise the tolerance of 570 * noise 50%. 571 */ 572 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 573 val &= ~DBG_MSE20DB_TH_MASK; 574 val |= (DBG_MSE20DB_TH_HI << 575 DBG_MSE20DB_TH_SHIFT); 576 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 577 } else if (media == IFM_100_TX) 578 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 579 DBG_MSE16DB_UP); 580 } 581 } else { 582 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 583 val &= ~ANEG_AFEE_10BT_100M_TH; 584 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 585 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 586 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 587 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 588 DBG_MSE16DB_DOWN); 589 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 590 val &= ~DBG_MSE20DB_TH_MASK; 591 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 592 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 593 } 594 } 595 } 596 597 static void 598 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 599 { 600 struct alc_softc *sc; 601 struct mii_data *mii; 602 603 sc = ifp->if_softc; 604 ALC_LOCK(sc); 605 if ((ifp->if_flags & IFF_UP) == 0) { 606 ALC_UNLOCK(sc); 607 return; 608 } 609 mii = device_get_softc(sc->alc_miibus); 610 611 mii_pollstat(mii); 612 ifmr->ifm_status = mii->mii_media_status; 613 ifmr->ifm_active = mii->mii_media_active; 614 ALC_UNLOCK(sc); 615 } 616 617 static int 618 alc_mediachange(struct ifnet *ifp) 619 { 620 struct alc_softc *sc; 621 int error; 622 623 sc = ifp->if_softc; 624 ALC_LOCK(sc); 625 error = alc_mediachange_locked(sc); 626 ALC_UNLOCK(sc); 627 628 return (error); 629 } 630 631 static int 632 alc_mediachange_locked(struct alc_softc *sc) 633 { 634 struct mii_data *mii; 635 struct mii_softc *miisc; 636 int error; 637 638 ALC_LOCK_ASSERT(sc); 639 640 mii = device_get_softc(sc->alc_miibus); 641 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 642 PHY_RESET(miisc); 643 error = mii_mediachg(mii); 644 645 return (error); 646 } 647 648 static struct alc_ident * 649 alc_find_ident(device_t dev) 650 { 651 struct alc_ident *ident; 652 uint16_t vendor, devid; 653 654 vendor = pci_get_vendor(dev); 655 devid = pci_get_device(dev); 656 for (ident = alc_ident_table; ident->name != NULL; ident++) { 657 if (vendor == ident->vendorid && devid == ident->deviceid) 658 return (ident); 659 } 660 661 return (NULL); 662 } 663 664 static int 665 alc_probe(device_t dev) 666 { 667 struct alc_ident *ident; 668 669 ident = alc_find_ident(dev); 670 if (ident != NULL) { 671 device_set_desc(dev, ident->name); 672 return (BUS_PROBE_DEFAULT); 673 } 674 675 return (ENXIO); 676 } 677 678 static void 679 alc_get_macaddr(struct alc_softc *sc) 680 { 681 682 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 683 alc_get_macaddr_816x(sc); 684 else 685 alc_get_macaddr_813x(sc); 686 } 687 688 static void 689 alc_get_macaddr_813x(struct alc_softc *sc) 690 { 691 uint32_t opt; 692 uint16_t val; 693 int eeprom, i; 694 695 eeprom = 0; 696 opt = CSR_READ_4(sc, ALC_OPT_CFG); 697 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 698 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 699 /* 700 * EEPROM found, let TWSI reload EEPROM configuration. 701 * This will set ethernet address of controller. 702 */ 703 eeprom++; 704 switch (sc->alc_ident->deviceid) { 705 case DEVICEID_ATHEROS_AR8131: 706 case DEVICEID_ATHEROS_AR8132: 707 if ((opt & OPT_CFG_CLK_ENB) == 0) { 708 opt |= OPT_CFG_CLK_ENB; 709 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 710 CSR_READ_4(sc, ALC_OPT_CFG); 711 DELAY(1000); 712 } 713 break; 714 case DEVICEID_ATHEROS_AR8151: 715 case DEVICEID_ATHEROS_AR8151_V2: 716 case DEVICEID_ATHEROS_AR8152_B: 717 case DEVICEID_ATHEROS_AR8152_B2: 718 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 719 ALC_MII_DBG_ADDR, 0x00); 720 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 721 ALC_MII_DBG_DATA); 722 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 723 ALC_MII_DBG_DATA, val & 0xFF7F); 724 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 725 ALC_MII_DBG_ADDR, 0x3B); 726 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_DATA); 728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA, val | 0x0008); 730 DELAY(20); 731 break; 732 } 733 734 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 735 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 736 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 737 CSR_READ_4(sc, ALC_WOL_CFG); 738 739 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 740 TWSI_CFG_SW_LD_START); 741 for (i = 100; i > 0; i--) { 742 DELAY(1000); 743 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 744 TWSI_CFG_SW_LD_START) == 0) 745 break; 746 } 747 if (i == 0) 748 device_printf(sc->alc_dev, 749 "reloading EEPROM timeout!\n"); 750 } else { 751 if (bootverbose) 752 device_printf(sc->alc_dev, "EEPROM not found!\n"); 753 } 754 if (eeprom != 0) { 755 switch (sc->alc_ident->deviceid) { 756 case DEVICEID_ATHEROS_AR8131: 757 case DEVICEID_ATHEROS_AR8132: 758 if ((opt & OPT_CFG_CLK_ENB) != 0) { 759 opt &= ~OPT_CFG_CLK_ENB; 760 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 761 CSR_READ_4(sc, ALC_OPT_CFG); 762 DELAY(1000); 763 } 764 break; 765 case DEVICEID_ATHEROS_AR8151: 766 case DEVICEID_ATHEROS_AR8151_V2: 767 case DEVICEID_ATHEROS_AR8152_B: 768 case DEVICEID_ATHEROS_AR8152_B2: 769 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 770 ALC_MII_DBG_ADDR, 0x00); 771 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 772 ALC_MII_DBG_DATA); 773 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 774 ALC_MII_DBG_DATA, val | 0x0080); 775 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 776 ALC_MII_DBG_ADDR, 0x3B); 777 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_DATA); 779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA, val & 0xFFF7); 781 DELAY(20); 782 break; 783 } 784 } 785 786 alc_get_macaddr_par(sc); 787 } 788 789 static void 790 alc_get_macaddr_816x(struct alc_softc *sc) 791 { 792 uint32_t reg; 793 int i, reloaded; 794 795 reloaded = 0; 796 /* Try to reload station address via TWSI. */ 797 for (i = 100; i > 0; i--) { 798 reg = CSR_READ_4(sc, ALC_SLD); 799 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 800 break; 801 DELAY(1000); 802 } 803 if (i != 0) { 804 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 805 for (i = 100; i > 0; i--) { 806 DELAY(1000); 807 reg = CSR_READ_4(sc, ALC_SLD); 808 if ((reg & SLD_START) == 0) 809 break; 810 } 811 if (i != 0) 812 reloaded++; 813 else if (bootverbose) 814 device_printf(sc->alc_dev, 815 "reloading station address via TWSI timed out!\n"); 816 } 817 818 /* Try to reload station address from EEPROM or FLASH. */ 819 if (reloaded == 0) { 820 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 821 if ((reg & (EEPROM_LD_EEPROM_EXIST | 822 EEPROM_LD_FLASH_EXIST)) != 0) { 823 for (i = 100; i > 0; i--) { 824 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 825 if ((reg & (EEPROM_LD_PROGRESS | 826 EEPROM_LD_START)) == 0) 827 break; 828 DELAY(1000); 829 } 830 if (i != 0) { 831 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 832 EEPROM_LD_START); 833 for (i = 100; i > 0; i--) { 834 DELAY(1000); 835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 836 if ((reg & EEPROM_LD_START) == 0) 837 break; 838 } 839 } else if (bootverbose) 840 device_printf(sc->alc_dev, 841 "reloading EEPROM/FLASH timed out!\n"); 842 } 843 } 844 845 alc_get_macaddr_par(sc); 846 } 847 848 static void 849 alc_get_macaddr_par(struct alc_softc *sc) 850 { 851 uint32_t ea[2]; 852 853 ea[0] = CSR_READ_4(sc, ALC_PAR0); 854 ea[1] = CSR_READ_4(sc, ALC_PAR1); 855 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 856 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 857 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 858 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 859 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 860 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 861 } 862 863 static void 864 alc_disable_l0s_l1(struct alc_softc *sc) 865 { 866 uint32_t pmcfg; 867 868 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 869 /* Another magic from vendor. */ 870 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 871 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 872 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 873 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 874 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 875 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 876 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 877 } 878 } 879 880 static void 881 alc_phy_reset(struct alc_softc *sc) 882 { 883 884 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 885 alc_phy_reset_816x(sc); 886 else 887 alc_phy_reset_813x(sc); 888 } 889 890 static void 891 alc_phy_reset_813x(struct alc_softc *sc) 892 { 893 uint16_t data; 894 895 /* Reset magic from Linux. */ 896 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 897 CSR_READ_2(sc, ALC_GPHY_CFG); 898 DELAY(10 * 1000); 899 900 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 901 GPHY_CFG_SEL_ANA_RESET); 902 CSR_READ_2(sc, ALC_GPHY_CFG); 903 DELAY(10 * 1000); 904 905 /* DSP fixup, Vendor magic. */ 906 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 907 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 908 ALC_MII_DBG_ADDR, 0x000A); 909 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 910 ALC_MII_DBG_DATA); 911 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 912 ALC_MII_DBG_DATA, data & 0xDFFF); 913 } 914 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 915 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 916 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 917 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, 0x003B); 920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA); 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA, data & 0xFFF7); 924 DELAY(20 * 1000); 925 } 926 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 927 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 928 ALC_MII_DBG_ADDR, 0x0029); 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_DATA, 0x929D); 931 } 932 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 933 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 934 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 935 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 936 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 937 ALC_MII_DBG_ADDR, 0x0029); 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_DATA, 0xB6DD); 940 } 941 942 /* Load DSP codes, vendor magic. */ 943 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 944 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 945 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 946 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_DATA, data); 949 950 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 951 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 952 ANA_SERDES_EN_LCKDT; 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_DATA, data); 957 958 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 959 ANA_LONG_CABLE_TH_100_MASK) | 960 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 961 ANA_SHORT_CABLE_TH_100_SHIFT) | 962 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 966 ALC_MII_DBG_DATA, data); 967 968 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 969 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 970 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 971 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 972 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 973 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_DATA, data); 976 977 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 978 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 979 ANA_OEN_125M; 980 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 981 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_DATA, data); 984 DELAY(1000); 985 986 /* Disable hibernation. */ 987 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 988 0x0029); 989 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 990 ALC_MII_DBG_DATA); 991 data &= ~0x8000; 992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 993 data); 994 995 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 996 0x000B); 997 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 998 ALC_MII_DBG_DATA); 999 data &= ~0x8000; 1000 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1001 data); 1002 } 1003 1004 static void 1005 alc_phy_reset_816x(struct alc_softc *sc) 1006 { 1007 uint32_t val; 1008 1009 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1010 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1011 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1012 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1013 val |= GPHY_CFG_SEL_ANA_RESET; 1014 #ifdef notyet 1015 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1016 #else 1017 /* Disable PHY hibernation. */ 1018 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1019 #endif 1020 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1021 DELAY(10); 1022 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1023 DELAY(800); 1024 1025 /* Vendor PHY magic. */ 1026 #ifdef notyet 1027 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1028 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1029 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1030 EXT_VDRVBIAS_DEFAULT); 1031 #else 1032 /* Disable PHY hibernation. */ 1033 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1034 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1035 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1036 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1037 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1038 #endif 1039 1040 /* XXX Disable EEE. */ 1041 val = CSR_READ_4(sc, ALC_LPI_CTL); 1042 val &= ~LPI_CTL_ENB; 1043 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1044 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1045 1046 /* PHY power saving. */ 1047 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1048 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1049 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1050 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1051 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1052 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1053 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1054 1055 /* RTL8139C, 120m issue. */ 1056 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1057 ANEG_NLP78_120M_DEFAULT); 1058 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1059 ANEG_S3DIG10_DEFAULT); 1060 1061 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1062 /* Turn off half amplitude. */ 1063 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1064 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1065 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1066 /* Turn off Green feature. */ 1067 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1068 val |= DBG_GREENCFG2_BP_GREEN; 1069 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1070 /* Turn off half bias. */ 1071 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1072 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1073 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1074 } 1075 } 1076 1077 static void 1078 alc_phy_down(struct alc_softc *sc) 1079 { 1080 uint32_t gphy; 1081 1082 switch (sc->alc_ident->deviceid) { 1083 case DEVICEID_ATHEROS_AR8161: 1084 case DEVICEID_ATHEROS_E2200: 1085 case DEVICEID_ATHEROS_E2400: 1086 case DEVICEID_ATHEROS_AR8162: 1087 case DEVICEID_ATHEROS_AR8171: 1088 case DEVICEID_ATHEROS_AR8172: 1089 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1090 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1091 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1092 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1093 GPHY_CFG_SEL_ANA_RESET; 1094 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1095 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1096 break; 1097 case DEVICEID_ATHEROS_AR8151: 1098 case DEVICEID_ATHEROS_AR8151_V2: 1099 case DEVICEID_ATHEROS_AR8152_B: 1100 case DEVICEID_ATHEROS_AR8152_B2: 1101 /* 1102 * GPHY power down caused more problems on AR8151 v2.0. 1103 * When driver is reloaded after GPHY power down, 1104 * accesses to PHY/MAC registers hung the system. Only 1105 * cold boot recovered from it. I'm not sure whether 1106 * AR8151 v1.0 also requires this one though. I don't 1107 * have AR8151 v1.0 controller in hand. 1108 * The only option left is to isolate the PHY and 1109 * initiates power down the PHY which in turn saves 1110 * more power when driver is unloaded. 1111 */ 1112 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1113 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1114 break; 1115 default: 1116 /* Force PHY down. */ 1117 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1118 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1119 GPHY_CFG_PWDOWN_HW); 1120 DELAY(1000); 1121 break; 1122 } 1123 } 1124 1125 static void 1126 alc_aspm(struct alc_softc *sc, int init, int media) 1127 { 1128 1129 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1130 alc_aspm_816x(sc, init); 1131 else 1132 alc_aspm_813x(sc, media); 1133 } 1134 1135 static void 1136 alc_aspm_813x(struct alc_softc *sc, int media) 1137 { 1138 uint32_t pmcfg; 1139 uint16_t linkcfg; 1140 1141 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1142 return; 1143 1144 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1145 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1146 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1147 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1148 PCIER_LINK_CTL); 1149 else 1150 linkcfg = 0; 1151 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1152 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1153 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1154 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1155 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1156 1157 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1158 /* Disable extended sync except AR8152 B v1.0 */ 1159 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1160 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1161 sc->alc_rev == ATHEROS_AR8152_B_V10) 1162 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1163 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1164 linkcfg); 1165 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1166 PM_CFG_HOTRST); 1167 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1168 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1169 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1170 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1171 PM_CFG_PM_REQ_TIMER_SHIFT); 1172 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1173 } 1174 1175 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1176 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1177 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1178 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1179 pmcfg |= PM_CFG_ASPM_L1_ENB; 1180 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1181 if (sc->alc_ident->deviceid == 1182 DEVICEID_ATHEROS_AR8152_B) 1183 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1184 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1185 PM_CFG_SERDES_PLL_L1_ENB | 1186 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1187 pmcfg |= PM_CFG_CLK_SWH_L1; 1188 if (media == IFM_100_TX || media == IFM_1000_T) { 1189 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1190 switch (sc->alc_ident->deviceid) { 1191 case DEVICEID_ATHEROS_AR8152_B: 1192 pmcfg |= (7 << 1193 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1194 break; 1195 case DEVICEID_ATHEROS_AR8152_B2: 1196 case DEVICEID_ATHEROS_AR8151_V2: 1197 pmcfg |= (4 << 1198 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1199 break; 1200 default: 1201 pmcfg |= (15 << 1202 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1203 break; 1204 } 1205 } 1206 } else { 1207 pmcfg |= PM_CFG_SERDES_L1_ENB | 1208 PM_CFG_SERDES_PLL_L1_ENB | 1209 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1210 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1211 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1212 } 1213 } else { 1214 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1215 PM_CFG_SERDES_PLL_L1_ENB); 1216 pmcfg |= PM_CFG_CLK_SWH_L1; 1217 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1218 pmcfg |= PM_CFG_ASPM_L1_ENB; 1219 } 1220 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1221 } 1222 1223 static void 1224 alc_aspm_816x(struct alc_softc *sc, int init) 1225 { 1226 uint32_t pmcfg; 1227 1228 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1229 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1230 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1231 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1232 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1233 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1234 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1235 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1236 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1237 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1238 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1239 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1240 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1241 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1242 (sc->alc_rev & 0x01) != 0) 1243 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1244 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1245 /* Link up, enable both L0s, L1s. */ 1246 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1247 PM_CFG_MAC_ASPM_CHK; 1248 } else { 1249 if (init != 0) 1250 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1251 PM_CFG_MAC_ASPM_CHK; 1252 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1253 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1254 } 1255 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1256 } 1257 1258 static void 1259 alc_init_pcie(struct alc_softc *sc) 1260 { 1261 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1262 uint32_t cap, ctl, val; 1263 int state; 1264 1265 /* Clear data link and flow-control protocol error. */ 1266 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1267 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1268 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1269 1270 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1271 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1272 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1273 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1274 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1275 PCIE_PHYMISC_FORCE_RCV_DET); 1276 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1277 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1278 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1279 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1280 PCIE_PHYMISC2_SERDES_TH_MASK); 1281 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1282 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1283 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1284 } 1285 /* Disable ASPM L0S and L1. */ 1286 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1287 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1288 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1289 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1290 sc->alc_rcb = DMA_CFG_RCB_128; 1291 if (bootverbose) 1292 device_printf(sc->alc_dev, "RCB %u bytes\n", 1293 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1294 state = ctl & PCIEM_LINK_CTL_ASPMC; 1295 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1296 sc->alc_flags |= ALC_FLAG_L0S; 1297 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1298 sc->alc_flags |= ALC_FLAG_L1S; 1299 if (bootverbose) 1300 device_printf(sc->alc_dev, "ASPM %s %s\n", 1301 aspm_state[state], 1302 state == 0 ? "disabled" : "enabled"); 1303 alc_disable_l0s_l1(sc); 1304 } else { 1305 if (bootverbose) 1306 device_printf(sc->alc_dev, 1307 "no ASPM support\n"); 1308 } 1309 } else { 1310 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1311 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1312 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1313 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1314 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1315 (sc->alc_rev & 0x01) != 0) { 1316 if ((val & MASTER_WAKEN_25M) == 0 || 1317 (val & MASTER_CLK_SEL_DIS) == 0) { 1318 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1319 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1320 } 1321 } else { 1322 if ((val & MASTER_WAKEN_25M) == 0 || 1323 (val & MASTER_CLK_SEL_DIS) != 0) { 1324 val |= MASTER_WAKEN_25M; 1325 val &= ~MASTER_CLK_SEL_DIS; 1326 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1327 } 1328 } 1329 } 1330 alc_aspm(sc, 1, IFM_UNKNOWN); 1331 } 1332 1333 static void 1334 alc_config_msi(struct alc_softc *sc) 1335 { 1336 uint32_t ctl, mod; 1337 1338 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1339 /* 1340 * It seems interrupt moderation is controlled by 1341 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1342 * Driver uses RX interrupt moderation parameter to 1343 * program ALC_MSI_RETRANS_TIMER register. 1344 */ 1345 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1346 ctl &= ~MSI_RETRANS_TIMER_MASK; 1347 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1348 mod = ALC_USECS(sc->alc_int_rx_mod); 1349 if (mod == 0) 1350 mod = 1; 1351 ctl |= mod; 1352 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1353 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1354 MSI_RETRANS_MASK_SEL_STD); 1355 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1356 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1357 MSI_RETRANS_MASK_SEL_LINE); 1358 else 1359 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1360 } 1361 } 1362 1363 static int 1364 alc_attach(device_t dev) 1365 { 1366 struct alc_softc *sc; 1367 struct ifnet *ifp; 1368 int base, error, i, msic, msixc; 1369 uint16_t burst; 1370 1371 error = 0; 1372 sc = device_get_softc(dev); 1373 sc->alc_dev = dev; 1374 sc->alc_rev = pci_get_revid(dev); 1375 1376 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1377 MTX_DEF); 1378 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1379 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1380 sc->alc_ident = alc_find_ident(dev); 1381 1382 /* Map the device. */ 1383 pci_enable_busmaster(dev); 1384 sc->alc_res_spec = alc_res_spec_mem; 1385 sc->alc_irq_spec = alc_irq_spec_legacy; 1386 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1387 if (error != 0) { 1388 device_printf(dev, "cannot allocate memory resources.\n"); 1389 goto fail; 1390 } 1391 1392 /* Set PHY address. */ 1393 sc->alc_phyaddr = ALC_PHY_ADDR; 1394 1395 /* 1396 * One odd thing is AR8132 uses the same PHY hardware(F1 1397 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1398 * the PHY supports 1000Mbps but that's not true. The PHY 1399 * used in AR8132 can't establish gigabit link even if it 1400 * shows the same PHY model/revision number of AR8131. 1401 */ 1402 switch (sc->alc_ident->deviceid) { 1403 case DEVICEID_ATHEROS_E2200: 1404 case DEVICEID_ATHEROS_E2400: 1405 sc->alc_flags |= ALC_FLAG_E2X00; 1406 /* FALLTHROUGH */ 1407 case DEVICEID_ATHEROS_AR8161: 1408 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1409 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1410 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1411 /* FALLTHROUGH */ 1412 case DEVICEID_ATHEROS_AR8171: 1413 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1414 break; 1415 case DEVICEID_ATHEROS_AR8162: 1416 case DEVICEID_ATHEROS_AR8172: 1417 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1418 break; 1419 case DEVICEID_ATHEROS_AR8152_B: 1420 case DEVICEID_ATHEROS_AR8152_B2: 1421 sc->alc_flags |= ALC_FLAG_APS; 1422 /* FALLTHROUGH */ 1423 case DEVICEID_ATHEROS_AR8132: 1424 sc->alc_flags |= ALC_FLAG_FASTETHER; 1425 break; 1426 case DEVICEID_ATHEROS_AR8151: 1427 case DEVICEID_ATHEROS_AR8151_V2: 1428 sc->alc_flags |= ALC_FLAG_APS; 1429 /* FALLTHROUGH */ 1430 default: 1431 break; 1432 } 1433 sc->alc_flags |= ALC_FLAG_JUMBO; 1434 1435 /* 1436 * It seems that AR813x/AR815x has silicon bug for SMB. In 1437 * addition, Atheros said that enabling SMB wouldn't improve 1438 * performance. However I think it's bad to access lots of 1439 * registers to extract MAC statistics. 1440 */ 1441 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1442 /* 1443 * Don't use Tx CMB. It is known to have silicon bug. 1444 */ 1445 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1446 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1447 MASTER_CHIP_REV_SHIFT; 1448 if (bootverbose) { 1449 device_printf(dev, "PCI device revision : 0x%04x\n", 1450 sc->alc_rev); 1451 device_printf(dev, "Chip id/revision : 0x%04x\n", 1452 sc->alc_chip_rev); 1453 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1454 device_printf(dev, "AR816x revision : 0x%x\n", 1455 AR816X_REV(sc->alc_rev)); 1456 } 1457 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1458 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1459 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1460 1461 /* Initialize DMA parameters. */ 1462 sc->alc_dma_rd_burst = 0; 1463 sc->alc_dma_wr_burst = 0; 1464 sc->alc_rcb = DMA_CFG_RCB_64; 1465 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1466 sc->alc_flags |= ALC_FLAG_PCIE; 1467 sc->alc_expcap = base; 1468 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1469 sc->alc_dma_rd_burst = 1470 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1471 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1472 if (bootverbose) { 1473 device_printf(dev, "Read request size : %u bytes.\n", 1474 alc_dma_burst[sc->alc_dma_rd_burst]); 1475 device_printf(dev, "TLP payload size : %u bytes.\n", 1476 alc_dma_burst[sc->alc_dma_wr_burst]); 1477 } 1478 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1479 sc->alc_dma_rd_burst = 3; 1480 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1481 sc->alc_dma_wr_burst = 3; 1482 /* 1483 * Force maximum payload size to 128 bytes for E2200/E2400. 1484 * Otherwise it triggers DMA write error. 1485 */ 1486 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1487 sc->alc_dma_wr_burst = 0; 1488 alc_init_pcie(sc); 1489 } 1490 1491 /* Reset PHY. */ 1492 alc_phy_reset(sc); 1493 1494 /* Reset the ethernet controller. */ 1495 alc_stop_mac(sc); 1496 alc_reset(sc); 1497 1498 /* Allocate IRQ resources. */ 1499 msixc = pci_msix_count(dev); 1500 msic = pci_msi_count(dev); 1501 if (bootverbose) { 1502 device_printf(dev, "MSIX count : %d\n", msixc); 1503 device_printf(dev, "MSI count : %d\n", msic); 1504 } 1505 if (msixc > 1) 1506 msixc = 1; 1507 if (msic > 1) 1508 msic = 1; 1509 /* 1510 * Prefer MSIX over MSI. 1511 * AR816x controller has a silicon bug that MSI interrupt 1512 * does not assert if PCIM_CMD_INTxDIS bit of command 1513 * register is set. pci(4) was taught to handle that case. 1514 */ 1515 if (msix_disable == 0 || msi_disable == 0) { 1516 if (msix_disable == 0 && msixc > 0 && 1517 pci_alloc_msix(dev, &msixc) == 0) { 1518 if (msic == 1) { 1519 device_printf(dev, 1520 "Using %d MSIX message(s).\n", msixc); 1521 sc->alc_flags |= ALC_FLAG_MSIX; 1522 sc->alc_irq_spec = alc_irq_spec_msix; 1523 } else 1524 pci_release_msi(dev); 1525 } 1526 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1527 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1528 if (msic == 1) { 1529 device_printf(dev, 1530 "Using %d MSI message(s).\n", msic); 1531 sc->alc_flags |= ALC_FLAG_MSI; 1532 sc->alc_irq_spec = alc_irq_spec_msi; 1533 } else 1534 pci_release_msi(dev); 1535 } 1536 } 1537 1538 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1539 if (error != 0) { 1540 device_printf(dev, "cannot allocate IRQ resources.\n"); 1541 goto fail; 1542 } 1543 1544 /* Create device sysctl node. */ 1545 alc_sysctl_node(sc); 1546 1547 if ((error = alc_dma_alloc(sc)) != 0) 1548 goto fail; 1549 1550 /* Load station address. */ 1551 alc_get_macaddr(sc); 1552 1553 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1554 if (ifp == NULL) { 1555 device_printf(dev, "cannot allocate ifnet structure.\n"); 1556 error = ENXIO; 1557 goto fail; 1558 } 1559 1560 ifp->if_softc = sc; 1561 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1562 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1563 ifp->if_ioctl = alc_ioctl; 1564 ifp->if_start = alc_start; 1565 ifp->if_init = alc_init; 1566 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1567 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1568 IFQ_SET_READY(&ifp->if_snd); 1569 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1570 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1571 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1572 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1573 sc->alc_flags |= ALC_FLAG_PM; 1574 sc->alc_pmcap = base; 1575 } 1576 ifp->if_capenable = ifp->if_capabilities; 1577 1578 /* Set up MII bus. */ 1579 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1580 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1581 MIIF_DOPAUSE); 1582 if (error != 0) { 1583 device_printf(dev, "attaching PHYs failed\n"); 1584 goto fail; 1585 } 1586 1587 ether_ifattach(ifp, sc->alc_eaddr); 1588 1589 /* VLAN capability setup. */ 1590 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1591 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1592 ifp->if_capenable = ifp->if_capabilities; 1593 /* 1594 * XXX 1595 * It seems enabling Tx checksum offloading makes more trouble. 1596 * Sometimes the controller does not receive any frames when 1597 * Tx checksum offloading is enabled. I'm not sure whether this 1598 * is a bug in Tx checksum offloading logic or I got broken 1599 * sample boards. To safety, don't enable Tx checksum offloading 1600 * by default but give chance to users to toggle it if they know 1601 * their controllers work without problems. 1602 * Fortunately, Tx checksum offloading for AR816x family 1603 * seems to work. 1604 */ 1605 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1606 ifp->if_capenable &= ~IFCAP_TXCSUM; 1607 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1608 } 1609 1610 /* Tell the upper layer(s) we support long frames. */ 1611 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1612 1613 /* Create local taskq. */ 1614 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1615 taskqueue_thread_enqueue, &sc->alc_tq); 1616 if (sc->alc_tq == NULL) { 1617 device_printf(dev, "could not create taskqueue.\n"); 1618 ether_ifdetach(ifp); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1623 device_get_nameunit(sc->alc_dev)); 1624 1625 alc_config_msi(sc); 1626 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1627 msic = ALC_MSIX_MESSAGES; 1628 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1629 msic = ALC_MSI_MESSAGES; 1630 else 1631 msic = 1; 1632 for (i = 0; i < msic; i++) { 1633 error = bus_setup_intr(dev, sc->alc_irq[i], 1634 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1635 &sc->alc_intrhand[i]); 1636 if (error != 0) 1637 break; 1638 } 1639 if (error != 0) { 1640 device_printf(dev, "could not set up interrupt handler.\n"); 1641 taskqueue_free(sc->alc_tq); 1642 sc->alc_tq = NULL; 1643 ether_ifdetach(ifp); 1644 goto fail; 1645 } 1646 1647 fail: 1648 if (error != 0) 1649 alc_detach(dev); 1650 1651 return (error); 1652 } 1653 1654 static int 1655 alc_detach(device_t dev) 1656 { 1657 struct alc_softc *sc; 1658 struct ifnet *ifp; 1659 int i, msic; 1660 1661 sc = device_get_softc(dev); 1662 1663 ifp = sc->alc_ifp; 1664 if (device_is_attached(dev)) { 1665 ether_ifdetach(ifp); 1666 ALC_LOCK(sc); 1667 alc_stop(sc); 1668 ALC_UNLOCK(sc); 1669 callout_drain(&sc->alc_tick_ch); 1670 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1671 } 1672 1673 if (sc->alc_tq != NULL) { 1674 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1675 taskqueue_free(sc->alc_tq); 1676 sc->alc_tq = NULL; 1677 } 1678 1679 if (sc->alc_miibus != NULL) { 1680 device_delete_child(dev, sc->alc_miibus); 1681 sc->alc_miibus = NULL; 1682 } 1683 bus_generic_detach(dev); 1684 alc_dma_free(sc); 1685 1686 if (ifp != NULL) { 1687 if_free(ifp); 1688 sc->alc_ifp = NULL; 1689 } 1690 1691 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1692 msic = ALC_MSIX_MESSAGES; 1693 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1694 msic = ALC_MSI_MESSAGES; 1695 else 1696 msic = 1; 1697 for (i = 0; i < msic; i++) { 1698 if (sc->alc_intrhand[i] != NULL) { 1699 bus_teardown_intr(dev, sc->alc_irq[i], 1700 sc->alc_intrhand[i]); 1701 sc->alc_intrhand[i] = NULL; 1702 } 1703 } 1704 if (sc->alc_res[0] != NULL) 1705 alc_phy_down(sc); 1706 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1707 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1708 pci_release_msi(dev); 1709 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1710 mtx_destroy(&sc->alc_mtx); 1711 1712 return (0); 1713 } 1714 1715 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1716 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1717 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1718 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1719 1720 static void 1721 alc_sysctl_node(struct alc_softc *sc) 1722 { 1723 struct sysctl_ctx_list *ctx; 1724 struct sysctl_oid_list *child, *parent; 1725 struct sysctl_oid *tree; 1726 struct alc_hw_stats *stats; 1727 int error; 1728 1729 stats = &sc->alc_stats; 1730 ctx = device_get_sysctl_ctx(sc->alc_dev); 1731 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1732 1733 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1734 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1735 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1736 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1737 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1738 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1739 /* Pull in device tunables. */ 1740 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1741 error = resource_int_value(device_get_name(sc->alc_dev), 1742 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1743 if (error == 0) { 1744 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1745 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1746 device_printf(sc->alc_dev, "int_rx_mod value out of " 1747 "range; using default: %d\n", 1748 ALC_IM_RX_TIMER_DEFAULT); 1749 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1750 } 1751 } 1752 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1753 error = resource_int_value(device_get_name(sc->alc_dev), 1754 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1755 if (error == 0) { 1756 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1757 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1758 device_printf(sc->alc_dev, "int_tx_mod value out of " 1759 "range; using default: %d\n", 1760 ALC_IM_TX_TIMER_DEFAULT); 1761 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1762 } 1763 } 1764 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1765 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1766 sysctl_hw_alc_proc_limit, "I", 1767 "max number of Rx events to process"); 1768 /* Pull in device tunables. */ 1769 sc->alc_process_limit = ALC_PROC_DEFAULT; 1770 error = resource_int_value(device_get_name(sc->alc_dev), 1771 device_get_unit(sc->alc_dev), "process_limit", 1772 &sc->alc_process_limit); 1773 if (error == 0) { 1774 if (sc->alc_process_limit < ALC_PROC_MIN || 1775 sc->alc_process_limit > ALC_PROC_MAX) { 1776 device_printf(sc->alc_dev, 1777 "process_limit value out of range; " 1778 "using default: %d\n", ALC_PROC_DEFAULT); 1779 sc->alc_process_limit = ALC_PROC_DEFAULT; 1780 } 1781 } 1782 1783 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1784 NULL, "ALC statistics"); 1785 parent = SYSCTL_CHILDREN(tree); 1786 1787 /* Rx statistics. */ 1788 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1789 NULL, "Rx MAC statistics"); 1790 child = SYSCTL_CHILDREN(tree); 1791 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1792 &stats->rx_frames, "Good frames"); 1793 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1794 &stats->rx_bcast_frames, "Good broadcast frames"); 1795 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1796 &stats->rx_mcast_frames, "Good multicast frames"); 1797 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1798 &stats->rx_pause_frames, "Pause control frames"); 1799 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1800 &stats->rx_control_frames, "Control frames"); 1801 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1802 &stats->rx_crcerrs, "CRC errors"); 1803 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1804 &stats->rx_lenerrs, "Frames with length mismatched"); 1805 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1806 &stats->rx_bytes, "Good octets"); 1807 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1808 &stats->rx_bcast_bytes, "Good broadcast octets"); 1809 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1810 &stats->rx_mcast_bytes, "Good multicast octets"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1812 &stats->rx_runts, "Too short frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1814 &stats->rx_fragments, "Fragmented frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1816 &stats->rx_pkts_64, "64 bytes frames"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1818 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1820 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1821 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1822 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1823 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1824 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1825 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1826 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1828 &stats->rx_pkts_1519_max, "1519 to max frames"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1830 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1832 &stats->rx_fifo_oflows, "FIFO overflows"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1834 &stats->rx_rrs_errs, "Return status write-back errors"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1836 &stats->rx_alignerrs, "Alignment errors"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1838 &stats->rx_pkts_filtered, 1839 "Frames dropped due to address filtering"); 1840 1841 /* Tx statistics. */ 1842 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1843 NULL, "Tx MAC statistics"); 1844 child = SYSCTL_CHILDREN(tree); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1846 &stats->tx_frames, "Good frames"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1848 &stats->tx_bcast_frames, "Good broadcast frames"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1850 &stats->tx_mcast_frames, "Good multicast frames"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1852 &stats->tx_pause_frames, "Pause control frames"); 1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1854 &stats->tx_control_frames, "Control frames"); 1855 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1856 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1857 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1858 &stats->tx_excess_defer, "Frames with derferrals"); 1859 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1860 &stats->tx_bytes, "Good octets"); 1861 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1862 &stats->tx_bcast_bytes, "Good broadcast octets"); 1863 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1864 &stats->tx_mcast_bytes, "Good multicast octets"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1866 &stats->tx_pkts_64, "64 bytes frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1868 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1870 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1872 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1874 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1875 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1876 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1877 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1878 &stats->tx_pkts_1519_max, "1519 to max frames"); 1879 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1880 &stats->tx_single_colls, "Single collisions"); 1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1882 &stats->tx_multi_colls, "Multiple collisions"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1884 &stats->tx_late_colls, "Late collisions"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1886 &stats->tx_excess_colls, "Excessive collisions"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1888 &stats->tx_underrun, "FIFO underruns"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1890 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1892 &stats->tx_lenerrs, "Frames with length mismatched"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1894 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1895 } 1896 1897 #undef ALC_SYSCTL_STAT_ADD32 1898 #undef ALC_SYSCTL_STAT_ADD64 1899 1900 struct alc_dmamap_arg { 1901 bus_addr_t alc_busaddr; 1902 }; 1903 1904 static void 1905 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1906 { 1907 struct alc_dmamap_arg *ctx; 1908 1909 if (error != 0) 1910 return; 1911 1912 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1913 1914 ctx = (struct alc_dmamap_arg *)arg; 1915 ctx->alc_busaddr = segs[0].ds_addr; 1916 } 1917 1918 /* 1919 * Normal and high Tx descriptors shares single Tx high address. 1920 * Four Rx descriptor/return rings and CMB shares the same Rx 1921 * high address. 1922 */ 1923 static int 1924 alc_check_boundary(struct alc_softc *sc) 1925 { 1926 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1927 1928 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1929 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1930 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1931 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1932 1933 /* 4GB boundary crossing is not allowed. */ 1934 if ((ALC_ADDR_HI(rx_ring_end) != 1935 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1936 (ALC_ADDR_HI(rr_ring_end) != 1937 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1938 (ALC_ADDR_HI(cmb_end) != 1939 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1940 (ALC_ADDR_HI(tx_ring_end) != 1941 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1942 return (EFBIG); 1943 /* 1944 * Make sure Rx return descriptor/Rx descriptor/CMB use 1945 * the same high address. 1946 */ 1947 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1948 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1949 return (EFBIG); 1950 1951 return (0); 1952 } 1953 1954 static int 1955 alc_dma_alloc(struct alc_softc *sc) 1956 { 1957 struct alc_txdesc *txd; 1958 struct alc_rxdesc *rxd; 1959 bus_addr_t lowaddr; 1960 struct alc_dmamap_arg ctx; 1961 int error, i; 1962 1963 lowaddr = BUS_SPACE_MAXADDR; 1964 again: 1965 /* Create parent DMA tag. */ 1966 error = bus_dma_tag_create( 1967 bus_get_dma_tag(sc->alc_dev), /* parent */ 1968 1, 0, /* alignment, boundary */ 1969 lowaddr, /* lowaddr */ 1970 BUS_SPACE_MAXADDR, /* highaddr */ 1971 NULL, NULL, /* filter, filterarg */ 1972 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1973 0, /* nsegments */ 1974 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1975 0, /* flags */ 1976 NULL, NULL, /* lockfunc, lockarg */ 1977 &sc->alc_cdata.alc_parent_tag); 1978 if (error != 0) { 1979 device_printf(sc->alc_dev, 1980 "could not create parent DMA tag.\n"); 1981 goto fail; 1982 } 1983 1984 /* Create DMA tag for Tx descriptor ring. */ 1985 error = bus_dma_tag_create( 1986 sc->alc_cdata.alc_parent_tag, /* parent */ 1987 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1988 BUS_SPACE_MAXADDR, /* lowaddr */ 1989 BUS_SPACE_MAXADDR, /* highaddr */ 1990 NULL, NULL, /* filter, filterarg */ 1991 ALC_TX_RING_SZ, /* maxsize */ 1992 1, /* nsegments */ 1993 ALC_TX_RING_SZ, /* maxsegsize */ 1994 0, /* flags */ 1995 NULL, NULL, /* lockfunc, lockarg */ 1996 &sc->alc_cdata.alc_tx_ring_tag); 1997 if (error != 0) { 1998 device_printf(sc->alc_dev, 1999 "could not create Tx ring DMA tag.\n"); 2000 goto fail; 2001 } 2002 2003 /* Create DMA tag for Rx free descriptor ring. */ 2004 error = bus_dma_tag_create( 2005 sc->alc_cdata.alc_parent_tag, /* parent */ 2006 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2007 BUS_SPACE_MAXADDR, /* lowaddr */ 2008 BUS_SPACE_MAXADDR, /* highaddr */ 2009 NULL, NULL, /* filter, filterarg */ 2010 ALC_RX_RING_SZ, /* maxsize */ 2011 1, /* nsegments */ 2012 ALC_RX_RING_SZ, /* maxsegsize */ 2013 0, /* flags */ 2014 NULL, NULL, /* lockfunc, lockarg */ 2015 &sc->alc_cdata.alc_rx_ring_tag); 2016 if (error != 0) { 2017 device_printf(sc->alc_dev, 2018 "could not create Rx ring DMA tag.\n"); 2019 goto fail; 2020 } 2021 /* Create DMA tag for Rx return descriptor ring. */ 2022 error = bus_dma_tag_create( 2023 sc->alc_cdata.alc_parent_tag, /* parent */ 2024 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2025 BUS_SPACE_MAXADDR, /* lowaddr */ 2026 BUS_SPACE_MAXADDR, /* highaddr */ 2027 NULL, NULL, /* filter, filterarg */ 2028 ALC_RR_RING_SZ, /* maxsize */ 2029 1, /* nsegments */ 2030 ALC_RR_RING_SZ, /* maxsegsize */ 2031 0, /* flags */ 2032 NULL, NULL, /* lockfunc, lockarg */ 2033 &sc->alc_cdata.alc_rr_ring_tag); 2034 if (error != 0) { 2035 device_printf(sc->alc_dev, 2036 "could not create Rx return ring DMA tag.\n"); 2037 goto fail; 2038 } 2039 2040 /* Create DMA tag for coalescing message block. */ 2041 error = bus_dma_tag_create( 2042 sc->alc_cdata.alc_parent_tag, /* parent */ 2043 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2044 BUS_SPACE_MAXADDR, /* lowaddr */ 2045 BUS_SPACE_MAXADDR, /* highaddr */ 2046 NULL, NULL, /* filter, filterarg */ 2047 ALC_CMB_SZ, /* maxsize */ 2048 1, /* nsegments */ 2049 ALC_CMB_SZ, /* maxsegsize */ 2050 0, /* flags */ 2051 NULL, NULL, /* lockfunc, lockarg */ 2052 &sc->alc_cdata.alc_cmb_tag); 2053 if (error != 0) { 2054 device_printf(sc->alc_dev, 2055 "could not create CMB DMA tag.\n"); 2056 goto fail; 2057 } 2058 /* Create DMA tag for status message block. */ 2059 error = bus_dma_tag_create( 2060 sc->alc_cdata.alc_parent_tag, /* parent */ 2061 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2062 BUS_SPACE_MAXADDR, /* lowaddr */ 2063 BUS_SPACE_MAXADDR, /* highaddr */ 2064 NULL, NULL, /* filter, filterarg */ 2065 ALC_SMB_SZ, /* maxsize */ 2066 1, /* nsegments */ 2067 ALC_SMB_SZ, /* maxsegsize */ 2068 0, /* flags */ 2069 NULL, NULL, /* lockfunc, lockarg */ 2070 &sc->alc_cdata.alc_smb_tag); 2071 if (error != 0) { 2072 device_printf(sc->alc_dev, 2073 "could not create SMB DMA tag.\n"); 2074 goto fail; 2075 } 2076 2077 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2078 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2079 (void **)&sc->alc_rdata.alc_tx_ring, 2080 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2081 &sc->alc_cdata.alc_tx_ring_map); 2082 if (error != 0) { 2083 device_printf(sc->alc_dev, 2084 "could not allocate DMA'able memory for Tx ring.\n"); 2085 goto fail; 2086 } 2087 ctx.alc_busaddr = 0; 2088 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2089 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2090 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2091 if (error != 0 || ctx.alc_busaddr == 0) { 2092 device_printf(sc->alc_dev, 2093 "could not load DMA'able memory for Tx ring.\n"); 2094 goto fail; 2095 } 2096 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2097 2098 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2099 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2100 (void **)&sc->alc_rdata.alc_rx_ring, 2101 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2102 &sc->alc_cdata.alc_rx_ring_map); 2103 if (error != 0) { 2104 device_printf(sc->alc_dev, 2105 "could not allocate DMA'able memory for Rx ring.\n"); 2106 goto fail; 2107 } 2108 ctx.alc_busaddr = 0; 2109 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2110 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2111 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2112 if (error != 0 || ctx.alc_busaddr == 0) { 2113 device_printf(sc->alc_dev, 2114 "could not load DMA'able memory for Rx ring.\n"); 2115 goto fail; 2116 } 2117 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2118 2119 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2120 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2121 (void **)&sc->alc_rdata.alc_rr_ring, 2122 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2123 &sc->alc_cdata.alc_rr_ring_map); 2124 if (error != 0) { 2125 device_printf(sc->alc_dev, 2126 "could not allocate DMA'able memory for Rx return ring.\n"); 2127 goto fail; 2128 } 2129 ctx.alc_busaddr = 0; 2130 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2131 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2132 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2133 if (error != 0 || ctx.alc_busaddr == 0) { 2134 device_printf(sc->alc_dev, 2135 "could not load DMA'able memory for Tx ring.\n"); 2136 goto fail; 2137 } 2138 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2139 2140 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2141 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2142 (void **)&sc->alc_rdata.alc_cmb, 2143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2144 &sc->alc_cdata.alc_cmb_map); 2145 if (error != 0) { 2146 device_printf(sc->alc_dev, 2147 "could not allocate DMA'able memory for CMB.\n"); 2148 goto fail; 2149 } 2150 ctx.alc_busaddr = 0; 2151 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2152 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2153 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2154 if (error != 0 || ctx.alc_busaddr == 0) { 2155 device_printf(sc->alc_dev, 2156 "could not load DMA'able memory for CMB.\n"); 2157 goto fail; 2158 } 2159 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2160 2161 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2162 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2163 (void **)&sc->alc_rdata.alc_smb, 2164 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2165 &sc->alc_cdata.alc_smb_map); 2166 if (error != 0) { 2167 device_printf(sc->alc_dev, 2168 "could not allocate DMA'able memory for SMB.\n"); 2169 goto fail; 2170 } 2171 ctx.alc_busaddr = 0; 2172 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2173 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2174 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2175 if (error != 0 || ctx.alc_busaddr == 0) { 2176 device_printf(sc->alc_dev, 2177 "could not load DMA'able memory for CMB.\n"); 2178 goto fail; 2179 } 2180 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2181 2182 /* Make sure we've not crossed 4GB boundary. */ 2183 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2184 (error = alc_check_boundary(sc)) != 0) { 2185 device_printf(sc->alc_dev, "4GB boundary crossed, " 2186 "switching to 32bit DMA addressing mode.\n"); 2187 alc_dma_free(sc); 2188 /* 2189 * Limit max allowable DMA address space to 32bit 2190 * and try again. 2191 */ 2192 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2193 goto again; 2194 } 2195 2196 /* 2197 * Create Tx buffer parent tag. 2198 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2199 * so it needs separate parent DMA tag as parent DMA address 2200 * space could be restricted to be within 32bit address space 2201 * by 4GB boundary crossing. 2202 */ 2203 error = bus_dma_tag_create( 2204 bus_get_dma_tag(sc->alc_dev), /* parent */ 2205 1, 0, /* alignment, boundary */ 2206 BUS_SPACE_MAXADDR, /* lowaddr */ 2207 BUS_SPACE_MAXADDR, /* highaddr */ 2208 NULL, NULL, /* filter, filterarg */ 2209 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2210 0, /* nsegments */ 2211 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2212 0, /* flags */ 2213 NULL, NULL, /* lockfunc, lockarg */ 2214 &sc->alc_cdata.alc_buffer_tag); 2215 if (error != 0) { 2216 device_printf(sc->alc_dev, 2217 "could not create parent buffer DMA tag.\n"); 2218 goto fail; 2219 } 2220 2221 /* Create DMA tag for Tx buffers. */ 2222 error = bus_dma_tag_create( 2223 sc->alc_cdata.alc_buffer_tag, /* parent */ 2224 1, 0, /* alignment, boundary */ 2225 BUS_SPACE_MAXADDR, /* lowaddr */ 2226 BUS_SPACE_MAXADDR, /* highaddr */ 2227 NULL, NULL, /* filter, filterarg */ 2228 ALC_TSO_MAXSIZE, /* maxsize */ 2229 ALC_MAXTXSEGS, /* nsegments */ 2230 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2231 0, /* flags */ 2232 NULL, NULL, /* lockfunc, lockarg */ 2233 &sc->alc_cdata.alc_tx_tag); 2234 if (error != 0) { 2235 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2236 goto fail; 2237 } 2238 2239 /* Create DMA tag for Rx buffers. */ 2240 error = bus_dma_tag_create( 2241 sc->alc_cdata.alc_buffer_tag, /* parent */ 2242 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2243 BUS_SPACE_MAXADDR, /* lowaddr */ 2244 BUS_SPACE_MAXADDR, /* highaddr */ 2245 NULL, NULL, /* filter, filterarg */ 2246 MCLBYTES, /* maxsize */ 2247 1, /* nsegments */ 2248 MCLBYTES, /* maxsegsize */ 2249 0, /* flags */ 2250 NULL, NULL, /* lockfunc, lockarg */ 2251 &sc->alc_cdata.alc_rx_tag); 2252 if (error != 0) { 2253 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2254 goto fail; 2255 } 2256 /* Create DMA maps for Tx buffers. */ 2257 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2258 txd = &sc->alc_cdata.alc_txdesc[i]; 2259 txd->tx_m = NULL; 2260 txd->tx_dmamap = NULL; 2261 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2262 &txd->tx_dmamap); 2263 if (error != 0) { 2264 device_printf(sc->alc_dev, 2265 "could not create Tx dmamap.\n"); 2266 goto fail; 2267 } 2268 } 2269 /* Create DMA maps for Rx buffers. */ 2270 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2271 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2272 device_printf(sc->alc_dev, 2273 "could not create spare Rx dmamap.\n"); 2274 goto fail; 2275 } 2276 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2277 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2278 rxd->rx_m = NULL; 2279 rxd->rx_dmamap = NULL; 2280 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2281 &rxd->rx_dmamap); 2282 if (error != 0) { 2283 device_printf(sc->alc_dev, 2284 "could not create Rx dmamap.\n"); 2285 goto fail; 2286 } 2287 } 2288 2289 fail: 2290 return (error); 2291 } 2292 2293 static void 2294 alc_dma_free(struct alc_softc *sc) 2295 { 2296 struct alc_txdesc *txd; 2297 struct alc_rxdesc *rxd; 2298 int i; 2299 2300 /* Tx buffers. */ 2301 if (sc->alc_cdata.alc_tx_tag != NULL) { 2302 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2303 txd = &sc->alc_cdata.alc_txdesc[i]; 2304 if (txd->tx_dmamap != NULL) { 2305 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2306 txd->tx_dmamap); 2307 txd->tx_dmamap = NULL; 2308 } 2309 } 2310 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2311 sc->alc_cdata.alc_tx_tag = NULL; 2312 } 2313 /* Rx buffers */ 2314 if (sc->alc_cdata.alc_rx_tag != NULL) { 2315 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2316 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2317 if (rxd->rx_dmamap != NULL) { 2318 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2319 rxd->rx_dmamap); 2320 rxd->rx_dmamap = NULL; 2321 } 2322 } 2323 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2324 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2325 sc->alc_cdata.alc_rx_sparemap); 2326 sc->alc_cdata.alc_rx_sparemap = NULL; 2327 } 2328 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2329 sc->alc_cdata.alc_rx_tag = NULL; 2330 } 2331 /* Tx descriptor ring. */ 2332 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2333 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2334 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2335 sc->alc_cdata.alc_tx_ring_map); 2336 if (sc->alc_rdata.alc_tx_ring != NULL) 2337 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2338 sc->alc_rdata.alc_tx_ring, 2339 sc->alc_cdata.alc_tx_ring_map); 2340 sc->alc_rdata.alc_tx_ring_paddr = 0; 2341 sc->alc_rdata.alc_tx_ring = NULL; 2342 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2343 sc->alc_cdata.alc_tx_ring_tag = NULL; 2344 } 2345 /* Rx ring. */ 2346 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2347 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2348 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2349 sc->alc_cdata.alc_rx_ring_map); 2350 if (sc->alc_rdata.alc_rx_ring != NULL) 2351 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2352 sc->alc_rdata.alc_rx_ring, 2353 sc->alc_cdata.alc_rx_ring_map); 2354 sc->alc_rdata.alc_rx_ring_paddr = 0; 2355 sc->alc_rdata.alc_rx_ring = NULL; 2356 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2357 sc->alc_cdata.alc_rx_ring_tag = NULL; 2358 } 2359 /* Rx return ring. */ 2360 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2361 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2362 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2363 sc->alc_cdata.alc_rr_ring_map); 2364 if (sc->alc_rdata.alc_rr_ring != NULL) 2365 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2366 sc->alc_rdata.alc_rr_ring, 2367 sc->alc_cdata.alc_rr_ring_map); 2368 sc->alc_rdata.alc_rr_ring_paddr = 0; 2369 sc->alc_rdata.alc_rr_ring = NULL; 2370 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2371 sc->alc_cdata.alc_rr_ring_tag = NULL; 2372 } 2373 /* CMB block */ 2374 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2375 if (sc->alc_rdata.alc_cmb_paddr != 0) 2376 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2377 sc->alc_cdata.alc_cmb_map); 2378 if (sc->alc_rdata.alc_cmb != NULL) 2379 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2380 sc->alc_rdata.alc_cmb, 2381 sc->alc_cdata.alc_cmb_map); 2382 sc->alc_rdata.alc_cmb_paddr = 0; 2383 sc->alc_rdata.alc_cmb = NULL; 2384 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2385 sc->alc_cdata.alc_cmb_tag = NULL; 2386 } 2387 /* SMB block */ 2388 if (sc->alc_cdata.alc_smb_tag != NULL) { 2389 if (sc->alc_rdata.alc_smb_paddr != 0) 2390 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2391 sc->alc_cdata.alc_smb_map); 2392 if (sc->alc_rdata.alc_smb != NULL) 2393 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2394 sc->alc_rdata.alc_smb, 2395 sc->alc_cdata.alc_smb_map); 2396 sc->alc_rdata.alc_smb_paddr = 0; 2397 sc->alc_rdata.alc_smb = NULL; 2398 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2399 sc->alc_cdata.alc_smb_tag = NULL; 2400 } 2401 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2402 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2403 sc->alc_cdata.alc_buffer_tag = NULL; 2404 } 2405 if (sc->alc_cdata.alc_parent_tag != NULL) { 2406 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2407 sc->alc_cdata.alc_parent_tag = NULL; 2408 } 2409 } 2410 2411 static int 2412 alc_shutdown(device_t dev) 2413 { 2414 2415 return (alc_suspend(dev)); 2416 } 2417 2418 /* 2419 * Note, this driver resets the link speed to 10/100Mbps by 2420 * restarting auto-negotiation in suspend/shutdown phase but we 2421 * don't know whether that auto-negotiation would succeed or not 2422 * as driver has no control after powering off/suspend operation. 2423 * If the renegotiation fail WOL may not work. Running at 1Gbps 2424 * will draw more power than 375mA at 3.3V which is specified in 2425 * PCI specification and that would result in complete 2426 * shutdowning power to ethernet controller. 2427 * 2428 * TODO 2429 * Save current negotiated media speed/duplex/flow-control to 2430 * softc and restore the same link again after resuming. PHY 2431 * handling such as power down/resetting to 100Mbps may be better 2432 * handled in suspend method in phy driver. 2433 */ 2434 static void 2435 alc_setlinkspeed(struct alc_softc *sc) 2436 { 2437 struct mii_data *mii; 2438 int aneg, i; 2439 2440 mii = device_get_softc(sc->alc_miibus); 2441 mii_pollstat(mii); 2442 aneg = 0; 2443 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2444 (IFM_ACTIVE | IFM_AVALID)) { 2445 switch IFM_SUBTYPE(mii->mii_media_active) { 2446 case IFM_10_T: 2447 case IFM_100_TX: 2448 return; 2449 case IFM_1000_T: 2450 aneg++; 2451 break; 2452 default: 2453 break; 2454 } 2455 } 2456 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2457 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2458 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2460 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2461 DELAY(1000); 2462 if (aneg != 0) { 2463 /* 2464 * Poll link state until alc(4) get a 10/100Mbps link. 2465 */ 2466 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2467 mii_pollstat(mii); 2468 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2469 == (IFM_ACTIVE | IFM_AVALID)) { 2470 switch (IFM_SUBTYPE( 2471 mii->mii_media_active)) { 2472 case IFM_10_T: 2473 case IFM_100_TX: 2474 alc_mac_config(sc); 2475 return; 2476 default: 2477 break; 2478 } 2479 } 2480 ALC_UNLOCK(sc); 2481 pause("alclnk", hz); 2482 ALC_LOCK(sc); 2483 } 2484 if (i == MII_ANEGTICKS_GIGE) 2485 device_printf(sc->alc_dev, 2486 "establishing a link failed, WOL may not work!"); 2487 } 2488 /* 2489 * No link, force MAC to have 100Mbps, full-duplex link. 2490 * This is the last resort and may/may not work. 2491 */ 2492 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2493 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2494 alc_mac_config(sc); 2495 } 2496 2497 static void 2498 alc_setwol(struct alc_softc *sc) 2499 { 2500 2501 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2502 alc_setwol_816x(sc); 2503 else 2504 alc_setwol_813x(sc); 2505 } 2506 2507 static void 2508 alc_setwol_813x(struct alc_softc *sc) 2509 { 2510 struct ifnet *ifp; 2511 uint32_t reg, pmcs; 2512 uint16_t pmstat; 2513 2514 ALC_LOCK_ASSERT(sc); 2515 2516 alc_disable_l0s_l1(sc); 2517 ifp = sc->alc_ifp; 2518 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2519 /* Disable WOL. */ 2520 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2521 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2522 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2523 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2524 /* Force PHY power down. */ 2525 alc_phy_down(sc); 2526 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2527 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2528 return; 2529 } 2530 2531 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2532 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2533 alc_setlinkspeed(sc); 2534 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2535 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2536 } 2537 2538 pmcs = 0; 2539 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2540 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2541 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2542 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2543 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2544 MAC_CFG_BCAST); 2545 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2546 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2547 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2548 reg |= MAC_CFG_RX_ENB; 2549 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2550 2551 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2552 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2553 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2554 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2555 /* WOL disabled, PHY power down. */ 2556 alc_phy_down(sc); 2557 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2558 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2559 } 2560 /* Request PME. */ 2561 pmstat = pci_read_config(sc->alc_dev, 2562 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2563 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2564 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2565 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2566 pci_write_config(sc->alc_dev, 2567 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2568 } 2569 2570 static void 2571 alc_setwol_816x(struct alc_softc *sc) 2572 { 2573 struct ifnet *ifp; 2574 uint32_t gphy, mac, master, pmcs, reg; 2575 uint16_t pmstat; 2576 2577 ALC_LOCK_ASSERT(sc); 2578 2579 ifp = sc->alc_ifp; 2580 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2581 master &= ~MASTER_CLK_SEL_DIS; 2582 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2583 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2584 GPHY_CFG_PHY_PLL_ON); 2585 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2586 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2587 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2588 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2589 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2590 } else { 2591 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2592 gphy |= GPHY_CFG_EXT_RESET; 2593 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2594 alc_setlinkspeed(sc); 2595 } 2596 pmcs = 0; 2597 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2598 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2599 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2600 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2601 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2602 MAC_CFG_BCAST); 2603 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2604 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2605 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2606 mac |= MAC_CFG_RX_ENB; 2607 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2608 ANEG_S3DIG10_SL); 2609 } 2610 2611 /* Enable OSC. */ 2612 reg = CSR_READ_4(sc, ALC_MISC); 2613 reg &= ~MISC_INTNLOSC_OPEN; 2614 CSR_WRITE_4(sc, ALC_MISC, reg); 2615 reg |= MISC_INTNLOSC_OPEN; 2616 CSR_WRITE_4(sc, ALC_MISC, reg); 2617 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2618 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2619 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2620 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2621 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2622 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2623 2624 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2625 /* Request PME. */ 2626 pmstat = pci_read_config(sc->alc_dev, 2627 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2628 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2629 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2630 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2631 pci_write_config(sc->alc_dev, 2632 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2633 } 2634 } 2635 2636 static int 2637 alc_suspend(device_t dev) 2638 { 2639 struct alc_softc *sc; 2640 2641 sc = device_get_softc(dev); 2642 2643 ALC_LOCK(sc); 2644 alc_stop(sc); 2645 alc_setwol(sc); 2646 ALC_UNLOCK(sc); 2647 2648 return (0); 2649 } 2650 2651 static int 2652 alc_resume(device_t dev) 2653 { 2654 struct alc_softc *sc; 2655 struct ifnet *ifp; 2656 uint16_t pmstat; 2657 2658 sc = device_get_softc(dev); 2659 2660 ALC_LOCK(sc); 2661 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2662 /* Disable PME and clear PME status. */ 2663 pmstat = pci_read_config(sc->alc_dev, 2664 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2665 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2666 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2667 pci_write_config(sc->alc_dev, 2668 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2669 } 2670 } 2671 /* Reset PHY. */ 2672 alc_phy_reset(sc); 2673 ifp = sc->alc_ifp; 2674 if ((ifp->if_flags & IFF_UP) != 0) { 2675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2676 alc_init_locked(sc); 2677 } 2678 ALC_UNLOCK(sc); 2679 2680 return (0); 2681 } 2682 2683 static int 2684 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2685 { 2686 struct alc_txdesc *txd, *txd_last; 2687 struct tx_desc *desc; 2688 struct mbuf *m; 2689 struct ip *ip; 2690 struct tcphdr *tcp; 2691 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2692 bus_dmamap_t map; 2693 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2694 int error, idx, nsegs, prod; 2695 2696 ALC_LOCK_ASSERT(sc); 2697 2698 M_ASSERTPKTHDR((*m_head)); 2699 2700 m = *m_head; 2701 ip = NULL; 2702 tcp = NULL; 2703 ip_off = poff = 0; 2704 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2705 /* 2706 * AR81[3567]x requires offset of TCP/UDP header in its 2707 * Tx descriptor to perform Tx checksum offloading. TSO 2708 * also requires TCP header offset and modification of 2709 * IP/TCP header. This kind of operation takes many CPU 2710 * cycles on FreeBSD so fast host CPU is required to get 2711 * smooth TSO performance. 2712 */ 2713 struct ether_header *eh; 2714 2715 if (M_WRITABLE(m) == 0) { 2716 /* Get a writable copy. */ 2717 m = m_dup(*m_head, M_NOWAIT); 2718 /* Release original mbufs. */ 2719 m_freem(*m_head); 2720 if (m == NULL) { 2721 *m_head = NULL; 2722 return (ENOBUFS); 2723 } 2724 *m_head = m; 2725 } 2726 2727 ip_off = sizeof(struct ether_header); 2728 m = m_pullup(m, ip_off); 2729 if (m == NULL) { 2730 *m_head = NULL; 2731 return (ENOBUFS); 2732 } 2733 eh = mtod(m, struct ether_header *); 2734 /* 2735 * Check if hardware VLAN insertion is off. 2736 * Additional check for LLC/SNAP frame? 2737 */ 2738 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2739 ip_off = sizeof(struct ether_vlan_header); 2740 m = m_pullup(m, ip_off); 2741 if (m == NULL) { 2742 *m_head = NULL; 2743 return (ENOBUFS); 2744 } 2745 } 2746 m = m_pullup(m, ip_off + sizeof(struct ip)); 2747 if (m == NULL) { 2748 *m_head = NULL; 2749 return (ENOBUFS); 2750 } 2751 ip = (struct ip *)(mtod(m, char *) + ip_off); 2752 poff = ip_off + (ip->ip_hl << 2); 2753 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2754 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2755 if (m == NULL) { 2756 *m_head = NULL; 2757 return (ENOBUFS); 2758 } 2759 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2760 m = m_pullup(m, poff + (tcp->th_off << 2)); 2761 if (m == NULL) { 2762 *m_head = NULL; 2763 return (ENOBUFS); 2764 } 2765 /* 2766 * Due to strict adherence of Microsoft NDIS 2767 * Large Send specification, hardware expects 2768 * a pseudo TCP checksum inserted by upper 2769 * stack. Unfortunately the pseudo TCP 2770 * checksum that NDIS refers to does not include 2771 * TCP payload length so driver should recompute 2772 * the pseudo checksum here. Hopefully this 2773 * wouldn't be much burden on modern CPUs. 2774 * 2775 * Reset IP checksum and recompute TCP pseudo 2776 * checksum as NDIS specification said. 2777 */ 2778 ip = (struct ip *)(mtod(m, char *) + ip_off); 2779 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2780 ip->ip_sum = 0; 2781 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2782 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2783 } 2784 *m_head = m; 2785 } 2786 2787 prod = sc->alc_cdata.alc_tx_prod; 2788 txd = &sc->alc_cdata.alc_txdesc[prod]; 2789 txd_last = txd; 2790 map = txd->tx_dmamap; 2791 2792 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2793 *m_head, txsegs, &nsegs, 0); 2794 if (error == EFBIG) { 2795 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2796 if (m == NULL) { 2797 m_freem(*m_head); 2798 *m_head = NULL; 2799 return (ENOMEM); 2800 } 2801 *m_head = m; 2802 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2803 *m_head, txsegs, &nsegs, 0); 2804 if (error != 0) { 2805 m_freem(*m_head); 2806 *m_head = NULL; 2807 return (error); 2808 } 2809 } else if (error != 0) 2810 return (error); 2811 if (nsegs == 0) { 2812 m_freem(*m_head); 2813 *m_head = NULL; 2814 return (EIO); 2815 } 2816 2817 /* Check descriptor overrun. */ 2818 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2819 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2820 return (ENOBUFS); 2821 } 2822 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2823 2824 m = *m_head; 2825 cflags = TD_ETHERNET; 2826 vtag = 0; 2827 desc = NULL; 2828 idx = 0; 2829 /* Configure VLAN hardware tag insertion. */ 2830 if ((m->m_flags & M_VLANTAG) != 0) { 2831 vtag = htons(m->m_pkthdr.ether_vtag); 2832 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2833 cflags |= TD_INS_VLAN_TAG; 2834 } 2835 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2836 /* Request TSO and set MSS. */ 2837 cflags |= TD_TSO | TD_TSO_DESCV1; 2838 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2839 TD_MSS_MASK; 2840 /* Set TCP header offset. */ 2841 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2842 TD_TCPHDR_OFFSET_MASK; 2843 /* 2844 * AR81[3567]x requires the first buffer should 2845 * only hold IP/TCP header data. Payload should 2846 * be handled in other descriptors. 2847 */ 2848 hdrlen = poff + (tcp->th_off << 2); 2849 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2850 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2851 desc->flags = htole32(cflags); 2852 desc->addr = htole64(txsegs[0].ds_addr); 2853 sc->alc_cdata.alc_tx_cnt++; 2854 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2855 if (m->m_len - hdrlen > 0) { 2856 /* Handle remaining payload of the first fragment. */ 2857 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2858 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2859 vtag)); 2860 desc->flags = htole32(cflags); 2861 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2862 sc->alc_cdata.alc_tx_cnt++; 2863 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2864 } 2865 /* Handle remaining fragments. */ 2866 idx = 1; 2867 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2868 /* Configure Tx checksum offload. */ 2869 #ifdef ALC_USE_CUSTOM_CSUM 2870 cflags |= TD_CUSTOM_CSUM; 2871 /* Set checksum start offset. */ 2872 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2873 TD_PLOAD_OFFSET_MASK; 2874 /* Set checksum insertion position of TCP/UDP. */ 2875 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2876 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2877 #else 2878 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2879 cflags |= TD_IPCSUM; 2880 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2881 cflags |= TD_TCPCSUM; 2882 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2883 cflags |= TD_UDPCSUM; 2884 /* Set TCP/UDP header offset. */ 2885 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2886 TD_L4HDR_OFFSET_MASK; 2887 #endif 2888 } 2889 for (; idx < nsegs; idx++) { 2890 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2891 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2892 desc->flags = htole32(cflags); 2893 desc->addr = htole64(txsegs[idx].ds_addr); 2894 sc->alc_cdata.alc_tx_cnt++; 2895 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2896 } 2897 /* Update producer index. */ 2898 sc->alc_cdata.alc_tx_prod = prod; 2899 2900 /* Finally set EOP on the last descriptor. */ 2901 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2902 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2903 desc->flags |= htole32(TD_EOP); 2904 2905 /* Swap dmamap of the first and the last. */ 2906 txd = &sc->alc_cdata.alc_txdesc[prod]; 2907 map = txd_last->tx_dmamap; 2908 txd_last->tx_dmamap = txd->tx_dmamap; 2909 txd->tx_dmamap = map; 2910 txd->tx_m = m; 2911 2912 return (0); 2913 } 2914 2915 static void 2916 alc_start(struct ifnet *ifp) 2917 { 2918 struct alc_softc *sc; 2919 2920 sc = ifp->if_softc; 2921 ALC_LOCK(sc); 2922 alc_start_locked(ifp); 2923 ALC_UNLOCK(sc); 2924 } 2925 2926 static void 2927 alc_start_locked(struct ifnet *ifp) 2928 { 2929 struct alc_softc *sc; 2930 struct mbuf *m_head; 2931 int enq; 2932 2933 sc = ifp->if_softc; 2934 2935 ALC_LOCK_ASSERT(sc); 2936 2937 /* Reclaim transmitted frames. */ 2938 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2939 alc_txeof(sc); 2940 2941 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2942 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2943 return; 2944 2945 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2946 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2947 if (m_head == NULL) 2948 break; 2949 /* 2950 * Pack the data into the transmit ring. If we 2951 * don't have room, set the OACTIVE flag and wait 2952 * for the NIC to drain the ring. 2953 */ 2954 if (alc_encap(sc, &m_head)) { 2955 if (m_head == NULL) 2956 break; 2957 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2958 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2959 break; 2960 } 2961 2962 enq++; 2963 /* 2964 * If there's a BPF listener, bounce a copy of this frame 2965 * to him. 2966 */ 2967 ETHER_BPF_MTAP(ifp, m_head); 2968 } 2969 2970 if (enq > 0) { 2971 /* Sync descriptors. */ 2972 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2973 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2974 /* Kick. Assume we're using normal Tx priority queue. */ 2975 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2976 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2977 (uint16_t)sc->alc_cdata.alc_tx_prod); 2978 else 2979 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2980 (sc->alc_cdata.alc_tx_prod << 2981 MBOX_TD_PROD_LO_IDX_SHIFT) & 2982 MBOX_TD_PROD_LO_IDX_MASK); 2983 /* Set a timeout in case the chip goes out to lunch. */ 2984 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2985 } 2986 } 2987 2988 static void 2989 alc_watchdog(struct alc_softc *sc) 2990 { 2991 struct ifnet *ifp; 2992 2993 ALC_LOCK_ASSERT(sc); 2994 2995 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2996 return; 2997 2998 ifp = sc->alc_ifp; 2999 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3000 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3001 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3002 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3003 alc_init_locked(sc); 3004 return; 3005 } 3006 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3007 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3008 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3009 alc_init_locked(sc); 3010 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3011 alc_start_locked(ifp); 3012 } 3013 3014 static int 3015 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3016 { 3017 struct alc_softc *sc; 3018 struct ifreq *ifr; 3019 struct mii_data *mii; 3020 int error, mask; 3021 3022 sc = ifp->if_softc; 3023 ifr = (struct ifreq *)data; 3024 error = 0; 3025 switch (cmd) { 3026 case SIOCSIFMTU: 3027 if (ifr->ifr_mtu < ETHERMIN || 3028 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3029 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3030 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3031 ifr->ifr_mtu > ETHERMTU)) 3032 error = EINVAL; 3033 else if (ifp->if_mtu != ifr->ifr_mtu) { 3034 ALC_LOCK(sc); 3035 ifp->if_mtu = ifr->ifr_mtu; 3036 /* AR81[3567]x has 13 bits MSS field. */ 3037 if (ifp->if_mtu > ALC_TSO_MTU && 3038 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3039 ifp->if_capenable &= ~IFCAP_TSO4; 3040 ifp->if_hwassist &= ~CSUM_TSO; 3041 VLAN_CAPABILITIES(ifp); 3042 } 3043 ALC_UNLOCK(sc); 3044 } 3045 break; 3046 case SIOCSIFFLAGS: 3047 ALC_LOCK(sc); 3048 if ((ifp->if_flags & IFF_UP) != 0) { 3049 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3050 ((ifp->if_flags ^ sc->alc_if_flags) & 3051 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3052 alc_rxfilter(sc); 3053 else 3054 alc_init_locked(sc); 3055 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3056 alc_stop(sc); 3057 sc->alc_if_flags = ifp->if_flags; 3058 ALC_UNLOCK(sc); 3059 break; 3060 case SIOCADDMULTI: 3061 case SIOCDELMULTI: 3062 ALC_LOCK(sc); 3063 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3064 alc_rxfilter(sc); 3065 ALC_UNLOCK(sc); 3066 break; 3067 case SIOCSIFMEDIA: 3068 case SIOCGIFMEDIA: 3069 mii = device_get_softc(sc->alc_miibus); 3070 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3071 break; 3072 case SIOCSIFCAP: 3073 ALC_LOCK(sc); 3074 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3075 if ((mask & IFCAP_TXCSUM) != 0 && 3076 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3077 ifp->if_capenable ^= IFCAP_TXCSUM; 3078 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3079 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3080 else 3081 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3082 } 3083 if ((mask & IFCAP_TSO4) != 0 && 3084 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3085 ifp->if_capenable ^= IFCAP_TSO4; 3086 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3087 /* AR81[3567]x has 13 bits MSS field. */ 3088 if (ifp->if_mtu > ALC_TSO_MTU) { 3089 ifp->if_capenable &= ~IFCAP_TSO4; 3090 ifp->if_hwassist &= ~CSUM_TSO; 3091 } else 3092 ifp->if_hwassist |= CSUM_TSO; 3093 } else 3094 ifp->if_hwassist &= ~CSUM_TSO; 3095 } 3096 if ((mask & IFCAP_WOL_MCAST) != 0 && 3097 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3098 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3099 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3100 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3101 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3102 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3103 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3104 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3105 alc_rxvlan(sc); 3106 } 3107 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3108 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3109 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3110 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3111 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3112 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3113 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3114 ifp->if_capenable &= 3115 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3116 ALC_UNLOCK(sc); 3117 VLAN_CAPABILITIES(ifp); 3118 break; 3119 default: 3120 error = ether_ioctl(ifp, cmd, data); 3121 break; 3122 } 3123 3124 return (error); 3125 } 3126 3127 static void 3128 alc_mac_config(struct alc_softc *sc) 3129 { 3130 struct mii_data *mii; 3131 uint32_t reg; 3132 3133 ALC_LOCK_ASSERT(sc); 3134 3135 mii = device_get_softc(sc->alc_miibus); 3136 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3137 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3138 MAC_CFG_SPEED_MASK); 3139 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3140 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3141 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3142 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3143 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3144 /* Reprogram MAC with resolved speed/duplex. */ 3145 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3146 case IFM_10_T: 3147 case IFM_100_TX: 3148 reg |= MAC_CFG_SPEED_10_100; 3149 break; 3150 case IFM_1000_T: 3151 reg |= MAC_CFG_SPEED_1000; 3152 break; 3153 } 3154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3155 reg |= MAC_CFG_FULL_DUPLEX; 3156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3157 reg |= MAC_CFG_TX_FC; 3158 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3159 reg |= MAC_CFG_RX_FC; 3160 } 3161 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3162 } 3163 3164 static void 3165 alc_stats_clear(struct alc_softc *sc) 3166 { 3167 struct smb sb, *smb; 3168 uint32_t *reg; 3169 int i; 3170 3171 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3172 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3173 sc->alc_cdata.alc_smb_map, 3174 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3175 smb = sc->alc_rdata.alc_smb; 3176 /* Update done, clear. */ 3177 smb->updated = 0; 3178 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3179 sc->alc_cdata.alc_smb_map, 3180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3181 } else { 3182 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3183 reg++) { 3184 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3185 i += sizeof(uint32_t); 3186 } 3187 /* Read Tx statistics. */ 3188 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3189 reg++) { 3190 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3191 i += sizeof(uint32_t); 3192 } 3193 } 3194 } 3195 3196 static void 3197 alc_stats_update(struct alc_softc *sc) 3198 { 3199 struct alc_hw_stats *stat; 3200 struct smb sb, *smb; 3201 struct ifnet *ifp; 3202 uint32_t *reg; 3203 int i; 3204 3205 ALC_LOCK_ASSERT(sc); 3206 3207 ifp = sc->alc_ifp; 3208 stat = &sc->alc_stats; 3209 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3210 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3211 sc->alc_cdata.alc_smb_map, 3212 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3213 smb = sc->alc_rdata.alc_smb; 3214 if (smb->updated == 0) 3215 return; 3216 } else { 3217 smb = &sb; 3218 /* Read Rx statistics. */ 3219 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3220 reg++) { 3221 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3222 i += sizeof(uint32_t); 3223 } 3224 /* Read Tx statistics. */ 3225 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3226 reg++) { 3227 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3228 i += sizeof(uint32_t); 3229 } 3230 } 3231 3232 /* Rx stats. */ 3233 stat->rx_frames += smb->rx_frames; 3234 stat->rx_bcast_frames += smb->rx_bcast_frames; 3235 stat->rx_mcast_frames += smb->rx_mcast_frames; 3236 stat->rx_pause_frames += smb->rx_pause_frames; 3237 stat->rx_control_frames += smb->rx_control_frames; 3238 stat->rx_crcerrs += smb->rx_crcerrs; 3239 stat->rx_lenerrs += smb->rx_lenerrs; 3240 stat->rx_bytes += smb->rx_bytes; 3241 stat->rx_runts += smb->rx_runts; 3242 stat->rx_fragments += smb->rx_fragments; 3243 stat->rx_pkts_64 += smb->rx_pkts_64; 3244 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3245 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3246 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3247 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3248 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3249 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3250 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3251 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3252 stat->rx_rrs_errs += smb->rx_rrs_errs; 3253 stat->rx_alignerrs += smb->rx_alignerrs; 3254 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3255 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3256 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3257 3258 /* Tx stats. */ 3259 stat->tx_frames += smb->tx_frames; 3260 stat->tx_bcast_frames += smb->tx_bcast_frames; 3261 stat->tx_mcast_frames += smb->tx_mcast_frames; 3262 stat->tx_pause_frames += smb->tx_pause_frames; 3263 stat->tx_excess_defer += smb->tx_excess_defer; 3264 stat->tx_control_frames += smb->tx_control_frames; 3265 stat->tx_deferred += smb->tx_deferred; 3266 stat->tx_bytes += smb->tx_bytes; 3267 stat->tx_pkts_64 += smb->tx_pkts_64; 3268 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3269 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3270 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3271 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3272 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3273 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3274 stat->tx_single_colls += smb->tx_single_colls; 3275 stat->tx_multi_colls += smb->tx_multi_colls; 3276 stat->tx_late_colls += smb->tx_late_colls; 3277 stat->tx_excess_colls += smb->tx_excess_colls; 3278 stat->tx_underrun += smb->tx_underrun; 3279 stat->tx_desc_underrun += smb->tx_desc_underrun; 3280 stat->tx_lenerrs += smb->tx_lenerrs; 3281 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3282 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3283 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3284 3285 /* Update counters in ifnet. */ 3286 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3287 3288 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3289 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3290 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3291 3292 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3293 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3294 3295 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3296 3297 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3298 smb->rx_crcerrs + smb->rx_lenerrs + 3299 smb->rx_runts + smb->rx_pkts_truncated + 3300 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3301 smb->rx_alignerrs); 3302 3303 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3304 /* Update done, clear. */ 3305 smb->updated = 0; 3306 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3307 sc->alc_cdata.alc_smb_map, 3308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3309 } 3310 } 3311 3312 static int 3313 alc_intr(void *arg) 3314 { 3315 struct alc_softc *sc; 3316 uint32_t status; 3317 3318 sc = (struct alc_softc *)arg; 3319 3320 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3321 if ((status & ALC_INTRS) == 0) 3322 return (FILTER_STRAY); 3323 /* Disable interrupts. */ 3324 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3325 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3326 3327 return (FILTER_HANDLED); 3328 } 3329 3330 static void 3331 alc_int_task(void *arg, int pending) 3332 { 3333 struct alc_softc *sc; 3334 struct ifnet *ifp; 3335 uint32_t status; 3336 int more; 3337 3338 sc = (struct alc_softc *)arg; 3339 ifp = sc->alc_ifp; 3340 3341 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3342 ALC_LOCK(sc); 3343 if (sc->alc_morework != 0) { 3344 sc->alc_morework = 0; 3345 status |= INTR_RX_PKT; 3346 } 3347 if ((status & ALC_INTRS) == 0) 3348 goto done; 3349 3350 /* Acknowledge interrupts but still disable interrupts. */ 3351 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3352 3353 more = 0; 3354 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3355 if ((status & INTR_RX_PKT) != 0) { 3356 more = alc_rxintr(sc, sc->alc_process_limit); 3357 if (more == EAGAIN) 3358 sc->alc_morework = 1; 3359 else if (more == EIO) { 3360 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3361 alc_init_locked(sc); 3362 ALC_UNLOCK(sc); 3363 return; 3364 } 3365 } 3366 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3367 INTR_TXQ_TO_RST)) != 0) { 3368 if ((status & INTR_DMA_RD_TO_RST) != 0) 3369 device_printf(sc->alc_dev, 3370 "DMA read error! -- resetting\n"); 3371 if ((status & INTR_DMA_WR_TO_RST) != 0) 3372 device_printf(sc->alc_dev, 3373 "DMA write error! -- resetting\n"); 3374 if ((status & INTR_TXQ_TO_RST) != 0) 3375 device_printf(sc->alc_dev, 3376 "TxQ reset! -- resetting\n"); 3377 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3378 alc_init_locked(sc); 3379 ALC_UNLOCK(sc); 3380 return; 3381 } 3382 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3383 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3384 alc_start_locked(ifp); 3385 } 3386 3387 if (more == EAGAIN || 3388 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3389 ALC_UNLOCK(sc); 3390 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3391 return; 3392 } 3393 3394 done: 3395 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3396 /* Re-enable interrupts if we're running. */ 3397 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3398 } 3399 ALC_UNLOCK(sc); 3400 } 3401 3402 static void 3403 alc_txeof(struct alc_softc *sc) 3404 { 3405 struct ifnet *ifp; 3406 struct alc_txdesc *txd; 3407 uint32_t cons, prod; 3408 int prog; 3409 3410 ALC_LOCK_ASSERT(sc); 3411 3412 ifp = sc->alc_ifp; 3413 3414 if (sc->alc_cdata.alc_tx_cnt == 0) 3415 return; 3416 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3417 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3418 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3419 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3420 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3421 prod = sc->alc_rdata.alc_cmb->cons; 3422 } else { 3423 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3424 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3425 else { 3426 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3427 /* Assume we're using normal Tx priority queue. */ 3428 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3429 MBOX_TD_CONS_LO_IDX_SHIFT; 3430 } 3431 } 3432 cons = sc->alc_cdata.alc_tx_cons; 3433 /* 3434 * Go through our Tx list and free mbufs for those 3435 * frames which have been transmitted. 3436 */ 3437 for (prog = 0; cons != prod; prog++, 3438 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3439 if (sc->alc_cdata.alc_tx_cnt <= 0) 3440 break; 3441 prog++; 3442 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3443 sc->alc_cdata.alc_tx_cnt--; 3444 txd = &sc->alc_cdata.alc_txdesc[cons]; 3445 if (txd->tx_m != NULL) { 3446 /* Reclaim transmitted mbufs. */ 3447 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3448 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3449 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3450 txd->tx_dmamap); 3451 m_freem(txd->tx_m); 3452 txd->tx_m = NULL; 3453 } 3454 } 3455 3456 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3457 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3458 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3459 sc->alc_cdata.alc_tx_cons = cons; 3460 /* 3461 * Unarm watchdog timer only when there is no pending 3462 * frames in Tx queue. 3463 */ 3464 if (sc->alc_cdata.alc_tx_cnt == 0) 3465 sc->alc_watchdog_timer = 0; 3466 } 3467 3468 static int 3469 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3470 { 3471 struct mbuf *m; 3472 bus_dma_segment_t segs[1]; 3473 bus_dmamap_t map; 3474 int nsegs; 3475 3476 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3477 if (m == NULL) 3478 return (ENOBUFS); 3479 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3480 #ifndef __NO_STRICT_ALIGNMENT 3481 m_adj(m, sizeof(uint64_t)); 3482 #endif 3483 3484 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3485 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3486 m_freem(m); 3487 return (ENOBUFS); 3488 } 3489 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3490 3491 if (rxd->rx_m != NULL) { 3492 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3493 BUS_DMASYNC_POSTREAD); 3494 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3495 } 3496 map = rxd->rx_dmamap; 3497 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3498 sc->alc_cdata.alc_rx_sparemap = map; 3499 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3500 BUS_DMASYNC_PREREAD); 3501 rxd->rx_m = m; 3502 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3503 return (0); 3504 } 3505 3506 static int 3507 alc_rxintr(struct alc_softc *sc, int count) 3508 { 3509 struct ifnet *ifp; 3510 struct rx_rdesc *rrd; 3511 uint32_t nsegs, status; 3512 int rr_cons, prog; 3513 3514 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3515 sc->alc_cdata.alc_rr_ring_map, 3516 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3517 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3518 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3519 rr_cons = sc->alc_cdata.alc_rr_cons; 3520 ifp = sc->alc_ifp; 3521 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3522 if (count-- <= 0) 3523 break; 3524 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3525 status = le32toh(rrd->status); 3526 if ((status & RRD_VALID) == 0) 3527 break; 3528 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3529 if (nsegs == 0) { 3530 /* This should not happen! */ 3531 device_printf(sc->alc_dev, 3532 "unexpected segment count -- resetting\n"); 3533 return (EIO); 3534 } 3535 alc_rxeof(sc, rrd); 3536 /* Clear Rx return status. */ 3537 rrd->status = 0; 3538 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3539 sc->alc_cdata.alc_rx_cons += nsegs; 3540 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3541 prog += nsegs; 3542 } 3543 3544 if (prog > 0) { 3545 /* Update the consumer index. */ 3546 sc->alc_cdata.alc_rr_cons = rr_cons; 3547 /* Sync Rx return descriptors. */ 3548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3549 sc->alc_cdata.alc_rr_ring_map, 3550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3551 /* 3552 * Sync updated Rx descriptors such that controller see 3553 * modified buffer addresses. 3554 */ 3555 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3556 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3557 /* 3558 * Let controller know availability of new Rx buffers. 3559 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3560 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3561 * only when Rx buffer pre-fetching is required. In 3562 * addition we already set ALC_RX_RD_FREE_THRESH to 3563 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3564 * it still seems that pre-fetching needs more 3565 * experimentation. 3566 */ 3567 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3568 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3569 (uint16_t)sc->alc_cdata.alc_rx_cons); 3570 else 3571 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3572 sc->alc_cdata.alc_rx_cons); 3573 } 3574 3575 return (count > 0 ? 0 : EAGAIN); 3576 } 3577 3578 #ifndef __NO_STRICT_ALIGNMENT 3579 static struct mbuf * 3580 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3581 { 3582 struct mbuf *n; 3583 int i; 3584 uint16_t *src, *dst; 3585 3586 src = mtod(m, uint16_t *); 3587 dst = src - 3; 3588 3589 if (m->m_next == NULL) { 3590 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3591 *dst++ = *src++; 3592 m->m_data -= 6; 3593 return (m); 3594 } 3595 /* 3596 * Append a new mbuf to received mbuf chain and copy ethernet 3597 * header from the mbuf chain. This can save lots of CPU 3598 * cycles for jumbo frame. 3599 */ 3600 MGETHDR(n, M_NOWAIT, MT_DATA); 3601 if (n == NULL) { 3602 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3603 m_freem(m); 3604 return (NULL); 3605 } 3606 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3607 m->m_data += ETHER_HDR_LEN; 3608 m->m_len -= ETHER_HDR_LEN; 3609 n->m_len = ETHER_HDR_LEN; 3610 M_MOVE_PKTHDR(n, m); 3611 n->m_next = m; 3612 return (n); 3613 } 3614 #endif 3615 3616 /* Receive a frame. */ 3617 static void 3618 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3619 { 3620 struct alc_rxdesc *rxd; 3621 struct ifnet *ifp; 3622 struct mbuf *mp, *m; 3623 uint32_t rdinfo, status, vtag; 3624 int count, nsegs, rx_cons; 3625 3626 ifp = sc->alc_ifp; 3627 status = le32toh(rrd->status); 3628 rdinfo = le32toh(rrd->rdinfo); 3629 rx_cons = RRD_RD_IDX(rdinfo); 3630 nsegs = RRD_RD_CNT(rdinfo); 3631 3632 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3633 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3634 /* 3635 * We want to pass the following frames to upper 3636 * layer regardless of error status of Rx return 3637 * ring. 3638 * 3639 * o IP/TCP/UDP checksum is bad. 3640 * o frame length and protocol specific length 3641 * does not match. 3642 * 3643 * Force network stack compute checksum for 3644 * errored frames. 3645 */ 3646 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3647 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3648 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3649 return; 3650 } 3651 3652 for (count = 0; count < nsegs; count++, 3653 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3654 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3655 mp = rxd->rx_m; 3656 /* Add a new receive buffer to the ring. */ 3657 if (alc_newbuf(sc, rxd) != 0) { 3658 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3659 /* Reuse Rx buffers. */ 3660 if (sc->alc_cdata.alc_rxhead != NULL) 3661 m_freem(sc->alc_cdata.alc_rxhead); 3662 break; 3663 } 3664 3665 /* 3666 * Assume we've received a full sized frame. 3667 * Actual size is fixed when we encounter the end of 3668 * multi-segmented frame. 3669 */ 3670 mp->m_len = sc->alc_buf_size; 3671 3672 /* Chain received mbufs. */ 3673 if (sc->alc_cdata.alc_rxhead == NULL) { 3674 sc->alc_cdata.alc_rxhead = mp; 3675 sc->alc_cdata.alc_rxtail = mp; 3676 } else { 3677 mp->m_flags &= ~M_PKTHDR; 3678 sc->alc_cdata.alc_rxprev_tail = 3679 sc->alc_cdata.alc_rxtail; 3680 sc->alc_cdata.alc_rxtail->m_next = mp; 3681 sc->alc_cdata.alc_rxtail = mp; 3682 } 3683 3684 if (count == nsegs - 1) { 3685 /* Last desc. for this frame. */ 3686 m = sc->alc_cdata.alc_rxhead; 3687 m->m_flags |= M_PKTHDR; 3688 /* 3689 * It seems that L1C/L2C controller has no way 3690 * to tell hardware to strip CRC bytes. 3691 */ 3692 m->m_pkthdr.len = 3693 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3694 if (nsegs > 1) { 3695 /* Set last mbuf size. */ 3696 mp->m_len = sc->alc_cdata.alc_rxlen - 3697 (nsegs - 1) * sc->alc_buf_size; 3698 /* Remove the CRC bytes in chained mbufs. */ 3699 if (mp->m_len <= ETHER_CRC_LEN) { 3700 sc->alc_cdata.alc_rxtail = 3701 sc->alc_cdata.alc_rxprev_tail; 3702 sc->alc_cdata.alc_rxtail->m_len -= 3703 (ETHER_CRC_LEN - mp->m_len); 3704 sc->alc_cdata.alc_rxtail->m_next = NULL; 3705 m_freem(mp); 3706 } else { 3707 mp->m_len -= ETHER_CRC_LEN; 3708 } 3709 } else 3710 m->m_len = m->m_pkthdr.len; 3711 m->m_pkthdr.rcvif = ifp; 3712 /* 3713 * Due to hardware bugs, Rx checksum offloading 3714 * was intentionally disabled. 3715 */ 3716 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3717 (status & RRD_VLAN_TAG) != 0) { 3718 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3719 m->m_pkthdr.ether_vtag = ntohs(vtag); 3720 m->m_flags |= M_VLANTAG; 3721 } 3722 #ifndef __NO_STRICT_ALIGNMENT 3723 m = alc_fixup_rx(ifp, m); 3724 if (m != NULL) 3725 #endif 3726 { 3727 /* Pass it on. */ 3728 ALC_UNLOCK(sc); 3729 (*ifp->if_input)(ifp, m); 3730 ALC_LOCK(sc); 3731 } 3732 } 3733 } 3734 /* Reset mbuf chains. */ 3735 ALC_RXCHAIN_RESET(sc); 3736 } 3737 3738 static void 3739 alc_tick(void *arg) 3740 { 3741 struct alc_softc *sc; 3742 struct mii_data *mii; 3743 3744 sc = (struct alc_softc *)arg; 3745 3746 ALC_LOCK_ASSERT(sc); 3747 3748 mii = device_get_softc(sc->alc_miibus); 3749 mii_tick(mii); 3750 alc_stats_update(sc); 3751 /* 3752 * alc(4) does not rely on Tx completion interrupts to reclaim 3753 * transferred buffers. Instead Tx completion interrupts are 3754 * used to hint for scheduling Tx task. So it's necessary to 3755 * release transmitted buffers by kicking Tx completion 3756 * handler. This limits the maximum reclamation delay to a hz. 3757 */ 3758 alc_txeof(sc); 3759 alc_watchdog(sc); 3760 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3761 } 3762 3763 static void 3764 alc_osc_reset(struct alc_softc *sc) 3765 { 3766 uint32_t reg; 3767 3768 reg = CSR_READ_4(sc, ALC_MISC3); 3769 reg &= ~MISC3_25M_BY_SW; 3770 reg |= MISC3_25M_NOTO_INTNL; 3771 CSR_WRITE_4(sc, ALC_MISC3, reg); 3772 3773 reg = CSR_READ_4(sc, ALC_MISC); 3774 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3775 /* 3776 * Restore over-current protection default value. 3777 * This value could be reset by MAC reset. 3778 */ 3779 reg &= ~MISC_PSW_OCP_MASK; 3780 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3781 reg &= ~MISC_INTNLOSC_OPEN; 3782 CSR_WRITE_4(sc, ALC_MISC, reg); 3783 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3784 reg = CSR_READ_4(sc, ALC_MISC2); 3785 reg &= ~MISC2_CALB_START; 3786 CSR_WRITE_4(sc, ALC_MISC2, reg); 3787 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3788 3789 } else { 3790 reg &= ~MISC_INTNLOSC_OPEN; 3791 /* Disable isolate for revision A devices. */ 3792 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3793 reg &= ~MISC_ISO_ENB; 3794 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3795 CSR_WRITE_4(sc, ALC_MISC, reg); 3796 } 3797 3798 DELAY(20); 3799 } 3800 3801 static void 3802 alc_reset(struct alc_softc *sc) 3803 { 3804 uint32_t pmcfg, reg; 3805 int i; 3806 3807 pmcfg = 0; 3808 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3809 /* Reset workaround. */ 3810 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3811 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3812 (sc->alc_rev & 0x01) != 0) { 3813 /* Disable L0s/L1s before reset. */ 3814 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3815 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3816 != 0) { 3817 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3818 PM_CFG_ASPM_L1_ENB); 3819 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3820 } 3821 } 3822 } 3823 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3824 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3825 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3826 3827 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3828 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3829 DELAY(10); 3830 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3831 break; 3832 } 3833 if (i == 0) 3834 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3835 } 3836 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3837 DELAY(10); 3838 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3839 break; 3840 } 3841 if (i == 0) 3842 device_printf(sc->alc_dev, "master reset timeout!\n"); 3843 3844 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3845 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3846 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3847 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3848 break; 3849 DELAY(10); 3850 } 3851 if (i == 0) 3852 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3853 3854 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3855 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3856 (sc->alc_rev & 0x01) != 0) { 3857 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3858 reg |= MASTER_CLK_SEL_DIS; 3859 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3860 /* Restore L0s/L1s config. */ 3861 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3862 != 0) 3863 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3864 } 3865 3866 alc_osc_reset(sc); 3867 reg = CSR_READ_4(sc, ALC_MISC3); 3868 reg &= ~MISC3_25M_BY_SW; 3869 reg |= MISC3_25M_NOTO_INTNL; 3870 CSR_WRITE_4(sc, ALC_MISC3, reg); 3871 reg = CSR_READ_4(sc, ALC_MISC); 3872 reg &= ~MISC_INTNLOSC_OPEN; 3873 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3874 reg &= ~MISC_ISO_ENB; 3875 CSR_WRITE_4(sc, ALC_MISC, reg); 3876 DELAY(20); 3877 } 3878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3879 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3880 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3881 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3882 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3883 SERDES_PHY_CLK_SLOWDOWN); 3884 } 3885 3886 static void 3887 alc_init(void *xsc) 3888 { 3889 struct alc_softc *sc; 3890 3891 sc = (struct alc_softc *)xsc; 3892 ALC_LOCK(sc); 3893 alc_init_locked(sc); 3894 ALC_UNLOCK(sc); 3895 } 3896 3897 static void 3898 alc_init_locked(struct alc_softc *sc) 3899 { 3900 struct ifnet *ifp; 3901 struct mii_data *mii; 3902 uint8_t eaddr[ETHER_ADDR_LEN]; 3903 bus_addr_t paddr; 3904 uint32_t reg, rxf_hi, rxf_lo; 3905 3906 ALC_LOCK_ASSERT(sc); 3907 3908 ifp = sc->alc_ifp; 3909 mii = device_get_softc(sc->alc_miibus); 3910 3911 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3912 return; 3913 /* 3914 * Cancel any pending I/O. 3915 */ 3916 alc_stop(sc); 3917 /* 3918 * Reset the chip to a known state. 3919 */ 3920 alc_reset(sc); 3921 3922 /* Initialize Rx descriptors. */ 3923 if (alc_init_rx_ring(sc) != 0) { 3924 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3925 alc_stop(sc); 3926 return; 3927 } 3928 alc_init_rr_ring(sc); 3929 alc_init_tx_ring(sc); 3930 alc_init_cmb(sc); 3931 alc_init_smb(sc); 3932 3933 /* Enable all clocks. */ 3934 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3935 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3936 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3937 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3938 CLK_GATING_RXMAC_ENB); 3939 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3940 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3941 IDLE_DECISN_TIMER_DEFAULT_1MS); 3942 } else 3943 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3944 3945 /* Reprogram the station address. */ 3946 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3947 CSR_WRITE_4(sc, ALC_PAR0, 3948 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3949 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3950 /* 3951 * Clear WOL status and disable all WOL feature as WOL 3952 * would interfere Rx operation under normal environments. 3953 */ 3954 CSR_READ_4(sc, ALC_WOL_CFG); 3955 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3956 /* Set Tx descriptor base addresses. */ 3957 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3958 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3959 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3960 /* We don't use high priority ring. */ 3961 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3962 /* Set Tx descriptor counter. */ 3963 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3964 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3965 /* Set Rx descriptor base addresses. */ 3966 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3967 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3968 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3969 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3970 /* We use one Rx ring. */ 3971 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3972 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3973 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3974 } 3975 /* Set Rx descriptor counter. */ 3976 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3977 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3978 3979 /* 3980 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3981 * if it do not fit the buffer size. Rx return descriptor holds 3982 * a counter that indicates how many fragments were made by the 3983 * hardware. The buffer size should be multiple of 8 bytes. 3984 * Since hardware has limit on the size of buffer size, always 3985 * use the maximum value. 3986 * For strict-alignment architectures make sure to reduce buffer 3987 * size by 8 bytes to make room for alignment fixup. 3988 */ 3989 #ifndef __NO_STRICT_ALIGNMENT 3990 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3991 #else 3992 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3993 #endif 3994 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3995 3996 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3997 /* Set Rx return descriptor base addresses. */ 3998 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3999 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4000 /* We use one Rx return ring. */ 4001 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4002 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4003 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4004 } 4005 /* Set Rx return descriptor counter. */ 4006 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4007 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4008 paddr = sc->alc_rdata.alc_cmb_paddr; 4009 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4010 paddr = sc->alc_rdata.alc_smb_paddr; 4011 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4012 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4013 4014 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4015 /* Reconfigure SRAM - Vendor magic. */ 4016 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4017 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4018 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4019 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4020 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4021 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4022 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4023 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4024 } 4025 4026 /* Tell hardware that we're ready to load DMA blocks. */ 4027 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4028 4029 /* Configure interrupt moderation timer. */ 4030 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4031 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4032 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4033 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4034 /* 4035 * We don't want to automatic interrupt clear as task queue 4036 * for the interrupt should know interrupt status. 4037 */ 4038 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4039 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4040 reg |= MASTER_SA_TIMER_ENB; 4041 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4042 reg |= MASTER_IM_RX_TIMER_ENB; 4043 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4044 ALC_USECS(sc->alc_int_tx_mod) != 0) 4045 reg |= MASTER_IM_TX_TIMER_ENB; 4046 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4047 /* 4048 * Disable interrupt re-trigger timer. We don't want automatic 4049 * re-triggering of un-ACKed interrupts. 4050 */ 4051 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4052 /* Configure CMB. */ 4053 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4054 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4055 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4056 ALC_USECS(sc->alc_int_tx_mod)); 4057 } else { 4058 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4059 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4060 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4061 } else 4062 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4063 } 4064 /* 4065 * Hardware can be configured to issue SMB interrupt based 4066 * on programmed interval. Since there is a callout that is 4067 * invoked for every hz in driver we use that instead of 4068 * relying on periodic SMB interrupt. 4069 */ 4070 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4071 /* Clear MAC statistics. */ 4072 alc_stats_clear(sc); 4073 4074 /* 4075 * Always use maximum frame size that controller can support. 4076 * Otherwise received frames that has larger frame length 4077 * than alc(4) MTU would be silently dropped in hardware. This 4078 * would make path-MTU discovery hard as sender wouldn't get 4079 * any responses from receiver. alc(4) supports 4080 * multi-fragmented frames on Rx path so it has no issue on 4081 * assembling fragmented frames. Using maximum frame size also 4082 * removes the need to reinitialize hardware when interface 4083 * MTU configuration was changed. 4084 * 4085 * Be conservative in what you do, be liberal in what you 4086 * accept from others - RFC 793. 4087 */ 4088 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4089 4090 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4091 /* Disable header split(?) */ 4092 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4093 4094 /* Configure IPG/IFG parameters. */ 4095 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4096 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4097 IPG_IFG_IPGT_MASK) | 4098 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4099 IPG_IFG_MIFG_MASK) | 4100 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4101 IPG_IFG_IPG1_MASK) | 4102 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4103 IPG_IFG_IPG2_MASK)); 4104 /* Set parameters for half-duplex media. */ 4105 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4106 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4107 HDPX_CFG_LCOL_MASK) | 4108 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4109 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4110 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4111 HDPX_CFG_ABEBT_MASK) | 4112 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4113 HDPX_CFG_JAMIPG_MASK)); 4114 } 4115 4116 /* 4117 * Set TSO/checksum offload threshold. For frames that is 4118 * larger than this threshold, hardware wouldn't do 4119 * TSO/checksum offloading. 4120 */ 4121 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4122 TSO_OFFLOAD_THRESH_MASK; 4123 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4124 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4125 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4126 /* Configure TxQ. */ 4127 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4128 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4129 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4130 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4131 reg >>= 1; 4132 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4133 TXQ_CFG_TD_BURST_MASK; 4134 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4135 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4136 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4137 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4138 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4139 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4140 HQTD_CFG_BURST_ENB); 4141 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4142 reg = WRR_PRI_RESTRICT_NONE; 4143 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4144 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4145 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4146 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4147 CSR_WRITE_4(sc, ALC_WRR, reg); 4148 } else { 4149 /* Configure Rx free descriptor pre-fetching. */ 4150 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4151 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4152 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4153 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4154 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4155 } 4156 4157 /* 4158 * Configure flow control parameters. 4159 * XON : 80% of Rx FIFO 4160 * XOFF : 30% of Rx FIFO 4161 */ 4162 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4163 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4164 reg &= SRAM_RX_FIFO_LEN_MASK; 4165 reg *= 8; 4166 if (reg > 8 * 1024) 4167 reg -= RX_FIFO_PAUSE_816X_RSVD; 4168 else 4169 reg -= RX_BUF_SIZE_MAX; 4170 reg /= 8; 4171 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4172 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4173 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4174 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4175 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4176 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4177 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4178 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4179 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4180 rxf_hi = (reg * 8) / 10; 4181 rxf_lo = (reg * 3) / 10; 4182 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4183 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4184 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4185 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4186 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4187 } 4188 4189 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4190 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4191 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4192 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4193 } 4194 4195 /* Configure RxQ. */ 4196 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4197 RXQ_CFG_RD_BURST_MASK; 4198 reg |= RXQ_CFG_RSS_MODE_DIS; 4199 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4200 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4201 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4202 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4203 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4204 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4205 } else { 4206 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4207 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4208 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4209 } 4210 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4211 4212 /* Configure DMA parameters. */ 4213 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4214 reg |= sc->alc_rcb; 4215 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4216 reg |= DMA_CFG_CMB_ENB; 4217 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4218 reg |= DMA_CFG_SMB_ENB; 4219 else 4220 reg |= DMA_CFG_SMB_DIS; 4221 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4222 DMA_CFG_RD_BURST_SHIFT; 4223 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4224 DMA_CFG_WR_BURST_SHIFT; 4225 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4226 DMA_CFG_RD_DELAY_CNT_MASK; 4227 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4228 DMA_CFG_WR_DELAY_CNT_MASK; 4229 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4230 switch (AR816X_REV(sc->alc_rev)) { 4231 case AR816X_REV_A0: 4232 case AR816X_REV_A1: 4233 reg |= DMA_CFG_RD_CHNL_SEL_2; 4234 break; 4235 case AR816X_REV_B0: 4236 /* FALLTHROUGH */ 4237 default: 4238 reg |= DMA_CFG_RD_CHNL_SEL_4; 4239 break; 4240 } 4241 } 4242 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4243 4244 /* 4245 * Configure Tx/Rx MACs. 4246 * - Auto-padding for short frames. 4247 * - Enable CRC generation. 4248 * Actual reconfiguration of MAC for resolved speed/duplex 4249 * is followed after detection of link establishment. 4250 * AR813x/AR815x always does checksum computation regardless 4251 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4252 * have bug in protocol field in Rx return structure so 4253 * these controllers can't handle fragmented frames. Disable 4254 * Rx checksum offloading until there is a newer controller 4255 * that has sane implementation. 4256 */ 4257 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4258 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4259 MAC_CFG_PREAMBLE_MASK); 4260 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4261 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4262 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4263 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4264 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4265 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4266 reg |= MAC_CFG_SPEED_10_100; 4267 else 4268 reg |= MAC_CFG_SPEED_1000; 4269 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4270 4271 /* Set up the receive filter. */ 4272 alc_rxfilter(sc); 4273 alc_rxvlan(sc); 4274 4275 /* Acknowledge all pending interrupts and clear it. */ 4276 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4277 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4278 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4279 4280 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4281 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4282 4283 sc->alc_flags &= ~ALC_FLAG_LINK; 4284 /* Switch to the current media. */ 4285 alc_mediachange_locked(sc); 4286 4287 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4288 } 4289 4290 static void 4291 alc_stop(struct alc_softc *sc) 4292 { 4293 struct ifnet *ifp; 4294 struct alc_txdesc *txd; 4295 struct alc_rxdesc *rxd; 4296 uint32_t reg; 4297 int i; 4298 4299 ALC_LOCK_ASSERT(sc); 4300 /* 4301 * Mark the interface down and cancel the watchdog timer. 4302 */ 4303 ifp = sc->alc_ifp; 4304 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4305 sc->alc_flags &= ~ALC_FLAG_LINK; 4306 callout_stop(&sc->alc_tick_ch); 4307 sc->alc_watchdog_timer = 0; 4308 alc_stats_update(sc); 4309 /* Disable interrupts. */ 4310 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4311 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4312 /* Disable DMA. */ 4313 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4314 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4315 reg |= DMA_CFG_SMB_DIS; 4316 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4317 DELAY(1000); 4318 /* Stop Rx/Tx MACs. */ 4319 alc_stop_mac(sc); 4320 /* Disable interrupts which might be touched in taskq handler. */ 4321 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4322 /* Disable L0s/L1s */ 4323 alc_aspm(sc, 0, IFM_UNKNOWN); 4324 /* Reclaim Rx buffers that have been processed. */ 4325 if (sc->alc_cdata.alc_rxhead != NULL) 4326 m_freem(sc->alc_cdata.alc_rxhead); 4327 ALC_RXCHAIN_RESET(sc); 4328 /* 4329 * Free Tx/Rx mbufs still in the queues. 4330 */ 4331 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4332 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4333 if (rxd->rx_m != NULL) { 4334 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4335 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4336 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4337 rxd->rx_dmamap); 4338 m_freem(rxd->rx_m); 4339 rxd->rx_m = NULL; 4340 } 4341 } 4342 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4343 txd = &sc->alc_cdata.alc_txdesc[i]; 4344 if (txd->tx_m != NULL) { 4345 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4346 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4347 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4348 txd->tx_dmamap); 4349 m_freem(txd->tx_m); 4350 txd->tx_m = NULL; 4351 } 4352 } 4353 } 4354 4355 static void 4356 alc_stop_mac(struct alc_softc *sc) 4357 { 4358 uint32_t reg; 4359 int i; 4360 4361 alc_stop_queue(sc); 4362 /* Disable Rx/Tx MAC. */ 4363 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4364 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4365 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4366 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4367 } 4368 for (i = ALC_TIMEOUT; i > 0; i--) { 4369 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4370 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4371 break; 4372 DELAY(10); 4373 } 4374 if (i == 0) 4375 device_printf(sc->alc_dev, 4376 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4377 } 4378 4379 static void 4380 alc_start_queue(struct alc_softc *sc) 4381 { 4382 uint32_t qcfg[] = { 4383 0, 4384 RXQ_CFG_QUEUE0_ENB, 4385 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4386 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4387 RXQ_CFG_ENB 4388 }; 4389 uint32_t cfg; 4390 4391 ALC_LOCK_ASSERT(sc); 4392 4393 /* Enable RxQ. */ 4394 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4395 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4396 cfg &= ~RXQ_CFG_ENB; 4397 cfg |= qcfg[1]; 4398 } else 4399 cfg |= RXQ_CFG_QUEUE0_ENB; 4400 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4401 /* Enable TxQ. */ 4402 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4403 cfg |= TXQ_CFG_ENB; 4404 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4405 } 4406 4407 static void 4408 alc_stop_queue(struct alc_softc *sc) 4409 { 4410 uint32_t reg; 4411 int i; 4412 4413 /* Disable RxQ. */ 4414 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4415 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4416 if ((reg & RXQ_CFG_ENB) != 0) { 4417 reg &= ~RXQ_CFG_ENB; 4418 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4419 } 4420 } else { 4421 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4422 reg &= ~RXQ_CFG_QUEUE0_ENB; 4423 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4424 } 4425 } 4426 /* Disable TxQ. */ 4427 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4428 if ((reg & TXQ_CFG_ENB) != 0) { 4429 reg &= ~TXQ_CFG_ENB; 4430 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4431 } 4432 DELAY(40); 4433 for (i = ALC_TIMEOUT; i > 0; i--) { 4434 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4435 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4436 break; 4437 DELAY(10); 4438 } 4439 if (i == 0) 4440 device_printf(sc->alc_dev, 4441 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4442 } 4443 4444 static void 4445 alc_init_tx_ring(struct alc_softc *sc) 4446 { 4447 struct alc_ring_data *rd; 4448 struct alc_txdesc *txd; 4449 int i; 4450 4451 ALC_LOCK_ASSERT(sc); 4452 4453 sc->alc_cdata.alc_tx_prod = 0; 4454 sc->alc_cdata.alc_tx_cons = 0; 4455 sc->alc_cdata.alc_tx_cnt = 0; 4456 4457 rd = &sc->alc_rdata; 4458 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4459 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4460 txd = &sc->alc_cdata.alc_txdesc[i]; 4461 txd->tx_m = NULL; 4462 } 4463 4464 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4465 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4466 } 4467 4468 static int 4469 alc_init_rx_ring(struct alc_softc *sc) 4470 { 4471 struct alc_ring_data *rd; 4472 struct alc_rxdesc *rxd; 4473 int i; 4474 4475 ALC_LOCK_ASSERT(sc); 4476 4477 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4478 sc->alc_morework = 0; 4479 rd = &sc->alc_rdata; 4480 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4481 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4482 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4483 rxd->rx_m = NULL; 4484 rxd->rx_desc = &rd->alc_rx_ring[i]; 4485 if (alc_newbuf(sc, rxd) != 0) 4486 return (ENOBUFS); 4487 } 4488 4489 /* 4490 * Since controller does not update Rx descriptors, driver 4491 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4492 * is enough to ensure coherence. 4493 */ 4494 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4495 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4496 /* Let controller know availability of new Rx buffers. */ 4497 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4498 4499 return (0); 4500 } 4501 4502 static void 4503 alc_init_rr_ring(struct alc_softc *sc) 4504 { 4505 struct alc_ring_data *rd; 4506 4507 ALC_LOCK_ASSERT(sc); 4508 4509 sc->alc_cdata.alc_rr_cons = 0; 4510 ALC_RXCHAIN_RESET(sc); 4511 4512 rd = &sc->alc_rdata; 4513 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4514 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4515 sc->alc_cdata.alc_rr_ring_map, 4516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4517 } 4518 4519 static void 4520 alc_init_cmb(struct alc_softc *sc) 4521 { 4522 struct alc_ring_data *rd; 4523 4524 ALC_LOCK_ASSERT(sc); 4525 4526 rd = &sc->alc_rdata; 4527 bzero(rd->alc_cmb, ALC_CMB_SZ); 4528 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4530 } 4531 4532 static void 4533 alc_init_smb(struct alc_softc *sc) 4534 { 4535 struct alc_ring_data *rd; 4536 4537 ALC_LOCK_ASSERT(sc); 4538 4539 rd = &sc->alc_rdata; 4540 bzero(rd->alc_smb, ALC_SMB_SZ); 4541 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4542 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4543 } 4544 4545 static void 4546 alc_rxvlan(struct alc_softc *sc) 4547 { 4548 struct ifnet *ifp; 4549 uint32_t reg; 4550 4551 ALC_LOCK_ASSERT(sc); 4552 4553 ifp = sc->alc_ifp; 4554 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4555 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4556 reg |= MAC_CFG_VLAN_TAG_STRIP; 4557 else 4558 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4559 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4560 } 4561 4562 static void 4563 alc_rxfilter(struct alc_softc *sc) 4564 { 4565 struct ifnet *ifp; 4566 struct ifmultiaddr *ifma; 4567 uint32_t crc; 4568 uint32_t mchash[2]; 4569 uint32_t rxcfg; 4570 4571 ALC_LOCK_ASSERT(sc); 4572 4573 ifp = sc->alc_ifp; 4574 4575 bzero(mchash, sizeof(mchash)); 4576 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4577 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4578 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4579 rxcfg |= MAC_CFG_BCAST; 4580 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4581 if ((ifp->if_flags & IFF_PROMISC) != 0) 4582 rxcfg |= MAC_CFG_PROMISC; 4583 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4584 rxcfg |= MAC_CFG_ALLMULTI; 4585 mchash[0] = 0xFFFFFFFF; 4586 mchash[1] = 0xFFFFFFFF; 4587 goto chipit; 4588 } 4589 4590 if_maddr_rlock(ifp); 4591 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4592 if (ifma->ifma_addr->sa_family != AF_LINK) 4593 continue; 4594 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4595 ifma->ifma_addr), ETHER_ADDR_LEN); 4596 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4597 } 4598 if_maddr_runlock(ifp); 4599 4600 chipit: 4601 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4602 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4603 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4604 } 4605 4606 static int 4607 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4608 { 4609 int error, value; 4610 4611 if (arg1 == NULL) 4612 return (EINVAL); 4613 value = *(int *)arg1; 4614 error = sysctl_handle_int(oidp, &value, 0, req); 4615 if (error || req->newptr == NULL) 4616 return (error); 4617 if (value < low || value > high) 4618 return (EINVAL); 4619 *(int *)arg1 = value; 4620 4621 return (0); 4622 } 4623 4624 static int 4625 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4626 { 4627 return (sysctl_int_range(oidp, arg1, arg2, req, 4628 ALC_PROC_MIN, ALC_PROC_MAX)); 4629 } 4630 4631 static int 4632 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4633 { 4634 4635 return (sysctl_int_range(oidp, arg1, arg2, req, 4636 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4637 } 4638