1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/debugnet.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 96 /* 97 * The default value of msix_disable is 2, which means to decide whether to 98 * enable MSI-X in alc_attach() depending on the card type. The operator can 99 * set this to 0 or 1 to override the default. 100 */ 101 static int msix_disable = 2; 102 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 103 104 /* 105 * Devices supported by this driver. 106 */ 107 static struct alc_ident alc_ident_table[] = { 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 109 "Atheros AR8131 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 111 "Atheros AR8132 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 117 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 121 "Atheros AR8161 PCIe Gigabit Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 123 "Atheros AR8162 PCIe Fast Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 125 "Atheros AR8171 PCIe Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 127 "Atheros AR8172 PCIe Fast Ethernet" }, 128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 129 "Killer E2200 Gigabit Ethernet" }, 130 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 131 "Killer E2400 Gigabit Ethernet" }, 132 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 133 "Killer E2500 Gigabit Ethernet" }, 134 { 0, 0, 0, NULL} 135 }; 136 137 static void alc_aspm(struct alc_softc *, int, int); 138 static void alc_aspm_813x(struct alc_softc *, int); 139 static void alc_aspm_816x(struct alc_softc *, int); 140 static int alc_attach(device_t); 141 static int alc_check_boundary(struct alc_softc *); 142 static void alc_config_msi(struct alc_softc *); 143 static int alc_detach(device_t); 144 static void alc_disable_l0s_l1(struct alc_softc *); 145 static int alc_dma_alloc(struct alc_softc *); 146 static void alc_dma_free(struct alc_softc *); 147 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 148 static void alc_dsp_fixup(struct alc_softc *, int); 149 static int alc_encap(struct alc_softc *, struct mbuf **); 150 static struct alc_ident * 151 alc_find_ident(device_t); 152 #ifndef __NO_STRICT_ALIGNMENT 153 static struct mbuf * 154 alc_fixup_rx(if_t, struct mbuf *); 155 #endif 156 static void alc_get_macaddr(struct alc_softc *); 157 static void alc_get_macaddr_813x(struct alc_softc *); 158 static void alc_get_macaddr_816x(struct alc_softc *); 159 static void alc_get_macaddr_par(struct alc_softc *); 160 static void alc_init(void *); 161 static void alc_init_cmb(struct alc_softc *); 162 static void alc_init_locked(struct alc_softc *); 163 static void alc_init_rr_ring(struct alc_softc *); 164 static int alc_init_rx_ring(struct alc_softc *); 165 static void alc_init_smb(struct alc_softc *); 166 static void alc_init_tx_ring(struct alc_softc *); 167 static void alc_int_task(void *, int); 168 static int alc_intr(void *); 169 static int alc_ioctl(if_t, u_long, caddr_t); 170 static void alc_mac_config(struct alc_softc *); 171 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 172 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 173 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 174 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 175 static int alc_miibus_readreg(device_t, int, int); 176 static void alc_miibus_statchg(device_t); 177 static int alc_miibus_writereg(device_t, int, int, int); 178 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 179 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 180 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 181 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 182 static int alc_mediachange(if_t); 183 static int alc_mediachange_locked(struct alc_softc *); 184 static void alc_mediastatus(if_t, struct ifmediareq *); 185 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 186 static void alc_osc_reset(struct alc_softc *); 187 static void alc_phy_down(struct alc_softc *); 188 static void alc_phy_reset(struct alc_softc *); 189 static void alc_phy_reset_813x(struct alc_softc *); 190 static void alc_phy_reset_816x(struct alc_softc *); 191 static int alc_probe(device_t); 192 static void alc_reset(struct alc_softc *); 193 static int alc_resume(device_t); 194 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 195 static int alc_rxintr(struct alc_softc *, int); 196 static void alc_rxfilter(struct alc_softc *); 197 static void alc_rxvlan(struct alc_softc *); 198 static void alc_setlinkspeed(struct alc_softc *); 199 static void alc_setwol(struct alc_softc *); 200 static void alc_setwol_813x(struct alc_softc *); 201 static void alc_setwol_816x(struct alc_softc *); 202 static int alc_shutdown(device_t); 203 static void alc_start(if_t); 204 static void alc_start_locked(if_t); 205 static void alc_start_queue(struct alc_softc *); 206 static void alc_start_tx(struct alc_softc *); 207 static void alc_stats_clear(struct alc_softc *); 208 static void alc_stats_update(struct alc_softc *); 209 static void alc_stop(struct alc_softc *); 210 static void alc_stop_mac(struct alc_softc *); 211 static void alc_stop_queue(struct alc_softc *); 212 static int alc_suspend(device_t); 213 static void alc_sysctl_node(struct alc_softc *); 214 static void alc_tick(void *); 215 static void alc_txeof(struct alc_softc *); 216 static void alc_watchdog(struct alc_softc *); 217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 218 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 219 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 220 221 DEBUGNET_DEFINE(alc); 222 223 static device_method_t alc_methods[] = { 224 /* Device interface. */ 225 DEVMETHOD(device_probe, alc_probe), 226 DEVMETHOD(device_attach, alc_attach), 227 DEVMETHOD(device_detach, alc_detach), 228 DEVMETHOD(device_shutdown, alc_shutdown), 229 DEVMETHOD(device_suspend, alc_suspend), 230 DEVMETHOD(device_resume, alc_resume), 231 232 /* MII interface. */ 233 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 234 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 235 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 236 237 DEVMETHOD_END 238 }; 239 240 static driver_t alc_driver = { 241 "alc", 242 alc_methods, 243 sizeof(struct alc_softc) 244 }; 245 246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 247 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 248 nitems(alc_ident_table) - 1); 249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 250 251 static struct resource_spec alc_res_spec_mem[] = { 252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 253 { -1, 0, 0 } 254 }; 255 256 static struct resource_spec alc_irq_spec_legacy[] = { 257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 258 { -1, 0, 0 } 259 }; 260 261 static struct resource_spec alc_irq_spec_msi[] = { 262 { SYS_RES_IRQ, 1, RF_ACTIVE }, 263 { -1, 0, 0 } 264 }; 265 266 static struct resource_spec alc_irq_spec_msix[] = { 267 { SYS_RES_IRQ, 1, RF_ACTIVE }, 268 { -1, 0, 0 } 269 }; 270 271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 272 273 static int 274 alc_miibus_readreg(device_t dev, int phy, int reg) 275 { 276 struct alc_softc *sc; 277 int v; 278 279 sc = device_get_softc(dev); 280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 281 v = alc_mii_readreg_816x(sc, phy, reg); 282 else 283 v = alc_mii_readreg_813x(sc, phy, reg); 284 return (v); 285 } 286 287 static uint32_t 288 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 289 { 290 uint32_t v; 291 int i; 292 293 /* 294 * For AR8132 fast ethernet controller, do not report 1000baseT 295 * capability to mii(4). Even though AR8132 uses the same 296 * model/revision number of F1 gigabit PHY, the PHY has no 297 * ability to establish 1000baseT link. 298 */ 299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 300 reg == MII_EXTSR) 301 return (0); 302 303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 304 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 306 DELAY(5); 307 v = CSR_READ_4(sc, ALC_MDIO); 308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 309 break; 310 } 311 312 if (i == 0) { 313 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 314 return (0); 315 } 316 317 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 318 } 319 320 static uint32_t 321 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 322 { 323 uint32_t clk, v; 324 int i; 325 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 327 clk = MDIO_CLK_25_128; 328 else 329 clk = MDIO_CLK_25_4; 330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 331 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 333 DELAY(5); 334 v = CSR_READ_4(sc, ALC_MDIO); 335 if ((v & MDIO_OP_BUSY) == 0) 336 break; 337 } 338 339 if (i == 0) { 340 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 341 return (0); 342 } 343 344 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 345 } 346 347 static int 348 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 349 { 350 struct alc_softc *sc; 351 int v; 352 353 sc = device_get_softc(dev); 354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 355 v = alc_mii_writereg_816x(sc, phy, reg, val); 356 else 357 v = alc_mii_writereg_813x(sc, phy, reg, val); 358 return (v); 359 } 360 361 static uint32_t 362 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 363 { 364 uint32_t v; 365 int i; 366 367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 368 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 369 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 v = CSR_READ_4(sc, ALC_MDIO); 373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 374 break; 375 } 376 377 if (i == 0) 378 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 379 380 return (0); 381 } 382 383 static uint32_t 384 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 385 { 386 uint32_t clk, v; 387 int i; 388 389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 390 clk = MDIO_CLK_25_128; 391 else 392 clk = MDIO_CLK_25_4; 393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 394 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 395 MDIO_SUP_PREAMBLE | clk); 396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 397 DELAY(5); 398 v = CSR_READ_4(sc, ALC_MDIO); 399 if ((v & MDIO_OP_BUSY) == 0) 400 break; 401 } 402 403 if (i == 0) 404 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 405 406 return (0); 407 } 408 409 static void 410 alc_miibus_statchg(device_t dev) 411 { 412 struct alc_softc *sc; 413 struct mii_data *mii; 414 if_t ifp; 415 uint32_t reg; 416 417 sc = device_get_softc(dev); 418 419 mii = device_get_softc(sc->alc_miibus); 420 ifp = sc->alc_ifp; 421 if (mii == NULL || ifp == NULL || 422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 423 return; 424 425 sc->alc_flags &= ~ALC_FLAG_LINK; 426 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 427 (IFM_ACTIVE | IFM_AVALID)) { 428 switch (IFM_SUBTYPE(mii->mii_media_active)) { 429 case IFM_10_T: 430 case IFM_100_TX: 431 sc->alc_flags |= ALC_FLAG_LINK; 432 break; 433 case IFM_1000_T: 434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 435 sc->alc_flags |= ALC_FLAG_LINK; 436 break; 437 default: 438 break; 439 } 440 } 441 /* Stop Rx/Tx MACs. */ 442 alc_stop_mac(sc); 443 444 /* Program MACs with resolved speed/duplex/flow-control. */ 445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 446 alc_start_queue(sc); 447 alc_mac_config(sc); 448 /* Re-enable Tx/Rx MACs. */ 449 reg = CSR_READ_4(sc, ALC_MAC_CFG); 450 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 452 } 453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 454 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 455 } 456 457 static uint32_t 458 alc_miidbg_readreg(struct alc_softc *sc, int reg) 459 { 460 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 462 reg); 463 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA)); 465 } 466 467 static uint32_t 468 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 469 { 470 471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 472 reg); 473 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 474 ALC_MII_DBG_DATA, val)); 475 } 476 477 static uint32_t 478 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 479 { 480 uint32_t clk, v; 481 int i; 482 483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 484 EXT_MDIO_DEVADDR(devaddr)); 485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 486 clk = MDIO_CLK_25_128; 487 else 488 clk = MDIO_CLK_25_4; 489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 490 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 492 DELAY(5); 493 v = CSR_READ_4(sc, ALC_MDIO); 494 if ((v & MDIO_OP_BUSY) == 0) 495 break; 496 } 497 498 if (i == 0) { 499 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 500 devaddr, reg); 501 return (0); 502 } 503 504 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 505 } 506 507 static uint32_t 508 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 509 { 510 uint32_t clk, v; 511 int i; 512 513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 514 EXT_MDIO_DEVADDR(devaddr)); 515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 516 clk = MDIO_CLK_25_128; 517 else 518 clk = MDIO_CLK_25_4; 519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 520 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 521 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 523 DELAY(5); 524 v = CSR_READ_4(sc, ALC_MDIO); 525 if ((v & MDIO_OP_BUSY) == 0) 526 break; 527 } 528 529 if (i == 0) 530 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 531 devaddr, reg); 532 533 return (0); 534 } 535 536 static void 537 alc_dsp_fixup(struct alc_softc *sc, int media) 538 { 539 uint16_t agc, len, val; 540 541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 542 return; 543 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 544 return; 545 546 /* 547 * Vendor PHY magic. 548 * 1000BT/AZ, wrong cable length 549 */ 550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 551 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 552 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 553 EXT_CLDCTL6_CAB_LEN_MASK; 554 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 555 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 556 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 557 agc > DBG_AGC_LONG1G_LIMT) || 558 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 559 agc > DBG_AGC_LONG1G_LIMT)) { 560 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 561 DBG_AZ_ANADECT_LONG); 562 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 563 MII_EXT_ANEG_AFE); 564 val |= ANEG_AFEE_10BT_100M_TH; 565 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 566 val); 567 } else { 568 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 569 DBG_AZ_ANADECT_DEFAULT); 570 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 571 MII_EXT_ANEG_AFE); 572 val &= ~ANEG_AFEE_10BT_100M_TH; 573 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 574 val); 575 } 576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 577 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 578 if (media == IFM_1000_T) { 579 /* 580 * Giga link threshold, raise the tolerance of 581 * noise 50%. 582 */ 583 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 584 val &= ~DBG_MSE20DB_TH_MASK; 585 val |= (DBG_MSE20DB_TH_HI << 586 DBG_MSE20DB_TH_SHIFT); 587 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 588 } else if (media == IFM_100_TX) 589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 590 DBG_MSE16DB_UP); 591 } 592 } else { 593 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 594 val &= ~ANEG_AFEE_10BT_100M_TH; 595 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 597 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 598 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 599 DBG_MSE16DB_DOWN); 600 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 601 val &= ~DBG_MSE20DB_TH_MASK; 602 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 603 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 604 } 605 } 606 } 607 608 static void 609 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 610 { 611 struct alc_softc *sc; 612 struct mii_data *mii; 613 614 sc = if_getsoftc(ifp); 615 ALC_LOCK(sc); 616 if ((if_getflags(ifp) & IFF_UP) == 0) { 617 ALC_UNLOCK(sc); 618 return; 619 } 620 mii = device_get_softc(sc->alc_miibus); 621 622 mii_pollstat(mii); 623 ifmr->ifm_status = mii->mii_media_status; 624 ifmr->ifm_active = mii->mii_media_active; 625 ALC_UNLOCK(sc); 626 } 627 628 static int 629 alc_mediachange(if_t ifp) 630 { 631 struct alc_softc *sc; 632 int error; 633 634 sc = if_getsoftc(ifp); 635 ALC_LOCK(sc); 636 error = alc_mediachange_locked(sc); 637 ALC_UNLOCK(sc); 638 639 return (error); 640 } 641 642 static int 643 alc_mediachange_locked(struct alc_softc *sc) 644 { 645 struct mii_data *mii; 646 struct mii_softc *miisc; 647 int error; 648 649 ALC_LOCK_ASSERT(sc); 650 651 mii = device_get_softc(sc->alc_miibus); 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 PHY_RESET(miisc); 654 error = mii_mediachg(mii); 655 656 return (error); 657 } 658 659 static struct alc_ident * 660 alc_find_ident(device_t dev) 661 { 662 struct alc_ident *ident; 663 uint16_t vendor, devid; 664 665 vendor = pci_get_vendor(dev); 666 devid = pci_get_device(dev); 667 for (ident = alc_ident_table; ident->name != NULL; ident++) { 668 if (vendor == ident->vendorid && devid == ident->deviceid) 669 return (ident); 670 } 671 672 return (NULL); 673 } 674 675 static int 676 alc_probe(device_t dev) 677 { 678 struct alc_ident *ident; 679 680 ident = alc_find_ident(dev); 681 if (ident != NULL) { 682 device_set_desc(dev, ident->name); 683 return (BUS_PROBE_DEFAULT); 684 } 685 686 return (ENXIO); 687 } 688 689 static void 690 alc_get_macaddr(struct alc_softc *sc) 691 { 692 693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 694 alc_get_macaddr_816x(sc); 695 else 696 alc_get_macaddr_813x(sc); 697 } 698 699 static void 700 alc_get_macaddr_813x(struct alc_softc *sc) 701 { 702 uint32_t opt; 703 uint16_t val; 704 int eeprom, i; 705 706 eeprom = 0; 707 opt = CSR_READ_4(sc, ALC_OPT_CFG); 708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 710 /* 711 * EEPROM found, let TWSI reload EEPROM configuration. 712 * This will set ethernet address of controller. 713 */ 714 eeprom++; 715 switch (sc->alc_ident->deviceid) { 716 case DEVICEID_ATHEROS_AR8131: 717 case DEVICEID_ATHEROS_AR8132: 718 if ((opt & OPT_CFG_CLK_ENB) == 0) { 719 opt |= OPT_CFG_CLK_ENB; 720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 721 CSR_READ_4(sc, ALC_OPT_CFG); 722 DELAY(1000); 723 } 724 break; 725 case DEVICEID_ATHEROS_AR8151: 726 case DEVICEID_ATHEROS_AR8151_V2: 727 case DEVICEID_ATHEROS_AR8152_B: 728 case DEVICEID_ATHEROS_AR8152_B2: 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_ADDR, 0x00); 731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 732 ALC_MII_DBG_DATA); 733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 734 ALC_MII_DBG_DATA, val & 0xFF7F); 735 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 736 ALC_MII_DBG_ADDR, 0x3B); 737 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 738 ALC_MII_DBG_DATA); 739 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 740 ALC_MII_DBG_DATA, val | 0x0008); 741 DELAY(20); 742 break; 743 } 744 745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 748 CSR_READ_4(sc, ALC_WOL_CFG); 749 750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 751 TWSI_CFG_SW_LD_START); 752 for (i = 100; i > 0; i--) { 753 DELAY(1000); 754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 755 TWSI_CFG_SW_LD_START) == 0) 756 break; 757 } 758 if (i == 0) 759 device_printf(sc->alc_dev, 760 "reloading EEPROM timeout!\n"); 761 } else { 762 if (bootverbose) 763 device_printf(sc->alc_dev, "EEPROM not found!\n"); 764 } 765 if (eeprom != 0) { 766 switch (sc->alc_ident->deviceid) { 767 case DEVICEID_ATHEROS_AR8131: 768 case DEVICEID_ATHEROS_AR8132: 769 if ((opt & OPT_CFG_CLK_ENB) != 0) { 770 opt &= ~OPT_CFG_CLK_ENB; 771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 772 CSR_READ_4(sc, ALC_OPT_CFG); 773 DELAY(1000); 774 } 775 break; 776 case DEVICEID_ATHEROS_AR8151: 777 case DEVICEID_ATHEROS_AR8151_V2: 778 case DEVICEID_ATHEROS_AR8152_B: 779 case DEVICEID_ATHEROS_AR8152_B2: 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_ADDR, 0x00); 782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 783 ALC_MII_DBG_DATA); 784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 785 ALC_MII_DBG_DATA, val | 0x0080); 786 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x3B); 788 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA); 790 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 791 ALC_MII_DBG_DATA, val & 0xFFF7); 792 DELAY(20); 793 break; 794 } 795 } 796 797 alc_get_macaddr_par(sc); 798 } 799 800 static void 801 alc_get_macaddr_816x(struct alc_softc *sc) 802 { 803 uint32_t reg; 804 int i, reloaded; 805 806 reloaded = 0; 807 /* Try to reload station address via TWSI. */ 808 for (i = 100; i > 0; i--) { 809 reg = CSR_READ_4(sc, ALC_SLD); 810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 811 break; 812 DELAY(1000); 813 } 814 if (i != 0) { 815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 816 for (i = 100; i > 0; i--) { 817 DELAY(1000); 818 reg = CSR_READ_4(sc, ALC_SLD); 819 if ((reg & SLD_START) == 0) 820 break; 821 } 822 if (i != 0) 823 reloaded++; 824 else if (bootverbose) 825 device_printf(sc->alc_dev, 826 "reloading station address via TWSI timed out!\n"); 827 } 828 829 /* Try to reload station address from EEPROM or FLASH. */ 830 if (reloaded == 0) { 831 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 832 if ((reg & (EEPROM_LD_EEPROM_EXIST | 833 EEPROM_LD_FLASH_EXIST)) != 0) { 834 for (i = 100; i > 0; i--) { 835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 836 if ((reg & (EEPROM_LD_PROGRESS | 837 EEPROM_LD_START)) == 0) 838 break; 839 DELAY(1000); 840 } 841 if (i != 0) { 842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 843 EEPROM_LD_START); 844 for (i = 100; i > 0; i--) { 845 DELAY(1000); 846 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 847 if ((reg & EEPROM_LD_START) == 0) 848 break; 849 } 850 } else if (bootverbose) 851 device_printf(sc->alc_dev, 852 "reloading EEPROM/FLASH timed out!\n"); 853 } 854 } 855 856 alc_get_macaddr_par(sc); 857 } 858 859 static void 860 alc_get_macaddr_par(struct alc_softc *sc) 861 { 862 uint32_t ea[2]; 863 864 ea[0] = CSR_READ_4(sc, ALC_PAR0); 865 ea[1] = CSR_READ_4(sc, ALC_PAR1); 866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 872 } 873 874 static void 875 alc_disable_l0s_l1(struct alc_softc *sc) 876 { 877 uint32_t pmcfg; 878 879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 880 /* Another magic from vendor. */ 881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 882 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 883 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 884 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 885 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 886 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 888 } 889 } 890 891 static void 892 alc_phy_reset(struct alc_softc *sc) 893 { 894 895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 896 alc_phy_reset_816x(sc); 897 else 898 alc_phy_reset_813x(sc); 899 } 900 901 static void 902 alc_phy_reset_813x(struct alc_softc *sc) 903 { 904 uint16_t data; 905 906 /* Reset magic from Linux. */ 907 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 908 CSR_READ_2(sc, ALC_GPHY_CFG); 909 DELAY(10 * 1000); 910 911 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 912 GPHY_CFG_SEL_ANA_RESET); 913 CSR_READ_2(sc, ALC_GPHY_CFG); 914 DELAY(10 * 1000); 915 916 /* DSP fixup, Vendor magic. */ 917 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, 0x000A); 920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA); 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA, data & 0xDFFF); 924 } 925 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_ADDR, 0x003B); 931 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_DATA); 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_DATA, data & 0xFFF7); 935 DELAY(20 * 1000); 936 } 937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_ADDR, 0x0029); 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_DATA, 0x929D); 942 } 943 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 946 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_ADDR, 0x0029); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_DATA, 0xB6DD); 951 } 952 953 /* Load DSP codes, vendor magic. */ 954 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 955 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 957 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 959 ALC_MII_DBG_DATA, data); 960 961 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 962 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 963 ANA_SERDES_EN_LCKDT; 964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 965 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 967 ALC_MII_DBG_DATA, data); 968 969 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 970 ANA_LONG_CABLE_TH_100_MASK) | 971 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 972 ANA_SHORT_CABLE_TH_100_SHIFT) | 973 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_DATA, data); 978 979 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 980 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 981 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 982 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 984 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 986 ALC_MII_DBG_DATA, data); 987 988 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 989 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 990 ANA_OEN_125M; 991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 992 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 994 ALC_MII_DBG_DATA, data); 995 DELAY(1000); 996 997 /* Disable hibernation. */ 998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 999 0x0029); 1000 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1001 ALC_MII_DBG_DATA); 1002 data &= ~0x8000; 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1004 data); 1005 1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1007 0x000B); 1008 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1009 ALC_MII_DBG_DATA); 1010 data &= ~0x8000; 1011 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1012 data); 1013 } 1014 1015 static void 1016 alc_phy_reset_816x(struct alc_softc *sc) 1017 { 1018 uint32_t val; 1019 1020 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1021 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1022 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1023 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1024 val |= GPHY_CFG_SEL_ANA_RESET; 1025 #ifdef notyet 1026 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1027 #else 1028 /* Disable PHY hibernation. */ 1029 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1030 #endif 1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1032 DELAY(10); 1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1034 DELAY(800); 1035 1036 /* Vendor PHY magic. */ 1037 #ifdef notyet 1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1039 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1040 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1041 EXT_VDRVBIAS_DEFAULT); 1042 #else 1043 /* Disable PHY hibernation. */ 1044 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1045 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1046 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1047 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1048 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1049 #endif 1050 1051 /* XXX Disable EEE. */ 1052 val = CSR_READ_4(sc, ALC_LPI_CTL); 1053 val &= ~LPI_CTL_ENB; 1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1056 1057 /* PHY power saving. */ 1058 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1061 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1062 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1063 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1064 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1065 1066 /* RTL8139C, 120m issue. */ 1067 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1068 ANEG_NLP78_120M_DEFAULT); 1069 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1070 ANEG_S3DIG10_DEFAULT); 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1073 /* Turn off half amplitude. */ 1074 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1075 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1076 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1077 /* Turn off Green feature. */ 1078 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1079 val |= DBG_GREENCFG2_BP_GREEN; 1080 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1081 /* Turn off half bias. */ 1082 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1083 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1084 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1085 } 1086 } 1087 1088 static void 1089 alc_phy_down(struct alc_softc *sc) 1090 { 1091 uint32_t gphy; 1092 1093 switch (sc->alc_ident->deviceid) { 1094 case DEVICEID_ATHEROS_AR8161: 1095 case DEVICEID_ATHEROS_E2200: 1096 case DEVICEID_ATHEROS_E2400: 1097 case DEVICEID_ATHEROS_E2500: 1098 case DEVICEID_ATHEROS_AR8162: 1099 case DEVICEID_ATHEROS_AR8171: 1100 case DEVICEID_ATHEROS_AR8172: 1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1102 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1103 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1104 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1105 GPHY_CFG_SEL_ANA_RESET; 1106 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1108 break; 1109 case DEVICEID_ATHEROS_AR8151: 1110 case DEVICEID_ATHEROS_AR8151_V2: 1111 case DEVICEID_ATHEROS_AR8152_B: 1112 case DEVICEID_ATHEROS_AR8152_B2: 1113 /* 1114 * GPHY power down caused more problems on AR8151 v2.0. 1115 * When driver is reloaded after GPHY power down, 1116 * accesses to PHY/MAC registers hung the system. Only 1117 * cold boot recovered from it. I'm not sure whether 1118 * AR8151 v1.0 also requires this one though. I don't 1119 * have AR8151 v1.0 controller in hand. 1120 * The only option left is to isolate the PHY and 1121 * initiates power down the PHY which in turn saves 1122 * more power when driver is unloaded. 1123 */ 1124 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1125 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1126 break; 1127 default: 1128 /* Force PHY down. */ 1129 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1130 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1131 GPHY_CFG_PWDOWN_HW); 1132 DELAY(1000); 1133 break; 1134 } 1135 } 1136 1137 static void 1138 alc_aspm(struct alc_softc *sc, int init, int media) 1139 { 1140 1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1142 alc_aspm_816x(sc, init); 1143 else 1144 alc_aspm_813x(sc, media); 1145 } 1146 1147 static void 1148 alc_aspm_813x(struct alc_softc *sc, int media) 1149 { 1150 uint32_t pmcfg; 1151 uint16_t linkcfg; 1152 1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1154 return; 1155 1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1157 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1158 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1159 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1160 PCIER_LINK_CTL); 1161 else 1162 linkcfg = 0; 1163 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1164 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1165 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1166 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1167 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1168 1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1170 /* Disable extended sync except AR8152 B v1.0 */ 1171 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1173 sc->alc_rev == ATHEROS_AR8152_B_V10) 1174 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1175 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1176 linkcfg); 1177 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1178 PM_CFG_HOTRST); 1179 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1180 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1181 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1182 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1183 PM_CFG_PM_REQ_TIMER_SHIFT); 1184 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1185 } 1186 1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1189 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1191 pmcfg |= PM_CFG_ASPM_L1_ENB; 1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1193 if (sc->alc_ident->deviceid == 1194 DEVICEID_ATHEROS_AR8152_B) 1195 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1196 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1197 PM_CFG_SERDES_PLL_L1_ENB | 1198 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1199 pmcfg |= PM_CFG_CLK_SWH_L1; 1200 if (media == IFM_100_TX || media == IFM_1000_T) { 1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1202 switch (sc->alc_ident->deviceid) { 1203 case DEVICEID_ATHEROS_AR8152_B: 1204 pmcfg |= (7 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 case DEVICEID_ATHEROS_AR8152_B2: 1208 case DEVICEID_ATHEROS_AR8151_V2: 1209 pmcfg |= (4 << 1210 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1211 break; 1212 default: 1213 pmcfg |= (15 << 1214 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1215 break; 1216 } 1217 } 1218 } else { 1219 pmcfg |= PM_CFG_SERDES_L1_ENB | 1220 PM_CFG_SERDES_PLL_L1_ENB | 1221 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1222 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1223 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1224 } 1225 } else { 1226 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1227 PM_CFG_SERDES_PLL_L1_ENB); 1228 pmcfg |= PM_CFG_CLK_SWH_L1; 1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1230 pmcfg |= PM_CFG_ASPM_L1_ENB; 1231 } 1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1233 } 1234 1235 static void 1236 alc_aspm_816x(struct alc_softc *sc, int init) 1237 { 1238 uint32_t pmcfg; 1239 1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1241 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1242 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1243 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1244 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1245 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1246 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1247 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1248 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1249 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1250 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1251 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1252 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1253 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1254 (sc->alc_rev & 0x01) != 0) 1255 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1257 /* Link up, enable both L0s, L1s. */ 1258 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1259 PM_CFG_MAC_ASPM_CHK; 1260 } else { 1261 if (init != 0) 1262 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1263 PM_CFG_MAC_ASPM_CHK; 1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1265 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1266 } 1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1268 } 1269 1270 static void 1271 alc_init_pcie(struct alc_softc *sc) 1272 { 1273 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1274 uint32_t cap, ctl, val; 1275 int state; 1276 1277 /* Clear data link and flow-control protocol error. */ 1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1279 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1281 1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1287 PCIE_PHYMISC_FORCE_RCV_DET); 1288 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1289 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1291 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1292 PCIE_PHYMISC2_SERDES_TH_MASK); 1293 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1294 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1296 } 1297 /* Disable ASPM L0S and L1. */ 1298 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1300 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1302 sc->alc_rcb = DMA_CFG_RCB_128; 1303 if (bootverbose) 1304 device_printf(sc->alc_dev, "RCB %u bytes\n", 1305 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1306 state = ctl & PCIEM_LINK_CTL_ASPMC; 1307 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1308 sc->alc_flags |= ALC_FLAG_L0S; 1309 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1310 sc->alc_flags |= ALC_FLAG_L1S; 1311 if (bootverbose) 1312 device_printf(sc->alc_dev, "ASPM %s %s\n", 1313 aspm_state[state], 1314 state == 0 ? "disabled" : "enabled"); 1315 alc_disable_l0s_l1(sc); 1316 } else { 1317 if (bootverbose) 1318 device_printf(sc->alc_dev, 1319 "no ASPM support\n"); 1320 } 1321 } else { 1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1323 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1325 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1326 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1327 (sc->alc_rev & 0x01) != 0) { 1328 if ((val & MASTER_WAKEN_25M) == 0 || 1329 (val & MASTER_CLK_SEL_DIS) == 0) { 1330 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1332 } 1333 } else { 1334 if ((val & MASTER_WAKEN_25M) == 0 || 1335 (val & MASTER_CLK_SEL_DIS) != 0) { 1336 val |= MASTER_WAKEN_25M; 1337 val &= ~MASTER_CLK_SEL_DIS; 1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1339 } 1340 } 1341 } 1342 alc_aspm(sc, 1, IFM_UNKNOWN); 1343 } 1344 1345 static void 1346 alc_config_msi(struct alc_softc *sc) 1347 { 1348 uint32_t ctl, mod; 1349 1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1351 /* 1352 * It seems interrupt moderation is controlled by 1353 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1354 * Driver uses RX interrupt moderation parameter to 1355 * program ALC_MSI_RETRANS_TIMER register. 1356 */ 1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1358 ctl &= ~MSI_RETRANS_TIMER_MASK; 1359 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1360 mod = ALC_USECS(sc->alc_int_rx_mod); 1361 if (mod == 0) 1362 mod = 1; 1363 ctl |= mod; 1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_STD); 1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1369 MSI_RETRANS_MASK_SEL_LINE); 1370 else 1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1372 } 1373 } 1374 1375 static int 1376 alc_attach(device_t dev) 1377 { 1378 struct alc_softc *sc; 1379 if_t ifp; 1380 int base, error, i, msic, msixc; 1381 uint16_t burst; 1382 1383 error = 0; 1384 sc = device_get_softc(dev); 1385 sc->alc_dev = dev; 1386 sc->alc_rev = pci_get_revid(dev); 1387 1388 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1389 MTX_DEF); 1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1392 sc->alc_ident = alc_find_ident(dev); 1393 1394 /* Map the device. */ 1395 pci_enable_busmaster(dev); 1396 sc->alc_res_spec = alc_res_spec_mem; 1397 sc->alc_irq_spec = alc_irq_spec_legacy; 1398 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1399 if (error != 0) { 1400 device_printf(dev, "cannot allocate memory resources.\n"); 1401 goto fail; 1402 } 1403 1404 /* Set PHY address. */ 1405 sc->alc_phyaddr = ALC_PHY_ADDR; 1406 1407 /* 1408 * One odd thing is AR8132 uses the same PHY hardware(F1 1409 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1410 * the PHY supports 1000Mbps but that's not true. The PHY 1411 * used in AR8132 can't establish gigabit link even if it 1412 * shows the same PHY model/revision number of AR8131. 1413 */ 1414 switch (sc->alc_ident->deviceid) { 1415 case DEVICEID_ATHEROS_E2200: 1416 case DEVICEID_ATHEROS_E2400: 1417 case DEVICEID_ATHEROS_E2500: 1418 sc->alc_flags |= ALC_FLAG_E2X00; 1419 1420 /* 1421 * Disable MSI-X by default on Killer devices, since this is 1422 * reported by several users to not work well. 1423 */ 1424 if (msix_disable == 2) 1425 msix_disable = 1; 1426 1427 /* FALLTHROUGH */ 1428 case DEVICEID_ATHEROS_AR8161: 1429 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1431 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8171: 1434 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1435 break; 1436 case DEVICEID_ATHEROS_AR8162: 1437 case DEVICEID_ATHEROS_AR8172: 1438 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1439 break; 1440 case DEVICEID_ATHEROS_AR8152_B: 1441 case DEVICEID_ATHEROS_AR8152_B2: 1442 sc->alc_flags |= ALC_FLAG_APS; 1443 /* FALLTHROUGH */ 1444 case DEVICEID_ATHEROS_AR8132: 1445 sc->alc_flags |= ALC_FLAG_FASTETHER; 1446 break; 1447 case DEVICEID_ATHEROS_AR8151: 1448 case DEVICEID_ATHEROS_AR8151_V2: 1449 sc->alc_flags |= ALC_FLAG_APS; 1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1451 sc->alc_flags |= ALC_FLAG_MT; 1452 /* FALLTHROUGH */ 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * The default value of msix_disable is 2, which means auto-detect. If 1459 * we didn't auto-detect it, default to enabling it. 1460 */ 1461 if (msix_disable == 2) 1462 msix_disable = 0; 1463 1464 sc->alc_flags |= ALC_FLAG_JUMBO; 1465 1466 /* 1467 * It seems that AR813x/AR815x has silicon bug for SMB. In 1468 * addition, Atheros said that enabling SMB wouldn't improve 1469 * performance. However I think it's bad to access lots of 1470 * registers to extract MAC statistics. 1471 */ 1472 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1473 /* 1474 * Don't use Tx CMB. It is known to have silicon bug. 1475 */ 1476 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1478 MASTER_CHIP_REV_SHIFT; 1479 if (bootverbose) { 1480 device_printf(dev, "PCI device revision : 0x%04x\n", 1481 sc->alc_rev); 1482 device_printf(dev, "Chip id/revision : 0x%04x\n", 1483 sc->alc_chip_rev); 1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1485 device_printf(dev, "AR816x revision : 0x%x\n", 1486 AR816X_REV(sc->alc_rev)); 1487 } 1488 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1491 1492 /* Initialize DMA parameters. */ 1493 sc->alc_dma_rd_burst = 0; 1494 sc->alc_dma_wr_burst = 0; 1495 sc->alc_rcb = DMA_CFG_RCB_64; 1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1497 sc->alc_flags |= ALC_FLAG_PCIE; 1498 sc->alc_expcap = base; 1499 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1500 sc->alc_dma_rd_burst = 1501 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1502 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1503 if (bootverbose) { 1504 device_printf(dev, "Read request size : %u bytes.\n", 1505 alc_dma_burst[sc->alc_dma_rd_burst]); 1506 device_printf(dev, "TLP payload size : %u bytes.\n", 1507 alc_dma_burst[sc->alc_dma_wr_burst]); 1508 } 1509 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1510 sc->alc_dma_rd_burst = 3; 1511 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1512 sc->alc_dma_wr_burst = 3; 1513 /* 1514 * Force maximum payload size to 128 bytes for 1515 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1516 * Otherwise it triggers DMA write error. 1517 */ 1518 if ((sc->alc_flags & 1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1520 sc->alc_dma_wr_burst = 0; 1521 alc_init_pcie(sc); 1522 } 1523 1524 /* Reset PHY. */ 1525 alc_phy_reset(sc); 1526 1527 /* Reset the ethernet controller. */ 1528 alc_stop_mac(sc); 1529 alc_reset(sc); 1530 1531 /* Allocate IRQ resources. */ 1532 msixc = pci_msix_count(dev); 1533 msic = pci_msi_count(dev); 1534 if (bootverbose) { 1535 device_printf(dev, "MSIX count : %d\n", msixc); 1536 device_printf(dev, "MSI count : %d\n", msic); 1537 } 1538 if (msixc > 1) 1539 msixc = 1; 1540 if (msic > 1) 1541 msic = 1; 1542 /* 1543 * Prefer MSIX over MSI. 1544 * AR816x controller has a silicon bug that MSI interrupt 1545 * does not assert if PCIM_CMD_INTxDIS bit of command 1546 * register is set. pci(4) was taught to handle that case. 1547 */ 1548 if (msix_disable == 0 || msi_disable == 0) { 1549 if (msix_disable == 0 && msixc > 0 && 1550 pci_alloc_msix(dev, &msixc) == 0) { 1551 if (msic == 1) { 1552 device_printf(dev, 1553 "Using %d MSIX message(s).\n", msixc); 1554 sc->alc_flags |= ALC_FLAG_MSIX; 1555 sc->alc_irq_spec = alc_irq_spec_msix; 1556 } else 1557 pci_release_msi(dev); 1558 } 1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1561 if (msic == 1) { 1562 device_printf(dev, 1563 "Using %d MSI message(s).\n", msic); 1564 sc->alc_flags |= ALC_FLAG_MSI; 1565 sc->alc_irq_spec = alc_irq_spec_msi; 1566 } else 1567 pci_release_msi(dev); 1568 } 1569 } 1570 1571 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1572 if (error != 0) { 1573 device_printf(dev, "cannot allocate IRQ resources.\n"); 1574 goto fail; 1575 } 1576 1577 /* Create device sysctl node. */ 1578 alc_sysctl_node(sc); 1579 1580 if ((error = alc_dma_alloc(sc)) != 0) 1581 goto fail; 1582 1583 /* Load station address. */ 1584 alc_get_macaddr(sc); 1585 1586 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1587 if_setsoftc(ifp, sc); 1588 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1589 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1590 if_setioctlfn(ifp, alc_ioctl); 1591 if_setstartfn(ifp, alc_start); 1592 if_setinitfn(ifp, alc_init); 1593 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1594 if_setsendqready(ifp); 1595 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1596 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1597 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1598 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1599 sc->alc_flags |= ALC_FLAG_PM; 1600 sc->alc_pmcap = base; 1601 } 1602 if_setcapenable(ifp, if_getcapabilities(ifp)); 1603 1604 /* Set up MII bus. */ 1605 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1606 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1607 MIIF_DOPAUSE); 1608 if (error != 0) { 1609 device_printf(dev, "attaching PHYs failed\n"); 1610 goto fail; 1611 } 1612 1613 ether_ifattach(ifp, sc->alc_eaddr); 1614 1615 /* VLAN capability setup. */ 1616 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1617 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1618 if_setcapenable(ifp, if_getcapabilities(ifp)); 1619 /* 1620 * XXX 1621 * It seems enabling Tx checksum offloading makes more trouble. 1622 * Sometimes the controller does not receive any frames when 1623 * Tx checksum offloading is enabled. I'm not sure whether this 1624 * is a bug in Tx checksum offloading logic or I got broken 1625 * sample boards. To safety, don't enable Tx checksum offloading 1626 * by default but give chance to users to toggle it if they know 1627 * their controllers work without problems. 1628 * Fortunately, Tx checksum offloading for AR816x family 1629 * seems to work. 1630 */ 1631 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1632 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1633 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1634 } 1635 1636 /* Tell the upper layer(s) we support long frames. */ 1637 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1638 1639 /* Create local taskq. */ 1640 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1641 taskqueue_thread_enqueue, &sc->alc_tq); 1642 if (sc->alc_tq == NULL) { 1643 device_printf(dev, "could not create taskqueue.\n"); 1644 ether_ifdetach(ifp); 1645 error = ENXIO; 1646 goto fail; 1647 } 1648 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1649 device_get_nameunit(sc->alc_dev)); 1650 1651 alc_config_msi(sc); 1652 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1653 msic = ALC_MSIX_MESSAGES; 1654 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1655 msic = ALC_MSI_MESSAGES; 1656 else 1657 msic = 1; 1658 for (i = 0; i < msic; i++) { 1659 error = bus_setup_intr(dev, sc->alc_irq[i], 1660 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1661 &sc->alc_intrhand[i]); 1662 if (error != 0) 1663 break; 1664 } 1665 if (error != 0) { 1666 device_printf(dev, "could not set up interrupt handler.\n"); 1667 taskqueue_free(sc->alc_tq); 1668 sc->alc_tq = NULL; 1669 ether_ifdetach(ifp); 1670 goto fail; 1671 } 1672 1673 /* Attach driver debugnet methods. */ 1674 DEBUGNET_SET(ifp, alc); 1675 1676 fail: 1677 if (error != 0) 1678 alc_detach(dev); 1679 1680 return (error); 1681 } 1682 1683 static int 1684 alc_detach(device_t dev) 1685 { 1686 struct alc_softc *sc; 1687 if_t ifp; 1688 int i, msic; 1689 1690 sc = device_get_softc(dev); 1691 1692 ifp = sc->alc_ifp; 1693 if (device_is_attached(dev)) { 1694 ether_ifdetach(ifp); 1695 ALC_LOCK(sc); 1696 alc_stop(sc); 1697 ALC_UNLOCK(sc); 1698 callout_drain(&sc->alc_tick_ch); 1699 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1700 } 1701 1702 if (sc->alc_tq != NULL) { 1703 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1704 taskqueue_free(sc->alc_tq); 1705 sc->alc_tq = NULL; 1706 } 1707 1708 if (sc->alc_miibus != NULL) { 1709 device_delete_child(dev, sc->alc_miibus); 1710 sc->alc_miibus = NULL; 1711 } 1712 bus_generic_detach(dev); 1713 alc_dma_free(sc); 1714 1715 if (ifp != NULL) { 1716 if_free(ifp); 1717 sc->alc_ifp = NULL; 1718 } 1719 1720 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1721 msic = ALC_MSIX_MESSAGES; 1722 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1723 msic = ALC_MSI_MESSAGES; 1724 else 1725 msic = 1; 1726 for (i = 0; i < msic; i++) { 1727 if (sc->alc_intrhand[i] != NULL) { 1728 bus_teardown_intr(dev, sc->alc_irq[i], 1729 sc->alc_intrhand[i]); 1730 sc->alc_intrhand[i] = NULL; 1731 } 1732 } 1733 if (sc->alc_res[0] != NULL) 1734 alc_phy_down(sc); 1735 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1736 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1737 pci_release_msi(dev); 1738 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1739 mtx_destroy(&sc->alc_mtx); 1740 1741 return (0); 1742 } 1743 1744 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1745 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1746 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1747 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1748 1749 static void 1750 alc_sysctl_node(struct alc_softc *sc) 1751 { 1752 struct sysctl_ctx_list *ctx; 1753 struct sysctl_oid_list *child, *parent; 1754 struct sysctl_oid *tree; 1755 struct alc_hw_stats *stats; 1756 int error; 1757 1758 stats = &sc->alc_stats; 1759 ctx = device_get_sysctl_ctx(sc->alc_dev); 1760 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1761 1762 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1763 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1764 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1765 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1766 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1767 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1768 /* Pull in device tunables. */ 1769 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1770 error = resource_int_value(device_get_name(sc->alc_dev), 1771 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1772 if (error == 0) { 1773 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1774 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1775 device_printf(sc->alc_dev, "int_rx_mod value out of " 1776 "range; using default: %d\n", 1777 ALC_IM_RX_TIMER_DEFAULT); 1778 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1779 } 1780 } 1781 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1782 error = resource_int_value(device_get_name(sc->alc_dev), 1783 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1784 if (error == 0) { 1785 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1786 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1787 device_printf(sc->alc_dev, "int_tx_mod value out of " 1788 "range; using default: %d\n", 1789 ALC_IM_TX_TIMER_DEFAULT); 1790 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1791 } 1792 } 1793 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1794 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1795 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1796 "max number of Rx events to process"); 1797 /* Pull in device tunables. */ 1798 sc->alc_process_limit = ALC_PROC_DEFAULT; 1799 error = resource_int_value(device_get_name(sc->alc_dev), 1800 device_get_unit(sc->alc_dev), "process_limit", 1801 &sc->alc_process_limit); 1802 if (error == 0) { 1803 if (sc->alc_process_limit < ALC_PROC_MIN || 1804 sc->alc_process_limit > ALC_PROC_MAX) { 1805 device_printf(sc->alc_dev, 1806 "process_limit value out of range; " 1807 "using default: %d\n", ALC_PROC_DEFAULT); 1808 sc->alc_process_limit = ALC_PROC_DEFAULT; 1809 } 1810 } 1811 1812 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1813 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1814 parent = SYSCTL_CHILDREN(tree); 1815 1816 /* Rx statistics. */ 1817 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1818 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1819 child = SYSCTL_CHILDREN(tree); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1821 &stats->rx_frames, "Good frames"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1823 &stats->rx_bcast_frames, "Good broadcast frames"); 1824 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1825 &stats->rx_mcast_frames, "Good multicast frames"); 1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1827 &stats->rx_pause_frames, "Pause control frames"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1829 &stats->rx_control_frames, "Control frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1831 &stats->rx_crcerrs, "CRC errors"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1833 &stats->rx_lenerrs, "Frames with length mismatched"); 1834 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1835 &stats->rx_bytes, "Good octets"); 1836 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1837 &stats->rx_bcast_bytes, "Good broadcast octets"); 1838 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1839 &stats->rx_mcast_bytes, "Good multicast octets"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1841 &stats->rx_runts, "Too short frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1843 &stats->rx_fragments, "Fragmented frames"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1845 &stats->rx_pkts_64, "64 bytes frames"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1847 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1849 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1851 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1853 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1855 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1857 &stats->rx_pkts_1519_max, "1519 to max frames"); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1859 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1861 &stats->rx_fifo_oflows, "FIFO overflows"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1863 &stats->rx_rrs_errs, "Return status write-back errors"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1865 &stats->rx_alignerrs, "Alignment errors"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1867 &stats->rx_pkts_filtered, 1868 "Frames dropped due to address filtering"); 1869 1870 /* Tx statistics. */ 1871 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1872 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1873 child = SYSCTL_CHILDREN(tree); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1875 &stats->tx_frames, "Good frames"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1877 &stats->tx_bcast_frames, "Good broadcast frames"); 1878 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1879 &stats->tx_mcast_frames, "Good multicast frames"); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1881 &stats->tx_pause_frames, "Pause control frames"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1883 &stats->tx_control_frames, "Control frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1885 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1887 &stats->tx_excess_defer, "Frames with derferrals"); 1888 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1889 &stats->tx_bytes, "Good octets"); 1890 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1891 &stats->tx_bcast_bytes, "Good broadcast octets"); 1892 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1893 &stats->tx_mcast_bytes, "Good multicast octets"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1895 &stats->tx_pkts_64, "64 bytes frames"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1897 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1899 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1901 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1903 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1905 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1907 &stats->tx_pkts_1519_max, "1519 to max frames"); 1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1909 &stats->tx_single_colls, "Single collisions"); 1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1911 &stats->tx_multi_colls, "Multiple collisions"); 1912 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1913 &stats->tx_late_colls, "Late collisions"); 1914 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1915 &stats->tx_excess_colls, "Excessive collisions"); 1916 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1917 &stats->tx_underrun, "FIFO underruns"); 1918 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1919 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1920 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1921 &stats->tx_lenerrs, "Frames with length mismatched"); 1922 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1923 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1924 } 1925 1926 #undef ALC_SYSCTL_STAT_ADD32 1927 #undef ALC_SYSCTL_STAT_ADD64 1928 1929 struct alc_dmamap_arg { 1930 bus_addr_t alc_busaddr; 1931 }; 1932 1933 static void 1934 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1935 { 1936 struct alc_dmamap_arg *ctx; 1937 1938 if (error != 0) 1939 return; 1940 1941 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1942 1943 ctx = (struct alc_dmamap_arg *)arg; 1944 ctx->alc_busaddr = segs[0].ds_addr; 1945 } 1946 1947 /* 1948 * Normal and high Tx descriptors shares single Tx high address. 1949 * Four Rx descriptor/return rings and CMB shares the same Rx 1950 * high address. 1951 */ 1952 static int 1953 alc_check_boundary(struct alc_softc *sc) 1954 { 1955 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1956 1957 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1958 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1959 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1960 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1961 1962 /* 4GB boundary crossing is not allowed. */ 1963 if ((ALC_ADDR_HI(rx_ring_end) != 1964 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1965 (ALC_ADDR_HI(rr_ring_end) != 1966 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1967 (ALC_ADDR_HI(cmb_end) != 1968 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1969 (ALC_ADDR_HI(tx_ring_end) != 1970 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1971 return (EFBIG); 1972 /* 1973 * Make sure Rx return descriptor/Rx descriptor/CMB use 1974 * the same high address. 1975 */ 1976 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1977 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1978 return (EFBIG); 1979 1980 return (0); 1981 } 1982 1983 static int 1984 alc_dma_alloc(struct alc_softc *sc) 1985 { 1986 struct alc_txdesc *txd; 1987 struct alc_rxdesc *rxd; 1988 bus_addr_t lowaddr; 1989 struct alc_dmamap_arg ctx; 1990 int error, i; 1991 1992 lowaddr = BUS_SPACE_MAXADDR; 1993 if (sc->alc_flags & ALC_FLAG_MT) 1994 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1995 again: 1996 /* Create parent DMA tag. */ 1997 error = bus_dma_tag_create( 1998 bus_get_dma_tag(sc->alc_dev), /* parent */ 1999 1, 0, /* alignment, boundary */ 2000 lowaddr, /* lowaddr */ 2001 BUS_SPACE_MAXADDR, /* highaddr */ 2002 NULL, NULL, /* filter, filterarg */ 2003 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2004 0, /* nsegments */ 2005 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2006 0, /* flags */ 2007 NULL, NULL, /* lockfunc, lockarg */ 2008 &sc->alc_cdata.alc_parent_tag); 2009 if (error != 0) { 2010 device_printf(sc->alc_dev, 2011 "could not create parent DMA tag.\n"); 2012 goto fail; 2013 } 2014 2015 /* Create DMA tag for Tx descriptor ring. */ 2016 error = bus_dma_tag_create( 2017 sc->alc_cdata.alc_parent_tag, /* parent */ 2018 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2019 BUS_SPACE_MAXADDR, /* lowaddr */ 2020 BUS_SPACE_MAXADDR, /* highaddr */ 2021 NULL, NULL, /* filter, filterarg */ 2022 ALC_TX_RING_SZ, /* maxsize */ 2023 1, /* nsegments */ 2024 ALC_TX_RING_SZ, /* maxsegsize */ 2025 0, /* flags */ 2026 NULL, NULL, /* lockfunc, lockarg */ 2027 &sc->alc_cdata.alc_tx_ring_tag); 2028 if (error != 0) { 2029 device_printf(sc->alc_dev, 2030 "could not create Tx ring DMA tag.\n"); 2031 goto fail; 2032 } 2033 2034 /* Create DMA tag for Rx free descriptor ring. */ 2035 error = bus_dma_tag_create( 2036 sc->alc_cdata.alc_parent_tag, /* parent */ 2037 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2038 BUS_SPACE_MAXADDR, /* lowaddr */ 2039 BUS_SPACE_MAXADDR, /* highaddr */ 2040 NULL, NULL, /* filter, filterarg */ 2041 ALC_RX_RING_SZ, /* maxsize */ 2042 1, /* nsegments */ 2043 ALC_RX_RING_SZ, /* maxsegsize */ 2044 0, /* flags */ 2045 NULL, NULL, /* lockfunc, lockarg */ 2046 &sc->alc_cdata.alc_rx_ring_tag); 2047 if (error != 0) { 2048 device_printf(sc->alc_dev, 2049 "could not create Rx ring DMA tag.\n"); 2050 goto fail; 2051 } 2052 /* Create DMA tag for Rx return descriptor ring. */ 2053 error = bus_dma_tag_create( 2054 sc->alc_cdata.alc_parent_tag, /* parent */ 2055 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2056 BUS_SPACE_MAXADDR, /* lowaddr */ 2057 BUS_SPACE_MAXADDR, /* highaddr */ 2058 NULL, NULL, /* filter, filterarg */ 2059 ALC_RR_RING_SZ, /* maxsize */ 2060 1, /* nsegments */ 2061 ALC_RR_RING_SZ, /* maxsegsize */ 2062 0, /* flags */ 2063 NULL, NULL, /* lockfunc, lockarg */ 2064 &sc->alc_cdata.alc_rr_ring_tag); 2065 if (error != 0) { 2066 device_printf(sc->alc_dev, 2067 "could not create Rx return ring DMA tag.\n"); 2068 goto fail; 2069 } 2070 2071 /* Create DMA tag for coalescing message block. */ 2072 error = bus_dma_tag_create( 2073 sc->alc_cdata.alc_parent_tag, /* parent */ 2074 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2075 BUS_SPACE_MAXADDR, /* lowaddr */ 2076 BUS_SPACE_MAXADDR, /* highaddr */ 2077 NULL, NULL, /* filter, filterarg */ 2078 ALC_CMB_SZ, /* maxsize */ 2079 1, /* nsegments */ 2080 ALC_CMB_SZ, /* maxsegsize */ 2081 0, /* flags */ 2082 NULL, NULL, /* lockfunc, lockarg */ 2083 &sc->alc_cdata.alc_cmb_tag); 2084 if (error != 0) { 2085 device_printf(sc->alc_dev, 2086 "could not create CMB DMA tag.\n"); 2087 goto fail; 2088 } 2089 /* Create DMA tag for status message block. */ 2090 error = bus_dma_tag_create( 2091 sc->alc_cdata.alc_parent_tag, /* parent */ 2092 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2093 BUS_SPACE_MAXADDR, /* lowaddr */ 2094 BUS_SPACE_MAXADDR, /* highaddr */ 2095 NULL, NULL, /* filter, filterarg */ 2096 ALC_SMB_SZ, /* maxsize */ 2097 1, /* nsegments */ 2098 ALC_SMB_SZ, /* maxsegsize */ 2099 0, /* flags */ 2100 NULL, NULL, /* lockfunc, lockarg */ 2101 &sc->alc_cdata.alc_smb_tag); 2102 if (error != 0) { 2103 device_printf(sc->alc_dev, 2104 "could not create SMB DMA tag.\n"); 2105 goto fail; 2106 } 2107 2108 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2109 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2110 (void **)&sc->alc_rdata.alc_tx_ring, 2111 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2112 &sc->alc_cdata.alc_tx_ring_map); 2113 if (error != 0) { 2114 device_printf(sc->alc_dev, 2115 "could not allocate DMA'able memory for Tx ring.\n"); 2116 goto fail; 2117 } 2118 ctx.alc_busaddr = 0; 2119 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2120 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2121 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2122 if (error != 0 || ctx.alc_busaddr == 0) { 2123 device_printf(sc->alc_dev, 2124 "could not load DMA'able memory for Tx ring.\n"); 2125 goto fail; 2126 } 2127 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2128 2129 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2130 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2131 (void **)&sc->alc_rdata.alc_rx_ring, 2132 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2133 &sc->alc_cdata.alc_rx_ring_map); 2134 if (error != 0) { 2135 device_printf(sc->alc_dev, 2136 "could not allocate DMA'able memory for Rx ring.\n"); 2137 goto fail; 2138 } 2139 ctx.alc_busaddr = 0; 2140 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2141 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2142 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2143 if (error != 0 || ctx.alc_busaddr == 0) { 2144 device_printf(sc->alc_dev, 2145 "could not load DMA'able memory for Rx ring.\n"); 2146 goto fail; 2147 } 2148 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2149 2150 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2151 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2152 (void **)&sc->alc_rdata.alc_rr_ring, 2153 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2154 &sc->alc_cdata.alc_rr_ring_map); 2155 if (error != 0) { 2156 device_printf(sc->alc_dev, 2157 "could not allocate DMA'able memory for Rx return ring.\n"); 2158 goto fail; 2159 } 2160 ctx.alc_busaddr = 0; 2161 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2162 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2163 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2164 if (error != 0 || ctx.alc_busaddr == 0) { 2165 device_printf(sc->alc_dev, 2166 "could not load DMA'able memory for Tx ring.\n"); 2167 goto fail; 2168 } 2169 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2170 2171 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2172 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2173 (void **)&sc->alc_rdata.alc_cmb, 2174 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2175 &sc->alc_cdata.alc_cmb_map); 2176 if (error != 0) { 2177 device_printf(sc->alc_dev, 2178 "could not allocate DMA'able memory for CMB.\n"); 2179 goto fail; 2180 } 2181 ctx.alc_busaddr = 0; 2182 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2183 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2184 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2185 if (error != 0 || ctx.alc_busaddr == 0) { 2186 device_printf(sc->alc_dev, 2187 "could not load DMA'able memory for CMB.\n"); 2188 goto fail; 2189 } 2190 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2191 2192 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2193 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2194 (void **)&sc->alc_rdata.alc_smb, 2195 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2196 &sc->alc_cdata.alc_smb_map); 2197 if (error != 0) { 2198 device_printf(sc->alc_dev, 2199 "could not allocate DMA'able memory for SMB.\n"); 2200 goto fail; 2201 } 2202 ctx.alc_busaddr = 0; 2203 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2204 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2205 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2206 if (error != 0 || ctx.alc_busaddr == 0) { 2207 device_printf(sc->alc_dev, 2208 "could not load DMA'able memory for CMB.\n"); 2209 goto fail; 2210 } 2211 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2212 2213 /* Make sure we've not crossed 4GB boundary. */ 2214 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2215 (error = alc_check_boundary(sc)) != 0) { 2216 device_printf(sc->alc_dev, "4GB boundary crossed, " 2217 "switching to 32bit DMA addressing mode.\n"); 2218 alc_dma_free(sc); 2219 /* 2220 * Limit max allowable DMA address space to 32bit 2221 * and try again. 2222 */ 2223 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2224 goto again; 2225 } 2226 2227 /* 2228 * Create Tx buffer parent tag. 2229 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2230 * so it needs separate parent DMA tag as parent DMA address 2231 * space could be restricted to be within 32bit address space 2232 * by 4GB boundary crossing. 2233 */ 2234 error = bus_dma_tag_create( 2235 bus_get_dma_tag(sc->alc_dev), /* parent */ 2236 1, 0, /* alignment, boundary */ 2237 lowaddr, /* lowaddr */ 2238 BUS_SPACE_MAXADDR, /* highaddr */ 2239 NULL, NULL, /* filter, filterarg */ 2240 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2241 0, /* nsegments */ 2242 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2243 0, /* flags */ 2244 NULL, NULL, /* lockfunc, lockarg */ 2245 &sc->alc_cdata.alc_buffer_tag); 2246 if (error != 0) { 2247 device_printf(sc->alc_dev, 2248 "could not create parent buffer DMA tag.\n"); 2249 goto fail; 2250 } 2251 2252 /* Create DMA tag for Tx buffers. */ 2253 error = bus_dma_tag_create( 2254 sc->alc_cdata.alc_buffer_tag, /* parent */ 2255 1, 0, /* alignment, boundary */ 2256 BUS_SPACE_MAXADDR, /* lowaddr */ 2257 BUS_SPACE_MAXADDR, /* highaddr */ 2258 NULL, NULL, /* filter, filterarg */ 2259 ALC_TSO_MAXSIZE, /* maxsize */ 2260 ALC_MAXTXSEGS, /* nsegments */ 2261 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2262 0, /* flags */ 2263 NULL, NULL, /* lockfunc, lockarg */ 2264 &sc->alc_cdata.alc_tx_tag); 2265 if (error != 0) { 2266 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2267 goto fail; 2268 } 2269 2270 /* Create DMA tag for Rx buffers. */ 2271 error = bus_dma_tag_create( 2272 sc->alc_cdata.alc_buffer_tag, /* parent */ 2273 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2274 BUS_SPACE_MAXADDR, /* lowaddr */ 2275 BUS_SPACE_MAXADDR, /* highaddr */ 2276 NULL, NULL, /* filter, filterarg */ 2277 MCLBYTES, /* maxsize */ 2278 1, /* nsegments */ 2279 MCLBYTES, /* maxsegsize */ 2280 0, /* flags */ 2281 NULL, NULL, /* lockfunc, lockarg */ 2282 &sc->alc_cdata.alc_rx_tag); 2283 if (error != 0) { 2284 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2285 goto fail; 2286 } 2287 /* Create DMA maps for Tx buffers. */ 2288 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2289 txd = &sc->alc_cdata.alc_txdesc[i]; 2290 txd->tx_m = NULL; 2291 txd->tx_dmamap = NULL; 2292 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2293 &txd->tx_dmamap); 2294 if (error != 0) { 2295 device_printf(sc->alc_dev, 2296 "could not create Tx dmamap.\n"); 2297 goto fail; 2298 } 2299 } 2300 /* Create DMA maps for Rx buffers. */ 2301 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2302 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2303 device_printf(sc->alc_dev, 2304 "could not create spare Rx dmamap.\n"); 2305 goto fail; 2306 } 2307 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2308 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2309 rxd->rx_m = NULL; 2310 rxd->rx_dmamap = NULL; 2311 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2312 &rxd->rx_dmamap); 2313 if (error != 0) { 2314 device_printf(sc->alc_dev, 2315 "could not create Rx dmamap.\n"); 2316 goto fail; 2317 } 2318 } 2319 2320 fail: 2321 return (error); 2322 } 2323 2324 static void 2325 alc_dma_free(struct alc_softc *sc) 2326 { 2327 struct alc_txdesc *txd; 2328 struct alc_rxdesc *rxd; 2329 int i; 2330 2331 /* Tx buffers. */ 2332 if (sc->alc_cdata.alc_tx_tag != NULL) { 2333 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2334 txd = &sc->alc_cdata.alc_txdesc[i]; 2335 if (txd->tx_dmamap != NULL) { 2336 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2337 txd->tx_dmamap); 2338 txd->tx_dmamap = NULL; 2339 } 2340 } 2341 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2342 sc->alc_cdata.alc_tx_tag = NULL; 2343 } 2344 /* Rx buffers */ 2345 if (sc->alc_cdata.alc_rx_tag != NULL) { 2346 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2347 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2348 if (rxd->rx_dmamap != NULL) { 2349 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2350 rxd->rx_dmamap); 2351 rxd->rx_dmamap = NULL; 2352 } 2353 } 2354 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2355 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2356 sc->alc_cdata.alc_rx_sparemap); 2357 sc->alc_cdata.alc_rx_sparemap = NULL; 2358 } 2359 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2360 sc->alc_cdata.alc_rx_tag = NULL; 2361 } 2362 /* Tx descriptor ring. */ 2363 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2364 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2365 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2366 sc->alc_cdata.alc_tx_ring_map); 2367 if (sc->alc_rdata.alc_tx_ring != NULL) 2368 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2369 sc->alc_rdata.alc_tx_ring, 2370 sc->alc_cdata.alc_tx_ring_map); 2371 sc->alc_rdata.alc_tx_ring_paddr = 0; 2372 sc->alc_rdata.alc_tx_ring = NULL; 2373 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2374 sc->alc_cdata.alc_tx_ring_tag = NULL; 2375 } 2376 /* Rx ring. */ 2377 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2378 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2379 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2380 sc->alc_cdata.alc_rx_ring_map); 2381 if (sc->alc_rdata.alc_rx_ring != NULL) 2382 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2383 sc->alc_rdata.alc_rx_ring, 2384 sc->alc_cdata.alc_rx_ring_map); 2385 sc->alc_rdata.alc_rx_ring_paddr = 0; 2386 sc->alc_rdata.alc_rx_ring = NULL; 2387 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2388 sc->alc_cdata.alc_rx_ring_tag = NULL; 2389 } 2390 /* Rx return ring. */ 2391 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2392 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2393 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2394 sc->alc_cdata.alc_rr_ring_map); 2395 if (sc->alc_rdata.alc_rr_ring != NULL) 2396 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2397 sc->alc_rdata.alc_rr_ring, 2398 sc->alc_cdata.alc_rr_ring_map); 2399 sc->alc_rdata.alc_rr_ring_paddr = 0; 2400 sc->alc_rdata.alc_rr_ring = NULL; 2401 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2402 sc->alc_cdata.alc_rr_ring_tag = NULL; 2403 } 2404 /* CMB block */ 2405 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2406 if (sc->alc_rdata.alc_cmb_paddr != 0) 2407 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2408 sc->alc_cdata.alc_cmb_map); 2409 if (sc->alc_rdata.alc_cmb != NULL) 2410 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2411 sc->alc_rdata.alc_cmb, 2412 sc->alc_cdata.alc_cmb_map); 2413 sc->alc_rdata.alc_cmb_paddr = 0; 2414 sc->alc_rdata.alc_cmb = NULL; 2415 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2416 sc->alc_cdata.alc_cmb_tag = NULL; 2417 } 2418 /* SMB block */ 2419 if (sc->alc_cdata.alc_smb_tag != NULL) { 2420 if (sc->alc_rdata.alc_smb_paddr != 0) 2421 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2422 sc->alc_cdata.alc_smb_map); 2423 if (sc->alc_rdata.alc_smb != NULL) 2424 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2425 sc->alc_rdata.alc_smb, 2426 sc->alc_cdata.alc_smb_map); 2427 sc->alc_rdata.alc_smb_paddr = 0; 2428 sc->alc_rdata.alc_smb = NULL; 2429 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2430 sc->alc_cdata.alc_smb_tag = NULL; 2431 } 2432 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2433 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2434 sc->alc_cdata.alc_buffer_tag = NULL; 2435 } 2436 if (sc->alc_cdata.alc_parent_tag != NULL) { 2437 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2438 sc->alc_cdata.alc_parent_tag = NULL; 2439 } 2440 } 2441 2442 static int 2443 alc_shutdown(device_t dev) 2444 { 2445 2446 return (alc_suspend(dev)); 2447 } 2448 2449 /* 2450 * Note, this driver resets the link speed to 10/100Mbps by 2451 * restarting auto-negotiation in suspend/shutdown phase but we 2452 * don't know whether that auto-negotiation would succeed or not 2453 * as driver has no control after powering off/suspend operation. 2454 * If the renegotiation fail WOL may not work. Running at 1Gbps 2455 * will draw more power than 375mA at 3.3V which is specified in 2456 * PCI specification and that would result in complete 2457 * shutdowning power to ethernet controller. 2458 * 2459 * TODO 2460 * Save current negotiated media speed/duplex/flow-control to 2461 * softc and restore the same link again after resuming. PHY 2462 * handling such as power down/resetting to 100Mbps may be better 2463 * handled in suspend method in phy driver. 2464 */ 2465 static void 2466 alc_setlinkspeed(struct alc_softc *sc) 2467 { 2468 struct mii_data *mii; 2469 int aneg, i; 2470 2471 mii = device_get_softc(sc->alc_miibus); 2472 mii_pollstat(mii); 2473 aneg = 0; 2474 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2475 (IFM_ACTIVE | IFM_AVALID)) { 2476 switch IFM_SUBTYPE(mii->mii_media_active) { 2477 case IFM_10_T: 2478 case IFM_100_TX: 2479 return; 2480 case IFM_1000_T: 2481 aneg++; 2482 break; 2483 default: 2484 break; 2485 } 2486 } 2487 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2488 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2489 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2490 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2491 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2492 DELAY(1000); 2493 if (aneg != 0) { 2494 /* 2495 * Poll link state until alc(4) get a 10/100Mbps link. 2496 */ 2497 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2498 mii_pollstat(mii); 2499 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2500 == (IFM_ACTIVE | IFM_AVALID)) { 2501 switch (IFM_SUBTYPE( 2502 mii->mii_media_active)) { 2503 case IFM_10_T: 2504 case IFM_100_TX: 2505 alc_mac_config(sc); 2506 return; 2507 default: 2508 break; 2509 } 2510 } 2511 ALC_UNLOCK(sc); 2512 pause("alclnk", hz); 2513 ALC_LOCK(sc); 2514 } 2515 if (i == MII_ANEGTICKS_GIGE) 2516 device_printf(sc->alc_dev, 2517 "establishing a link failed, WOL may not work!"); 2518 } 2519 /* 2520 * No link, force MAC to have 100Mbps, full-duplex link. 2521 * This is the last resort and may/may not work. 2522 */ 2523 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2524 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2525 alc_mac_config(sc); 2526 } 2527 2528 static void 2529 alc_setwol(struct alc_softc *sc) 2530 { 2531 2532 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2533 alc_setwol_816x(sc); 2534 else 2535 alc_setwol_813x(sc); 2536 } 2537 2538 static void 2539 alc_setwol_813x(struct alc_softc *sc) 2540 { 2541 if_t ifp; 2542 uint32_t reg, pmcs; 2543 uint16_t pmstat; 2544 2545 ALC_LOCK_ASSERT(sc); 2546 2547 alc_disable_l0s_l1(sc); 2548 ifp = sc->alc_ifp; 2549 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2550 /* Disable WOL. */ 2551 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2552 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2553 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2554 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2555 /* Force PHY power down. */ 2556 alc_phy_down(sc); 2557 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2558 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2559 return; 2560 } 2561 2562 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2563 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2564 alc_setlinkspeed(sc); 2565 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2566 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2567 } 2568 2569 pmcs = 0; 2570 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2571 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2572 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2573 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2574 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2575 MAC_CFG_BCAST); 2576 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2577 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2578 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2579 reg |= MAC_CFG_RX_ENB; 2580 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2581 2582 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2583 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2584 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2585 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2586 /* WOL disabled, PHY power down. */ 2587 alc_phy_down(sc); 2588 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2589 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2590 } 2591 /* Request PME. */ 2592 pmstat = pci_read_config(sc->alc_dev, 2593 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2594 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2595 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2596 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2597 pci_write_config(sc->alc_dev, 2598 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2599 } 2600 2601 static void 2602 alc_setwol_816x(struct alc_softc *sc) 2603 { 2604 if_t ifp; 2605 uint32_t gphy, mac, master, pmcs, reg; 2606 uint16_t pmstat; 2607 2608 ALC_LOCK_ASSERT(sc); 2609 2610 ifp = sc->alc_ifp; 2611 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2612 master &= ~MASTER_CLK_SEL_DIS; 2613 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2614 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2615 GPHY_CFG_PHY_PLL_ON); 2616 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2617 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2618 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2619 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2620 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2621 } else { 2622 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2623 gphy |= GPHY_CFG_EXT_RESET; 2624 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2625 alc_setlinkspeed(sc); 2626 } 2627 pmcs = 0; 2628 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2629 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2630 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2631 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2632 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2633 MAC_CFG_BCAST); 2634 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2635 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2636 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2637 mac |= MAC_CFG_RX_ENB; 2638 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2639 ANEG_S3DIG10_SL); 2640 } 2641 2642 /* Enable OSC. */ 2643 reg = CSR_READ_4(sc, ALC_MISC); 2644 reg &= ~MISC_INTNLOSC_OPEN; 2645 CSR_WRITE_4(sc, ALC_MISC, reg); 2646 reg |= MISC_INTNLOSC_OPEN; 2647 CSR_WRITE_4(sc, ALC_MISC, reg); 2648 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2649 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2650 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2651 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2652 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2653 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2654 2655 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2656 /* Request PME. */ 2657 pmstat = pci_read_config(sc->alc_dev, 2658 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2659 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2660 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2661 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2662 pci_write_config(sc->alc_dev, 2663 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2664 } 2665 } 2666 2667 static int 2668 alc_suspend(device_t dev) 2669 { 2670 struct alc_softc *sc; 2671 2672 sc = device_get_softc(dev); 2673 2674 ALC_LOCK(sc); 2675 alc_stop(sc); 2676 alc_setwol(sc); 2677 ALC_UNLOCK(sc); 2678 2679 return (0); 2680 } 2681 2682 static int 2683 alc_resume(device_t dev) 2684 { 2685 struct alc_softc *sc; 2686 if_t ifp; 2687 uint16_t pmstat; 2688 2689 sc = device_get_softc(dev); 2690 2691 ALC_LOCK(sc); 2692 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2693 /* Disable PME and clear PME status. */ 2694 pmstat = pci_read_config(sc->alc_dev, 2695 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2696 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2697 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2698 pci_write_config(sc->alc_dev, 2699 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2700 } 2701 } 2702 /* Reset PHY. */ 2703 alc_phy_reset(sc); 2704 ifp = sc->alc_ifp; 2705 if ((if_getflags(ifp) & IFF_UP) != 0) { 2706 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2707 alc_init_locked(sc); 2708 } 2709 ALC_UNLOCK(sc); 2710 2711 return (0); 2712 } 2713 2714 static int 2715 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2716 { 2717 struct alc_txdesc *txd, *txd_last; 2718 struct tx_desc *desc; 2719 struct mbuf *m; 2720 struct ip *ip; 2721 struct tcphdr *tcp; 2722 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2723 bus_dmamap_t map; 2724 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2725 int error, idx, nsegs, prod; 2726 2727 ALC_LOCK_ASSERT(sc); 2728 2729 M_ASSERTPKTHDR((*m_head)); 2730 2731 m = *m_head; 2732 ip = NULL; 2733 tcp = NULL; 2734 ip_off = poff = 0; 2735 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2736 /* 2737 * AR81[3567]x requires offset of TCP/UDP header in its 2738 * Tx descriptor to perform Tx checksum offloading. TSO 2739 * also requires TCP header offset and modification of 2740 * IP/TCP header. This kind of operation takes many CPU 2741 * cycles on FreeBSD so fast host CPU is required to get 2742 * smooth TSO performance. 2743 */ 2744 struct ether_header *eh; 2745 2746 if (M_WRITABLE(m) == 0) { 2747 /* Get a writable copy. */ 2748 m = m_dup(*m_head, M_NOWAIT); 2749 /* Release original mbufs. */ 2750 m_freem(*m_head); 2751 if (m == NULL) { 2752 *m_head = NULL; 2753 return (ENOBUFS); 2754 } 2755 *m_head = m; 2756 } 2757 2758 ip_off = sizeof(struct ether_header); 2759 m = m_pullup(m, ip_off); 2760 if (m == NULL) { 2761 *m_head = NULL; 2762 return (ENOBUFS); 2763 } 2764 eh = mtod(m, struct ether_header *); 2765 /* 2766 * Check if hardware VLAN insertion is off. 2767 * Additional check for LLC/SNAP frame? 2768 */ 2769 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2770 ip_off = sizeof(struct ether_vlan_header); 2771 m = m_pullup(m, ip_off); 2772 if (m == NULL) { 2773 *m_head = NULL; 2774 return (ENOBUFS); 2775 } 2776 } 2777 m = m_pullup(m, ip_off + sizeof(struct ip)); 2778 if (m == NULL) { 2779 *m_head = NULL; 2780 return (ENOBUFS); 2781 } 2782 ip = (struct ip *)(mtod(m, char *) + ip_off); 2783 poff = ip_off + (ip->ip_hl << 2); 2784 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2785 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2786 if (m == NULL) { 2787 *m_head = NULL; 2788 return (ENOBUFS); 2789 } 2790 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2791 m = m_pullup(m, poff + (tcp->th_off << 2)); 2792 if (m == NULL) { 2793 *m_head = NULL; 2794 return (ENOBUFS); 2795 } 2796 /* 2797 * Due to strict adherence of Microsoft NDIS 2798 * Large Send specification, hardware expects 2799 * a pseudo TCP checksum inserted by upper 2800 * stack. Unfortunately the pseudo TCP 2801 * checksum that NDIS refers to does not include 2802 * TCP payload length so driver should recompute 2803 * the pseudo checksum here. Hopefully this 2804 * wouldn't be much burden on modern CPUs. 2805 * 2806 * Reset IP checksum and recompute TCP pseudo 2807 * checksum as NDIS specification said. 2808 */ 2809 ip = (struct ip *)(mtod(m, char *) + ip_off); 2810 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2811 ip->ip_sum = 0; 2812 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2813 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2814 } 2815 *m_head = m; 2816 } 2817 2818 prod = sc->alc_cdata.alc_tx_prod; 2819 txd = &sc->alc_cdata.alc_txdesc[prod]; 2820 txd_last = txd; 2821 map = txd->tx_dmamap; 2822 2823 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2824 *m_head, txsegs, &nsegs, 0); 2825 if (error == EFBIG) { 2826 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2827 if (m == NULL) { 2828 m_freem(*m_head); 2829 *m_head = NULL; 2830 return (ENOMEM); 2831 } 2832 *m_head = m; 2833 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2834 *m_head, txsegs, &nsegs, 0); 2835 if (error != 0) { 2836 m_freem(*m_head); 2837 *m_head = NULL; 2838 return (error); 2839 } 2840 } else if (error != 0) 2841 return (error); 2842 if (nsegs == 0) { 2843 m_freem(*m_head); 2844 *m_head = NULL; 2845 return (EIO); 2846 } 2847 2848 /* Check descriptor overrun. */ 2849 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2850 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2851 return (ENOBUFS); 2852 } 2853 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2854 2855 m = *m_head; 2856 cflags = TD_ETHERNET; 2857 vtag = 0; 2858 desc = NULL; 2859 idx = 0; 2860 /* Configure VLAN hardware tag insertion. */ 2861 if ((m->m_flags & M_VLANTAG) != 0) { 2862 vtag = htons(m->m_pkthdr.ether_vtag); 2863 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2864 cflags |= TD_INS_VLAN_TAG; 2865 } 2866 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2867 /* Request TSO and set MSS. */ 2868 cflags |= TD_TSO | TD_TSO_DESCV1; 2869 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2870 TD_MSS_MASK; 2871 /* Set TCP header offset. */ 2872 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2873 TD_TCPHDR_OFFSET_MASK; 2874 /* 2875 * AR81[3567]x requires the first buffer should 2876 * only hold IP/TCP header data. Payload should 2877 * be handled in other descriptors. 2878 */ 2879 hdrlen = poff + (tcp->th_off << 2); 2880 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2881 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2882 desc->flags = htole32(cflags); 2883 desc->addr = htole64(txsegs[0].ds_addr); 2884 sc->alc_cdata.alc_tx_cnt++; 2885 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2886 if (m->m_len - hdrlen > 0) { 2887 /* Handle remaining payload of the first fragment. */ 2888 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2889 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2890 vtag)); 2891 desc->flags = htole32(cflags); 2892 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2893 sc->alc_cdata.alc_tx_cnt++; 2894 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2895 } 2896 /* Handle remaining fragments. */ 2897 idx = 1; 2898 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2899 /* Configure Tx checksum offload. */ 2900 #ifdef ALC_USE_CUSTOM_CSUM 2901 cflags |= TD_CUSTOM_CSUM; 2902 /* Set checksum start offset. */ 2903 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2904 TD_PLOAD_OFFSET_MASK; 2905 /* Set checksum insertion position of TCP/UDP. */ 2906 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2907 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2908 #else 2909 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2910 cflags |= TD_IPCSUM; 2911 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2912 cflags |= TD_TCPCSUM; 2913 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2914 cflags |= TD_UDPCSUM; 2915 /* Set TCP/UDP header offset. */ 2916 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2917 TD_L4HDR_OFFSET_MASK; 2918 #endif 2919 } 2920 for (; idx < nsegs; idx++) { 2921 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2922 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2923 desc->flags = htole32(cflags); 2924 desc->addr = htole64(txsegs[idx].ds_addr); 2925 sc->alc_cdata.alc_tx_cnt++; 2926 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2927 } 2928 /* Update producer index. */ 2929 sc->alc_cdata.alc_tx_prod = prod; 2930 2931 /* Finally set EOP on the last descriptor. */ 2932 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2933 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2934 desc->flags |= htole32(TD_EOP); 2935 2936 /* Swap dmamap of the first and the last. */ 2937 txd = &sc->alc_cdata.alc_txdesc[prod]; 2938 map = txd_last->tx_dmamap; 2939 txd_last->tx_dmamap = txd->tx_dmamap; 2940 txd->tx_dmamap = map; 2941 txd->tx_m = m; 2942 2943 return (0); 2944 } 2945 2946 static void 2947 alc_start(if_t ifp) 2948 { 2949 struct alc_softc *sc; 2950 2951 sc = if_getsoftc(ifp); 2952 ALC_LOCK(sc); 2953 alc_start_locked(ifp); 2954 ALC_UNLOCK(sc); 2955 } 2956 2957 static void 2958 alc_start_locked(if_t ifp) 2959 { 2960 struct alc_softc *sc; 2961 struct mbuf *m_head; 2962 int enq; 2963 2964 sc = if_getsoftc(ifp); 2965 2966 ALC_LOCK_ASSERT(sc); 2967 2968 /* Reclaim transmitted frames. */ 2969 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2970 alc_txeof(sc); 2971 2972 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2973 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2974 return; 2975 2976 for (enq = 0; !if_sendq_empty(ifp); ) { 2977 m_head = if_dequeue(ifp); 2978 if (m_head == NULL) 2979 break; 2980 /* 2981 * Pack the data into the transmit ring. If we 2982 * don't have room, set the OACTIVE flag and wait 2983 * for the NIC to drain the ring. 2984 */ 2985 if (alc_encap(sc, &m_head)) { 2986 if (m_head == NULL) 2987 break; 2988 if_sendq_prepend(ifp, m_head); 2989 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2990 break; 2991 } 2992 2993 enq++; 2994 /* 2995 * If there's a BPF listener, bounce a copy of this frame 2996 * to him. 2997 */ 2998 ETHER_BPF_MTAP(ifp, m_head); 2999 } 3000 3001 if (enq > 0) 3002 alc_start_tx(sc); 3003 } 3004 3005 static void 3006 alc_start_tx(struct alc_softc *sc) 3007 { 3008 3009 /* Sync descriptors. */ 3010 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3011 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3012 /* Kick. Assume we're using normal Tx priority queue. */ 3013 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3014 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3015 (uint16_t)sc->alc_cdata.alc_tx_prod); 3016 else 3017 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3018 (sc->alc_cdata.alc_tx_prod << 3019 MBOX_TD_PROD_LO_IDX_SHIFT) & 3020 MBOX_TD_PROD_LO_IDX_MASK); 3021 /* Set a timeout in case the chip goes out to lunch. */ 3022 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3023 } 3024 3025 static void 3026 alc_watchdog(struct alc_softc *sc) 3027 { 3028 if_t ifp; 3029 3030 ALC_LOCK_ASSERT(sc); 3031 3032 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3033 return; 3034 3035 ifp = sc->alc_ifp; 3036 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3037 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3038 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3039 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3040 alc_init_locked(sc); 3041 return; 3042 } 3043 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3044 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3045 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3046 alc_init_locked(sc); 3047 if (!if_sendq_empty(ifp)) 3048 alc_start_locked(ifp); 3049 } 3050 3051 static int 3052 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3053 { 3054 struct alc_softc *sc; 3055 struct ifreq *ifr; 3056 struct mii_data *mii; 3057 int error, mask; 3058 3059 sc = if_getsoftc(ifp); 3060 ifr = (struct ifreq *)data; 3061 error = 0; 3062 switch (cmd) { 3063 case SIOCSIFMTU: 3064 if (ifr->ifr_mtu < ETHERMIN || 3065 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3066 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3067 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3068 ifr->ifr_mtu > ETHERMTU)) 3069 error = EINVAL; 3070 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3071 ALC_LOCK(sc); 3072 if_setmtu(ifp, ifr->ifr_mtu); 3073 /* AR81[3567]x has 13 bits MSS field. */ 3074 if (if_getmtu(ifp) > ALC_TSO_MTU && 3075 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3076 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3077 if_sethwassistbits(ifp, 0, CSUM_TSO); 3078 VLAN_CAPABILITIES(ifp); 3079 } 3080 ALC_UNLOCK(sc); 3081 } 3082 break; 3083 case SIOCSIFFLAGS: 3084 ALC_LOCK(sc); 3085 if ((if_getflags(ifp) & IFF_UP) != 0) { 3086 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3087 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3088 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3089 alc_rxfilter(sc); 3090 else 3091 alc_init_locked(sc); 3092 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3093 alc_stop(sc); 3094 sc->alc_if_flags = if_getflags(ifp); 3095 ALC_UNLOCK(sc); 3096 break; 3097 case SIOCADDMULTI: 3098 case SIOCDELMULTI: 3099 ALC_LOCK(sc); 3100 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3101 alc_rxfilter(sc); 3102 ALC_UNLOCK(sc); 3103 break; 3104 case SIOCSIFMEDIA: 3105 case SIOCGIFMEDIA: 3106 mii = device_get_softc(sc->alc_miibus); 3107 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3108 break; 3109 case SIOCSIFCAP: 3110 ALC_LOCK(sc); 3111 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3112 if ((mask & IFCAP_TXCSUM) != 0 && 3113 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3114 if_togglecapenable(ifp, IFCAP_TXCSUM); 3115 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3116 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3117 else 3118 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3119 } 3120 if ((mask & IFCAP_TSO4) != 0 && 3121 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3122 if_togglecapenable(ifp, IFCAP_TSO4); 3123 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3124 /* AR81[3567]x has 13 bits MSS field. */ 3125 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3126 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3127 if_sethwassistbits(ifp, 0, CSUM_TSO); 3128 } else 3129 if_sethwassistbits(ifp, CSUM_TSO, 0); 3130 } else 3131 if_sethwassistbits(ifp, 0, CSUM_TSO); 3132 } 3133 if ((mask & IFCAP_WOL_MCAST) != 0 && 3134 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3135 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3136 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3137 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3138 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3139 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3140 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3141 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3142 alc_rxvlan(sc); 3143 } 3144 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3145 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3146 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3147 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3148 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3149 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3150 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3151 if_setcapenablebit(ifp, 0, 3152 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3153 ALC_UNLOCK(sc); 3154 VLAN_CAPABILITIES(ifp); 3155 break; 3156 default: 3157 error = ether_ioctl(ifp, cmd, data); 3158 break; 3159 } 3160 3161 return (error); 3162 } 3163 3164 static void 3165 alc_mac_config(struct alc_softc *sc) 3166 { 3167 struct mii_data *mii; 3168 uint32_t reg; 3169 3170 ALC_LOCK_ASSERT(sc); 3171 3172 mii = device_get_softc(sc->alc_miibus); 3173 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3174 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3175 MAC_CFG_SPEED_MASK); 3176 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3177 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3178 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3179 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3180 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3181 /* Reprogram MAC with resolved speed/duplex. */ 3182 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3183 case IFM_10_T: 3184 case IFM_100_TX: 3185 reg |= MAC_CFG_SPEED_10_100; 3186 break; 3187 case IFM_1000_T: 3188 reg |= MAC_CFG_SPEED_1000; 3189 break; 3190 } 3191 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3192 reg |= MAC_CFG_FULL_DUPLEX; 3193 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3194 reg |= MAC_CFG_TX_FC; 3195 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3196 reg |= MAC_CFG_RX_FC; 3197 } 3198 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3199 } 3200 3201 static void 3202 alc_stats_clear(struct alc_softc *sc) 3203 { 3204 struct smb sb, *smb; 3205 uint32_t *reg; 3206 int i; 3207 3208 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3209 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3210 sc->alc_cdata.alc_smb_map, 3211 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3212 smb = sc->alc_rdata.alc_smb; 3213 /* Update done, clear. */ 3214 smb->updated = 0; 3215 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3216 sc->alc_cdata.alc_smb_map, 3217 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3218 } else { 3219 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3220 reg++) { 3221 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3222 i += sizeof(uint32_t); 3223 } 3224 /* Read Tx statistics. */ 3225 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3226 reg++) { 3227 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3228 i += sizeof(uint32_t); 3229 } 3230 } 3231 } 3232 3233 static void 3234 alc_stats_update(struct alc_softc *sc) 3235 { 3236 struct alc_hw_stats *stat; 3237 struct smb sb, *smb; 3238 if_t ifp; 3239 uint32_t *reg; 3240 int i; 3241 3242 ALC_LOCK_ASSERT(sc); 3243 3244 ifp = sc->alc_ifp; 3245 stat = &sc->alc_stats; 3246 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3247 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3248 sc->alc_cdata.alc_smb_map, 3249 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3250 smb = sc->alc_rdata.alc_smb; 3251 if (smb->updated == 0) 3252 return; 3253 } else { 3254 smb = &sb; 3255 /* Read Rx statistics. */ 3256 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3257 reg++) { 3258 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3259 i += sizeof(uint32_t); 3260 } 3261 /* Read Tx statistics. */ 3262 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3263 reg++) { 3264 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3265 i += sizeof(uint32_t); 3266 } 3267 } 3268 3269 /* Rx stats. */ 3270 stat->rx_frames += smb->rx_frames; 3271 stat->rx_bcast_frames += smb->rx_bcast_frames; 3272 stat->rx_mcast_frames += smb->rx_mcast_frames; 3273 stat->rx_pause_frames += smb->rx_pause_frames; 3274 stat->rx_control_frames += smb->rx_control_frames; 3275 stat->rx_crcerrs += smb->rx_crcerrs; 3276 stat->rx_lenerrs += smb->rx_lenerrs; 3277 stat->rx_bytes += smb->rx_bytes; 3278 stat->rx_runts += smb->rx_runts; 3279 stat->rx_fragments += smb->rx_fragments; 3280 stat->rx_pkts_64 += smb->rx_pkts_64; 3281 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3282 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3283 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3284 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3285 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3286 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3287 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3288 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3289 stat->rx_rrs_errs += smb->rx_rrs_errs; 3290 stat->rx_alignerrs += smb->rx_alignerrs; 3291 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3292 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3293 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3294 3295 /* Tx stats. */ 3296 stat->tx_frames += smb->tx_frames; 3297 stat->tx_bcast_frames += smb->tx_bcast_frames; 3298 stat->tx_mcast_frames += smb->tx_mcast_frames; 3299 stat->tx_pause_frames += smb->tx_pause_frames; 3300 stat->tx_excess_defer += smb->tx_excess_defer; 3301 stat->tx_control_frames += smb->tx_control_frames; 3302 stat->tx_deferred += smb->tx_deferred; 3303 stat->tx_bytes += smb->tx_bytes; 3304 stat->tx_pkts_64 += smb->tx_pkts_64; 3305 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3306 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3307 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3308 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3309 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3310 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3311 stat->tx_single_colls += smb->tx_single_colls; 3312 stat->tx_multi_colls += smb->tx_multi_colls; 3313 stat->tx_late_colls += smb->tx_late_colls; 3314 stat->tx_excess_colls += smb->tx_excess_colls; 3315 stat->tx_underrun += smb->tx_underrun; 3316 stat->tx_desc_underrun += smb->tx_desc_underrun; 3317 stat->tx_lenerrs += smb->tx_lenerrs; 3318 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3319 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3320 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3321 3322 /* Update counters in ifnet. */ 3323 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3324 3325 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3326 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3327 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3328 3329 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3330 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3331 3332 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3333 3334 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3335 smb->rx_crcerrs + smb->rx_lenerrs + 3336 smb->rx_runts + smb->rx_pkts_truncated + 3337 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3338 smb->rx_alignerrs); 3339 3340 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3341 /* Update done, clear. */ 3342 smb->updated = 0; 3343 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3344 sc->alc_cdata.alc_smb_map, 3345 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3346 } 3347 } 3348 3349 static int 3350 alc_intr(void *arg) 3351 { 3352 struct alc_softc *sc; 3353 uint32_t status; 3354 3355 sc = (struct alc_softc *)arg; 3356 3357 if (sc->alc_flags & ALC_FLAG_MT) { 3358 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3359 return (FILTER_HANDLED); 3360 } 3361 3362 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3363 if ((status & ALC_INTRS) == 0) 3364 return (FILTER_STRAY); 3365 /* Disable interrupts. */ 3366 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3367 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3368 3369 return (FILTER_HANDLED); 3370 } 3371 3372 static void 3373 alc_int_task(void *arg, int pending) 3374 { 3375 struct alc_softc *sc; 3376 if_t ifp; 3377 uint32_t status; 3378 int more; 3379 3380 sc = (struct alc_softc *)arg; 3381 ifp = sc->alc_ifp; 3382 3383 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3384 ALC_LOCK(sc); 3385 if (sc->alc_morework != 0) { 3386 sc->alc_morework = 0; 3387 status |= INTR_RX_PKT; 3388 } 3389 if ((status & ALC_INTRS) == 0) 3390 goto done; 3391 3392 /* Acknowledge interrupts but still disable interrupts. */ 3393 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3394 3395 more = 0; 3396 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3397 if ((status & INTR_RX_PKT) != 0) { 3398 more = alc_rxintr(sc, sc->alc_process_limit); 3399 if (more == EAGAIN) 3400 sc->alc_morework = 1; 3401 else if (more == EIO) { 3402 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3403 alc_init_locked(sc); 3404 ALC_UNLOCK(sc); 3405 return; 3406 } 3407 } 3408 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3409 INTR_TXQ_TO_RST)) != 0) { 3410 if ((status & INTR_DMA_RD_TO_RST) != 0) 3411 device_printf(sc->alc_dev, 3412 "DMA read error! -- resetting\n"); 3413 if ((status & INTR_DMA_WR_TO_RST) != 0) 3414 device_printf(sc->alc_dev, 3415 "DMA write error! -- resetting\n"); 3416 if ((status & INTR_TXQ_TO_RST) != 0) 3417 device_printf(sc->alc_dev, 3418 "TxQ reset! -- resetting\n"); 3419 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3420 alc_init_locked(sc); 3421 ALC_UNLOCK(sc); 3422 return; 3423 } 3424 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3425 !if_sendq_empty(ifp)) 3426 alc_start_locked(ifp); 3427 } 3428 3429 if (more == EAGAIN || 3430 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3431 ALC_UNLOCK(sc); 3432 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3433 return; 3434 } 3435 3436 done: 3437 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3438 /* Re-enable interrupts if we're running. */ 3439 if (sc->alc_flags & ALC_FLAG_MT) 3440 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3441 else 3442 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3443 } 3444 ALC_UNLOCK(sc); 3445 } 3446 3447 static void 3448 alc_txeof(struct alc_softc *sc) 3449 { 3450 if_t ifp; 3451 struct alc_txdesc *txd; 3452 uint32_t cons, prod; 3453 3454 ALC_LOCK_ASSERT(sc); 3455 3456 ifp = sc->alc_ifp; 3457 3458 if (sc->alc_cdata.alc_tx_cnt == 0) 3459 return; 3460 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3461 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3462 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3463 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3464 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3465 prod = sc->alc_rdata.alc_cmb->cons; 3466 } else { 3467 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3468 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3469 else { 3470 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3471 /* Assume we're using normal Tx priority queue. */ 3472 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3473 MBOX_TD_CONS_LO_IDX_SHIFT; 3474 } 3475 } 3476 cons = sc->alc_cdata.alc_tx_cons; 3477 /* 3478 * Go through our Tx list and free mbufs for those 3479 * frames which have been transmitted. 3480 */ 3481 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3482 if (sc->alc_cdata.alc_tx_cnt <= 0) 3483 break; 3484 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3485 sc->alc_cdata.alc_tx_cnt--; 3486 txd = &sc->alc_cdata.alc_txdesc[cons]; 3487 if (txd->tx_m != NULL) { 3488 /* Reclaim transmitted mbufs. */ 3489 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3490 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3491 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3492 txd->tx_dmamap); 3493 m_freem(txd->tx_m); 3494 txd->tx_m = NULL; 3495 } 3496 } 3497 3498 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3499 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3500 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3501 sc->alc_cdata.alc_tx_cons = cons; 3502 /* 3503 * Unarm watchdog timer only when there is no pending 3504 * frames in Tx queue. 3505 */ 3506 if (sc->alc_cdata.alc_tx_cnt == 0) 3507 sc->alc_watchdog_timer = 0; 3508 } 3509 3510 static int 3511 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3512 { 3513 struct mbuf *m; 3514 bus_dma_segment_t segs[1]; 3515 bus_dmamap_t map; 3516 int nsegs; 3517 3518 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3519 if (m == NULL) 3520 return (ENOBUFS); 3521 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3522 #ifndef __NO_STRICT_ALIGNMENT 3523 m_adj(m, sizeof(uint64_t)); 3524 #endif 3525 3526 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3527 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3528 m_freem(m); 3529 return (ENOBUFS); 3530 } 3531 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3532 3533 if (rxd->rx_m != NULL) { 3534 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3535 BUS_DMASYNC_POSTREAD); 3536 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3537 } 3538 map = rxd->rx_dmamap; 3539 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3540 sc->alc_cdata.alc_rx_sparemap = map; 3541 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3542 BUS_DMASYNC_PREREAD); 3543 rxd->rx_m = m; 3544 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3545 return (0); 3546 } 3547 3548 static int 3549 alc_rxintr(struct alc_softc *sc, int count) 3550 { 3551 if_t ifp; 3552 struct rx_rdesc *rrd; 3553 uint32_t nsegs, status; 3554 int rr_cons, prog; 3555 3556 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3557 sc->alc_cdata.alc_rr_ring_map, 3558 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3559 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3560 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3561 rr_cons = sc->alc_cdata.alc_rr_cons; 3562 ifp = sc->alc_ifp; 3563 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3564 if (count-- <= 0) 3565 break; 3566 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3567 status = le32toh(rrd->status); 3568 if ((status & RRD_VALID) == 0) 3569 break; 3570 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3571 if (nsegs == 0) { 3572 /* This should not happen! */ 3573 device_printf(sc->alc_dev, 3574 "unexpected segment count -- resetting\n"); 3575 return (EIO); 3576 } 3577 alc_rxeof(sc, rrd); 3578 /* Clear Rx return status. */ 3579 rrd->status = 0; 3580 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3581 sc->alc_cdata.alc_rx_cons += nsegs; 3582 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3583 prog += nsegs; 3584 } 3585 3586 if (prog > 0) { 3587 /* Update the consumer index. */ 3588 sc->alc_cdata.alc_rr_cons = rr_cons; 3589 /* Sync Rx return descriptors. */ 3590 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3591 sc->alc_cdata.alc_rr_ring_map, 3592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3593 /* 3594 * Sync updated Rx descriptors such that controller see 3595 * modified buffer addresses. 3596 */ 3597 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3598 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3599 /* 3600 * Let controller know availability of new Rx buffers. 3601 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3602 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3603 * only when Rx buffer pre-fetching is required. In 3604 * addition we already set ALC_RX_RD_FREE_THRESH to 3605 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3606 * it still seems that pre-fetching needs more 3607 * experimentation. 3608 */ 3609 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3610 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3611 (uint16_t)sc->alc_cdata.alc_rx_cons); 3612 else 3613 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3614 sc->alc_cdata.alc_rx_cons); 3615 } 3616 3617 return (count > 0 ? 0 : EAGAIN); 3618 } 3619 3620 #ifndef __NO_STRICT_ALIGNMENT 3621 static struct mbuf * 3622 alc_fixup_rx(if_t ifp, struct mbuf *m) 3623 { 3624 struct mbuf *n; 3625 int i; 3626 uint16_t *src, *dst; 3627 3628 src = mtod(m, uint16_t *); 3629 dst = src - 3; 3630 3631 if (m->m_next == NULL) { 3632 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3633 *dst++ = *src++; 3634 m->m_data -= 6; 3635 return (m); 3636 } 3637 /* 3638 * Append a new mbuf to received mbuf chain and copy ethernet 3639 * header from the mbuf chain. This can save lots of CPU 3640 * cycles for jumbo frame. 3641 */ 3642 MGETHDR(n, M_NOWAIT, MT_DATA); 3643 if (n == NULL) { 3644 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3645 m_freem(m); 3646 return (NULL); 3647 } 3648 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3649 m->m_data += ETHER_HDR_LEN; 3650 m->m_len -= ETHER_HDR_LEN; 3651 n->m_len = ETHER_HDR_LEN; 3652 M_MOVE_PKTHDR(n, m); 3653 n->m_next = m; 3654 return (n); 3655 } 3656 #endif 3657 3658 /* Receive a frame. */ 3659 static void 3660 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3661 { 3662 struct alc_rxdesc *rxd; 3663 if_t ifp; 3664 struct mbuf *mp, *m; 3665 uint32_t rdinfo, status, vtag; 3666 int count, nsegs, rx_cons; 3667 3668 ifp = sc->alc_ifp; 3669 status = le32toh(rrd->status); 3670 rdinfo = le32toh(rrd->rdinfo); 3671 rx_cons = RRD_RD_IDX(rdinfo); 3672 nsegs = RRD_RD_CNT(rdinfo); 3673 3674 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3675 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3676 /* 3677 * We want to pass the following frames to upper 3678 * layer regardless of error status of Rx return 3679 * ring. 3680 * 3681 * o IP/TCP/UDP checksum is bad. 3682 * o frame length and protocol specific length 3683 * does not match. 3684 * 3685 * Force network stack compute checksum for 3686 * errored frames. 3687 */ 3688 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3689 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3690 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3691 return; 3692 } 3693 3694 for (count = 0; count < nsegs; count++, 3695 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3696 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3697 mp = rxd->rx_m; 3698 /* Add a new receive buffer to the ring. */ 3699 if (alc_newbuf(sc, rxd) != 0) { 3700 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3701 /* Reuse Rx buffers. */ 3702 if (sc->alc_cdata.alc_rxhead != NULL) 3703 m_freem(sc->alc_cdata.alc_rxhead); 3704 break; 3705 } 3706 3707 /* 3708 * Assume we've received a full sized frame. 3709 * Actual size is fixed when we encounter the end of 3710 * multi-segmented frame. 3711 */ 3712 mp->m_len = sc->alc_buf_size; 3713 3714 /* Chain received mbufs. */ 3715 if (sc->alc_cdata.alc_rxhead == NULL) { 3716 sc->alc_cdata.alc_rxhead = mp; 3717 sc->alc_cdata.alc_rxtail = mp; 3718 } else { 3719 mp->m_flags &= ~M_PKTHDR; 3720 sc->alc_cdata.alc_rxprev_tail = 3721 sc->alc_cdata.alc_rxtail; 3722 sc->alc_cdata.alc_rxtail->m_next = mp; 3723 sc->alc_cdata.alc_rxtail = mp; 3724 } 3725 3726 if (count == nsegs - 1) { 3727 /* Last desc. for this frame. */ 3728 m = sc->alc_cdata.alc_rxhead; 3729 m->m_flags |= M_PKTHDR; 3730 /* 3731 * It seems that L1C/L2C controller has no way 3732 * to tell hardware to strip CRC bytes. 3733 */ 3734 m->m_pkthdr.len = 3735 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3736 if (nsegs > 1) { 3737 /* Set last mbuf size. */ 3738 mp->m_len = sc->alc_cdata.alc_rxlen - 3739 (nsegs - 1) * sc->alc_buf_size; 3740 /* Remove the CRC bytes in chained mbufs. */ 3741 if (mp->m_len <= ETHER_CRC_LEN) { 3742 sc->alc_cdata.alc_rxtail = 3743 sc->alc_cdata.alc_rxprev_tail; 3744 sc->alc_cdata.alc_rxtail->m_len -= 3745 (ETHER_CRC_LEN - mp->m_len); 3746 sc->alc_cdata.alc_rxtail->m_next = NULL; 3747 m_freem(mp); 3748 } else { 3749 mp->m_len -= ETHER_CRC_LEN; 3750 } 3751 } else 3752 m->m_len = m->m_pkthdr.len; 3753 m->m_pkthdr.rcvif = ifp; 3754 /* 3755 * Due to hardware bugs, Rx checksum offloading 3756 * was intentionally disabled. 3757 */ 3758 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3759 (status & RRD_VLAN_TAG) != 0) { 3760 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3761 m->m_pkthdr.ether_vtag = ntohs(vtag); 3762 m->m_flags |= M_VLANTAG; 3763 } 3764 #ifndef __NO_STRICT_ALIGNMENT 3765 m = alc_fixup_rx(ifp, m); 3766 if (m != NULL) 3767 #endif 3768 { 3769 /* Pass it on. */ 3770 ALC_UNLOCK(sc); 3771 if_input(ifp, m); 3772 ALC_LOCK(sc); 3773 } 3774 } 3775 } 3776 /* Reset mbuf chains. */ 3777 ALC_RXCHAIN_RESET(sc); 3778 } 3779 3780 static void 3781 alc_tick(void *arg) 3782 { 3783 struct alc_softc *sc; 3784 struct mii_data *mii; 3785 3786 sc = (struct alc_softc *)arg; 3787 3788 ALC_LOCK_ASSERT(sc); 3789 3790 mii = device_get_softc(sc->alc_miibus); 3791 mii_tick(mii); 3792 alc_stats_update(sc); 3793 /* 3794 * alc(4) does not rely on Tx completion interrupts to reclaim 3795 * transferred buffers. Instead Tx completion interrupts are 3796 * used to hint for scheduling Tx task. So it's necessary to 3797 * release transmitted buffers by kicking Tx completion 3798 * handler. This limits the maximum reclamation delay to a hz. 3799 */ 3800 alc_txeof(sc); 3801 alc_watchdog(sc); 3802 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3803 } 3804 3805 static void 3806 alc_osc_reset(struct alc_softc *sc) 3807 { 3808 uint32_t reg; 3809 3810 reg = CSR_READ_4(sc, ALC_MISC3); 3811 reg &= ~MISC3_25M_BY_SW; 3812 reg |= MISC3_25M_NOTO_INTNL; 3813 CSR_WRITE_4(sc, ALC_MISC3, reg); 3814 3815 reg = CSR_READ_4(sc, ALC_MISC); 3816 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3817 /* 3818 * Restore over-current protection default value. 3819 * This value could be reset by MAC reset. 3820 */ 3821 reg &= ~MISC_PSW_OCP_MASK; 3822 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3823 reg &= ~MISC_INTNLOSC_OPEN; 3824 CSR_WRITE_4(sc, ALC_MISC, reg); 3825 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3826 reg = CSR_READ_4(sc, ALC_MISC2); 3827 reg &= ~MISC2_CALB_START; 3828 CSR_WRITE_4(sc, ALC_MISC2, reg); 3829 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3830 3831 } else { 3832 reg &= ~MISC_INTNLOSC_OPEN; 3833 /* Disable isolate for revision A devices. */ 3834 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3835 reg &= ~MISC_ISO_ENB; 3836 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3837 CSR_WRITE_4(sc, ALC_MISC, reg); 3838 } 3839 3840 DELAY(20); 3841 } 3842 3843 static void 3844 alc_reset(struct alc_softc *sc) 3845 { 3846 uint32_t pmcfg, reg; 3847 int i; 3848 3849 pmcfg = 0; 3850 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3851 /* Reset workaround. */ 3852 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3853 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3854 (sc->alc_rev & 0x01) != 0) { 3855 /* Disable L0s/L1s before reset. */ 3856 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3857 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3858 != 0) { 3859 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3860 PM_CFG_ASPM_L1_ENB); 3861 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3862 } 3863 } 3864 } 3865 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3866 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3867 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3868 3869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3870 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3871 DELAY(10); 3872 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3873 break; 3874 } 3875 if (i == 0) 3876 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3877 } 3878 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3879 DELAY(10); 3880 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3881 break; 3882 } 3883 if (i == 0) 3884 device_printf(sc->alc_dev, "master reset timeout!\n"); 3885 3886 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3887 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3888 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3889 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3890 break; 3891 DELAY(10); 3892 } 3893 if (i == 0) 3894 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3895 3896 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3897 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3898 (sc->alc_rev & 0x01) != 0) { 3899 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3900 reg |= MASTER_CLK_SEL_DIS; 3901 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3902 /* Restore L0s/L1s config. */ 3903 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3904 != 0) 3905 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3906 } 3907 3908 alc_osc_reset(sc); 3909 reg = CSR_READ_4(sc, ALC_MISC3); 3910 reg &= ~MISC3_25M_BY_SW; 3911 reg |= MISC3_25M_NOTO_INTNL; 3912 CSR_WRITE_4(sc, ALC_MISC3, reg); 3913 reg = CSR_READ_4(sc, ALC_MISC); 3914 reg &= ~MISC_INTNLOSC_OPEN; 3915 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3916 reg &= ~MISC_ISO_ENB; 3917 CSR_WRITE_4(sc, ALC_MISC, reg); 3918 DELAY(20); 3919 } 3920 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3921 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3922 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3923 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3924 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3925 SERDES_PHY_CLK_SLOWDOWN); 3926 } 3927 3928 static void 3929 alc_init(void *xsc) 3930 { 3931 struct alc_softc *sc; 3932 3933 sc = (struct alc_softc *)xsc; 3934 ALC_LOCK(sc); 3935 alc_init_locked(sc); 3936 ALC_UNLOCK(sc); 3937 } 3938 3939 static void 3940 alc_init_locked(struct alc_softc *sc) 3941 { 3942 if_t ifp; 3943 uint8_t eaddr[ETHER_ADDR_LEN]; 3944 bus_addr_t paddr; 3945 uint32_t reg, rxf_hi, rxf_lo; 3946 3947 ALC_LOCK_ASSERT(sc); 3948 3949 ifp = sc->alc_ifp; 3950 3951 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3952 return; 3953 /* 3954 * Cancel any pending I/O. 3955 */ 3956 alc_stop(sc); 3957 /* 3958 * Reset the chip to a known state. 3959 */ 3960 alc_reset(sc); 3961 3962 /* Initialize Rx descriptors. */ 3963 if (alc_init_rx_ring(sc) != 0) { 3964 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3965 alc_stop(sc); 3966 return; 3967 } 3968 alc_init_rr_ring(sc); 3969 alc_init_tx_ring(sc); 3970 alc_init_cmb(sc); 3971 alc_init_smb(sc); 3972 3973 /* Enable all clocks. */ 3974 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3975 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3976 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3977 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3978 CLK_GATING_RXMAC_ENB); 3979 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3980 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3981 IDLE_DECISN_TIMER_DEFAULT_1MS); 3982 } else 3983 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3984 3985 /* Reprogram the station address. */ 3986 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3987 CSR_WRITE_4(sc, ALC_PAR0, 3988 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3989 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3990 /* 3991 * Clear WOL status and disable all WOL feature as WOL 3992 * would interfere Rx operation under normal environments. 3993 */ 3994 CSR_READ_4(sc, ALC_WOL_CFG); 3995 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3996 /* Set Tx descriptor base addresses. */ 3997 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3998 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3999 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4000 /* We don't use high priority ring. */ 4001 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 4002 /* Set Tx descriptor counter. */ 4003 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 4004 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 4005 /* Set Rx descriptor base addresses. */ 4006 paddr = sc->alc_rdata.alc_rx_ring_paddr; 4007 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4008 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4009 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4010 /* We use one Rx ring. */ 4011 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4012 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4013 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4014 } 4015 /* Set Rx descriptor counter. */ 4016 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4017 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4018 4019 /* 4020 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4021 * if it do not fit the buffer size. Rx return descriptor holds 4022 * a counter that indicates how many fragments were made by the 4023 * hardware. The buffer size should be multiple of 8 bytes. 4024 * Since hardware has limit on the size of buffer size, always 4025 * use the maximum value. 4026 * For strict-alignment architectures make sure to reduce buffer 4027 * size by 8 bytes to make room for alignment fixup. 4028 */ 4029 #ifndef __NO_STRICT_ALIGNMENT 4030 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4031 #else 4032 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4033 #endif 4034 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4035 4036 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4037 /* Set Rx return descriptor base addresses. */ 4038 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4039 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4040 /* We use one Rx return ring. */ 4041 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4042 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4043 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4044 } 4045 /* Set Rx return descriptor counter. */ 4046 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4047 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4048 paddr = sc->alc_rdata.alc_cmb_paddr; 4049 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4050 paddr = sc->alc_rdata.alc_smb_paddr; 4051 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4052 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4053 4054 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4055 /* Reconfigure SRAM - Vendor magic. */ 4056 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4057 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4058 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4059 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4060 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4061 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4062 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4063 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4064 } 4065 4066 /* Tell hardware that we're ready to load DMA blocks. */ 4067 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4068 4069 /* Configure interrupt moderation timer. */ 4070 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4071 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4072 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4073 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4074 /* 4075 * We don't want to automatic interrupt clear as task queue 4076 * for the interrupt should know interrupt status. 4077 */ 4078 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4079 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4080 reg |= MASTER_SA_TIMER_ENB; 4081 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4082 reg |= MASTER_IM_RX_TIMER_ENB; 4083 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4084 ALC_USECS(sc->alc_int_tx_mod) != 0) 4085 reg |= MASTER_IM_TX_TIMER_ENB; 4086 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4087 /* 4088 * Disable interrupt re-trigger timer. We don't want automatic 4089 * re-triggering of un-ACKed interrupts. 4090 */ 4091 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4092 /* Configure CMB. */ 4093 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4094 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4095 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4096 ALC_USECS(sc->alc_int_tx_mod)); 4097 } else { 4098 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4099 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4100 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4101 } else 4102 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4103 } 4104 /* 4105 * Hardware can be configured to issue SMB interrupt based 4106 * on programmed interval. Since there is a callout that is 4107 * invoked for every hz in driver we use that instead of 4108 * relying on periodic SMB interrupt. 4109 */ 4110 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4111 /* Clear MAC statistics. */ 4112 alc_stats_clear(sc); 4113 4114 /* 4115 * Always use maximum frame size that controller can support. 4116 * Otherwise received frames that has larger frame length 4117 * than alc(4) MTU would be silently dropped in hardware. This 4118 * would make path-MTU discovery hard as sender wouldn't get 4119 * any responses from receiver. alc(4) supports 4120 * multi-fragmented frames on Rx path so it has no issue on 4121 * assembling fragmented frames. Using maximum frame size also 4122 * removes the need to reinitialize hardware when interface 4123 * MTU configuration was changed. 4124 * 4125 * Be conservative in what you do, be liberal in what you 4126 * accept from others - RFC 793. 4127 */ 4128 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4129 4130 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4131 /* Disable header split(?) */ 4132 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4133 4134 /* Configure IPG/IFG parameters. */ 4135 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4136 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4137 IPG_IFG_IPGT_MASK) | 4138 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4139 IPG_IFG_MIFG_MASK) | 4140 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4141 IPG_IFG_IPG1_MASK) | 4142 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4143 IPG_IFG_IPG2_MASK)); 4144 /* Set parameters for half-duplex media. */ 4145 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4146 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4147 HDPX_CFG_LCOL_MASK) | 4148 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4149 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4150 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4151 HDPX_CFG_ABEBT_MASK) | 4152 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4153 HDPX_CFG_JAMIPG_MASK)); 4154 } 4155 4156 /* 4157 * Set TSO/checksum offload threshold. For frames that is 4158 * larger than this threshold, hardware wouldn't do 4159 * TSO/checksum offloading. 4160 */ 4161 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4162 TSO_OFFLOAD_THRESH_MASK; 4163 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4164 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4165 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4166 /* Configure TxQ. */ 4167 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4168 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4169 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4170 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4171 reg >>= 1; 4172 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4173 TXQ_CFG_TD_BURST_MASK; 4174 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4175 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4176 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4177 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4178 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4179 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4180 HQTD_CFG_BURST_ENB); 4181 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4182 reg = WRR_PRI_RESTRICT_NONE; 4183 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4184 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4185 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4186 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4187 CSR_WRITE_4(sc, ALC_WRR, reg); 4188 } else { 4189 /* Configure Rx free descriptor pre-fetching. */ 4190 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4191 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4192 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4193 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4194 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4195 } 4196 4197 /* 4198 * Configure flow control parameters. 4199 * XON : 80% of Rx FIFO 4200 * XOFF : 30% of Rx FIFO 4201 */ 4202 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4203 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4204 reg &= SRAM_RX_FIFO_LEN_MASK; 4205 reg *= 8; 4206 if (reg > 8 * 1024) 4207 reg -= RX_FIFO_PAUSE_816X_RSVD; 4208 else 4209 reg -= RX_BUF_SIZE_MAX; 4210 reg /= 8; 4211 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4212 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4213 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4214 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4215 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4216 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4217 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4218 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4219 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4220 rxf_hi = (reg * 8) / 10; 4221 rxf_lo = (reg * 3) / 10; 4222 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4223 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4224 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4225 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4226 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4227 } 4228 4229 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4230 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4231 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4232 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4233 } 4234 4235 /* Configure RxQ. */ 4236 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4237 RXQ_CFG_RD_BURST_MASK; 4238 reg |= RXQ_CFG_RSS_MODE_DIS; 4239 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4240 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4241 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4242 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4243 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4244 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4245 } else { 4246 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4247 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4248 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4249 } 4250 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4251 4252 /* Configure DMA parameters. */ 4253 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4254 reg |= sc->alc_rcb; 4255 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4256 reg |= DMA_CFG_CMB_ENB; 4257 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4258 reg |= DMA_CFG_SMB_ENB; 4259 else 4260 reg |= DMA_CFG_SMB_DIS; 4261 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4262 DMA_CFG_RD_BURST_SHIFT; 4263 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4264 DMA_CFG_WR_BURST_SHIFT; 4265 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4266 DMA_CFG_RD_DELAY_CNT_MASK; 4267 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4268 DMA_CFG_WR_DELAY_CNT_MASK; 4269 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4270 switch (AR816X_REV(sc->alc_rev)) { 4271 case AR816X_REV_A0: 4272 case AR816X_REV_A1: 4273 reg |= DMA_CFG_RD_CHNL_SEL_2; 4274 break; 4275 case AR816X_REV_B0: 4276 /* FALLTHROUGH */ 4277 default: 4278 reg |= DMA_CFG_RD_CHNL_SEL_4; 4279 break; 4280 } 4281 } 4282 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4283 4284 /* 4285 * Configure Tx/Rx MACs. 4286 * - Auto-padding for short frames. 4287 * - Enable CRC generation. 4288 * Actual reconfiguration of MAC for resolved speed/duplex 4289 * is followed after detection of link establishment. 4290 * AR813x/AR815x always does checksum computation regardless 4291 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4292 * have bug in protocol field in Rx return structure so 4293 * these controllers can't handle fragmented frames. Disable 4294 * Rx checksum offloading until there is a newer controller 4295 * that has sane implementation. 4296 */ 4297 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4298 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4299 MAC_CFG_PREAMBLE_MASK); 4300 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4301 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4302 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4303 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4304 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4305 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4306 reg |= MAC_CFG_SPEED_10_100; 4307 else 4308 reg |= MAC_CFG_SPEED_1000; 4309 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4310 4311 /* Set up the receive filter. */ 4312 alc_rxfilter(sc); 4313 alc_rxvlan(sc); 4314 4315 /* Acknowledge all pending interrupts and clear it. */ 4316 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4317 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4318 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4319 4320 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4321 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4322 4323 sc->alc_flags &= ~ALC_FLAG_LINK; 4324 /* Switch to the current media. */ 4325 alc_mediachange_locked(sc); 4326 4327 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4328 } 4329 4330 static void 4331 alc_stop(struct alc_softc *sc) 4332 { 4333 if_t ifp; 4334 struct alc_txdesc *txd; 4335 struct alc_rxdesc *rxd; 4336 uint32_t reg; 4337 int i; 4338 4339 ALC_LOCK_ASSERT(sc); 4340 /* 4341 * Mark the interface down and cancel the watchdog timer. 4342 */ 4343 ifp = sc->alc_ifp; 4344 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4345 sc->alc_flags &= ~ALC_FLAG_LINK; 4346 callout_stop(&sc->alc_tick_ch); 4347 sc->alc_watchdog_timer = 0; 4348 alc_stats_update(sc); 4349 /* Disable interrupts. */ 4350 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4351 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4352 /* Disable DMA. */ 4353 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4354 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4355 reg |= DMA_CFG_SMB_DIS; 4356 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4357 DELAY(1000); 4358 /* Stop Rx/Tx MACs. */ 4359 alc_stop_mac(sc); 4360 /* Disable interrupts which might be touched in taskq handler. */ 4361 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4362 /* Disable L0s/L1s */ 4363 alc_aspm(sc, 0, IFM_UNKNOWN); 4364 /* Reclaim Rx buffers that have been processed. */ 4365 if (sc->alc_cdata.alc_rxhead != NULL) 4366 m_freem(sc->alc_cdata.alc_rxhead); 4367 ALC_RXCHAIN_RESET(sc); 4368 /* 4369 * Free Tx/Rx mbufs still in the queues. 4370 */ 4371 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4372 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4373 if (rxd->rx_m != NULL) { 4374 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4375 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4376 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4377 rxd->rx_dmamap); 4378 m_freem(rxd->rx_m); 4379 rxd->rx_m = NULL; 4380 } 4381 } 4382 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4383 txd = &sc->alc_cdata.alc_txdesc[i]; 4384 if (txd->tx_m != NULL) { 4385 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4386 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4387 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4388 txd->tx_dmamap); 4389 m_freem(txd->tx_m); 4390 txd->tx_m = NULL; 4391 } 4392 } 4393 } 4394 4395 static void 4396 alc_stop_mac(struct alc_softc *sc) 4397 { 4398 uint32_t reg; 4399 int i; 4400 4401 alc_stop_queue(sc); 4402 /* Disable Rx/Tx MAC. */ 4403 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4404 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4405 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4406 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4407 } 4408 for (i = ALC_TIMEOUT; i > 0; i--) { 4409 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4410 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4411 break; 4412 DELAY(10); 4413 } 4414 if (i == 0) 4415 device_printf(sc->alc_dev, 4416 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4417 } 4418 4419 static void 4420 alc_start_queue(struct alc_softc *sc) 4421 { 4422 uint32_t qcfg[] = { 4423 0, 4424 RXQ_CFG_QUEUE0_ENB, 4425 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4426 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4427 RXQ_CFG_ENB 4428 }; 4429 uint32_t cfg; 4430 4431 ALC_LOCK_ASSERT(sc); 4432 4433 /* Enable RxQ. */ 4434 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4435 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4436 cfg &= ~RXQ_CFG_ENB; 4437 cfg |= qcfg[1]; 4438 } else 4439 cfg |= RXQ_CFG_QUEUE0_ENB; 4440 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4441 /* Enable TxQ. */ 4442 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4443 cfg |= TXQ_CFG_ENB; 4444 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4445 } 4446 4447 static void 4448 alc_stop_queue(struct alc_softc *sc) 4449 { 4450 uint32_t reg; 4451 int i; 4452 4453 /* Disable RxQ. */ 4454 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4455 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4456 if ((reg & RXQ_CFG_ENB) != 0) { 4457 reg &= ~RXQ_CFG_ENB; 4458 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4459 } 4460 } else { 4461 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4462 reg &= ~RXQ_CFG_QUEUE0_ENB; 4463 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4464 } 4465 } 4466 /* Disable TxQ. */ 4467 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4468 if ((reg & TXQ_CFG_ENB) != 0) { 4469 reg &= ~TXQ_CFG_ENB; 4470 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4471 } 4472 DELAY(40); 4473 for (i = ALC_TIMEOUT; i > 0; i--) { 4474 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4475 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4476 break; 4477 DELAY(10); 4478 } 4479 if (i == 0) 4480 device_printf(sc->alc_dev, 4481 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4482 } 4483 4484 static void 4485 alc_init_tx_ring(struct alc_softc *sc) 4486 { 4487 struct alc_ring_data *rd; 4488 struct alc_txdesc *txd; 4489 int i; 4490 4491 ALC_LOCK_ASSERT(sc); 4492 4493 sc->alc_cdata.alc_tx_prod = 0; 4494 sc->alc_cdata.alc_tx_cons = 0; 4495 sc->alc_cdata.alc_tx_cnt = 0; 4496 4497 rd = &sc->alc_rdata; 4498 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4499 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4500 txd = &sc->alc_cdata.alc_txdesc[i]; 4501 txd->tx_m = NULL; 4502 } 4503 4504 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4505 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4506 } 4507 4508 static int 4509 alc_init_rx_ring(struct alc_softc *sc) 4510 { 4511 struct alc_ring_data *rd; 4512 struct alc_rxdesc *rxd; 4513 int i; 4514 4515 ALC_LOCK_ASSERT(sc); 4516 4517 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4518 sc->alc_morework = 0; 4519 rd = &sc->alc_rdata; 4520 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4521 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4522 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4523 rxd->rx_m = NULL; 4524 rxd->rx_desc = &rd->alc_rx_ring[i]; 4525 if (alc_newbuf(sc, rxd) != 0) 4526 return (ENOBUFS); 4527 } 4528 4529 /* 4530 * Since controller does not update Rx descriptors, driver 4531 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4532 * is enough to ensure coherence. 4533 */ 4534 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4535 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4536 /* Let controller know availability of new Rx buffers. */ 4537 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4538 4539 return (0); 4540 } 4541 4542 static void 4543 alc_init_rr_ring(struct alc_softc *sc) 4544 { 4545 struct alc_ring_data *rd; 4546 4547 ALC_LOCK_ASSERT(sc); 4548 4549 sc->alc_cdata.alc_rr_cons = 0; 4550 ALC_RXCHAIN_RESET(sc); 4551 4552 rd = &sc->alc_rdata; 4553 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4554 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4555 sc->alc_cdata.alc_rr_ring_map, 4556 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4557 } 4558 4559 static void 4560 alc_init_cmb(struct alc_softc *sc) 4561 { 4562 struct alc_ring_data *rd; 4563 4564 ALC_LOCK_ASSERT(sc); 4565 4566 rd = &sc->alc_rdata; 4567 bzero(rd->alc_cmb, ALC_CMB_SZ); 4568 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4570 } 4571 4572 static void 4573 alc_init_smb(struct alc_softc *sc) 4574 { 4575 struct alc_ring_data *rd; 4576 4577 ALC_LOCK_ASSERT(sc); 4578 4579 rd = &sc->alc_rdata; 4580 bzero(rd->alc_smb, ALC_SMB_SZ); 4581 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4582 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4583 } 4584 4585 static void 4586 alc_rxvlan(struct alc_softc *sc) 4587 { 4588 if_t ifp; 4589 uint32_t reg; 4590 4591 ALC_LOCK_ASSERT(sc); 4592 4593 ifp = sc->alc_ifp; 4594 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4595 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4596 reg |= MAC_CFG_VLAN_TAG_STRIP; 4597 else 4598 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4599 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4600 } 4601 4602 static u_int 4603 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4604 { 4605 uint32_t *mchash = arg; 4606 uint32_t crc; 4607 4608 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4609 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4610 4611 return (1); 4612 } 4613 4614 static void 4615 alc_rxfilter(struct alc_softc *sc) 4616 { 4617 if_t ifp; 4618 uint32_t mchash[2]; 4619 uint32_t rxcfg; 4620 4621 ALC_LOCK_ASSERT(sc); 4622 4623 ifp = sc->alc_ifp; 4624 4625 bzero(mchash, sizeof(mchash)); 4626 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4627 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4628 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4629 rxcfg |= MAC_CFG_BCAST; 4630 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4631 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4632 rxcfg |= MAC_CFG_PROMISC; 4633 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4634 rxcfg |= MAC_CFG_ALLMULTI; 4635 mchash[0] = 0xFFFFFFFF; 4636 mchash[1] = 0xFFFFFFFF; 4637 goto chipit; 4638 } 4639 4640 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4641 4642 chipit: 4643 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4644 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4645 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4646 } 4647 4648 static int 4649 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4650 { 4651 int error, value; 4652 4653 if (arg1 == NULL) 4654 return (EINVAL); 4655 value = *(int *)arg1; 4656 error = sysctl_handle_int(oidp, &value, 0, req); 4657 if (error || req->newptr == NULL) 4658 return (error); 4659 if (value < low || value > high) 4660 return (EINVAL); 4661 *(int *)arg1 = value; 4662 4663 return (0); 4664 } 4665 4666 static int 4667 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4668 { 4669 return (sysctl_int_range(oidp, arg1, arg2, req, 4670 ALC_PROC_MIN, ALC_PROC_MAX)); 4671 } 4672 4673 static int 4674 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4675 { 4676 4677 return (sysctl_int_range(oidp, arg1, arg2, req, 4678 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4679 } 4680 4681 #ifdef DEBUGNET 4682 static void 4683 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4684 { 4685 struct alc_softc *sc __diagused; 4686 4687 sc = if_getsoftc(ifp); 4688 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4689 4690 *nrxr = ALC_RX_RING_CNT; 4691 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4692 *clsize = MCLBYTES; 4693 } 4694 4695 static void 4696 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4697 { 4698 } 4699 4700 static int 4701 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4702 { 4703 struct alc_softc *sc; 4704 int error; 4705 4706 sc = if_getsoftc(ifp); 4707 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4708 IFF_DRV_RUNNING) 4709 return (EBUSY); 4710 4711 error = alc_encap(sc, &m); 4712 if (error == 0) 4713 alc_start_tx(sc); 4714 return (error); 4715 } 4716 4717 static int 4718 alc_debugnet_poll(if_t ifp, int count) 4719 { 4720 struct alc_softc *sc; 4721 4722 sc = if_getsoftc(ifp); 4723 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4724 IFF_DRV_RUNNING) 4725 return (EBUSY); 4726 4727 alc_txeof(sc); 4728 return (alc_rxintr(sc, count)); 4729 } 4730 #endif /* DEBUGNET */ 4731