1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 static int msix_disable = 0; 95 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98 /* 99 * Devices supported by this driver. 100 */ 101 static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { 0, 0, 0, NULL} 115 }; 116 117 static void alc_aspm(struct alc_softc *, int); 118 static int alc_attach(device_t); 119 static int alc_check_boundary(struct alc_softc *); 120 static int alc_detach(device_t); 121 static void alc_disable_l0s_l1(struct alc_softc *); 122 static int alc_dma_alloc(struct alc_softc *); 123 static void alc_dma_free(struct alc_softc *); 124 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 125 static int alc_encap(struct alc_softc *, struct mbuf **); 126 static struct alc_ident * 127 alc_find_ident(device_t); 128 #ifndef __NO_STRICT_ALIGNMENT 129 static struct mbuf * 130 alc_fixup_rx(struct ifnet *, struct mbuf *); 131 #endif 132 static void alc_get_macaddr(struct alc_softc *); 133 static void alc_init(void *); 134 static void alc_init_cmb(struct alc_softc *); 135 static void alc_init_locked(struct alc_softc *); 136 static void alc_init_rr_ring(struct alc_softc *); 137 static int alc_init_rx_ring(struct alc_softc *); 138 static void alc_init_smb(struct alc_softc *); 139 static void alc_init_tx_ring(struct alc_softc *); 140 static void alc_int_task(void *, int); 141 static int alc_intr(void *); 142 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 143 static void alc_mac_config(struct alc_softc *); 144 static int alc_miibus_readreg(device_t, int, int); 145 static void alc_miibus_statchg(device_t); 146 static int alc_miibus_writereg(device_t, int, int, int); 147 static int alc_mediachange(struct ifnet *); 148 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 149 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 150 static void alc_phy_down(struct alc_softc *); 151 static void alc_phy_reset(struct alc_softc *); 152 static int alc_probe(device_t); 153 static void alc_reset(struct alc_softc *); 154 static int alc_resume(device_t); 155 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 156 static int alc_rxintr(struct alc_softc *, int); 157 static void alc_rxfilter(struct alc_softc *); 158 static void alc_rxvlan(struct alc_softc *); 159 static void alc_setlinkspeed(struct alc_softc *); 160 static void alc_setwol(struct alc_softc *); 161 static int alc_shutdown(device_t); 162 static void alc_start(struct ifnet *); 163 static void alc_start_locked(struct ifnet *); 164 static void alc_start_queue(struct alc_softc *); 165 static void alc_stats_clear(struct alc_softc *); 166 static void alc_stats_update(struct alc_softc *); 167 static void alc_stop(struct alc_softc *); 168 static void alc_stop_mac(struct alc_softc *); 169 static void alc_stop_queue(struct alc_softc *); 170 static int alc_suspend(device_t); 171 static void alc_sysctl_node(struct alc_softc *); 172 static void alc_tick(void *); 173 static void alc_txeof(struct alc_softc *); 174 static void alc_watchdog(struct alc_softc *); 175 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 176 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 177 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 178 179 static device_method_t alc_methods[] = { 180 /* Device interface. */ 181 DEVMETHOD(device_probe, alc_probe), 182 DEVMETHOD(device_attach, alc_attach), 183 DEVMETHOD(device_detach, alc_detach), 184 DEVMETHOD(device_shutdown, alc_shutdown), 185 DEVMETHOD(device_suspend, alc_suspend), 186 DEVMETHOD(device_resume, alc_resume), 187 188 /* MII interface. */ 189 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 190 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 191 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 192 193 { NULL, NULL } 194 }; 195 196 static driver_t alc_driver = { 197 "alc", 198 alc_methods, 199 sizeof(struct alc_softc) 200 }; 201 202 static devclass_t alc_devclass; 203 204 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 205 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 206 207 static struct resource_spec alc_res_spec_mem[] = { 208 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 209 { -1, 0, 0 } 210 }; 211 212 static struct resource_spec alc_irq_spec_legacy[] = { 213 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 214 { -1, 0, 0 } 215 }; 216 217 static struct resource_spec alc_irq_spec_msi[] = { 218 { SYS_RES_IRQ, 1, RF_ACTIVE }, 219 { -1, 0, 0 } 220 }; 221 222 static struct resource_spec alc_irq_spec_msix[] = { 223 { SYS_RES_IRQ, 1, RF_ACTIVE }, 224 { -1, 0, 0 } 225 }; 226 227 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 228 229 static int 230 alc_miibus_readreg(device_t dev, int phy, int reg) 231 { 232 struct alc_softc *sc; 233 uint32_t v; 234 int i; 235 236 sc = device_get_softc(dev); 237 238 /* 239 * For AR8132 fast ethernet controller, do not report 1000baseT 240 * capability to mii(4). Even though AR8132 uses the same 241 * model/revision number of F1 gigabit PHY, the PHY has no 242 * ability to establish 1000baseT link. 243 */ 244 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 245 reg == MII_EXTSR) 246 return (0); 247 248 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 250 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(5); 252 v = CSR_READ_4(sc, ALC_MDIO); 253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 254 break; 255 } 256 257 if (i == 0) { 258 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 259 return (0); 260 } 261 262 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 263 } 264 265 static int 266 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 267 { 268 struct alc_softc *sc; 269 uint32_t v; 270 int i; 271 272 sc = device_get_softc(dev); 273 274 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 275 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 276 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 277 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 278 DELAY(5); 279 v = CSR_READ_4(sc, ALC_MDIO); 280 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 281 break; 282 } 283 284 if (i == 0) 285 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 286 287 return (0); 288 } 289 290 static void 291 alc_miibus_statchg(device_t dev) 292 { 293 struct alc_softc *sc; 294 struct mii_data *mii; 295 struct ifnet *ifp; 296 uint32_t reg; 297 298 sc = device_get_softc(dev); 299 300 mii = device_get_softc(sc->alc_miibus); 301 ifp = sc->alc_ifp; 302 if (mii == NULL || ifp == NULL || 303 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 304 return; 305 306 sc->alc_flags &= ~ALC_FLAG_LINK; 307 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 308 (IFM_ACTIVE | IFM_AVALID)) { 309 switch (IFM_SUBTYPE(mii->mii_media_active)) { 310 case IFM_10_T: 311 case IFM_100_TX: 312 sc->alc_flags |= ALC_FLAG_LINK; 313 break; 314 case IFM_1000_T: 315 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 316 sc->alc_flags |= ALC_FLAG_LINK; 317 break; 318 default: 319 break; 320 } 321 } 322 alc_stop_queue(sc); 323 /* Stop Rx/Tx MACs. */ 324 alc_stop_mac(sc); 325 326 /* Program MACs with resolved speed/duplex/flow-control. */ 327 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 328 alc_start_queue(sc); 329 alc_mac_config(sc); 330 /* Re-enable Tx/Rx MACs. */ 331 reg = CSR_READ_4(sc, ALC_MAC_CFG); 332 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 333 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 334 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 335 } 336 } 337 338 static void 339 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 340 { 341 struct alc_softc *sc; 342 struct mii_data *mii; 343 344 sc = ifp->if_softc; 345 ALC_LOCK(sc); 346 if ((ifp->if_flags & IFF_UP) == 0) { 347 ALC_UNLOCK(sc); 348 return; 349 } 350 mii = device_get_softc(sc->alc_miibus); 351 352 mii_pollstat(mii); 353 ifmr->ifm_status = mii->mii_media_status; 354 ifmr->ifm_active = mii->mii_media_active; 355 ALC_UNLOCK(sc); 356 } 357 358 static int 359 alc_mediachange(struct ifnet *ifp) 360 { 361 struct alc_softc *sc; 362 struct mii_data *mii; 363 struct mii_softc *miisc; 364 int error; 365 366 sc = ifp->if_softc; 367 ALC_LOCK(sc); 368 mii = device_get_softc(sc->alc_miibus); 369 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 370 PHY_RESET(miisc); 371 error = mii_mediachg(mii); 372 ALC_UNLOCK(sc); 373 374 return (error); 375 } 376 377 static struct alc_ident * 378 alc_find_ident(device_t dev) 379 { 380 struct alc_ident *ident; 381 uint16_t vendor, devid; 382 383 vendor = pci_get_vendor(dev); 384 devid = pci_get_device(dev); 385 for (ident = alc_ident_table; ident->name != NULL; ident++) { 386 if (vendor == ident->vendorid && devid == ident->deviceid) 387 return (ident); 388 } 389 390 return (NULL); 391 } 392 393 static int 394 alc_probe(device_t dev) 395 { 396 struct alc_ident *ident; 397 398 ident = alc_find_ident(dev); 399 if (ident != NULL) { 400 device_set_desc(dev, ident->name); 401 return (BUS_PROBE_DEFAULT); 402 } 403 404 return (ENXIO); 405 } 406 407 static void 408 alc_get_macaddr(struct alc_softc *sc) 409 { 410 uint32_t ea[2], opt; 411 uint16_t val; 412 int eeprom, i; 413 414 eeprom = 0; 415 opt = CSR_READ_4(sc, ALC_OPT_CFG); 416 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 417 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 418 /* 419 * EEPROM found, let TWSI reload EEPROM configuration. 420 * This will set ethernet address of controller. 421 */ 422 eeprom++; 423 switch (sc->alc_ident->deviceid) { 424 case DEVICEID_ATHEROS_AR8131: 425 case DEVICEID_ATHEROS_AR8132: 426 if ((opt & OPT_CFG_CLK_ENB) == 0) { 427 opt |= OPT_CFG_CLK_ENB; 428 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 429 CSR_READ_4(sc, ALC_OPT_CFG); 430 DELAY(1000); 431 } 432 break; 433 case DEVICEID_ATHEROS_AR8151: 434 case DEVICEID_ATHEROS_AR8151_V2: 435 case DEVICEID_ATHEROS_AR8152_B: 436 case DEVICEID_ATHEROS_AR8152_B2: 437 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 438 ALC_MII_DBG_ADDR, 0x00); 439 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 440 ALC_MII_DBG_DATA); 441 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 442 ALC_MII_DBG_DATA, val & 0xFF7F); 443 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 444 ALC_MII_DBG_ADDR, 0x3B); 445 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_DATA); 447 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 448 ALC_MII_DBG_DATA, val | 0x0008); 449 DELAY(20); 450 break; 451 } 452 453 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 454 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 455 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 456 CSR_READ_4(sc, ALC_WOL_CFG); 457 458 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 459 TWSI_CFG_SW_LD_START); 460 for (i = 100; i > 0; i--) { 461 DELAY(1000); 462 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 463 TWSI_CFG_SW_LD_START) == 0) 464 break; 465 } 466 if (i == 0) 467 device_printf(sc->alc_dev, 468 "reloading EEPROM timeout!\n"); 469 } else { 470 if (bootverbose) 471 device_printf(sc->alc_dev, "EEPROM not found!\n"); 472 } 473 if (eeprom != 0) { 474 switch (sc->alc_ident->deviceid) { 475 case DEVICEID_ATHEROS_AR8131: 476 case DEVICEID_ATHEROS_AR8132: 477 if ((opt & OPT_CFG_CLK_ENB) != 0) { 478 opt &= ~OPT_CFG_CLK_ENB; 479 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 480 CSR_READ_4(sc, ALC_OPT_CFG); 481 DELAY(1000); 482 } 483 break; 484 case DEVICEID_ATHEROS_AR8151: 485 case DEVICEID_ATHEROS_AR8151_V2: 486 case DEVICEID_ATHEROS_AR8152_B: 487 case DEVICEID_ATHEROS_AR8152_B2: 488 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_ADDR, 0x00); 490 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 491 ALC_MII_DBG_DATA); 492 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 493 ALC_MII_DBG_DATA, val | 0x0080); 494 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 495 ALC_MII_DBG_ADDR, 0x3B); 496 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_DATA); 498 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 499 ALC_MII_DBG_DATA, val & 0xFFF7); 500 DELAY(20); 501 break; 502 } 503 } 504 505 ea[0] = CSR_READ_4(sc, ALC_PAR0); 506 ea[1] = CSR_READ_4(sc, ALC_PAR1); 507 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 508 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 509 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 510 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 511 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 512 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 513 } 514 515 static void 516 alc_disable_l0s_l1(struct alc_softc *sc) 517 { 518 uint32_t pmcfg; 519 520 /* Another magic from vendor. */ 521 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 522 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 523 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 524 PM_CFG_SERDES_PD_EX_L1); 525 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 526 PM_CFG_SERDES_L1_ENB; 527 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 528 } 529 530 static void 531 alc_phy_reset(struct alc_softc *sc) 532 { 533 uint16_t data; 534 535 /* Reset magic from Linux. */ 536 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 537 CSR_READ_2(sc, ALC_GPHY_CFG); 538 DELAY(10 * 1000); 539 540 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 541 GPHY_CFG_SEL_ANA_RESET); 542 CSR_READ_2(sc, ALC_GPHY_CFG); 543 DELAY(10 * 1000); 544 545 /* DSP fixup, Vendor magic. */ 546 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 547 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 548 ALC_MII_DBG_ADDR, 0x000A); 549 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 550 ALC_MII_DBG_DATA); 551 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 552 ALC_MII_DBG_DATA, data & 0xDFFF); 553 } 554 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 555 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 556 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 557 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 558 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 559 ALC_MII_DBG_ADDR, 0x003B); 560 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 561 ALC_MII_DBG_DATA); 562 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 563 ALC_MII_DBG_DATA, data & 0xFFF7); 564 DELAY(20 * 1000); 565 } 566 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 567 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 568 ALC_MII_DBG_ADDR, 0x0029); 569 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 570 ALC_MII_DBG_DATA, 0x929D); 571 } 572 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 573 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 574 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 575 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 576 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 577 ALC_MII_DBG_ADDR, 0x0029); 578 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 579 ALC_MII_DBG_DATA, 0xB6DD); 580 } 581 582 /* Load DSP codes, vendor magic. */ 583 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 584 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 585 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 586 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 587 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 588 ALC_MII_DBG_DATA, data); 589 590 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 591 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 592 ANA_SERDES_EN_LCKDT; 593 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 594 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 595 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 596 ALC_MII_DBG_DATA, data); 597 598 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 599 ANA_LONG_CABLE_TH_100_MASK) | 600 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 601 ANA_SHORT_CABLE_TH_100_SHIFT) | 602 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 603 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 604 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 605 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 606 ALC_MII_DBG_DATA, data); 607 608 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 609 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 610 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 611 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 612 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 613 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 614 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 615 ALC_MII_DBG_DATA, data); 616 617 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 618 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 619 ANA_OEN_125M; 620 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 621 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 622 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_DATA, data); 624 DELAY(1000); 625 626 /* Disable hibernation. */ 627 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 628 0x0029); 629 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 630 ALC_MII_DBG_DATA); 631 data &= ~0x8000; 632 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 633 data); 634 635 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 636 0x000B); 637 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 638 ALC_MII_DBG_DATA); 639 data &= ~0x8000; 640 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 641 data); 642 } 643 644 static void 645 alc_phy_down(struct alc_softc *sc) 646 { 647 648 switch (sc->alc_ident->deviceid) { 649 case DEVICEID_ATHEROS_AR8151: 650 case DEVICEID_ATHEROS_AR8151_V2: 651 /* 652 * GPHY power down caused more problems on AR8151 v2.0. 653 * When driver is reloaded after GPHY power down, 654 * accesses to PHY/MAC registers hung the system. Only 655 * cold boot recovered from it. I'm not sure whether 656 * AR8151 v1.0 also requires this one though. I don't 657 * have AR8151 v1.0 controller in hand. 658 * The only option left is to isolate the PHY and 659 * initiates power down the PHY which in turn saves 660 * more power when driver is unloaded. 661 */ 662 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 663 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 664 break; 665 default: 666 /* Force PHY down. */ 667 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 668 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 669 GPHY_CFG_PWDOWN_HW); 670 DELAY(1000); 671 break; 672 } 673 } 674 675 static void 676 alc_aspm(struct alc_softc *sc, int media) 677 { 678 uint32_t pmcfg; 679 uint16_t linkcfg; 680 681 ALC_LOCK_ASSERT(sc); 682 683 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 684 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 685 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 686 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 687 PCIER_LINK_CTL); 688 else 689 linkcfg = 0; 690 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 691 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 692 pmcfg |= PM_CFG_MAC_ASPM_CHK; 693 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 694 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 695 696 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 697 /* Disable extended sync except AR8152 B v1.0 */ 698 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 699 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 700 sc->alc_rev == ATHEROS_AR8152_B_V10) 701 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 702 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 703 linkcfg); 704 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 705 PM_CFG_HOTRST); 706 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 707 PM_CFG_L1_ENTRY_TIMER_SHIFT); 708 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 709 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 710 PM_CFG_PM_REQ_TIMER_SHIFT); 711 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 712 } 713 714 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 715 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 716 pmcfg |= PM_CFG_ASPM_L0S_ENB; 717 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 718 pmcfg |= PM_CFG_ASPM_L1_ENB; 719 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 720 if (sc->alc_ident->deviceid == 721 DEVICEID_ATHEROS_AR8152_B) 722 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 723 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 724 PM_CFG_SERDES_PLL_L1_ENB | 725 PM_CFG_SERDES_BUDS_RX_L1_ENB); 726 pmcfg |= PM_CFG_CLK_SWH_L1; 727 if (media == IFM_100_TX || media == IFM_1000_T) { 728 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 729 switch (sc->alc_ident->deviceid) { 730 case DEVICEID_ATHEROS_AR8152_B: 731 pmcfg |= (7 << 732 PM_CFG_L1_ENTRY_TIMER_SHIFT); 733 break; 734 case DEVICEID_ATHEROS_AR8152_B2: 735 case DEVICEID_ATHEROS_AR8151_V2: 736 pmcfg |= (4 << 737 PM_CFG_L1_ENTRY_TIMER_SHIFT); 738 break; 739 default: 740 pmcfg |= (15 << 741 PM_CFG_L1_ENTRY_TIMER_SHIFT); 742 break; 743 } 744 } 745 } else { 746 pmcfg |= PM_CFG_SERDES_L1_ENB | 747 PM_CFG_SERDES_PLL_L1_ENB | 748 PM_CFG_SERDES_BUDS_RX_L1_ENB; 749 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 750 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 751 } 752 } else { 753 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 754 PM_CFG_SERDES_PLL_L1_ENB); 755 pmcfg |= PM_CFG_CLK_SWH_L1; 756 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 757 pmcfg |= PM_CFG_ASPM_L1_ENB; 758 } 759 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 760 } 761 762 static int 763 alc_attach(device_t dev) 764 { 765 struct alc_softc *sc; 766 struct ifnet *ifp; 767 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 768 uint16_t burst; 769 int base, error, i, msic, msixc, state; 770 uint32_t cap, ctl, val; 771 772 error = 0; 773 sc = device_get_softc(dev); 774 sc->alc_dev = dev; 775 776 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 777 MTX_DEF); 778 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 779 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 780 sc->alc_ident = alc_find_ident(dev); 781 782 /* Map the device. */ 783 pci_enable_busmaster(dev); 784 sc->alc_res_spec = alc_res_spec_mem; 785 sc->alc_irq_spec = alc_irq_spec_legacy; 786 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 787 if (error != 0) { 788 device_printf(dev, "cannot allocate memory resources.\n"); 789 goto fail; 790 } 791 792 /* Set PHY address. */ 793 sc->alc_phyaddr = ALC_PHY_ADDR; 794 795 /* Initialize DMA parameters. */ 796 sc->alc_dma_rd_burst = 0; 797 sc->alc_dma_wr_burst = 0; 798 sc->alc_rcb = DMA_CFG_RCB_64; 799 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 800 sc->alc_flags |= ALC_FLAG_PCIE; 801 sc->alc_expcap = base; 802 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 803 sc->alc_dma_rd_burst = 804 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 805 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 806 if (bootverbose) { 807 device_printf(dev, "Read request size : %u bytes.\n", 808 alc_dma_burst[sc->alc_dma_rd_burst]); 809 device_printf(dev, "TLP payload size : %u bytes.\n", 810 alc_dma_burst[sc->alc_dma_wr_burst]); 811 } 812 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 813 sc->alc_dma_rd_burst = 3; 814 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 815 sc->alc_dma_wr_burst = 3; 816 /* Clear data link and flow-control protocol error. */ 817 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 818 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 819 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 820 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 821 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 822 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 823 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 824 PCIE_PHYMISC_FORCE_RCV_DET); 825 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 826 pci_get_revid(dev) == ATHEROS_AR8152_B_V10) { 827 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 828 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 829 PCIE_PHYMISC2_SERDES_TH_MASK); 830 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 831 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 832 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 833 } 834 /* Disable ASPM L0S and L1. */ 835 cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); 836 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 837 ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); 838 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 839 sc->alc_rcb = DMA_CFG_RCB_128; 840 if (bootverbose) 841 device_printf(dev, "RCB %u bytes\n", 842 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 843 state = ctl & PCIEM_LINK_CTL_ASPMC; 844 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 845 sc->alc_flags |= ALC_FLAG_L0S; 846 if (state & PCIEM_LINK_CTL_ASPMC_L1) 847 sc->alc_flags |= ALC_FLAG_L1S; 848 if (bootverbose) 849 device_printf(sc->alc_dev, "ASPM %s %s\n", 850 aspm_state[state], 851 state == 0 ? "disabled" : "enabled"); 852 alc_disable_l0s_l1(sc); 853 } else { 854 if (bootverbose) 855 device_printf(sc->alc_dev, 856 "no ASPM support\n"); 857 } 858 } 859 860 /* Reset PHY. */ 861 alc_phy_reset(sc); 862 863 /* Reset the ethernet controller. */ 864 alc_reset(sc); 865 866 /* 867 * One odd thing is AR8132 uses the same PHY hardware(F1 868 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 869 * the PHY supports 1000Mbps but that's not true. The PHY 870 * used in AR8132 can't establish gigabit link even if it 871 * shows the same PHY model/revision number of AR8131. 872 */ 873 switch (sc->alc_ident->deviceid) { 874 case DEVICEID_ATHEROS_AR8152_B: 875 case DEVICEID_ATHEROS_AR8152_B2: 876 sc->alc_flags |= ALC_FLAG_APS; 877 /* FALLTHROUGH */ 878 case DEVICEID_ATHEROS_AR8132: 879 sc->alc_flags |= ALC_FLAG_FASTETHER; 880 break; 881 case DEVICEID_ATHEROS_AR8151: 882 case DEVICEID_ATHEROS_AR8151_V2: 883 sc->alc_flags |= ALC_FLAG_APS; 884 /* FALLTHROUGH */ 885 default: 886 break; 887 } 888 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 889 890 /* 891 * It seems that AR813x/AR815x has silicon bug for SMB. In 892 * addition, Atheros said that enabling SMB wouldn't improve 893 * performance. However I think it's bad to access lots of 894 * registers to extract MAC statistics. 895 */ 896 sc->alc_flags |= ALC_FLAG_SMB_BUG; 897 /* 898 * Don't use Tx CMB. It is known to have silicon bug. 899 */ 900 sc->alc_flags |= ALC_FLAG_CMB_BUG; 901 sc->alc_rev = pci_get_revid(dev); 902 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 903 MASTER_CHIP_REV_SHIFT; 904 if (bootverbose) { 905 device_printf(dev, "PCI device revision : 0x%04x\n", 906 sc->alc_rev); 907 device_printf(dev, "Chip id/revision : 0x%04x\n", 908 sc->alc_chip_rev); 909 } 910 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 911 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 912 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 913 914 /* Allocate IRQ resources. */ 915 msixc = pci_msix_count(dev); 916 msic = pci_msi_count(dev); 917 if (bootverbose) { 918 device_printf(dev, "MSIX count : %d\n", msixc); 919 device_printf(dev, "MSI count : %d\n", msic); 920 } 921 /* Prefer MSIX over MSI. */ 922 if (msix_disable == 0 || msi_disable == 0) { 923 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 924 pci_alloc_msix(dev, &msixc) == 0) { 925 if (msic == ALC_MSIX_MESSAGES) { 926 device_printf(dev, 927 "Using %d MSIX message(s).\n", msixc); 928 sc->alc_flags |= ALC_FLAG_MSIX; 929 sc->alc_irq_spec = alc_irq_spec_msix; 930 } else 931 pci_release_msi(dev); 932 } 933 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 934 msic == ALC_MSI_MESSAGES && 935 pci_alloc_msi(dev, &msic) == 0) { 936 if (msic == ALC_MSI_MESSAGES) { 937 device_printf(dev, 938 "Using %d MSI message(s).\n", msic); 939 sc->alc_flags |= ALC_FLAG_MSI; 940 sc->alc_irq_spec = alc_irq_spec_msi; 941 } else 942 pci_release_msi(dev); 943 } 944 } 945 946 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 947 if (error != 0) { 948 device_printf(dev, "cannot allocate IRQ resources.\n"); 949 goto fail; 950 } 951 952 /* Create device sysctl node. */ 953 alc_sysctl_node(sc); 954 955 if ((error = alc_dma_alloc(sc) != 0)) 956 goto fail; 957 958 /* Load station address. */ 959 alc_get_macaddr(sc); 960 961 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 962 if (ifp == NULL) { 963 device_printf(dev, "cannot allocate ifnet structure.\n"); 964 error = ENXIO; 965 goto fail; 966 } 967 968 ifp->if_softc = sc; 969 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 970 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 971 ifp->if_ioctl = alc_ioctl; 972 ifp->if_start = alc_start; 973 ifp->if_init = alc_init; 974 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 975 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 976 IFQ_SET_READY(&ifp->if_snd); 977 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 978 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 979 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 980 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 981 sc->alc_flags |= ALC_FLAG_PM; 982 sc->alc_pmcap = base; 983 } 984 ifp->if_capenable = ifp->if_capabilities; 985 986 /* Set up MII bus. */ 987 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 988 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 989 MIIF_DOPAUSE); 990 if (error != 0) { 991 device_printf(dev, "attaching PHYs failed\n"); 992 goto fail; 993 } 994 995 ether_ifattach(ifp, sc->alc_eaddr); 996 997 /* VLAN capability setup. */ 998 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 999 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1000 ifp->if_capenable = ifp->if_capabilities; 1001 /* 1002 * XXX 1003 * It seems enabling Tx checksum offloading makes more trouble. 1004 * Sometimes the controller does not receive any frames when 1005 * Tx checksum offloading is enabled. I'm not sure whether this 1006 * is a bug in Tx checksum offloading logic or I got broken 1007 * sample boards. To safety, don't enable Tx checksum offloading 1008 * by default but give chance to users to toggle it if they know 1009 * their controllers work without problems. 1010 */ 1011 ifp->if_capenable &= ~IFCAP_TXCSUM; 1012 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1013 1014 /* Tell the upper layer(s) we support long frames. */ 1015 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1016 1017 /* Create local taskq. */ 1018 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1019 taskqueue_thread_enqueue, &sc->alc_tq); 1020 if (sc->alc_tq == NULL) { 1021 device_printf(dev, "could not create taskqueue.\n"); 1022 ether_ifdetach(ifp); 1023 error = ENXIO; 1024 goto fail; 1025 } 1026 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1027 device_get_nameunit(sc->alc_dev)); 1028 1029 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1030 msic = ALC_MSIX_MESSAGES; 1031 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1032 msic = ALC_MSI_MESSAGES; 1033 else 1034 msic = 1; 1035 for (i = 0; i < msic; i++) { 1036 error = bus_setup_intr(dev, sc->alc_irq[i], 1037 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1038 &sc->alc_intrhand[i]); 1039 if (error != 0) 1040 break; 1041 } 1042 if (error != 0) { 1043 device_printf(dev, "could not set up interrupt handler.\n"); 1044 taskqueue_free(sc->alc_tq); 1045 sc->alc_tq = NULL; 1046 ether_ifdetach(ifp); 1047 goto fail; 1048 } 1049 1050 fail: 1051 if (error != 0) 1052 alc_detach(dev); 1053 1054 return (error); 1055 } 1056 1057 static int 1058 alc_detach(device_t dev) 1059 { 1060 struct alc_softc *sc; 1061 struct ifnet *ifp; 1062 int i, msic; 1063 1064 sc = device_get_softc(dev); 1065 1066 ifp = sc->alc_ifp; 1067 if (device_is_attached(dev)) { 1068 ether_ifdetach(ifp); 1069 ALC_LOCK(sc); 1070 alc_stop(sc); 1071 ALC_UNLOCK(sc); 1072 callout_drain(&sc->alc_tick_ch); 1073 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1074 } 1075 1076 if (sc->alc_tq != NULL) { 1077 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1078 taskqueue_free(sc->alc_tq); 1079 sc->alc_tq = NULL; 1080 } 1081 1082 if (sc->alc_miibus != NULL) { 1083 device_delete_child(dev, sc->alc_miibus); 1084 sc->alc_miibus = NULL; 1085 } 1086 bus_generic_detach(dev); 1087 alc_dma_free(sc); 1088 1089 if (ifp != NULL) { 1090 if_free(ifp); 1091 sc->alc_ifp = NULL; 1092 } 1093 1094 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1095 msic = ALC_MSIX_MESSAGES; 1096 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1097 msic = ALC_MSI_MESSAGES; 1098 else 1099 msic = 1; 1100 for (i = 0; i < msic; i++) { 1101 if (sc->alc_intrhand[i] != NULL) { 1102 bus_teardown_intr(dev, sc->alc_irq[i], 1103 sc->alc_intrhand[i]); 1104 sc->alc_intrhand[i] = NULL; 1105 } 1106 } 1107 if (sc->alc_res[0] != NULL) 1108 alc_phy_down(sc); 1109 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1110 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1111 pci_release_msi(dev); 1112 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1113 mtx_destroy(&sc->alc_mtx); 1114 1115 return (0); 1116 } 1117 1118 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1119 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1120 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1121 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1122 1123 static void 1124 alc_sysctl_node(struct alc_softc *sc) 1125 { 1126 struct sysctl_ctx_list *ctx; 1127 struct sysctl_oid_list *child, *parent; 1128 struct sysctl_oid *tree; 1129 struct alc_hw_stats *stats; 1130 int error; 1131 1132 stats = &sc->alc_stats; 1133 ctx = device_get_sysctl_ctx(sc->alc_dev); 1134 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1135 1136 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1137 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1138 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1139 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1140 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1141 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1142 /* Pull in device tunables. */ 1143 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1144 error = resource_int_value(device_get_name(sc->alc_dev), 1145 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1146 if (error == 0) { 1147 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1148 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1149 device_printf(sc->alc_dev, "int_rx_mod value out of " 1150 "range; using default: %d\n", 1151 ALC_IM_RX_TIMER_DEFAULT); 1152 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1153 } 1154 } 1155 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1156 error = resource_int_value(device_get_name(sc->alc_dev), 1157 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1158 if (error == 0) { 1159 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1160 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1161 device_printf(sc->alc_dev, "int_tx_mod value out of " 1162 "range; using default: %d\n", 1163 ALC_IM_TX_TIMER_DEFAULT); 1164 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1165 } 1166 } 1167 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1168 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1169 sysctl_hw_alc_proc_limit, "I", 1170 "max number of Rx events to process"); 1171 /* Pull in device tunables. */ 1172 sc->alc_process_limit = ALC_PROC_DEFAULT; 1173 error = resource_int_value(device_get_name(sc->alc_dev), 1174 device_get_unit(sc->alc_dev), "process_limit", 1175 &sc->alc_process_limit); 1176 if (error == 0) { 1177 if (sc->alc_process_limit < ALC_PROC_MIN || 1178 sc->alc_process_limit > ALC_PROC_MAX) { 1179 device_printf(sc->alc_dev, 1180 "process_limit value out of range; " 1181 "using default: %d\n", ALC_PROC_DEFAULT); 1182 sc->alc_process_limit = ALC_PROC_DEFAULT; 1183 } 1184 } 1185 1186 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1187 NULL, "ALC statistics"); 1188 parent = SYSCTL_CHILDREN(tree); 1189 1190 /* Rx statistics. */ 1191 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1192 NULL, "Rx MAC statistics"); 1193 child = SYSCTL_CHILDREN(tree); 1194 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1195 &stats->rx_frames, "Good frames"); 1196 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1197 &stats->rx_bcast_frames, "Good broadcast frames"); 1198 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1199 &stats->rx_mcast_frames, "Good multicast frames"); 1200 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1201 &stats->rx_pause_frames, "Pause control frames"); 1202 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1203 &stats->rx_control_frames, "Control frames"); 1204 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1205 &stats->rx_crcerrs, "CRC errors"); 1206 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1207 &stats->rx_lenerrs, "Frames with length mismatched"); 1208 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1209 &stats->rx_bytes, "Good octets"); 1210 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1211 &stats->rx_bcast_bytes, "Good broadcast octets"); 1212 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1213 &stats->rx_mcast_bytes, "Good multicast octets"); 1214 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1215 &stats->rx_runts, "Too short frames"); 1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1217 &stats->rx_fragments, "Fragmented frames"); 1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1219 &stats->rx_pkts_64, "64 bytes frames"); 1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1221 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1223 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1225 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1226 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1227 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1228 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1229 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1230 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1231 &stats->rx_pkts_1519_max, "1519 to max frames"); 1232 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1233 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1234 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1235 &stats->rx_fifo_oflows, "FIFO overflows"); 1236 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1237 &stats->rx_rrs_errs, "Return status write-back errors"); 1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1239 &stats->rx_alignerrs, "Alignment errors"); 1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1241 &stats->rx_pkts_filtered, 1242 "Frames dropped due to address filtering"); 1243 1244 /* Tx statistics. */ 1245 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1246 NULL, "Tx MAC statistics"); 1247 child = SYSCTL_CHILDREN(tree); 1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1249 &stats->tx_frames, "Good frames"); 1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1251 &stats->tx_bcast_frames, "Good broadcast frames"); 1252 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1253 &stats->tx_mcast_frames, "Good multicast frames"); 1254 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1255 &stats->tx_pause_frames, "Pause control frames"); 1256 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1257 &stats->tx_control_frames, "Control frames"); 1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1259 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1260 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1261 &stats->tx_excess_defer, "Frames with derferrals"); 1262 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1263 &stats->tx_bytes, "Good octets"); 1264 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1265 &stats->tx_bcast_bytes, "Good broadcast octets"); 1266 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1267 &stats->tx_mcast_bytes, "Good multicast octets"); 1268 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1269 &stats->tx_pkts_64, "64 bytes frames"); 1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1271 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1273 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1275 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1277 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1279 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1280 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1281 &stats->tx_pkts_1519_max, "1519 to max frames"); 1282 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1283 &stats->tx_single_colls, "Single collisions"); 1284 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1285 &stats->tx_multi_colls, "Multiple collisions"); 1286 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1287 &stats->tx_late_colls, "Late collisions"); 1288 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1289 &stats->tx_excess_colls, "Excessive collisions"); 1290 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1291 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1292 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1293 &stats->tx_underrun, "FIFO underruns"); 1294 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1295 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1296 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1297 &stats->tx_lenerrs, "Frames with length mismatched"); 1298 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1299 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1300 } 1301 1302 #undef ALC_SYSCTL_STAT_ADD32 1303 #undef ALC_SYSCTL_STAT_ADD64 1304 1305 struct alc_dmamap_arg { 1306 bus_addr_t alc_busaddr; 1307 }; 1308 1309 static void 1310 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1311 { 1312 struct alc_dmamap_arg *ctx; 1313 1314 if (error != 0) 1315 return; 1316 1317 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1318 1319 ctx = (struct alc_dmamap_arg *)arg; 1320 ctx->alc_busaddr = segs[0].ds_addr; 1321 } 1322 1323 /* 1324 * Normal and high Tx descriptors shares single Tx high address. 1325 * Four Rx descriptor/return rings and CMB shares the same Rx 1326 * high address. 1327 */ 1328 static int 1329 alc_check_boundary(struct alc_softc *sc) 1330 { 1331 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1332 1333 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1334 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1335 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1336 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1337 1338 /* 4GB boundary crossing is not allowed. */ 1339 if ((ALC_ADDR_HI(rx_ring_end) != 1340 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1341 (ALC_ADDR_HI(rr_ring_end) != 1342 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1343 (ALC_ADDR_HI(cmb_end) != 1344 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1345 (ALC_ADDR_HI(tx_ring_end) != 1346 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1347 return (EFBIG); 1348 /* 1349 * Make sure Rx return descriptor/Rx descriptor/CMB use 1350 * the same high address. 1351 */ 1352 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1353 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1354 return (EFBIG); 1355 1356 return (0); 1357 } 1358 1359 static int 1360 alc_dma_alloc(struct alc_softc *sc) 1361 { 1362 struct alc_txdesc *txd; 1363 struct alc_rxdesc *rxd; 1364 bus_addr_t lowaddr; 1365 struct alc_dmamap_arg ctx; 1366 int error, i; 1367 1368 lowaddr = BUS_SPACE_MAXADDR; 1369 again: 1370 /* Create parent DMA tag. */ 1371 error = bus_dma_tag_create( 1372 bus_get_dma_tag(sc->alc_dev), /* parent */ 1373 1, 0, /* alignment, boundary */ 1374 lowaddr, /* lowaddr */ 1375 BUS_SPACE_MAXADDR, /* highaddr */ 1376 NULL, NULL, /* filter, filterarg */ 1377 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1378 0, /* nsegments */ 1379 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1380 0, /* flags */ 1381 NULL, NULL, /* lockfunc, lockarg */ 1382 &sc->alc_cdata.alc_parent_tag); 1383 if (error != 0) { 1384 device_printf(sc->alc_dev, 1385 "could not create parent DMA tag.\n"); 1386 goto fail; 1387 } 1388 1389 /* Create DMA tag for Tx descriptor ring. */ 1390 error = bus_dma_tag_create( 1391 sc->alc_cdata.alc_parent_tag, /* parent */ 1392 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1393 BUS_SPACE_MAXADDR, /* lowaddr */ 1394 BUS_SPACE_MAXADDR, /* highaddr */ 1395 NULL, NULL, /* filter, filterarg */ 1396 ALC_TX_RING_SZ, /* maxsize */ 1397 1, /* nsegments */ 1398 ALC_TX_RING_SZ, /* maxsegsize */ 1399 0, /* flags */ 1400 NULL, NULL, /* lockfunc, lockarg */ 1401 &sc->alc_cdata.alc_tx_ring_tag); 1402 if (error != 0) { 1403 device_printf(sc->alc_dev, 1404 "could not create Tx ring DMA tag.\n"); 1405 goto fail; 1406 } 1407 1408 /* Create DMA tag for Rx free descriptor ring. */ 1409 error = bus_dma_tag_create( 1410 sc->alc_cdata.alc_parent_tag, /* parent */ 1411 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1412 BUS_SPACE_MAXADDR, /* lowaddr */ 1413 BUS_SPACE_MAXADDR, /* highaddr */ 1414 NULL, NULL, /* filter, filterarg */ 1415 ALC_RX_RING_SZ, /* maxsize */ 1416 1, /* nsegments */ 1417 ALC_RX_RING_SZ, /* maxsegsize */ 1418 0, /* flags */ 1419 NULL, NULL, /* lockfunc, lockarg */ 1420 &sc->alc_cdata.alc_rx_ring_tag); 1421 if (error != 0) { 1422 device_printf(sc->alc_dev, 1423 "could not create Rx ring DMA tag.\n"); 1424 goto fail; 1425 } 1426 /* Create DMA tag for Rx return descriptor ring. */ 1427 error = bus_dma_tag_create( 1428 sc->alc_cdata.alc_parent_tag, /* parent */ 1429 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1430 BUS_SPACE_MAXADDR, /* lowaddr */ 1431 BUS_SPACE_MAXADDR, /* highaddr */ 1432 NULL, NULL, /* filter, filterarg */ 1433 ALC_RR_RING_SZ, /* maxsize */ 1434 1, /* nsegments */ 1435 ALC_RR_RING_SZ, /* maxsegsize */ 1436 0, /* flags */ 1437 NULL, NULL, /* lockfunc, lockarg */ 1438 &sc->alc_cdata.alc_rr_ring_tag); 1439 if (error != 0) { 1440 device_printf(sc->alc_dev, 1441 "could not create Rx return ring DMA tag.\n"); 1442 goto fail; 1443 } 1444 1445 /* Create DMA tag for coalescing message block. */ 1446 error = bus_dma_tag_create( 1447 sc->alc_cdata.alc_parent_tag, /* parent */ 1448 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1449 BUS_SPACE_MAXADDR, /* lowaddr */ 1450 BUS_SPACE_MAXADDR, /* highaddr */ 1451 NULL, NULL, /* filter, filterarg */ 1452 ALC_CMB_SZ, /* maxsize */ 1453 1, /* nsegments */ 1454 ALC_CMB_SZ, /* maxsegsize */ 1455 0, /* flags */ 1456 NULL, NULL, /* lockfunc, lockarg */ 1457 &sc->alc_cdata.alc_cmb_tag); 1458 if (error != 0) { 1459 device_printf(sc->alc_dev, 1460 "could not create CMB DMA tag.\n"); 1461 goto fail; 1462 } 1463 /* Create DMA tag for status message block. */ 1464 error = bus_dma_tag_create( 1465 sc->alc_cdata.alc_parent_tag, /* parent */ 1466 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1467 BUS_SPACE_MAXADDR, /* lowaddr */ 1468 BUS_SPACE_MAXADDR, /* highaddr */ 1469 NULL, NULL, /* filter, filterarg */ 1470 ALC_SMB_SZ, /* maxsize */ 1471 1, /* nsegments */ 1472 ALC_SMB_SZ, /* maxsegsize */ 1473 0, /* flags */ 1474 NULL, NULL, /* lockfunc, lockarg */ 1475 &sc->alc_cdata.alc_smb_tag); 1476 if (error != 0) { 1477 device_printf(sc->alc_dev, 1478 "could not create SMB DMA tag.\n"); 1479 goto fail; 1480 } 1481 1482 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1483 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1484 (void **)&sc->alc_rdata.alc_tx_ring, 1485 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1486 &sc->alc_cdata.alc_tx_ring_map); 1487 if (error != 0) { 1488 device_printf(sc->alc_dev, 1489 "could not allocate DMA'able memory for Tx ring.\n"); 1490 goto fail; 1491 } 1492 ctx.alc_busaddr = 0; 1493 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1494 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1495 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1496 if (error != 0 || ctx.alc_busaddr == 0) { 1497 device_printf(sc->alc_dev, 1498 "could not load DMA'able memory for Tx ring.\n"); 1499 goto fail; 1500 } 1501 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1502 1503 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1504 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1505 (void **)&sc->alc_rdata.alc_rx_ring, 1506 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1507 &sc->alc_cdata.alc_rx_ring_map); 1508 if (error != 0) { 1509 device_printf(sc->alc_dev, 1510 "could not allocate DMA'able memory for Rx ring.\n"); 1511 goto fail; 1512 } 1513 ctx.alc_busaddr = 0; 1514 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1515 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1516 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1517 if (error != 0 || ctx.alc_busaddr == 0) { 1518 device_printf(sc->alc_dev, 1519 "could not load DMA'able memory for Rx ring.\n"); 1520 goto fail; 1521 } 1522 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1523 1524 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1525 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1526 (void **)&sc->alc_rdata.alc_rr_ring, 1527 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1528 &sc->alc_cdata.alc_rr_ring_map); 1529 if (error != 0) { 1530 device_printf(sc->alc_dev, 1531 "could not allocate DMA'able memory for Rx return ring.\n"); 1532 goto fail; 1533 } 1534 ctx.alc_busaddr = 0; 1535 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1536 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1537 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1538 if (error != 0 || ctx.alc_busaddr == 0) { 1539 device_printf(sc->alc_dev, 1540 "could not load DMA'able memory for Tx ring.\n"); 1541 goto fail; 1542 } 1543 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1544 1545 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1546 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1547 (void **)&sc->alc_rdata.alc_cmb, 1548 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1549 &sc->alc_cdata.alc_cmb_map); 1550 if (error != 0) { 1551 device_printf(sc->alc_dev, 1552 "could not allocate DMA'able memory for CMB.\n"); 1553 goto fail; 1554 } 1555 ctx.alc_busaddr = 0; 1556 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1557 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1558 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1559 if (error != 0 || ctx.alc_busaddr == 0) { 1560 device_printf(sc->alc_dev, 1561 "could not load DMA'able memory for CMB.\n"); 1562 goto fail; 1563 } 1564 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1565 1566 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1567 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1568 (void **)&sc->alc_rdata.alc_smb, 1569 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1570 &sc->alc_cdata.alc_smb_map); 1571 if (error != 0) { 1572 device_printf(sc->alc_dev, 1573 "could not allocate DMA'able memory for SMB.\n"); 1574 goto fail; 1575 } 1576 ctx.alc_busaddr = 0; 1577 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1578 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1579 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1580 if (error != 0 || ctx.alc_busaddr == 0) { 1581 device_printf(sc->alc_dev, 1582 "could not load DMA'able memory for CMB.\n"); 1583 goto fail; 1584 } 1585 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1586 1587 /* Make sure we've not crossed 4GB boundary. */ 1588 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1589 (error = alc_check_boundary(sc)) != 0) { 1590 device_printf(sc->alc_dev, "4GB boundary crossed, " 1591 "switching to 32bit DMA addressing mode.\n"); 1592 alc_dma_free(sc); 1593 /* 1594 * Limit max allowable DMA address space to 32bit 1595 * and try again. 1596 */ 1597 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1598 goto again; 1599 } 1600 1601 /* 1602 * Create Tx buffer parent tag. 1603 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1604 * so it needs separate parent DMA tag as parent DMA address 1605 * space could be restricted to be within 32bit address space 1606 * by 4GB boundary crossing. 1607 */ 1608 error = bus_dma_tag_create( 1609 bus_get_dma_tag(sc->alc_dev), /* parent */ 1610 1, 0, /* alignment, boundary */ 1611 BUS_SPACE_MAXADDR, /* lowaddr */ 1612 BUS_SPACE_MAXADDR, /* highaddr */ 1613 NULL, NULL, /* filter, filterarg */ 1614 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1615 0, /* nsegments */ 1616 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1617 0, /* flags */ 1618 NULL, NULL, /* lockfunc, lockarg */ 1619 &sc->alc_cdata.alc_buffer_tag); 1620 if (error != 0) { 1621 device_printf(sc->alc_dev, 1622 "could not create parent buffer DMA tag.\n"); 1623 goto fail; 1624 } 1625 1626 /* Create DMA tag for Tx buffers. */ 1627 error = bus_dma_tag_create( 1628 sc->alc_cdata.alc_buffer_tag, /* parent */ 1629 1, 0, /* alignment, boundary */ 1630 BUS_SPACE_MAXADDR, /* lowaddr */ 1631 BUS_SPACE_MAXADDR, /* highaddr */ 1632 NULL, NULL, /* filter, filterarg */ 1633 ALC_TSO_MAXSIZE, /* maxsize */ 1634 ALC_MAXTXSEGS, /* nsegments */ 1635 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1636 0, /* flags */ 1637 NULL, NULL, /* lockfunc, lockarg */ 1638 &sc->alc_cdata.alc_tx_tag); 1639 if (error != 0) { 1640 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1641 goto fail; 1642 } 1643 1644 /* Create DMA tag for Rx buffers. */ 1645 error = bus_dma_tag_create( 1646 sc->alc_cdata.alc_buffer_tag, /* parent */ 1647 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1648 BUS_SPACE_MAXADDR, /* lowaddr */ 1649 BUS_SPACE_MAXADDR, /* highaddr */ 1650 NULL, NULL, /* filter, filterarg */ 1651 MCLBYTES, /* maxsize */ 1652 1, /* nsegments */ 1653 MCLBYTES, /* maxsegsize */ 1654 0, /* flags */ 1655 NULL, NULL, /* lockfunc, lockarg */ 1656 &sc->alc_cdata.alc_rx_tag); 1657 if (error != 0) { 1658 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1659 goto fail; 1660 } 1661 /* Create DMA maps for Tx buffers. */ 1662 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1663 txd = &sc->alc_cdata.alc_txdesc[i]; 1664 txd->tx_m = NULL; 1665 txd->tx_dmamap = NULL; 1666 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1667 &txd->tx_dmamap); 1668 if (error != 0) { 1669 device_printf(sc->alc_dev, 1670 "could not create Tx dmamap.\n"); 1671 goto fail; 1672 } 1673 } 1674 /* Create DMA maps for Rx buffers. */ 1675 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1676 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1677 device_printf(sc->alc_dev, 1678 "could not create spare Rx dmamap.\n"); 1679 goto fail; 1680 } 1681 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1682 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1683 rxd->rx_m = NULL; 1684 rxd->rx_dmamap = NULL; 1685 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1686 &rxd->rx_dmamap); 1687 if (error != 0) { 1688 device_printf(sc->alc_dev, 1689 "could not create Rx dmamap.\n"); 1690 goto fail; 1691 } 1692 } 1693 1694 fail: 1695 return (error); 1696 } 1697 1698 static void 1699 alc_dma_free(struct alc_softc *sc) 1700 { 1701 struct alc_txdesc *txd; 1702 struct alc_rxdesc *rxd; 1703 int i; 1704 1705 /* Tx buffers. */ 1706 if (sc->alc_cdata.alc_tx_tag != NULL) { 1707 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1708 txd = &sc->alc_cdata.alc_txdesc[i]; 1709 if (txd->tx_dmamap != NULL) { 1710 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1711 txd->tx_dmamap); 1712 txd->tx_dmamap = NULL; 1713 } 1714 } 1715 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1716 sc->alc_cdata.alc_tx_tag = NULL; 1717 } 1718 /* Rx buffers */ 1719 if (sc->alc_cdata.alc_rx_tag != NULL) { 1720 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1721 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1722 if (rxd->rx_dmamap != NULL) { 1723 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1724 rxd->rx_dmamap); 1725 rxd->rx_dmamap = NULL; 1726 } 1727 } 1728 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1729 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1730 sc->alc_cdata.alc_rx_sparemap); 1731 sc->alc_cdata.alc_rx_sparemap = NULL; 1732 } 1733 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1734 sc->alc_cdata.alc_rx_tag = NULL; 1735 } 1736 /* Tx descriptor ring. */ 1737 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1738 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1739 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1740 sc->alc_cdata.alc_tx_ring_map); 1741 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1742 sc->alc_rdata.alc_tx_ring != NULL) 1743 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1744 sc->alc_rdata.alc_tx_ring, 1745 sc->alc_cdata.alc_tx_ring_map); 1746 sc->alc_rdata.alc_tx_ring = NULL; 1747 sc->alc_cdata.alc_tx_ring_map = NULL; 1748 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1749 sc->alc_cdata.alc_tx_ring_tag = NULL; 1750 } 1751 /* Rx ring. */ 1752 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1753 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1754 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1755 sc->alc_cdata.alc_rx_ring_map); 1756 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1757 sc->alc_rdata.alc_rx_ring != NULL) 1758 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1759 sc->alc_rdata.alc_rx_ring, 1760 sc->alc_cdata.alc_rx_ring_map); 1761 sc->alc_rdata.alc_rx_ring = NULL; 1762 sc->alc_cdata.alc_rx_ring_map = NULL; 1763 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1764 sc->alc_cdata.alc_rx_ring_tag = NULL; 1765 } 1766 /* Rx return ring. */ 1767 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1768 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1769 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1770 sc->alc_cdata.alc_rr_ring_map); 1771 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1772 sc->alc_rdata.alc_rr_ring != NULL) 1773 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1774 sc->alc_rdata.alc_rr_ring, 1775 sc->alc_cdata.alc_rr_ring_map); 1776 sc->alc_rdata.alc_rr_ring = NULL; 1777 sc->alc_cdata.alc_rr_ring_map = NULL; 1778 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1779 sc->alc_cdata.alc_rr_ring_tag = NULL; 1780 } 1781 /* CMB block */ 1782 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1783 if (sc->alc_cdata.alc_cmb_map != NULL) 1784 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1785 sc->alc_cdata.alc_cmb_map); 1786 if (sc->alc_cdata.alc_cmb_map != NULL && 1787 sc->alc_rdata.alc_cmb != NULL) 1788 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1789 sc->alc_rdata.alc_cmb, 1790 sc->alc_cdata.alc_cmb_map); 1791 sc->alc_rdata.alc_cmb = NULL; 1792 sc->alc_cdata.alc_cmb_map = NULL; 1793 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1794 sc->alc_cdata.alc_cmb_tag = NULL; 1795 } 1796 /* SMB block */ 1797 if (sc->alc_cdata.alc_smb_tag != NULL) { 1798 if (sc->alc_cdata.alc_smb_map != NULL) 1799 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1800 sc->alc_cdata.alc_smb_map); 1801 if (sc->alc_cdata.alc_smb_map != NULL && 1802 sc->alc_rdata.alc_smb != NULL) 1803 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1804 sc->alc_rdata.alc_smb, 1805 sc->alc_cdata.alc_smb_map); 1806 sc->alc_rdata.alc_smb = NULL; 1807 sc->alc_cdata.alc_smb_map = NULL; 1808 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1809 sc->alc_cdata.alc_smb_tag = NULL; 1810 } 1811 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1812 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1813 sc->alc_cdata.alc_buffer_tag = NULL; 1814 } 1815 if (sc->alc_cdata.alc_parent_tag != NULL) { 1816 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1817 sc->alc_cdata.alc_parent_tag = NULL; 1818 } 1819 } 1820 1821 static int 1822 alc_shutdown(device_t dev) 1823 { 1824 1825 return (alc_suspend(dev)); 1826 } 1827 1828 /* 1829 * Note, this driver resets the link speed to 10/100Mbps by 1830 * restarting auto-negotiation in suspend/shutdown phase but we 1831 * don't know whether that auto-negotiation would succeed or not 1832 * as driver has no control after powering off/suspend operation. 1833 * If the renegotiation fail WOL may not work. Running at 1Gbps 1834 * will draw more power than 375mA at 3.3V which is specified in 1835 * PCI specification and that would result in complete 1836 * shutdowning power to ethernet controller. 1837 * 1838 * TODO 1839 * Save current negotiated media speed/duplex/flow-control to 1840 * softc and restore the same link again after resuming. PHY 1841 * handling such as power down/resetting to 100Mbps may be better 1842 * handled in suspend method in phy driver. 1843 */ 1844 static void 1845 alc_setlinkspeed(struct alc_softc *sc) 1846 { 1847 struct mii_data *mii; 1848 int aneg, i; 1849 1850 mii = device_get_softc(sc->alc_miibus); 1851 mii_pollstat(mii); 1852 aneg = 0; 1853 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1854 (IFM_ACTIVE | IFM_AVALID)) { 1855 switch IFM_SUBTYPE(mii->mii_media_active) { 1856 case IFM_10_T: 1857 case IFM_100_TX: 1858 return; 1859 case IFM_1000_T: 1860 aneg++; 1861 break; 1862 default: 1863 break; 1864 } 1865 } 1866 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1867 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1868 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1869 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1870 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1871 DELAY(1000); 1872 if (aneg != 0) { 1873 /* 1874 * Poll link state until alc(4) get a 10/100Mbps link. 1875 */ 1876 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1877 mii_pollstat(mii); 1878 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1879 == (IFM_ACTIVE | IFM_AVALID)) { 1880 switch (IFM_SUBTYPE( 1881 mii->mii_media_active)) { 1882 case IFM_10_T: 1883 case IFM_100_TX: 1884 alc_mac_config(sc); 1885 return; 1886 default: 1887 break; 1888 } 1889 } 1890 ALC_UNLOCK(sc); 1891 pause("alclnk", hz); 1892 ALC_LOCK(sc); 1893 } 1894 if (i == MII_ANEGTICKS_GIGE) 1895 device_printf(sc->alc_dev, 1896 "establishing a link failed, WOL may not work!"); 1897 } 1898 /* 1899 * No link, force MAC to have 100Mbps, full-duplex link. 1900 * This is the last resort and may/may not work. 1901 */ 1902 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1903 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1904 alc_mac_config(sc); 1905 } 1906 1907 static void 1908 alc_setwol(struct alc_softc *sc) 1909 { 1910 struct ifnet *ifp; 1911 uint32_t reg, pmcs; 1912 uint16_t pmstat; 1913 1914 ALC_LOCK_ASSERT(sc); 1915 1916 alc_disable_l0s_l1(sc); 1917 ifp = sc->alc_ifp; 1918 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1919 /* Disable WOL. */ 1920 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1921 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1922 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1923 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1924 /* Force PHY power down. */ 1925 alc_phy_down(sc); 1926 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1927 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1928 return; 1929 } 1930 1931 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1932 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1933 alc_setlinkspeed(sc); 1934 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1935 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1936 } 1937 1938 pmcs = 0; 1939 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1940 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1941 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1942 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1943 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1944 MAC_CFG_BCAST); 1945 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1946 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1947 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1948 reg |= MAC_CFG_RX_ENB; 1949 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1950 1951 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1952 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1953 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1954 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1955 /* WOL disabled, PHY power down. */ 1956 alc_phy_down(sc); 1957 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1958 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1959 } 1960 /* Request PME. */ 1961 pmstat = pci_read_config(sc->alc_dev, 1962 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1963 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1964 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1965 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1966 pci_write_config(sc->alc_dev, 1967 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1968 } 1969 1970 static int 1971 alc_suspend(device_t dev) 1972 { 1973 struct alc_softc *sc; 1974 1975 sc = device_get_softc(dev); 1976 1977 ALC_LOCK(sc); 1978 alc_stop(sc); 1979 alc_setwol(sc); 1980 ALC_UNLOCK(sc); 1981 1982 return (0); 1983 } 1984 1985 static int 1986 alc_resume(device_t dev) 1987 { 1988 struct alc_softc *sc; 1989 struct ifnet *ifp; 1990 uint16_t pmstat; 1991 1992 sc = device_get_softc(dev); 1993 1994 ALC_LOCK(sc); 1995 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1996 /* Disable PME and clear PME status. */ 1997 pmstat = pci_read_config(sc->alc_dev, 1998 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1999 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2000 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2001 pci_write_config(sc->alc_dev, 2002 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2003 } 2004 } 2005 /* Reset PHY. */ 2006 alc_phy_reset(sc); 2007 ifp = sc->alc_ifp; 2008 if ((ifp->if_flags & IFF_UP) != 0) { 2009 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2010 alc_init_locked(sc); 2011 } 2012 ALC_UNLOCK(sc); 2013 2014 return (0); 2015 } 2016 2017 static int 2018 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2019 { 2020 struct alc_txdesc *txd, *txd_last; 2021 struct tx_desc *desc; 2022 struct mbuf *m; 2023 struct ip *ip; 2024 struct tcphdr *tcp; 2025 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2026 bus_dmamap_t map; 2027 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2028 int error, idx, nsegs, prod; 2029 2030 ALC_LOCK_ASSERT(sc); 2031 2032 M_ASSERTPKTHDR((*m_head)); 2033 2034 m = *m_head; 2035 ip = NULL; 2036 tcp = NULL; 2037 ip_off = poff = 0; 2038 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2039 /* 2040 * AR813x/AR815x requires offset of TCP/UDP header in its 2041 * Tx descriptor to perform Tx checksum offloading. TSO 2042 * also requires TCP header offset and modification of 2043 * IP/TCP header. This kind of operation takes many CPU 2044 * cycles on FreeBSD so fast host CPU is required to get 2045 * smooth TSO performance. 2046 */ 2047 struct ether_header *eh; 2048 2049 if (M_WRITABLE(m) == 0) { 2050 /* Get a writable copy. */ 2051 m = m_dup(*m_head, M_NOWAIT); 2052 /* Release original mbufs. */ 2053 m_freem(*m_head); 2054 if (m == NULL) { 2055 *m_head = NULL; 2056 return (ENOBUFS); 2057 } 2058 *m_head = m; 2059 } 2060 2061 ip_off = sizeof(struct ether_header); 2062 m = m_pullup(m, ip_off); 2063 if (m == NULL) { 2064 *m_head = NULL; 2065 return (ENOBUFS); 2066 } 2067 eh = mtod(m, struct ether_header *); 2068 /* 2069 * Check if hardware VLAN insertion is off. 2070 * Additional check for LLC/SNAP frame? 2071 */ 2072 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2073 ip_off = sizeof(struct ether_vlan_header); 2074 m = m_pullup(m, ip_off); 2075 if (m == NULL) { 2076 *m_head = NULL; 2077 return (ENOBUFS); 2078 } 2079 } 2080 m = m_pullup(m, ip_off + sizeof(struct ip)); 2081 if (m == NULL) { 2082 *m_head = NULL; 2083 return (ENOBUFS); 2084 } 2085 ip = (struct ip *)(mtod(m, char *) + ip_off); 2086 poff = ip_off + (ip->ip_hl << 2); 2087 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2088 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2089 if (m == NULL) { 2090 *m_head = NULL; 2091 return (ENOBUFS); 2092 } 2093 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2094 m = m_pullup(m, poff + (tcp->th_off << 2)); 2095 if (m == NULL) { 2096 *m_head = NULL; 2097 return (ENOBUFS); 2098 } 2099 /* 2100 * Due to strict adherence of Microsoft NDIS 2101 * Large Send specification, hardware expects 2102 * a pseudo TCP checksum inserted by upper 2103 * stack. Unfortunately the pseudo TCP 2104 * checksum that NDIS refers to does not include 2105 * TCP payload length so driver should recompute 2106 * the pseudo checksum here. Hopefully this 2107 * wouldn't be much burden on modern CPUs. 2108 * 2109 * Reset IP checksum and recompute TCP pseudo 2110 * checksum as NDIS specification said. 2111 */ 2112 ip = (struct ip *)(mtod(m, char *) + ip_off); 2113 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2114 ip->ip_sum = 0; 2115 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2116 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2117 } 2118 *m_head = m; 2119 } 2120 2121 prod = sc->alc_cdata.alc_tx_prod; 2122 txd = &sc->alc_cdata.alc_txdesc[prod]; 2123 txd_last = txd; 2124 map = txd->tx_dmamap; 2125 2126 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2127 *m_head, txsegs, &nsegs, 0); 2128 if (error == EFBIG) { 2129 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2130 if (m == NULL) { 2131 m_freem(*m_head); 2132 *m_head = NULL; 2133 return (ENOMEM); 2134 } 2135 *m_head = m; 2136 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2137 *m_head, txsegs, &nsegs, 0); 2138 if (error != 0) { 2139 m_freem(*m_head); 2140 *m_head = NULL; 2141 return (error); 2142 } 2143 } else if (error != 0) 2144 return (error); 2145 if (nsegs == 0) { 2146 m_freem(*m_head); 2147 *m_head = NULL; 2148 return (EIO); 2149 } 2150 2151 /* Check descriptor overrun. */ 2152 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2153 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2154 return (ENOBUFS); 2155 } 2156 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2157 2158 m = *m_head; 2159 cflags = TD_ETHERNET; 2160 vtag = 0; 2161 desc = NULL; 2162 idx = 0; 2163 /* Configure VLAN hardware tag insertion. */ 2164 if ((m->m_flags & M_VLANTAG) != 0) { 2165 vtag = htons(m->m_pkthdr.ether_vtag); 2166 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2167 cflags |= TD_INS_VLAN_TAG; 2168 } 2169 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2170 /* Request TSO and set MSS. */ 2171 cflags |= TD_TSO | TD_TSO_DESCV1; 2172 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2173 TD_MSS_MASK; 2174 /* Set TCP header offset. */ 2175 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2176 TD_TCPHDR_OFFSET_MASK; 2177 /* 2178 * AR813x/AR815x requires the first buffer should 2179 * only hold IP/TCP header data. Payload should 2180 * be handled in other descriptors. 2181 */ 2182 hdrlen = poff + (tcp->th_off << 2); 2183 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2184 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2185 desc->flags = htole32(cflags); 2186 desc->addr = htole64(txsegs[0].ds_addr); 2187 sc->alc_cdata.alc_tx_cnt++; 2188 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2189 if (m->m_len - hdrlen > 0) { 2190 /* Handle remaining payload of the first fragment. */ 2191 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2192 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2193 vtag)); 2194 desc->flags = htole32(cflags); 2195 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2196 sc->alc_cdata.alc_tx_cnt++; 2197 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2198 } 2199 /* Handle remaining fragments. */ 2200 idx = 1; 2201 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2202 /* Configure Tx checksum offload. */ 2203 #ifdef ALC_USE_CUSTOM_CSUM 2204 cflags |= TD_CUSTOM_CSUM; 2205 /* Set checksum start offset. */ 2206 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2207 TD_PLOAD_OFFSET_MASK; 2208 /* Set checksum insertion position of TCP/UDP. */ 2209 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2210 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2211 #else 2212 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2213 cflags |= TD_IPCSUM; 2214 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2215 cflags |= TD_TCPCSUM; 2216 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2217 cflags |= TD_UDPCSUM; 2218 /* Set TCP/UDP header offset. */ 2219 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2220 TD_L4HDR_OFFSET_MASK; 2221 #endif 2222 } 2223 for (; idx < nsegs; idx++) { 2224 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2225 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2226 desc->flags = htole32(cflags); 2227 desc->addr = htole64(txsegs[idx].ds_addr); 2228 sc->alc_cdata.alc_tx_cnt++; 2229 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2230 } 2231 /* Update producer index. */ 2232 sc->alc_cdata.alc_tx_prod = prod; 2233 2234 /* Finally set EOP on the last descriptor. */ 2235 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2236 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2237 desc->flags |= htole32(TD_EOP); 2238 2239 /* Swap dmamap of the first and the last. */ 2240 txd = &sc->alc_cdata.alc_txdesc[prod]; 2241 map = txd_last->tx_dmamap; 2242 txd_last->tx_dmamap = txd->tx_dmamap; 2243 txd->tx_dmamap = map; 2244 txd->tx_m = m; 2245 2246 return (0); 2247 } 2248 2249 static void 2250 alc_start(struct ifnet *ifp) 2251 { 2252 struct alc_softc *sc; 2253 2254 sc = ifp->if_softc; 2255 ALC_LOCK(sc); 2256 alc_start_locked(ifp); 2257 ALC_UNLOCK(sc); 2258 } 2259 2260 static void 2261 alc_start_locked(struct ifnet *ifp) 2262 { 2263 struct alc_softc *sc; 2264 struct mbuf *m_head; 2265 int enq; 2266 2267 sc = ifp->if_softc; 2268 2269 ALC_LOCK_ASSERT(sc); 2270 2271 /* Reclaim transmitted frames. */ 2272 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2273 alc_txeof(sc); 2274 2275 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2276 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2277 return; 2278 2279 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2280 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2281 if (m_head == NULL) 2282 break; 2283 /* 2284 * Pack the data into the transmit ring. If we 2285 * don't have room, set the OACTIVE flag and wait 2286 * for the NIC to drain the ring. 2287 */ 2288 if (alc_encap(sc, &m_head)) { 2289 if (m_head == NULL) 2290 break; 2291 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2292 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2293 break; 2294 } 2295 2296 enq++; 2297 /* 2298 * If there's a BPF listener, bounce a copy of this frame 2299 * to him. 2300 */ 2301 ETHER_BPF_MTAP(ifp, m_head); 2302 } 2303 2304 if (enq > 0) { 2305 /* Sync descriptors. */ 2306 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2307 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2308 /* Kick. Assume we're using normal Tx priority queue. */ 2309 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2310 (sc->alc_cdata.alc_tx_prod << 2311 MBOX_TD_PROD_LO_IDX_SHIFT) & 2312 MBOX_TD_PROD_LO_IDX_MASK); 2313 /* Set a timeout in case the chip goes out to lunch. */ 2314 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2315 } 2316 } 2317 2318 static void 2319 alc_watchdog(struct alc_softc *sc) 2320 { 2321 struct ifnet *ifp; 2322 2323 ALC_LOCK_ASSERT(sc); 2324 2325 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2326 return; 2327 2328 ifp = sc->alc_ifp; 2329 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2330 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2331 ifp->if_oerrors++; 2332 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2333 alc_init_locked(sc); 2334 return; 2335 } 2336 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2337 ifp->if_oerrors++; 2338 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2339 alc_init_locked(sc); 2340 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2341 alc_start_locked(ifp); 2342 } 2343 2344 static int 2345 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2346 { 2347 struct alc_softc *sc; 2348 struct ifreq *ifr; 2349 struct mii_data *mii; 2350 int error, mask; 2351 2352 sc = ifp->if_softc; 2353 ifr = (struct ifreq *)data; 2354 error = 0; 2355 switch (cmd) { 2356 case SIOCSIFMTU: 2357 if (ifr->ifr_mtu < ETHERMIN || 2358 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2359 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2360 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2361 ifr->ifr_mtu > ETHERMTU)) 2362 error = EINVAL; 2363 else if (ifp->if_mtu != ifr->ifr_mtu) { 2364 ALC_LOCK(sc); 2365 ifp->if_mtu = ifr->ifr_mtu; 2366 /* AR813x/AR815x has 13 bits MSS field. */ 2367 if (ifp->if_mtu > ALC_TSO_MTU && 2368 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2369 ifp->if_capenable &= ~IFCAP_TSO4; 2370 ifp->if_hwassist &= ~CSUM_TSO; 2371 VLAN_CAPABILITIES(ifp); 2372 } 2373 ALC_UNLOCK(sc); 2374 } 2375 break; 2376 case SIOCSIFFLAGS: 2377 ALC_LOCK(sc); 2378 if ((ifp->if_flags & IFF_UP) != 0) { 2379 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2380 ((ifp->if_flags ^ sc->alc_if_flags) & 2381 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2382 alc_rxfilter(sc); 2383 else 2384 alc_init_locked(sc); 2385 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2386 alc_stop(sc); 2387 sc->alc_if_flags = ifp->if_flags; 2388 ALC_UNLOCK(sc); 2389 break; 2390 case SIOCADDMULTI: 2391 case SIOCDELMULTI: 2392 ALC_LOCK(sc); 2393 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2394 alc_rxfilter(sc); 2395 ALC_UNLOCK(sc); 2396 break; 2397 case SIOCSIFMEDIA: 2398 case SIOCGIFMEDIA: 2399 mii = device_get_softc(sc->alc_miibus); 2400 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2401 break; 2402 case SIOCSIFCAP: 2403 ALC_LOCK(sc); 2404 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2405 if ((mask & IFCAP_TXCSUM) != 0 && 2406 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2407 ifp->if_capenable ^= IFCAP_TXCSUM; 2408 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2409 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2410 else 2411 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2412 } 2413 if ((mask & IFCAP_TSO4) != 0 && 2414 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2415 ifp->if_capenable ^= IFCAP_TSO4; 2416 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2417 /* AR813x/AR815x has 13 bits MSS field. */ 2418 if (ifp->if_mtu > ALC_TSO_MTU) { 2419 ifp->if_capenable &= ~IFCAP_TSO4; 2420 ifp->if_hwassist &= ~CSUM_TSO; 2421 } else 2422 ifp->if_hwassist |= CSUM_TSO; 2423 } else 2424 ifp->if_hwassist &= ~CSUM_TSO; 2425 } 2426 if ((mask & IFCAP_WOL_MCAST) != 0 && 2427 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2428 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2429 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2430 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2431 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2432 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2433 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2434 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2435 alc_rxvlan(sc); 2436 } 2437 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2438 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2439 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2440 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2441 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2442 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2443 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2444 ifp->if_capenable &= 2445 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2446 ALC_UNLOCK(sc); 2447 VLAN_CAPABILITIES(ifp); 2448 break; 2449 default: 2450 error = ether_ioctl(ifp, cmd, data); 2451 break; 2452 } 2453 2454 return (error); 2455 } 2456 2457 static void 2458 alc_mac_config(struct alc_softc *sc) 2459 { 2460 struct mii_data *mii; 2461 uint32_t reg; 2462 2463 ALC_LOCK_ASSERT(sc); 2464 2465 mii = device_get_softc(sc->alc_miibus); 2466 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2467 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2468 MAC_CFG_SPEED_MASK); 2469 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2470 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2471 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2472 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2473 /* Reprogram MAC with resolved speed/duplex. */ 2474 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2475 case IFM_10_T: 2476 case IFM_100_TX: 2477 reg |= MAC_CFG_SPEED_10_100; 2478 break; 2479 case IFM_1000_T: 2480 reg |= MAC_CFG_SPEED_1000; 2481 break; 2482 } 2483 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2484 reg |= MAC_CFG_FULL_DUPLEX; 2485 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2486 reg |= MAC_CFG_TX_FC; 2487 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2488 reg |= MAC_CFG_RX_FC; 2489 } 2490 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2491 } 2492 2493 static void 2494 alc_stats_clear(struct alc_softc *sc) 2495 { 2496 struct smb sb, *smb; 2497 uint32_t *reg; 2498 int i; 2499 2500 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2501 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2502 sc->alc_cdata.alc_smb_map, 2503 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2504 smb = sc->alc_rdata.alc_smb; 2505 /* Update done, clear. */ 2506 smb->updated = 0; 2507 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2508 sc->alc_cdata.alc_smb_map, 2509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2510 } else { 2511 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2512 reg++) { 2513 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2514 i += sizeof(uint32_t); 2515 } 2516 /* Read Tx statistics. */ 2517 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2518 reg++) { 2519 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2520 i += sizeof(uint32_t); 2521 } 2522 } 2523 } 2524 2525 static void 2526 alc_stats_update(struct alc_softc *sc) 2527 { 2528 struct alc_hw_stats *stat; 2529 struct smb sb, *smb; 2530 struct ifnet *ifp; 2531 uint32_t *reg; 2532 int i; 2533 2534 ALC_LOCK_ASSERT(sc); 2535 2536 ifp = sc->alc_ifp; 2537 stat = &sc->alc_stats; 2538 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2539 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2540 sc->alc_cdata.alc_smb_map, 2541 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2542 smb = sc->alc_rdata.alc_smb; 2543 if (smb->updated == 0) 2544 return; 2545 } else { 2546 smb = &sb; 2547 /* Read Rx statistics. */ 2548 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2549 reg++) { 2550 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2551 i += sizeof(uint32_t); 2552 } 2553 /* Read Tx statistics. */ 2554 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2555 reg++) { 2556 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2557 i += sizeof(uint32_t); 2558 } 2559 } 2560 2561 /* Rx stats. */ 2562 stat->rx_frames += smb->rx_frames; 2563 stat->rx_bcast_frames += smb->rx_bcast_frames; 2564 stat->rx_mcast_frames += smb->rx_mcast_frames; 2565 stat->rx_pause_frames += smb->rx_pause_frames; 2566 stat->rx_control_frames += smb->rx_control_frames; 2567 stat->rx_crcerrs += smb->rx_crcerrs; 2568 stat->rx_lenerrs += smb->rx_lenerrs; 2569 stat->rx_bytes += smb->rx_bytes; 2570 stat->rx_runts += smb->rx_runts; 2571 stat->rx_fragments += smb->rx_fragments; 2572 stat->rx_pkts_64 += smb->rx_pkts_64; 2573 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2574 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2575 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2576 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2577 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2578 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2579 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2580 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2581 stat->rx_rrs_errs += smb->rx_rrs_errs; 2582 stat->rx_alignerrs += smb->rx_alignerrs; 2583 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2584 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2585 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2586 2587 /* Tx stats. */ 2588 stat->tx_frames += smb->tx_frames; 2589 stat->tx_bcast_frames += smb->tx_bcast_frames; 2590 stat->tx_mcast_frames += smb->tx_mcast_frames; 2591 stat->tx_pause_frames += smb->tx_pause_frames; 2592 stat->tx_excess_defer += smb->tx_excess_defer; 2593 stat->tx_control_frames += smb->tx_control_frames; 2594 stat->tx_deferred += smb->tx_deferred; 2595 stat->tx_bytes += smb->tx_bytes; 2596 stat->tx_pkts_64 += smb->tx_pkts_64; 2597 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2598 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2599 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2600 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2601 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2602 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2603 stat->tx_single_colls += smb->tx_single_colls; 2604 stat->tx_multi_colls += smb->tx_multi_colls; 2605 stat->tx_late_colls += smb->tx_late_colls; 2606 stat->tx_excess_colls += smb->tx_excess_colls; 2607 stat->tx_abort += smb->tx_abort; 2608 stat->tx_underrun += smb->tx_underrun; 2609 stat->tx_desc_underrun += smb->tx_desc_underrun; 2610 stat->tx_lenerrs += smb->tx_lenerrs; 2611 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2612 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2613 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2614 2615 /* Update counters in ifnet. */ 2616 ifp->if_opackets += smb->tx_frames; 2617 2618 ifp->if_collisions += smb->tx_single_colls + 2619 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2620 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2621 2622 /* 2623 * XXX 2624 * tx_pkts_truncated counter looks suspicious. It constantly 2625 * increments with no sign of Tx errors. This may indicate 2626 * the counter name is not correct one so I've removed the 2627 * counter in output errors. 2628 */ 2629 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2630 smb->tx_underrun; 2631 2632 ifp->if_ipackets += smb->rx_frames; 2633 2634 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2635 smb->rx_runts + smb->rx_pkts_truncated + 2636 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2637 smb->rx_alignerrs; 2638 2639 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2640 /* Update done, clear. */ 2641 smb->updated = 0; 2642 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2643 sc->alc_cdata.alc_smb_map, 2644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2645 } 2646 } 2647 2648 static int 2649 alc_intr(void *arg) 2650 { 2651 struct alc_softc *sc; 2652 uint32_t status; 2653 2654 sc = (struct alc_softc *)arg; 2655 2656 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2657 if ((status & ALC_INTRS) == 0) 2658 return (FILTER_STRAY); 2659 /* Disable interrupts. */ 2660 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2661 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2662 2663 return (FILTER_HANDLED); 2664 } 2665 2666 static void 2667 alc_int_task(void *arg, int pending) 2668 { 2669 struct alc_softc *sc; 2670 struct ifnet *ifp; 2671 uint32_t status; 2672 int more; 2673 2674 sc = (struct alc_softc *)arg; 2675 ifp = sc->alc_ifp; 2676 2677 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2678 ALC_LOCK(sc); 2679 if (sc->alc_morework != 0) { 2680 sc->alc_morework = 0; 2681 status |= INTR_RX_PKT; 2682 } 2683 if ((status & ALC_INTRS) == 0) 2684 goto done; 2685 2686 /* Acknowledge interrupts but still disable interrupts. */ 2687 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2688 2689 more = 0; 2690 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2691 if ((status & INTR_RX_PKT) != 0) { 2692 more = alc_rxintr(sc, sc->alc_process_limit); 2693 if (more == EAGAIN) 2694 sc->alc_morework = 1; 2695 else if (more == EIO) { 2696 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2697 alc_init_locked(sc); 2698 ALC_UNLOCK(sc); 2699 return; 2700 } 2701 } 2702 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2703 INTR_TXQ_TO_RST)) != 0) { 2704 if ((status & INTR_DMA_RD_TO_RST) != 0) 2705 device_printf(sc->alc_dev, 2706 "DMA read error! -- resetting\n"); 2707 if ((status & INTR_DMA_WR_TO_RST) != 0) 2708 device_printf(sc->alc_dev, 2709 "DMA write error! -- resetting\n"); 2710 if ((status & INTR_TXQ_TO_RST) != 0) 2711 device_printf(sc->alc_dev, 2712 "TxQ reset! -- resetting\n"); 2713 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2714 alc_init_locked(sc); 2715 ALC_UNLOCK(sc); 2716 return; 2717 } 2718 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2719 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2720 alc_start_locked(ifp); 2721 } 2722 2723 if (more == EAGAIN || 2724 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2725 ALC_UNLOCK(sc); 2726 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2727 return; 2728 } 2729 2730 done: 2731 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2732 /* Re-enable interrupts if we're running. */ 2733 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2734 } 2735 ALC_UNLOCK(sc); 2736 } 2737 2738 static void 2739 alc_txeof(struct alc_softc *sc) 2740 { 2741 struct ifnet *ifp; 2742 struct alc_txdesc *txd; 2743 uint32_t cons, prod; 2744 int prog; 2745 2746 ALC_LOCK_ASSERT(sc); 2747 2748 ifp = sc->alc_ifp; 2749 2750 if (sc->alc_cdata.alc_tx_cnt == 0) 2751 return; 2752 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2753 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2754 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2755 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2756 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2757 prod = sc->alc_rdata.alc_cmb->cons; 2758 } else 2759 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2760 /* Assume we're using normal Tx priority queue. */ 2761 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2762 MBOX_TD_CONS_LO_IDX_SHIFT; 2763 cons = sc->alc_cdata.alc_tx_cons; 2764 /* 2765 * Go through our Tx list and free mbufs for those 2766 * frames which have been transmitted. 2767 */ 2768 for (prog = 0; cons != prod; prog++, 2769 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2770 if (sc->alc_cdata.alc_tx_cnt <= 0) 2771 break; 2772 prog++; 2773 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2774 sc->alc_cdata.alc_tx_cnt--; 2775 txd = &sc->alc_cdata.alc_txdesc[cons]; 2776 if (txd->tx_m != NULL) { 2777 /* Reclaim transmitted mbufs. */ 2778 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2779 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2780 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2781 txd->tx_dmamap); 2782 m_freem(txd->tx_m); 2783 txd->tx_m = NULL; 2784 } 2785 } 2786 2787 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2788 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2789 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2790 sc->alc_cdata.alc_tx_cons = cons; 2791 /* 2792 * Unarm watchdog timer only when there is no pending 2793 * frames in Tx queue. 2794 */ 2795 if (sc->alc_cdata.alc_tx_cnt == 0) 2796 sc->alc_watchdog_timer = 0; 2797 } 2798 2799 static int 2800 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2801 { 2802 struct mbuf *m; 2803 bus_dma_segment_t segs[1]; 2804 bus_dmamap_t map; 2805 int nsegs; 2806 2807 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2808 if (m == NULL) 2809 return (ENOBUFS); 2810 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2811 #ifndef __NO_STRICT_ALIGNMENT 2812 m_adj(m, sizeof(uint64_t)); 2813 #endif 2814 2815 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2816 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2817 m_freem(m); 2818 return (ENOBUFS); 2819 } 2820 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2821 2822 if (rxd->rx_m != NULL) { 2823 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2824 BUS_DMASYNC_POSTREAD); 2825 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2826 } 2827 map = rxd->rx_dmamap; 2828 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2829 sc->alc_cdata.alc_rx_sparemap = map; 2830 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2831 BUS_DMASYNC_PREREAD); 2832 rxd->rx_m = m; 2833 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2834 return (0); 2835 } 2836 2837 static int 2838 alc_rxintr(struct alc_softc *sc, int count) 2839 { 2840 struct ifnet *ifp; 2841 struct rx_rdesc *rrd; 2842 uint32_t nsegs, status; 2843 int rr_cons, prog; 2844 2845 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2846 sc->alc_cdata.alc_rr_ring_map, 2847 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2848 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2849 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2850 rr_cons = sc->alc_cdata.alc_rr_cons; 2851 ifp = sc->alc_ifp; 2852 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2853 if (count-- <= 0) 2854 break; 2855 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2856 status = le32toh(rrd->status); 2857 if ((status & RRD_VALID) == 0) 2858 break; 2859 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2860 if (nsegs == 0) { 2861 /* This should not happen! */ 2862 device_printf(sc->alc_dev, 2863 "unexpected segment count -- resetting\n"); 2864 return (EIO); 2865 } 2866 alc_rxeof(sc, rrd); 2867 /* Clear Rx return status. */ 2868 rrd->status = 0; 2869 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2870 sc->alc_cdata.alc_rx_cons += nsegs; 2871 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2872 prog += nsegs; 2873 } 2874 2875 if (prog > 0) { 2876 /* Update the consumer index. */ 2877 sc->alc_cdata.alc_rr_cons = rr_cons; 2878 /* Sync Rx return descriptors. */ 2879 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2880 sc->alc_cdata.alc_rr_ring_map, 2881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2882 /* 2883 * Sync updated Rx descriptors such that controller see 2884 * modified buffer addresses. 2885 */ 2886 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2887 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2888 /* 2889 * Let controller know availability of new Rx buffers. 2890 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2891 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2892 * only when Rx buffer pre-fetching is required. In 2893 * addition we already set ALC_RX_RD_FREE_THRESH to 2894 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2895 * it still seems that pre-fetching needs more 2896 * experimentation. 2897 */ 2898 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2899 sc->alc_cdata.alc_rx_cons); 2900 } 2901 2902 return (count > 0 ? 0 : EAGAIN); 2903 } 2904 2905 #ifndef __NO_STRICT_ALIGNMENT 2906 static struct mbuf * 2907 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2908 { 2909 struct mbuf *n; 2910 int i; 2911 uint16_t *src, *dst; 2912 2913 src = mtod(m, uint16_t *); 2914 dst = src - 3; 2915 2916 if (m->m_next == NULL) { 2917 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2918 *dst++ = *src++; 2919 m->m_data -= 6; 2920 return (m); 2921 } 2922 /* 2923 * Append a new mbuf to received mbuf chain and copy ethernet 2924 * header from the mbuf chain. This can save lots of CPU 2925 * cycles for jumbo frame. 2926 */ 2927 MGETHDR(n, M_NOWAIT, MT_DATA); 2928 if (n == NULL) { 2929 ifp->if_iqdrops++; 2930 m_freem(m); 2931 return (NULL); 2932 } 2933 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2934 m->m_data += ETHER_HDR_LEN; 2935 m->m_len -= ETHER_HDR_LEN; 2936 n->m_len = ETHER_HDR_LEN; 2937 M_MOVE_PKTHDR(n, m); 2938 n->m_next = m; 2939 return (n); 2940 } 2941 #endif 2942 2943 /* Receive a frame. */ 2944 static void 2945 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2946 { 2947 struct alc_rxdesc *rxd; 2948 struct ifnet *ifp; 2949 struct mbuf *mp, *m; 2950 uint32_t rdinfo, status, vtag; 2951 int count, nsegs, rx_cons; 2952 2953 ifp = sc->alc_ifp; 2954 status = le32toh(rrd->status); 2955 rdinfo = le32toh(rrd->rdinfo); 2956 rx_cons = RRD_RD_IDX(rdinfo); 2957 nsegs = RRD_RD_CNT(rdinfo); 2958 2959 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2960 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2961 /* 2962 * We want to pass the following frames to upper 2963 * layer regardless of error status of Rx return 2964 * ring. 2965 * 2966 * o IP/TCP/UDP checksum is bad. 2967 * o frame length and protocol specific length 2968 * does not match. 2969 * 2970 * Force network stack compute checksum for 2971 * errored frames. 2972 */ 2973 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2974 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2975 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2976 return; 2977 } 2978 2979 for (count = 0; count < nsegs; count++, 2980 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2981 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2982 mp = rxd->rx_m; 2983 /* Add a new receive buffer to the ring. */ 2984 if (alc_newbuf(sc, rxd) != 0) { 2985 ifp->if_iqdrops++; 2986 /* Reuse Rx buffers. */ 2987 if (sc->alc_cdata.alc_rxhead != NULL) 2988 m_freem(sc->alc_cdata.alc_rxhead); 2989 break; 2990 } 2991 2992 /* 2993 * Assume we've received a full sized frame. 2994 * Actual size is fixed when we encounter the end of 2995 * multi-segmented frame. 2996 */ 2997 mp->m_len = sc->alc_buf_size; 2998 2999 /* Chain received mbufs. */ 3000 if (sc->alc_cdata.alc_rxhead == NULL) { 3001 sc->alc_cdata.alc_rxhead = mp; 3002 sc->alc_cdata.alc_rxtail = mp; 3003 } else { 3004 mp->m_flags &= ~M_PKTHDR; 3005 sc->alc_cdata.alc_rxprev_tail = 3006 sc->alc_cdata.alc_rxtail; 3007 sc->alc_cdata.alc_rxtail->m_next = mp; 3008 sc->alc_cdata.alc_rxtail = mp; 3009 } 3010 3011 if (count == nsegs - 1) { 3012 /* Last desc. for this frame. */ 3013 m = sc->alc_cdata.alc_rxhead; 3014 m->m_flags |= M_PKTHDR; 3015 /* 3016 * It seems that L1C/L2C controller has no way 3017 * to tell hardware to strip CRC bytes. 3018 */ 3019 m->m_pkthdr.len = 3020 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3021 if (nsegs > 1) { 3022 /* Set last mbuf size. */ 3023 mp->m_len = sc->alc_cdata.alc_rxlen - 3024 (nsegs - 1) * sc->alc_buf_size; 3025 /* Remove the CRC bytes in chained mbufs. */ 3026 if (mp->m_len <= ETHER_CRC_LEN) { 3027 sc->alc_cdata.alc_rxtail = 3028 sc->alc_cdata.alc_rxprev_tail; 3029 sc->alc_cdata.alc_rxtail->m_len -= 3030 (ETHER_CRC_LEN - mp->m_len); 3031 sc->alc_cdata.alc_rxtail->m_next = NULL; 3032 m_freem(mp); 3033 } else { 3034 mp->m_len -= ETHER_CRC_LEN; 3035 } 3036 } else 3037 m->m_len = m->m_pkthdr.len; 3038 m->m_pkthdr.rcvif = ifp; 3039 /* 3040 * Due to hardware bugs, Rx checksum offloading 3041 * was intentionally disabled. 3042 */ 3043 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3044 (status & RRD_VLAN_TAG) != 0) { 3045 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3046 m->m_pkthdr.ether_vtag = ntohs(vtag); 3047 m->m_flags |= M_VLANTAG; 3048 } 3049 #ifndef __NO_STRICT_ALIGNMENT 3050 m = alc_fixup_rx(ifp, m); 3051 if (m != NULL) 3052 #endif 3053 { 3054 /* Pass it on. */ 3055 ALC_UNLOCK(sc); 3056 (*ifp->if_input)(ifp, m); 3057 ALC_LOCK(sc); 3058 } 3059 } 3060 } 3061 /* Reset mbuf chains. */ 3062 ALC_RXCHAIN_RESET(sc); 3063 } 3064 3065 static void 3066 alc_tick(void *arg) 3067 { 3068 struct alc_softc *sc; 3069 struct mii_data *mii; 3070 3071 sc = (struct alc_softc *)arg; 3072 3073 ALC_LOCK_ASSERT(sc); 3074 3075 mii = device_get_softc(sc->alc_miibus); 3076 mii_tick(mii); 3077 alc_stats_update(sc); 3078 /* 3079 * alc(4) does not rely on Tx completion interrupts to reclaim 3080 * transferred buffers. Instead Tx completion interrupts are 3081 * used to hint for scheduling Tx task. So it's necessary to 3082 * release transmitted buffers by kicking Tx completion 3083 * handler. This limits the maximum reclamation delay to a hz. 3084 */ 3085 alc_txeof(sc); 3086 alc_watchdog(sc); 3087 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3088 } 3089 3090 static void 3091 alc_reset(struct alc_softc *sc) 3092 { 3093 uint32_t reg; 3094 int i; 3095 3096 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3097 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3098 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3099 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3100 DELAY(10); 3101 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3102 break; 3103 } 3104 if (i == 0) 3105 device_printf(sc->alc_dev, "master reset timeout!\n"); 3106 3107 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3108 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3109 break; 3110 DELAY(10); 3111 } 3112 3113 if (i == 0) 3114 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3115 } 3116 3117 static void 3118 alc_init(void *xsc) 3119 { 3120 struct alc_softc *sc; 3121 3122 sc = (struct alc_softc *)xsc; 3123 ALC_LOCK(sc); 3124 alc_init_locked(sc); 3125 ALC_UNLOCK(sc); 3126 } 3127 3128 static void 3129 alc_init_locked(struct alc_softc *sc) 3130 { 3131 struct ifnet *ifp; 3132 struct mii_data *mii; 3133 uint8_t eaddr[ETHER_ADDR_LEN]; 3134 bus_addr_t paddr; 3135 uint32_t reg, rxf_hi, rxf_lo; 3136 3137 ALC_LOCK_ASSERT(sc); 3138 3139 ifp = sc->alc_ifp; 3140 mii = device_get_softc(sc->alc_miibus); 3141 3142 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3143 return; 3144 /* 3145 * Cancel any pending I/O. 3146 */ 3147 alc_stop(sc); 3148 /* 3149 * Reset the chip to a known state. 3150 */ 3151 alc_reset(sc); 3152 3153 /* Initialize Rx descriptors. */ 3154 if (alc_init_rx_ring(sc) != 0) { 3155 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3156 alc_stop(sc); 3157 return; 3158 } 3159 alc_init_rr_ring(sc); 3160 alc_init_tx_ring(sc); 3161 alc_init_cmb(sc); 3162 alc_init_smb(sc); 3163 3164 /* Enable all clocks. */ 3165 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3166 3167 /* Reprogram the station address. */ 3168 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3169 CSR_WRITE_4(sc, ALC_PAR0, 3170 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3171 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3172 /* 3173 * Clear WOL status and disable all WOL feature as WOL 3174 * would interfere Rx operation under normal environments. 3175 */ 3176 CSR_READ_4(sc, ALC_WOL_CFG); 3177 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3178 /* Set Tx descriptor base addresses. */ 3179 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3180 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3181 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3182 /* We don't use high priority ring. */ 3183 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3184 /* Set Tx descriptor counter. */ 3185 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3186 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3187 /* Set Rx descriptor base addresses. */ 3188 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3189 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3190 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3191 /* We use one Rx ring. */ 3192 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3193 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3194 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3195 /* Set Rx descriptor counter. */ 3196 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3197 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3198 3199 /* 3200 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3201 * if it do not fit the buffer size. Rx return descriptor holds 3202 * a counter that indicates how many fragments were made by the 3203 * hardware. The buffer size should be multiple of 8 bytes. 3204 * Since hardware has limit on the size of buffer size, always 3205 * use the maximum value. 3206 * For strict-alignment architectures make sure to reduce buffer 3207 * size by 8 bytes to make room for alignment fixup. 3208 */ 3209 #ifndef __NO_STRICT_ALIGNMENT 3210 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3211 #else 3212 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3213 #endif 3214 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3215 3216 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3217 /* Set Rx return descriptor base addresses. */ 3218 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3219 /* We use one Rx return ring. */ 3220 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3221 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3222 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3223 /* Set Rx return descriptor counter. */ 3224 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3225 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3226 paddr = sc->alc_rdata.alc_cmb_paddr; 3227 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3228 paddr = sc->alc_rdata.alc_smb_paddr; 3229 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3230 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3231 3232 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3233 /* Reconfigure SRAM - Vendor magic. */ 3234 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3235 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3236 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3237 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3238 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3239 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3240 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3241 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3242 } 3243 3244 /* Tell hardware that we're ready to load DMA blocks. */ 3245 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3246 3247 /* Configure interrupt moderation timer. */ 3248 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3249 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3250 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3251 /* 3252 * We don't want to automatic interrupt clear as task queue 3253 * for the interrupt should know interrupt status. 3254 */ 3255 reg = MASTER_SA_TIMER_ENB; 3256 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3257 reg |= MASTER_IM_RX_TIMER_ENB; 3258 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3259 reg |= MASTER_IM_TX_TIMER_ENB; 3260 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3261 /* 3262 * Disable interrupt re-trigger timer. We don't want automatic 3263 * re-triggering of un-ACKed interrupts. 3264 */ 3265 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3266 /* Configure CMB. */ 3267 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3268 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3269 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3270 } else 3271 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3272 /* 3273 * Hardware can be configured to issue SMB interrupt based 3274 * on programmed interval. Since there is a callout that is 3275 * invoked for every hz in driver we use that instead of 3276 * relying on periodic SMB interrupt. 3277 */ 3278 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3279 /* Clear MAC statistics. */ 3280 alc_stats_clear(sc); 3281 3282 /* 3283 * Always use maximum frame size that controller can support. 3284 * Otherwise received frames that has larger frame length 3285 * than alc(4) MTU would be silently dropped in hardware. This 3286 * would make path-MTU discovery hard as sender wouldn't get 3287 * any responses from receiver. alc(4) supports 3288 * multi-fragmented frames on Rx path so it has no issue on 3289 * assembling fragmented frames. Using maximum frame size also 3290 * removes the need to reinitialize hardware when interface 3291 * MTU configuration was changed. 3292 * 3293 * Be conservative in what you do, be liberal in what you 3294 * accept from others - RFC 793. 3295 */ 3296 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3297 3298 /* Disable header split(?) */ 3299 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3300 3301 /* Configure IPG/IFG parameters. */ 3302 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3303 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3304 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3305 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3306 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3307 /* Set parameters for half-duplex media. */ 3308 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3309 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3310 HDPX_CFG_LCOL_MASK) | 3311 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3312 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3313 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3314 HDPX_CFG_ABEBT_MASK) | 3315 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3316 HDPX_CFG_JAMIPG_MASK)); 3317 /* 3318 * Set TSO/checksum offload threshold. For frames that is 3319 * larger than this threshold, hardware wouldn't do 3320 * TSO/checksum offloading. 3321 */ 3322 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3323 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3324 TSO_OFFLOAD_THRESH_MASK); 3325 /* Configure TxQ. */ 3326 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3327 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3328 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3329 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3330 reg >>= 1; 3331 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3332 TXQ_CFG_TD_BURST_MASK; 3333 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3334 3335 /* Configure Rx free descriptor pre-fetching. */ 3336 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3337 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3338 RX_RD_FREE_THRESH_HI_MASK) | 3339 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3340 RX_RD_FREE_THRESH_LO_MASK)); 3341 3342 /* 3343 * Configure flow control parameters. 3344 * XON : 80% of Rx FIFO 3345 * XOFF : 30% of Rx FIFO 3346 */ 3347 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3348 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3349 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3350 rxf_hi = (reg * 8) / 10; 3351 rxf_lo = (reg * 3) / 10; 3352 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3353 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3354 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3355 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3356 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3357 } 3358 3359 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3360 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3361 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3362 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3363 SERDES_PHY_CLK_SLOWDOWN); 3364 3365 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3366 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3367 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3368 3369 /* Configure RxQ. */ 3370 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3371 RXQ_CFG_RD_BURST_MASK; 3372 reg |= RXQ_CFG_RSS_MODE_DIS; 3373 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3374 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3375 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3376 3377 /* Configure DMA parameters. */ 3378 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3379 reg |= sc->alc_rcb; 3380 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3381 reg |= DMA_CFG_CMB_ENB; 3382 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3383 reg |= DMA_CFG_SMB_ENB; 3384 else 3385 reg |= DMA_CFG_SMB_DIS; 3386 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3387 DMA_CFG_RD_BURST_SHIFT; 3388 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3389 DMA_CFG_WR_BURST_SHIFT; 3390 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3391 DMA_CFG_RD_DELAY_CNT_MASK; 3392 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3393 DMA_CFG_WR_DELAY_CNT_MASK; 3394 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3395 3396 /* 3397 * Configure Tx/Rx MACs. 3398 * - Auto-padding for short frames. 3399 * - Enable CRC generation. 3400 * Actual reconfiguration of MAC for resolved speed/duplex 3401 * is followed after detection of link establishment. 3402 * AR813x/AR815x always does checksum computation regardless 3403 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3404 * have bug in protocol field in Rx return structure so 3405 * these controllers can't handle fragmented frames. Disable 3406 * Rx checksum offloading until there is a newer controller 3407 * that has sane implementation. 3408 */ 3409 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3410 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3411 MAC_CFG_PREAMBLE_MASK); 3412 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3413 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3414 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3415 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3416 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3417 reg |= MAC_CFG_SPEED_10_100; 3418 else 3419 reg |= MAC_CFG_SPEED_1000; 3420 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3421 3422 /* Set up the receive filter. */ 3423 alc_rxfilter(sc); 3424 alc_rxvlan(sc); 3425 3426 /* Acknowledge all pending interrupts and clear it. */ 3427 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3428 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3429 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3430 3431 sc->alc_flags &= ~ALC_FLAG_LINK; 3432 /* Switch to the current media. */ 3433 mii_mediachg(mii); 3434 3435 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3436 3437 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3438 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3439 } 3440 3441 static void 3442 alc_stop(struct alc_softc *sc) 3443 { 3444 struct ifnet *ifp; 3445 struct alc_txdesc *txd; 3446 struct alc_rxdesc *rxd; 3447 uint32_t reg; 3448 int i; 3449 3450 ALC_LOCK_ASSERT(sc); 3451 /* 3452 * Mark the interface down and cancel the watchdog timer. 3453 */ 3454 ifp = sc->alc_ifp; 3455 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3456 sc->alc_flags &= ~ALC_FLAG_LINK; 3457 callout_stop(&sc->alc_tick_ch); 3458 sc->alc_watchdog_timer = 0; 3459 alc_stats_update(sc); 3460 /* Disable interrupts. */ 3461 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3462 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3463 alc_stop_queue(sc); 3464 /* Disable DMA. */ 3465 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3466 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3467 reg |= DMA_CFG_SMB_DIS; 3468 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3469 DELAY(1000); 3470 /* Stop Rx/Tx MACs. */ 3471 alc_stop_mac(sc); 3472 /* Disable interrupts which might be touched in taskq handler. */ 3473 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3474 3475 /* Reclaim Rx buffers that have been processed. */ 3476 if (sc->alc_cdata.alc_rxhead != NULL) 3477 m_freem(sc->alc_cdata.alc_rxhead); 3478 ALC_RXCHAIN_RESET(sc); 3479 /* 3480 * Free Tx/Rx mbufs still in the queues. 3481 */ 3482 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3483 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3484 if (rxd->rx_m != NULL) { 3485 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3486 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3487 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3488 rxd->rx_dmamap); 3489 m_freem(rxd->rx_m); 3490 rxd->rx_m = NULL; 3491 } 3492 } 3493 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3494 txd = &sc->alc_cdata.alc_txdesc[i]; 3495 if (txd->tx_m != NULL) { 3496 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3497 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3498 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3499 txd->tx_dmamap); 3500 m_freem(txd->tx_m); 3501 txd->tx_m = NULL; 3502 } 3503 } 3504 } 3505 3506 static void 3507 alc_stop_mac(struct alc_softc *sc) 3508 { 3509 uint32_t reg; 3510 int i; 3511 3512 ALC_LOCK_ASSERT(sc); 3513 3514 /* Disable Rx/Tx MAC. */ 3515 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3516 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3517 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3518 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3519 } 3520 for (i = ALC_TIMEOUT; i > 0; i--) { 3521 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3522 if (reg == 0) 3523 break; 3524 DELAY(10); 3525 } 3526 if (i == 0) 3527 device_printf(sc->alc_dev, 3528 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3529 } 3530 3531 static void 3532 alc_start_queue(struct alc_softc *sc) 3533 { 3534 uint32_t qcfg[] = { 3535 0, 3536 RXQ_CFG_QUEUE0_ENB, 3537 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3538 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3539 RXQ_CFG_ENB 3540 }; 3541 uint32_t cfg; 3542 3543 ALC_LOCK_ASSERT(sc); 3544 3545 /* Enable RxQ. */ 3546 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3547 cfg &= ~RXQ_CFG_ENB; 3548 cfg |= qcfg[1]; 3549 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3550 /* Enable TxQ. */ 3551 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3552 cfg |= TXQ_CFG_ENB; 3553 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3554 } 3555 3556 static void 3557 alc_stop_queue(struct alc_softc *sc) 3558 { 3559 uint32_t reg; 3560 int i; 3561 3562 ALC_LOCK_ASSERT(sc); 3563 3564 /* Disable RxQ. */ 3565 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3566 if ((reg & RXQ_CFG_ENB) != 0) { 3567 reg &= ~RXQ_CFG_ENB; 3568 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3569 } 3570 /* Disable TxQ. */ 3571 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3572 if ((reg & TXQ_CFG_ENB) != 0) { 3573 reg &= ~TXQ_CFG_ENB; 3574 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3575 } 3576 for (i = ALC_TIMEOUT; i > 0; i--) { 3577 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3578 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3579 break; 3580 DELAY(10); 3581 } 3582 if (i == 0) 3583 device_printf(sc->alc_dev, 3584 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3585 } 3586 3587 static void 3588 alc_init_tx_ring(struct alc_softc *sc) 3589 { 3590 struct alc_ring_data *rd; 3591 struct alc_txdesc *txd; 3592 int i; 3593 3594 ALC_LOCK_ASSERT(sc); 3595 3596 sc->alc_cdata.alc_tx_prod = 0; 3597 sc->alc_cdata.alc_tx_cons = 0; 3598 sc->alc_cdata.alc_tx_cnt = 0; 3599 3600 rd = &sc->alc_rdata; 3601 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3602 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3603 txd = &sc->alc_cdata.alc_txdesc[i]; 3604 txd->tx_m = NULL; 3605 } 3606 3607 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3608 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3609 } 3610 3611 static int 3612 alc_init_rx_ring(struct alc_softc *sc) 3613 { 3614 struct alc_ring_data *rd; 3615 struct alc_rxdesc *rxd; 3616 int i; 3617 3618 ALC_LOCK_ASSERT(sc); 3619 3620 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3621 sc->alc_morework = 0; 3622 rd = &sc->alc_rdata; 3623 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3624 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3625 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3626 rxd->rx_m = NULL; 3627 rxd->rx_desc = &rd->alc_rx_ring[i]; 3628 if (alc_newbuf(sc, rxd) != 0) 3629 return (ENOBUFS); 3630 } 3631 3632 /* 3633 * Since controller does not update Rx descriptors, driver 3634 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3635 * is enough to ensure coherence. 3636 */ 3637 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3638 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3639 /* Let controller know availability of new Rx buffers. */ 3640 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3641 3642 return (0); 3643 } 3644 3645 static void 3646 alc_init_rr_ring(struct alc_softc *sc) 3647 { 3648 struct alc_ring_data *rd; 3649 3650 ALC_LOCK_ASSERT(sc); 3651 3652 sc->alc_cdata.alc_rr_cons = 0; 3653 ALC_RXCHAIN_RESET(sc); 3654 3655 rd = &sc->alc_rdata; 3656 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3657 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3658 sc->alc_cdata.alc_rr_ring_map, 3659 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3660 } 3661 3662 static void 3663 alc_init_cmb(struct alc_softc *sc) 3664 { 3665 struct alc_ring_data *rd; 3666 3667 ALC_LOCK_ASSERT(sc); 3668 3669 rd = &sc->alc_rdata; 3670 bzero(rd->alc_cmb, ALC_CMB_SZ); 3671 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3673 } 3674 3675 static void 3676 alc_init_smb(struct alc_softc *sc) 3677 { 3678 struct alc_ring_data *rd; 3679 3680 ALC_LOCK_ASSERT(sc); 3681 3682 rd = &sc->alc_rdata; 3683 bzero(rd->alc_smb, ALC_SMB_SZ); 3684 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3686 } 3687 3688 static void 3689 alc_rxvlan(struct alc_softc *sc) 3690 { 3691 struct ifnet *ifp; 3692 uint32_t reg; 3693 3694 ALC_LOCK_ASSERT(sc); 3695 3696 ifp = sc->alc_ifp; 3697 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3698 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3699 reg |= MAC_CFG_VLAN_TAG_STRIP; 3700 else 3701 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3702 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3703 } 3704 3705 static void 3706 alc_rxfilter(struct alc_softc *sc) 3707 { 3708 struct ifnet *ifp; 3709 struct ifmultiaddr *ifma; 3710 uint32_t crc; 3711 uint32_t mchash[2]; 3712 uint32_t rxcfg; 3713 3714 ALC_LOCK_ASSERT(sc); 3715 3716 ifp = sc->alc_ifp; 3717 3718 bzero(mchash, sizeof(mchash)); 3719 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3720 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3721 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3722 rxcfg |= MAC_CFG_BCAST; 3723 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3724 if ((ifp->if_flags & IFF_PROMISC) != 0) 3725 rxcfg |= MAC_CFG_PROMISC; 3726 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3727 rxcfg |= MAC_CFG_ALLMULTI; 3728 mchash[0] = 0xFFFFFFFF; 3729 mchash[1] = 0xFFFFFFFF; 3730 goto chipit; 3731 } 3732 3733 if_maddr_rlock(ifp); 3734 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3735 if (ifma->ifma_addr->sa_family != AF_LINK) 3736 continue; 3737 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3738 ifma->ifma_addr), ETHER_ADDR_LEN); 3739 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3740 } 3741 if_maddr_runlock(ifp); 3742 3743 chipit: 3744 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3745 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3746 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3747 } 3748 3749 static int 3750 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3751 { 3752 int error, value; 3753 3754 if (arg1 == NULL) 3755 return (EINVAL); 3756 value = *(int *)arg1; 3757 error = sysctl_handle_int(oidp, &value, 0, req); 3758 if (error || req->newptr == NULL) 3759 return (error); 3760 if (value < low || value > high) 3761 return (EINVAL); 3762 *(int *)arg1 = value; 3763 3764 return (0); 3765 } 3766 3767 static int 3768 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3769 { 3770 return (sysctl_int_range(oidp, arg1, arg2, req, 3771 ALC_PROC_MIN, ALC_PROC_MAX)); 3772 } 3773 3774 static int 3775 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3776 { 3777 3778 return (sysctl_int_range(oidp, arg1, arg2, req, 3779 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3780 } 3781