1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/bus.h> 72 #include <machine/in_cksum.h> 73 74 #include <dev/alc/if_alcreg.h> 75 #include <dev/alc/if_alcvar.h> 76 77 /* "device miibus" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 #undef ALC_USE_CUSTOM_CSUM 80 81 #ifdef ALC_USE_CUSTOM_CSUM 82 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 #else 84 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 #endif 86 87 MODULE_DEPEND(alc, pci, 1, 1, 1); 88 MODULE_DEPEND(alc, ether, 1, 1, 1); 89 MODULE_DEPEND(alc, miibus, 1, 1, 1); 90 91 /* Tunables. */ 92 static int msi_disable = 0; 93 static int msix_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96 97 /* 98 * Devices supported by this driver. 99 */ 100 static struct alc_ident alc_ident_table[] = { 101 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102 "Atheros AR8131 PCIe Gigabit Ethernet" }, 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 104 "Atheros AR8132 PCIe Fast Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 106 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 108 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 110 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 112 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 113 { 0, 0, 0, NULL} 114 }; 115 116 static void alc_aspm(struct alc_softc *, int); 117 static int alc_attach(device_t); 118 static int alc_check_boundary(struct alc_softc *); 119 static int alc_detach(device_t); 120 static void alc_disable_l0s_l1(struct alc_softc *); 121 static int alc_dma_alloc(struct alc_softc *); 122 static void alc_dma_free(struct alc_softc *); 123 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 124 static int alc_encap(struct alc_softc *, struct mbuf **); 125 static struct alc_ident * 126 alc_find_ident(device_t); 127 #ifndef __NO_STRICT_ALIGNMENT 128 static struct mbuf * 129 alc_fixup_rx(struct ifnet *, struct mbuf *); 130 #endif 131 static void alc_get_macaddr(struct alc_softc *); 132 static void alc_init(void *); 133 static void alc_init_cmb(struct alc_softc *); 134 static void alc_init_locked(struct alc_softc *); 135 static void alc_init_rr_ring(struct alc_softc *); 136 static int alc_init_rx_ring(struct alc_softc *); 137 static void alc_init_smb(struct alc_softc *); 138 static void alc_init_tx_ring(struct alc_softc *); 139 static void alc_int_task(void *, int); 140 static int alc_intr(void *); 141 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 142 static void alc_mac_config(struct alc_softc *); 143 static int alc_miibus_readreg(device_t, int, int); 144 static void alc_miibus_statchg(device_t); 145 static int alc_miibus_writereg(device_t, int, int, int); 146 static int alc_mediachange(struct ifnet *); 147 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 148 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 149 static void alc_phy_down(struct alc_softc *); 150 static void alc_phy_reset(struct alc_softc *); 151 static int alc_probe(device_t); 152 static void alc_reset(struct alc_softc *); 153 static int alc_resume(device_t); 154 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 155 static int alc_rxintr(struct alc_softc *, int); 156 static void alc_rxfilter(struct alc_softc *); 157 static void alc_rxvlan(struct alc_softc *); 158 static void alc_setlinkspeed(struct alc_softc *); 159 static void alc_setwol(struct alc_softc *); 160 static int alc_shutdown(device_t); 161 static void alc_start(struct ifnet *); 162 static void alc_start_queue(struct alc_softc *); 163 static void alc_stats_clear(struct alc_softc *); 164 static void alc_stats_update(struct alc_softc *); 165 static void alc_stop(struct alc_softc *); 166 static void alc_stop_mac(struct alc_softc *); 167 static void alc_stop_queue(struct alc_softc *); 168 static int alc_suspend(device_t); 169 static void alc_sysctl_node(struct alc_softc *); 170 static void alc_tick(void *); 171 static void alc_tx_task(void *, int); 172 static void alc_txeof(struct alc_softc *); 173 static void alc_watchdog(struct alc_softc *); 174 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 175 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 176 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 177 178 static device_method_t alc_methods[] = { 179 /* Device interface. */ 180 DEVMETHOD(device_probe, alc_probe), 181 DEVMETHOD(device_attach, alc_attach), 182 DEVMETHOD(device_detach, alc_detach), 183 DEVMETHOD(device_shutdown, alc_shutdown), 184 DEVMETHOD(device_suspend, alc_suspend), 185 DEVMETHOD(device_resume, alc_resume), 186 187 /* MII interface. */ 188 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 189 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 190 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 191 192 { NULL, NULL } 193 }; 194 195 static driver_t alc_driver = { 196 "alc", 197 alc_methods, 198 sizeof(struct alc_softc) 199 }; 200 201 static devclass_t alc_devclass; 202 203 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 204 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 205 206 static struct resource_spec alc_res_spec_mem[] = { 207 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 208 { -1, 0, 0 } 209 }; 210 211 static struct resource_spec alc_irq_spec_legacy[] = { 212 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 213 { -1, 0, 0 } 214 }; 215 216 static struct resource_spec alc_irq_spec_msi[] = { 217 { SYS_RES_IRQ, 1, RF_ACTIVE }, 218 { -1, 0, 0 } 219 }; 220 221 static struct resource_spec alc_irq_spec_msix[] = { 222 { SYS_RES_IRQ, 1, RF_ACTIVE }, 223 { -1, 0, 0 } 224 }; 225 226 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 227 228 static int 229 alc_miibus_readreg(device_t dev, int phy, int reg) 230 { 231 struct alc_softc *sc; 232 uint32_t v; 233 int i; 234 235 sc = device_get_softc(dev); 236 237 /* 238 * For AR8132 fast ethernet controller, do not report 1000baseT 239 * capability to mii(4). Even though AR8132 uses the same 240 * model/revision number of F1 gigabit PHY, the PHY has no 241 * ability to establish 1000baseT link. 242 */ 243 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 244 reg == MII_EXTSR) 245 return (0); 246 247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALC_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) { 257 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262 } 263 264 static int 265 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266 { 267 struct alc_softc *sc; 268 uint32_t v; 269 int i; 270 271 sc = device_get_softc(dev); 272 273 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277 DELAY(5); 278 v = CSR_READ_4(sc, ALC_MDIO); 279 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280 break; 281 } 282 283 if (i == 0) 284 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285 286 return (0); 287 } 288 289 static void 290 alc_miibus_statchg(device_t dev) 291 { 292 struct alc_softc *sc; 293 struct mii_data *mii; 294 struct ifnet *ifp; 295 uint32_t reg; 296 297 sc = device_get_softc(dev); 298 299 mii = device_get_softc(sc->alc_miibus); 300 ifp = sc->alc_ifp; 301 if (mii == NULL || ifp == NULL || 302 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303 return; 304 305 sc->alc_flags &= ~ALC_FLAG_LINK; 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 sc->alc_flags |= ALC_FLAG_LINK; 312 break; 313 case IFM_1000_T: 314 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315 sc->alc_flags |= ALC_FLAG_LINK; 316 break; 317 default: 318 break; 319 } 320 } 321 alc_stop_queue(sc); 322 /* Stop Rx/Tx MACs. */ 323 alc_stop_mac(sc); 324 325 /* Program MACs with resolved speed/duplex/flow-control. */ 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327 alc_start_queue(sc); 328 alc_mac_config(sc); 329 /* Re-enable Tx/Rx MACs. */ 330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 331 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 333 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 334 } 335 } 336 337 static void 338 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339 { 340 struct alc_softc *sc; 341 struct mii_data *mii; 342 343 sc = ifp->if_softc; 344 ALC_LOCK(sc); 345 if ((ifp->if_flags & IFF_UP) == 0) { 346 ALC_UNLOCK(sc); 347 return; 348 } 349 mii = device_get_softc(sc->alc_miibus); 350 351 mii_pollstat(mii); 352 ALC_UNLOCK(sc); 353 ifmr->ifm_status = mii->mii_media_status; 354 ifmr->ifm_active = mii->mii_media_active; 355 } 356 357 static int 358 alc_mediachange(struct ifnet *ifp) 359 { 360 struct alc_softc *sc; 361 struct mii_data *mii; 362 struct mii_softc *miisc; 363 int error; 364 365 sc = ifp->if_softc; 366 ALC_LOCK(sc); 367 mii = device_get_softc(sc->alc_miibus); 368 if (mii->mii_instance != 0) { 369 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 370 mii_phy_reset(miisc); 371 } 372 error = mii_mediachg(mii); 373 ALC_UNLOCK(sc); 374 375 return (error); 376 } 377 378 static struct alc_ident * 379 alc_find_ident(device_t dev) 380 { 381 struct alc_ident *ident; 382 uint16_t vendor, devid; 383 384 vendor = pci_get_vendor(dev); 385 devid = pci_get_device(dev); 386 for (ident = alc_ident_table; ident->name != NULL; ident++) { 387 if (vendor == ident->vendorid && devid == ident->deviceid) 388 return (ident); 389 } 390 391 return (NULL); 392 } 393 394 static int 395 alc_probe(device_t dev) 396 { 397 struct alc_ident *ident; 398 399 ident = alc_find_ident(dev); 400 if (ident != NULL) { 401 device_set_desc(dev, ident->name); 402 return (BUS_PROBE_DEFAULT); 403 } 404 405 return (ENXIO); 406 } 407 408 static void 409 alc_get_macaddr(struct alc_softc *sc) 410 { 411 uint32_t ea[2], opt; 412 uint16_t val; 413 int eeprom, i; 414 415 eeprom = 0; 416 opt = CSR_READ_4(sc, ALC_OPT_CFG); 417 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 418 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 419 /* 420 * EEPROM found, let TWSI reload EEPROM configuration. 421 * This will set ethernet address of controller. 422 */ 423 eeprom++; 424 switch (sc->alc_ident->deviceid) { 425 case DEVICEID_ATHEROS_AR8131: 426 case DEVICEID_ATHEROS_AR8132: 427 if ((opt & OPT_CFG_CLK_ENB) == 0) { 428 opt |= OPT_CFG_CLK_ENB; 429 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 430 CSR_READ_4(sc, ALC_OPT_CFG); 431 DELAY(1000); 432 } 433 break; 434 case DEVICEID_ATHEROS_AR8151: 435 case DEVICEID_ATHEROS_AR8151_V2: 436 case DEVICEID_ATHEROS_AR8152_B: 437 case DEVICEID_ATHEROS_AR8152_B2: 438 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 439 ALC_MII_DBG_ADDR, 0x00); 440 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 441 ALC_MII_DBG_DATA); 442 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 443 ALC_MII_DBG_DATA, val & 0xFF7F); 444 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 445 ALC_MII_DBG_ADDR, 0x3B); 446 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 447 ALC_MII_DBG_DATA); 448 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 449 ALC_MII_DBG_DATA, val | 0x0008); 450 DELAY(20); 451 break; 452 } 453 454 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 455 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 456 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 457 CSR_READ_4(sc, ALC_WOL_CFG); 458 459 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 460 TWSI_CFG_SW_LD_START); 461 for (i = 100; i > 0; i--) { 462 DELAY(1000); 463 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 464 TWSI_CFG_SW_LD_START) == 0) 465 break; 466 } 467 if (i == 0) 468 device_printf(sc->alc_dev, 469 "reloading EEPROM timeout!\n"); 470 } else { 471 if (bootverbose) 472 device_printf(sc->alc_dev, "EEPROM not found!\n"); 473 } 474 if (eeprom != 0) { 475 switch (sc->alc_ident->deviceid) { 476 case DEVICEID_ATHEROS_AR8131: 477 case DEVICEID_ATHEROS_AR8132: 478 if ((opt & OPT_CFG_CLK_ENB) != 0) { 479 opt &= ~OPT_CFG_CLK_ENB; 480 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 481 CSR_READ_4(sc, ALC_OPT_CFG); 482 DELAY(1000); 483 } 484 break; 485 case DEVICEID_ATHEROS_AR8151: 486 case DEVICEID_ATHEROS_AR8151_V2: 487 case DEVICEID_ATHEROS_AR8152_B: 488 case DEVICEID_ATHEROS_AR8152_B2: 489 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 490 ALC_MII_DBG_ADDR, 0x00); 491 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 492 ALC_MII_DBG_DATA); 493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 494 ALC_MII_DBG_DATA, val | 0x0080); 495 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_ADDR, 0x3B); 497 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA); 499 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 500 ALC_MII_DBG_DATA, val & 0xFFF7); 501 DELAY(20); 502 break; 503 } 504 } 505 506 ea[0] = CSR_READ_4(sc, ALC_PAR0); 507 ea[1] = CSR_READ_4(sc, ALC_PAR1); 508 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 509 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 510 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 511 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 512 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 513 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 514 } 515 516 static void 517 alc_disable_l0s_l1(struct alc_softc *sc) 518 { 519 uint32_t pmcfg; 520 521 /* Another magic from vendor. */ 522 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 523 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 524 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 525 PM_CFG_SERDES_PD_EX_L1); 526 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 527 PM_CFG_SERDES_L1_ENB; 528 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 529 } 530 531 static void 532 alc_phy_reset(struct alc_softc *sc) 533 { 534 uint16_t data; 535 536 /* Reset magic from Linux. */ 537 CSR_WRITE_2(sc, ALC_GPHY_CFG, 538 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 539 CSR_READ_2(sc, ALC_GPHY_CFG); 540 DELAY(10 * 1000); 541 542 CSR_WRITE_2(sc, ALC_GPHY_CFG, 543 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 544 GPHY_CFG_SEL_ANA_RESET); 545 CSR_READ_2(sc, ALC_GPHY_CFG); 546 DELAY(10 * 1000); 547 548 /* DSP fixup, Vendor magic. */ 549 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 550 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 551 ALC_MII_DBG_ADDR, 0x000A); 552 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 553 ALC_MII_DBG_DATA); 554 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 555 ALC_MII_DBG_DATA, data & 0xDFFF); 556 } 557 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 558 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 559 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 560 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 561 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 562 ALC_MII_DBG_ADDR, 0x003B); 563 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 564 ALC_MII_DBG_DATA); 565 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 566 ALC_MII_DBG_DATA, data & 0xFFF7); 567 DELAY(20 * 1000); 568 } 569 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 570 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_ADDR, 0x0029); 572 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 573 ALC_MII_DBG_DATA, 0x929D); 574 } 575 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 576 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 578 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 579 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 580 ALC_MII_DBG_ADDR, 0x0029); 581 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 582 ALC_MII_DBG_DATA, 0xB6DD); 583 } 584 585 /* Load DSP codes, vendor magic. */ 586 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 587 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 588 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 590 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 591 ALC_MII_DBG_DATA, data); 592 593 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 594 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 595 ANA_SERDES_EN_LCKDT; 596 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 597 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 598 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 599 ALC_MII_DBG_DATA, data); 600 601 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 602 ANA_LONG_CABLE_TH_100_MASK) | 603 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 604 ANA_SHORT_CABLE_TH_100_SHIFT) | 605 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 606 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 607 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 608 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 609 ALC_MII_DBG_DATA, data); 610 611 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 612 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 613 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 614 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 617 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 618 ALC_MII_DBG_DATA, data); 619 620 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 621 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 622 ANA_OEN_125M; 623 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 625 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_DATA, data); 627 DELAY(1000); 628 } 629 630 static void 631 alc_phy_down(struct alc_softc *sc) 632 { 633 634 switch (sc->alc_ident->deviceid) { 635 case DEVICEID_ATHEROS_AR8151: 636 case DEVICEID_ATHEROS_AR8151_V2: 637 /* 638 * GPHY power down caused more problems on AR8151 v2.0. 639 * When driver is reloaded after GPHY power down, 640 * accesses to PHY/MAC registers hung the system. Only 641 * cold boot recovered from it. I'm not sure whether 642 * AR8151 v1.0 also requires this one though. I don't 643 * have AR8151 v1.0 controller in hand. 644 * The only option left is to isolate the PHY and 645 * initiates power down the PHY which in turn saves 646 * more power when driver is unloaded. 647 */ 648 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 649 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 650 break; 651 default: 652 /* Force PHY down. */ 653 CSR_WRITE_2(sc, ALC_GPHY_CFG, 654 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 655 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 656 GPHY_CFG_PWDOWN_HW); 657 DELAY(1000); 658 break; 659 } 660 } 661 662 static void 663 alc_aspm(struct alc_softc *sc, int media) 664 { 665 uint32_t pmcfg; 666 uint16_t linkcfg; 667 668 ALC_LOCK_ASSERT(sc); 669 670 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 671 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 672 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 673 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 674 PCIR_EXPRESS_LINK_CTL); 675 else 676 linkcfg = 0; 677 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 678 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 679 pmcfg |= PM_CFG_MAC_ASPM_CHK; 680 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 681 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 682 683 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 684 /* Disable extended sync except AR8152 B v1.0 */ 685 linkcfg &= ~0x80; 686 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 687 sc->alc_rev == ATHEROS_AR8152_B_V10) 688 linkcfg |= 0x80; 689 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 690 linkcfg); 691 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 692 PM_CFG_HOTRST); 693 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 694 PM_CFG_L1_ENTRY_TIMER_SHIFT); 695 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 696 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 697 PM_CFG_PM_REQ_TIMER_SHIFT); 698 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 699 } 700 701 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 702 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 703 pmcfg |= PM_CFG_ASPM_L0S_ENB; 704 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 705 pmcfg |= PM_CFG_ASPM_L1_ENB; 706 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 707 if (sc->alc_ident->deviceid == 708 DEVICEID_ATHEROS_AR8152_B) 709 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 710 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 711 PM_CFG_SERDES_PLL_L1_ENB | 712 PM_CFG_SERDES_BUDS_RX_L1_ENB); 713 pmcfg |= PM_CFG_CLK_SWH_L1; 714 if (media == IFM_100_TX || media == IFM_1000_T) { 715 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 716 switch (sc->alc_ident->deviceid) { 717 case DEVICEID_ATHEROS_AR8152_B: 718 pmcfg |= (7 << 719 PM_CFG_L1_ENTRY_TIMER_SHIFT); 720 break; 721 case DEVICEID_ATHEROS_AR8152_B2: 722 case DEVICEID_ATHEROS_AR8151_V2: 723 pmcfg |= (4 << 724 PM_CFG_L1_ENTRY_TIMER_SHIFT); 725 break; 726 default: 727 pmcfg |= (15 << 728 PM_CFG_L1_ENTRY_TIMER_SHIFT); 729 break; 730 } 731 } 732 } else { 733 pmcfg |= PM_CFG_SERDES_L1_ENB | 734 PM_CFG_SERDES_PLL_L1_ENB | 735 PM_CFG_SERDES_BUDS_RX_L1_ENB; 736 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 737 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 738 } 739 } else { 740 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 741 PM_CFG_SERDES_PLL_L1_ENB); 742 pmcfg |= PM_CFG_CLK_SWH_L1; 743 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 744 pmcfg |= PM_CFG_ASPM_L1_ENB; 745 } 746 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 747 } 748 749 static int 750 alc_attach(device_t dev) 751 { 752 struct alc_softc *sc; 753 struct ifnet *ifp; 754 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 755 uint16_t burst; 756 int base, error, i, msic, msixc, state; 757 uint32_t cap, ctl, val; 758 759 error = 0; 760 sc = device_get_softc(dev); 761 sc->alc_dev = dev; 762 763 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 764 MTX_DEF); 765 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 766 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 767 sc->alc_ident = alc_find_ident(dev); 768 769 /* Map the device. */ 770 pci_enable_busmaster(dev); 771 sc->alc_res_spec = alc_res_spec_mem; 772 sc->alc_irq_spec = alc_irq_spec_legacy; 773 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 774 if (error != 0) { 775 device_printf(dev, "cannot allocate memory resources.\n"); 776 goto fail; 777 } 778 779 /* Set PHY address. */ 780 sc->alc_phyaddr = ALC_PHY_ADDR; 781 782 /* Initialize DMA parameters. */ 783 sc->alc_dma_rd_burst = 0; 784 sc->alc_dma_wr_burst = 0; 785 sc->alc_rcb = DMA_CFG_RCB_64; 786 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 787 sc->alc_flags |= ALC_FLAG_PCIE; 788 sc->alc_expcap = base; 789 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 790 sc->alc_dma_rd_burst = 791 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 792 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 793 if (bootverbose) { 794 device_printf(dev, "Read request size : %u bytes.\n", 795 alc_dma_burst[sc->alc_dma_rd_burst]); 796 device_printf(dev, "TLP payload size : %u bytes.\n", 797 alc_dma_burst[sc->alc_dma_wr_burst]); 798 } 799 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 800 sc->alc_dma_rd_burst = 3; 801 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 802 sc->alc_dma_wr_burst = 3; 803 /* Clear data link and flow-control protocol error. */ 804 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 805 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 806 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 807 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 808 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 809 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 810 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 811 PCIE_PHYMISC_FORCE_RCV_DET); 812 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 813 sc->alc_rev == ATHEROS_AR8152_B_V10) { 814 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 815 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 816 PCIE_PHYMISC2_SERDES_TH_MASK); 817 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 818 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 819 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 820 } 821 /* Disable ASPM L0S and L1. */ 822 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 823 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 824 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 825 if ((ctl & 0x08) != 0) 826 sc->alc_rcb = DMA_CFG_RCB_128; 827 if (bootverbose) 828 device_printf(dev, "RCB %u bytes\n", 829 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 830 state = ctl & 0x03; 831 if (state & 0x01) 832 sc->alc_flags |= ALC_FLAG_L0S; 833 if (state & 0x02) 834 sc->alc_flags |= ALC_FLAG_L1S; 835 if (bootverbose) 836 device_printf(sc->alc_dev, "ASPM %s %s\n", 837 aspm_state[state], 838 state == 0 ? "disabled" : "enabled"); 839 alc_disable_l0s_l1(sc); 840 } else { 841 if (bootverbose) 842 device_printf(sc->alc_dev, 843 "no ASPM support\n"); 844 } 845 } 846 847 /* Reset PHY. */ 848 alc_phy_reset(sc); 849 850 /* Reset the ethernet controller. */ 851 alc_reset(sc); 852 853 /* 854 * One odd thing is AR8132 uses the same PHY hardware(F1 855 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 856 * the PHY supports 1000Mbps but that's not true. The PHY 857 * used in AR8132 can't establish gigabit link even if it 858 * shows the same PHY model/revision number of AR8131. 859 */ 860 switch (sc->alc_ident->deviceid) { 861 case DEVICEID_ATHEROS_AR8152_B: 862 case DEVICEID_ATHEROS_AR8152_B2: 863 sc->alc_flags |= ALC_FLAG_APS; 864 /* FALLTHROUGH */ 865 case DEVICEID_ATHEROS_AR8132: 866 sc->alc_flags |= ALC_FLAG_FASTETHER; 867 break; 868 case DEVICEID_ATHEROS_AR8151: 869 case DEVICEID_ATHEROS_AR8151_V2: 870 sc->alc_flags |= ALC_FLAG_APS; 871 /* FALLTHROUGH */ 872 default: 873 break; 874 } 875 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 876 877 /* 878 * It seems that AR813x/AR815x has silicon bug for SMB. In 879 * addition, Atheros said that enabling SMB wouldn't improve 880 * performance. However I think it's bad to access lots of 881 * registers to extract MAC statistics. 882 */ 883 sc->alc_flags |= ALC_FLAG_SMB_BUG; 884 /* 885 * Don't use Tx CMB. It is known to have silicon bug. 886 */ 887 sc->alc_flags |= ALC_FLAG_CMB_BUG; 888 sc->alc_rev = pci_get_revid(dev); 889 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 890 MASTER_CHIP_REV_SHIFT; 891 if (bootverbose) { 892 device_printf(dev, "PCI device revision : 0x%04x\n", 893 sc->alc_rev); 894 device_printf(dev, "Chip id/revision : 0x%04x\n", 895 sc->alc_chip_rev); 896 } 897 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 898 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 899 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 900 901 /* Allocate IRQ resources. */ 902 msixc = pci_msix_count(dev); 903 msic = pci_msi_count(dev); 904 if (bootverbose) { 905 device_printf(dev, "MSIX count : %d\n", msixc); 906 device_printf(dev, "MSI count : %d\n", msic); 907 } 908 /* Prefer MSIX over MSI. */ 909 if (msix_disable == 0 || msi_disable == 0) { 910 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 911 pci_alloc_msix(dev, &msixc) == 0) { 912 if (msic == ALC_MSIX_MESSAGES) { 913 device_printf(dev, 914 "Using %d MSIX message(s).\n", msixc); 915 sc->alc_flags |= ALC_FLAG_MSIX; 916 sc->alc_irq_spec = alc_irq_spec_msix; 917 } else 918 pci_release_msi(dev); 919 } 920 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 921 msic == ALC_MSI_MESSAGES && 922 pci_alloc_msi(dev, &msic) == 0) { 923 if (msic == ALC_MSI_MESSAGES) { 924 device_printf(dev, 925 "Using %d MSI message(s).\n", msic); 926 sc->alc_flags |= ALC_FLAG_MSI; 927 sc->alc_irq_spec = alc_irq_spec_msi; 928 } else 929 pci_release_msi(dev); 930 } 931 } 932 933 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 934 if (error != 0) { 935 device_printf(dev, "cannot allocate IRQ resources.\n"); 936 goto fail; 937 } 938 939 /* Create device sysctl node. */ 940 alc_sysctl_node(sc); 941 942 if ((error = alc_dma_alloc(sc) != 0)) 943 goto fail; 944 945 /* Load station address. */ 946 alc_get_macaddr(sc); 947 948 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 949 if (ifp == NULL) { 950 device_printf(dev, "cannot allocate ifnet structure.\n"); 951 error = ENXIO; 952 goto fail; 953 } 954 955 ifp->if_softc = sc; 956 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 957 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 958 ifp->if_ioctl = alc_ioctl; 959 ifp->if_start = alc_start; 960 ifp->if_init = alc_init; 961 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 962 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 963 IFQ_SET_READY(&ifp->if_snd); 964 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 965 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 966 if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { 967 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 968 sc->alc_flags |= ALC_FLAG_PM; 969 sc->alc_pmcap = base; 970 } 971 ifp->if_capenable = ifp->if_capabilities; 972 973 /* Set up MII bus. */ 974 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 975 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 976 MIIF_DOPAUSE); 977 if (error != 0) { 978 device_printf(dev, "attaching PHYs failed\n"); 979 goto fail; 980 } 981 982 ether_ifattach(ifp, sc->alc_eaddr); 983 984 /* VLAN capability setup. */ 985 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 986 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 987 ifp->if_capenable = ifp->if_capabilities; 988 /* 989 * XXX 990 * It seems enabling Tx checksum offloading makes more trouble. 991 * Sometimes the controller does not receive any frames when 992 * Tx checksum offloading is enabled. I'm not sure whether this 993 * is a bug in Tx checksum offloading logic or I got broken 994 * sample boards. To safety, don't enable Tx checksum offloading 995 * by default but give chance to users to toggle it if they know 996 * their controllers work without problems. 997 */ 998 ifp->if_capenable &= ~IFCAP_TXCSUM; 999 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1000 1001 /* Tell the upper layer(s) we support long frames. */ 1002 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1003 1004 /* Create local taskq. */ 1005 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1006 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1007 taskqueue_thread_enqueue, &sc->alc_tq); 1008 if (sc->alc_tq == NULL) { 1009 device_printf(dev, "could not create taskqueue.\n"); 1010 ether_ifdetach(ifp); 1011 error = ENXIO; 1012 goto fail; 1013 } 1014 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1015 device_get_nameunit(sc->alc_dev)); 1016 1017 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1018 msic = ALC_MSIX_MESSAGES; 1019 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1020 msic = ALC_MSI_MESSAGES; 1021 else 1022 msic = 1; 1023 for (i = 0; i < msic; i++) { 1024 error = bus_setup_intr(dev, sc->alc_irq[i], 1025 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1026 &sc->alc_intrhand[i]); 1027 if (error != 0) 1028 break; 1029 } 1030 if (error != 0) { 1031 device_printf(dev, "could not set up interrupt handler.\n"); 1032 taskqueue_free(sc->alc_tq); 1033 sc->alc_tq = NULL; 1034 ether_ifdetach(ifp); 1035 goto fail; 1036 } 1037 1038 fail: 1039 if (error != 0) 1040 alc_detach(dev); 1041 1042 return (error); 1043 } 1044 1045 static int 1046 alc_detach(device_t dev) 1047 { 1048 struct alc_softc *sc; 1049 struct ifnet *ifp; 1050 int i, msic; 1051 1052 sc = device_get_softc(dev); 1053 1054 ifp = sc->alc_ifp; 1055 if (device_is_attached(dev)) { 1056 ALC_LOCK(sc); 1057 sc->alc_flags |= ALC_FLAG_DETACH; 1058 alc_stop(sc); 1059 ALC_UNLOCK(sc); 1060 callout_drain(&sc->alc_tick_ch); 1061 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1062 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1063 ether_ifdetach(ifp); 1064 } 1065 1066 if (sc->alc_tq != NULL) { 1067 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1068 taskqueue_free(sc->alc_tq); 1069 sc->alc_tq = NULL; 1070 } 1071 1072 if (sc->alc_miibus != NULL) { 1073 device_delete_child(dev, sc->alc_miibus); 1074 sc->alc_miibus = NULL; 1075 } 1076 bus_generic_detach(dev); 1077 alc_dma_free(sc); 1078 1079 if (ifp != NULL) { 1080 if_free(ifp); 1081 sc->alc_ifp = NULL; 1082 } 1083 1084 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1085 msic = ALC_MSIX_MESSAGES; 1086 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1087 msic = ALC_MSI_MESSAGES; 1088 else 1089 msic = 1; 1090 for (i = 0; i < msic; i++) { 1091 if (sc->alc_intrhand[i] != NULL) { 1092 bus_teardown_intr(dev, sc->alc_irq[i], 1093 sc->alc_intrhand[i]); 1094 sc->alc_intrhand[i] = NULL; 1095 } 1096 } 1097 if (sc->alc_res[0] != NULL) 1098 alc_phy_down(sc); 1099 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1100 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1101 pci_release_msi(dev); 1102 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1103 mtx_destroy(&sc->alc_mtx); 1104 1105 return (0); 1106 } 1107 1108 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1109 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1110 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1111 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1112 1113 static void 1114 alc_sysctl_node(struct alc_softc *sc) 1115 { 1116 struct sysctl_ctx_list *ctx; 1117 struct sysctl_oid_list *child, *parent; 1118 struct sysctl_oid *tree; 1119 struct alc_hw_stats *stats; 1120 int error; 1121 1122 stats = &sc->alc_stats; 1123 ctx = device_get_sysctl_ctx(sc->alc_dev); 1124 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1125 1126 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1127 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1128 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1129 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1130 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1131 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1132 /* Pull in device tunables. */ 1133 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1134 error = resource_int_value(device_get_name(sc->alc_dev), 1135 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1136 if (error == 0) { 1137 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1138 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1139 device_printf(sc->alc_dev, "int_rx_mod value out of " 1140 "range; using default: %d\n", 1141 ALC_IM_RX_TIMER_DEFAULT); 1142 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1143 } 1144 } 1145 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1146 error = resource_int_value(device_get_name(sc->alc_dev), 1147 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1148 if (error == 0) { 1149 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1150 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1151 device_printf(sc->alc_dev, "int_tx_mod value out of " 1152 "range; using default: %d\n", 1153 ALC_IM_TX_TIMER_DEFAULT); 1154 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1155 } 1156 } 1157 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1158 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1159 sysctl_hw_alc_proc_limit, "I", 1160 "max number of Rx events to process"); 1161 /* Pull in device tunables. */ 1162 sc->alc_process_limit = ALC_PROC_DEFAULT; 1163 error = resource_int_value(device_get_name(sc->alc_dev), 1164 device_get_unit(sc->alc_dev), "process_limit", 1165 &sc->alc_process_limit); 1166 if (error == 0) { 1167 if (sc->alc_process_limit < ALC_PROC_MIN || 1168 sc->alc_process_limit > ALC_PROC_MAX) { 1169 device_printf(sc->alc_dev, 1170 "process_limit value out of range; " 1171 "using default: %d\n", ALC_PROC_DEFAULT); 1172 sc->alc_process_limit = ALC_PROC_DEFAULT; 1173 } 1174 } 1175 1176 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1177 NULL, "ALC statistics"); 1178 parent = SYSCTL_CHILDREN(tree); 1179 1180 /* Rx statistics. */ 1181 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1182 NULL, "Rx MAC statistics"); 1183 child = SYSCTL_CHILDREN(tree); 1184 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1185 &stats->rx_frames, "Good frames"); 1186 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1187 &stats->rx_bcast_frames, "Good broadcast frames"); 1188 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1189 &stats->rx_mcast_frames, "Good multicast frames"); 1190 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1191 &stats->rx_pause_frames, "Pause control frames"); 1192 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1193 &stats->rx_control_frames, "Control frames"); 1194 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1195 &stats->rx_crcerrs, "CRC errors"); 1196 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1197 &stats->rx_lenerrs, "Frames with length mismatched"); 1198 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1199 &stats->rx_bytes, "Good octets"); 1200 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1201 &stats->rx_bcast_bytes, "Good broadcast octets"); 1202 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1203 &stats->rx_mcast_bytes, "Good multicast octets"); 1204 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1205 &stats->rx_runts, "Too short frames"); 1206 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1207 &stats->rx_fragments, "Fragmented frames"); 1208 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1209 &stats->rx_pkts_64, "64 bytes frames"); 1210 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1211 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1212 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1213 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1214 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1215 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1217 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1219 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1221 &stats->rx_pkts_1519_max, "1519 to max frames"); 1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1223 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1225 &stats->rx_fifo_oflows, "FIFO overflows"); 1226 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1227 &stats->rx_rrs_errs, "Return status write-back errors"); 1228 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1229 &stats->rx_alignerrs, "Alignment errors"); 1230 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1231 &stats->rx_pkts_filtered, 1232 "Frames dropped due to address filtering"); 1233 1234 /* Tx statistics. */ 1235 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1236 NULL, "Tx MAC statistics"); 1237 child = SYSCTL_CHILDREN(tree); 1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1239 &stats->tx_frames, "Good frames"); 1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1241 &stats->tx_bcast_frames, "Good broadcast frames"); 1242 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1243 &stats->tx_mcast_frames, "Good multicast frames"); 1244 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1245 &stats->tx_pause_frames, "Pause control frames"); 1246 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1247 &stats->tx_control_frames, "Control frames"); 1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1249 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1251 &stats->tx_excess_defer, "Frames with derferrals"); 1252 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1253 &stats->tx_bytes, "Good octets"); 1254 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1255 &stats->tx_bcast_bytes, "Good broadcast octets"); 1256 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1257 &stats->tx_mcast_bytes, "Good multicast octets"); 1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1259 &stats->tx_pkts_64, "64 bytes frames"); 1260 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1261 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1262 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1263 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1264 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1265 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1266 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1267 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1268 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1269 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1271 &stats->tx_pkts_1519_max, "1519 to max frames"); 1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1273 &stats->tx_single_colls, "Single collisions"); 1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1275 &stats->tx_multi_colls, "Multiple collisions"); 1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1277 &stats->tx_late_colls, "Late collisions"); 1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1279 &stats->tx_excess_colls, "Excessive collisions"); 1280 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1281 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1282 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1283 &stats->tx_underrun, "FIFO underruns"); 1284 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1285 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1286 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1287 &stats->tx_lenerrs, "Frames with length mismatched"); 1288 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1289 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1290 } 1291 1292 #undef ALC_SYSCTL_STAT_ADD32 1293 #undef ALC_SYSCTL_STAT_ADD64 1294 1295 struct alc_dmamap_arg { 1296 bus_addr_t alc_busaddr; 1297 }; 1298 1299 static void 1300 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1301 { 1302 struct alc_dmamap_arg *ctx; 1303 1304 if (error != 0) 1305 return; 1306 1307 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1308 1309 ctx = (struct alc_dmamap_arg *)arg; 1310 ctx->alc_busaddr = segs[0].ds_addr; 1311 } 1312 1313 /* 1314 * Normal and high Tx descriptors shares single Tx high address. 1315 * Four Rx descriptor/return rings and CMB shares the same Rx 1316 * high address. 1317 */ 1318 static int 1319 alc_check_boundary(struct alc_softc *sc) 1320 { 1321 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1322 1323 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1324 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1325 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1326 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1327 1328 /* 4GB boundary crossing is not allowed. */ 1329 if ((ALC_ADDR_HI(rx_ring_end) != 1330 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1331 (ALC_ADDR_HI(rr_ring_end) != 1332 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1333 (ALC_ADDR_HI(cmb_end) != 1334 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1335 (ALC_ADDR_HI(tx_ring_end) != 1336 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1337 return (EFBIG); 1338 /* 1339 * Make sure Rx return descriptor/Rx descriptor/CMB use 1340 * the same high address. 1341 */ 1342 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1343 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1344 return (EFBIG); 1345 1346 return (0); 1347 } 1348 1349 static int 1350 alc_dma_alloc(struct alc_softc *sc) 1351 { 1352 struct alc_txdesc *txd; 1353 struct alc_rxdesc *rxd; 1354 bus_addr_t lowaddr; 1355 struct alc_dmamap_arg ctx; 1356 int error, i; 1357 1358 lowaddr = BUS_SPACE_MAXADDR; 1359 again: 1360 /* Create parent DMA tag. */ 1361 error = bus_dma_tag_create( 1362 bus_get_dma_tag(sc->alc_dev), /* parent */ 1363 1, 0, /* alignment, boundary */ 1364 lowaddr, /* lowaddr */ 1365 BUS_SPACE_MAXADDR, /* highaddr */ 1366 NULL, NULL, /* filter, filterarg */ 1367 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1368 0, /* nsegments */ 1369 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1370 0, /* flags */ 1371 NULL, NULL, /* lockfunc, lockarg */ 1372 &sc->alc_cdata.alc_parent_tag); 1373 if (error != 0) { 1374 device_printf(sc->alc_dev, 1375 "could not create parent DMA tag.\n"); 1376 goto fail; 1377 } 1378 1379 /* Create DMA tag for Tx descriptor ring. */ 1380 error = bus_dma_tag_create( 1381 sc->alc_cdata.alc_parent_tag, /* parent */ 1382 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1383 BUS_SPACE_MAXADDR, /* lowaddr */ 1384 BUS_SPACE_MAXADDR, /* highaddr */ 1385 NULL, NULL, /* filter, filterarg */ 1386 ALC_TX_RING_SZ, /* maxsize */ 1387 1, /* nsegments */ 1388 ALC_TX_RING_SZ, /* maxsegsize */ 1389 0, /* flags */ 1390 NULL, NULL, /* lockfunc, lockarg */ 1391 &sc->alc_cdata.alc_tx_ring_tag); 1392 if (error != 0) { 1393 device_printf(sc->alc_dev, 1394 "could not create Tx ring DMA tag.\n"); 1395 goto fail; 1396 } 1397 1398 /* Create DMA tag for Rx free descriptor ring. */ 1399 error = bus_dma_tag_create( 1400 sc->alc_cdata.alc_parent_tag, /* parent */ 1401 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1402 BUS_SPACE_MAXADDR, /* lowaddr */ 1403 BUS_SPACE_MAXADDR, /* highaddr */ 1404 NULL, NULL, /* filter, filterarg */ 1405 ALC_RX_RING_SZ, /* maxsize */ 1406 1, /* nsegments */ 1407 ALC_RX_RING_SZ, /* maxsegsize */ 1408 0, /* flags */ 1409 NULL, NULL, /* lockfunc, lockarg */ 1410 &sc->alc_cdata.alc_rx_ring_tag); 1411 if (error != 0) { 1412 device_printf(sc->alc_dev, 1413 "could not create Rx ring DMA tag.\n"); 1414 goto fail; 1415 } 1416 /* Create DMA tag for Rx return descriptor ring. */ 1417 error = bus_dma_tag_create( 1418 sc->alc_cdata.alc_parent_tag, /* parent */ 1419 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1420 BUS_SPACE_MAXADDR, /* lowaddr */ 1421 BUS_SPACE_MAXADDR, /* highaddr */ 1422 NULL, NULL, /* filter, filterarg */ 1423 ALC_RR_RING_SZ, /* maxsize */ 1424 1, /* nsegments */ 1425 ALC_RR_RING_SZ, /* maxsegsize */ 1426 0, /* flags */ 1427 NULL, NULL, /* lockfunc, lockarg */ 1428 &sc->alc_cdata.alc_rr_ring_tag); 1429 if (error != 0) { 1430 device_printf(sc->alc_dev, 1431 "could not create Rx return ring DMA tag.\n"); 1432 goto fail; 1433 } 1434 1435 /* Create DMA tag for coalescing message block. */ 1436 error = bus_dma_tag_create( 1437 sc->alc_cdata.alc_parent_tag, /* parent */ 1438 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1439 BUS_SPACE_MAXADDR, /* lowaddr */ 1440 BUS_SPACE_MAXADDR, /* highaddr */ 1441 NULL, NULL, /* filter, filterarg */ 1442 ALC_CMB_SZ, /* maxsize */ 1443 1, /* nsegments */ 1444 ALC_CMB_SZ, /* maxsegsize */ 1445 0, /* flags */ 1446 NULL, NULL, /* lockfunc, lockarg */ 1447 &sc->alc_cdata.alc_cmb_tag); 1448 if (error != 0) { 1449 device_printf(sc->alc_dev, 1450 "could not create CMB DMA tag.\n"); 1451 goto fail; 1452 } 1453 /* Create DMA tag for status message block. */ 1454 error = bus_dma_tag_create( 1455 sc->alc_cdata.alc_parent_tag, /* parent */ 1456 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1457 BUS_SPACE_MAXADDR, /* lowaddr */ 1458 BUS_SPACE_MAXADDR, /* highaddr */ 1459 NULL, NULL, /* filter, filterarg */ 1460 ALC_SMB_SZ, /* maxsize */ 1461 1, /* nsegments */ 1462 ALC_SMB_SZ, /* maxsegsize */ 1463 0, /* flags */ 1464 NULL, NULL, /* lockfunc, lockarg */ 1465 &sc->alc_cdata.alc_smb_tag); 1466 if (error != 0) { 1467 device_printf(sc->alc_dev, 1468 "could not create SMB DMA tag.\n"); 1469 goto fail; 1470 } 1471 1472 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1473 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1474 (void **)&sc->alc_rdata.alc_tx_ring, 1475 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1476 &sc->alc_cdata.alc_tx_ring_map); 1477 if (error != 0) { 1478 device_printf(sc->alc_dev, 1479 "could not allocate DMA'able memory for Tx ring.\n"); 1480 goto fail; 1481 } 1482 ctx.alc_busaddr = 0; 1483 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1484 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1485 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1486 if (error != 0 || ctx.alc_busaddr == 0) { 1487 device_printf(sc->alc_dev, 1488 "could not load DMA'able memory for Tx ring.\n"); 1489 goto fail; 1490 } 1491 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1492 1493 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1494 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1495 (void **)&sc->alc_rdata.alc_rx_ring, 1496 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1497 &sc->alc_cdata.alc_rx_ring_map); 1498 if (error != 0) { 1499 device_printf(sc->alc_dev, 1500 "could not allocate DMA'able memory for Rx ring.\n"); 1501 goto fail; 1502 } 1503 ctx.alc_busaddr = 0; 1504 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1505 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1506 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1507 if (error != 0 || ctx.alc_busaddr == 0) { 1508 device_printf(sc->alc_dev, 1509 "could not load DMA'able memory for Rx ring.\n"); 1510 goto fail; 1511 } 1512 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1513 1514 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1515 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1516 (void **)&sc->alc_rdata.alc_rr_ring, 1517 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1518 &sc->alc_cdata.alc_rr_ring_map); 1519 if (error != 0) { 1520 device_printf(sc->alc_dev, 1521 "could not allocate DMA'able memory for Rx return ring.\n"); 1522 goto fail; 1523 } 1524 ctx.alc_busaddr = 0; 1525 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1526 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1527 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1528 if (error != 0 || ctx.alc_busaddr == 0) { 1529 device_printf(sc->alc_dev, 1530 "could not load DMA'able memory for Tx ring.\n"); 1531 goto fail; 1532 } 1533 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1534 1535 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1536 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1537 (void **)&sc->alc_rdata.alc_cmb, 1538 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1539 &sc->alc_cdata.alc_cmb_map); 1540 if (error != 0) { 1541 device_printf(sc->alc_dev, 1542 "could not allocate DMA'able memory for CMB.\n"); 1543 goto fail; 1544 } 1545 ctx.alc_busaddr = 0; 1546 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1547 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1548 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1549 if (error != 0 || ctx.alc_busaddr == 0) { 1550 device_printf(sc->alc_dev, 1551 "could not load DMA'able memory for CMB.\n"); 1552 goto fail; 1553 } 1554 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1555 1556 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1557 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1558 (void **)&sc->alc_rdata.alc_smb, 1559 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1560 &sc->alc_cdata.alc_smb_map); 1561 if (error != 0) { 1562 device_printf(sc->alc_dev, 1563 "could not allocate DMA'able memory for SMB.\n"); 1564 goto fail; 1565 } 1566 ctx.alc_busaddr = 0; 1567 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1568 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1569 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1570 if (error != 0 || ctx.alc_busaddr == 0) { 1571 device_printf(sc->alc_dev, 1572 "could not load DMA'able memory for CMB.\n"); 1573 goto fail; 1574 } 1575 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1576 1577 /* Make sure we've not crossed 4GB boundary. */ 1578 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1579 (error = alc_check_boundary(sc)) != 0) { 1580 device_printf(sc->alc_dev, "4GB boundary crossed, " 1581 "switching to 32bit DMA addressing mode.\n"); 1582 alc_dma_free(sc); 1583 /* 1584 * Limit max allowable DMA address space to 32bit 1585 * and try again. 1586 */ 1587 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1588 goto again; 1589 } 1590 1591 /* 1592 * Create Tx buffer parent tag. 1593 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1594 * so it needs separate parent DMA tag as parent DMA address 1595 * space could be restricted to be within 32bit address space 1596 * by 4GB boundary crossing. 1597 */ 1598 error = bus_dma_tag_create( 1599 bus_get_dma_tag(sc->alc_dev), /* parent */ 1600 1, 0, /* alignment, boundary */ 1601 BUS_SPACE_MAXADDR, /* lowaddr */ 1602 BUS_SPACE_MAXADDR, /* highaddr */ 1603 NULL, NULL, /* filter, filterarg */ 1604 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1605 0, /* nsegments */ 1606 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1607 0, /* flags */ 1608 NULL, NULL, /* lockfunc, lockarg */ 1609 &sc->alc_cdata.alc_buffer_tag); 1610 if (error != 0) { 1611 device_printf(sc->alc_dev, 1612 "could not create parent buffer DMA tag.\n"); 1613 goto fail; 1614 } 1615 1616 /* Create DMA tag for Tx buffers. */ 1617 error = bus_dma_tag_create( 1618 sc->alc_cdata.alc_buffer_tag, /* parent */ 1619 1, 0, /* alignment, boundary */ 1620 BUS_SPACE_MAXADDR, /* lowaddr */ 1621 BUS_SPACE_MAXADDR, /* highaddr */ 1622 NULL, NULL, /* filter, filterarg */ 1623 ALC_TSO_MAXSIZE, /* maxsize */ 1624 ALC_MAXTXSEGS, /* nsegments */ 1625 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1626 0, /* flags */ 1627 NULL, NULL, /* lockfunc, lockarg */ 1628 &sc->alc_cdata.alc_tx_tag); 1629 if (error != 0) { 1630 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1631 goto fail; 1632 } 1633 1634 /* Create DMA tag for Rx buffers. */ 1635 error = bus_dma_tag_create( 1636 sc->alc_cdata.alc_buffer_tag, /* parent */ 1637 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1638 BUS_SPACE_MAXADDR, /* lowaddr */ 1639 BUS_SPACE_MAXADDR, /* highaddr */ 1640 NULL, NULL, /* filter, filterarg */ 1641 MCLBYTES, /* maxsize */ 1642 1, /* nsegments */ 1643 MCLBYTES, /* maxsegsize */ 1644 0, /* flags */ 1645 NULL, NULL, /* lockfunc, lockarg */ 1646 &sc->alc_cdata.alc_rx_tag); 1647 if (error != 0) { 1648 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1649 goto fail; 1650 } 1651 /* Create DMA maps for Tx buffers. */ 1652 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1653 txd = &sc->alc_cdata.alc_txdesc[i]; 1654 txd->tx_m = NULL; 1655 txd->tx_dmamap = NULL; 1656 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1657 &txd->tx_dmamap); 1658 if (error != 0) { 1659 device_printf(sc->alc_dev, 1660 "could not create Tx dmamap.\n"); 1661 goto fail; 1662 } 1663 } 1664 /* Create DMA maps for Rx buffers. */ 1665 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1666 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1667 device_printf(sc->alc_dev, 1668 "could not create spare Rx dmamap.\n"); 1669 goto fail; 1670 } 1671 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1672 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1673 rxd->rx_m = NULL; 1674 rxd->rx_dmamap = NULL; 1675 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1676 &rxd->rx_dmamap); 1677 if (error != 0) { 1678 device_printf(sc->alc_dev, 1679 "could not create Rx dmamap.\n"); 1680 goto fail; 1681 } 1682 } 1683 1684 fail: 1685 return (error); 1686 } 1687 1688 static void 1689 alc_dma_free(struct alc_softc *sc) 1690 { 1691 struct alc_txdesc *txd; 1692 struct alc_rxdesc *rxd; 1693 int i; 1694 1695 /* Tx buffers. */ 1696 if (sc->alc_cdata.alc_tx_tag != NULL) { 1697 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1698 txd = &sc->alc_cdata.alc_txdesc[i]; 1699 if (txd->tx_dmamap != NULL) { 1700 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1701 txd->tx_dmamap); 1702 txd->tx_dmamap = NULL; 1703 } 1704 } 1705 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1706 sc->alc_cdata.alc_tx_tag = NULL; 1707 } 1708 /* Rx buffers */ 1709 if (sc->alc_cdata.alc_rx_tag != NULL) { 1710 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1711 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1712 if (rxd->rx_dmamap != NULL) { 1713 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1714 rxd->rx_dmamap); 1715 rxd->rx_dmamap = NULL; 1716 } 1717 } 1718 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1719 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1720 sc->alc_cdata.alc_rx_sparemap); 1721 sc->alc_cdata.alc_rx_sparemap = NULL; 1722 } 1723 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1724 sc->alc_cdata.alc_rx_tag = NULL; 1725 } 1726 /* Tx descriptor ring. */ 1727 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1728 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1729 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1730 sc->alc_cdata.alc_tx_ring_map); 1731 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1732 sc->alc_rdata.alc_tx_ring != NULL) 1733 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1734 sc->alc_rdata.alc_tx_ring, 1735 sc->alc_cdata.alc_tx_ring_map); 1736 sc->alc_rdata.alc_tx_ring = NULL; 1737 sc->alc_cdata.alc_tx_ring_map = NULL; 1738 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1739 sc->alc_cdata.alc_tx_ring_tag = NULL; 1740 } 1741 /* Rx ring. */ 1742 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1743 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1744 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1745 sc->alc_cdata.alc_rx_ring_map); 1746 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1747 sc->alc_rdata.alc_rx_ring != NULL) 1748 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1749 sc->alc_rdata.alc_rx_ring, 1750 sc->alc_cdata.alc_rx_ring_map); 1751 sc->alc_rdata.alc_rx_ring = NULL; 1752 sc->alc_cdata.alc_rx_ring_map = NULL; 1753 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1754 sc->alc_cdata.alc_rx_ring_tag = NULL; 1755 } 1756 /* Rx return ring. */ 1757 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1758 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1759 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1760 sc->alc_cdata.alc_rr_ring_map); 1761 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1762 sc->alc_rdata.alc_rr_ring != NULL) 1763 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1764 sc->alc_rdata.alc_rr_ring, 1765 sc->alc_cdata.alc_rr_ring_map); 1766 sc->alc_rdata.alc_rr_ring = NULL; 1767 sc->alc_cdata.alc_rr_ring_map = NULL; 1768 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1769 sc->alc_cdata.alc_rr_ring_tag = NULL; 1770 } 1771 /* CMB block */ 1772 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1773 if (sc->alc_cdata.alc_cmb_map != NULL) 1774 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1775 sc->alc_cdata.alc_cmb_map); 1776 if (sc->alc_cdata.alc_cmb_map != NULL && 1777 sc->alc_rdata.alc_cmb != NULL) 1778 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1779 sc->alc_rdata.alc_cmb, 1780 sc->alc_cdata.alc_cmb_map); 1781 sc->alc_rdata.alc_cmb = NULL; 1782 sc->alc_cdata.alc_cmb_map = NULL; 1783 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1784 sc->alc_cdata.alc_cmb_tag = NULL; 1785 } 1786 /* SMB block */ 1787 if (sc->alc_cdata.alc_smb_tag != NULL) { 1788 if (sc->alc_cdata.alc_smb_map != NULL) 1789 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1790 sc->alc_cdata.alc_smb_map); 1791 if (sc->alc_cdata.alc_smb_map != NULL && 1792 sc->alc_rdata.alc_smb != NULL) 1793 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1794 sc->alc_rdata.alc_smb, 1795 sc->alc_cdata.alc_smb_map); 1796 sc->alc_rdata.alc_smb = NULL; 1797 sc->alc_cdata.alc_smb_map = NULL; 1798 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1799 sc->alc_cdata.alc_smb_tag = NULL; 1800 } 1801 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1802 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1803 sc->alc_cdata.alc_buffer_tag = NULL; 1804 } 1805 if (sc->alc_cdata.alc_parent_tag != NULL) { 1806 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1807 sc->alc_cdata.alc_parent_tag = NULL; 1808 } 1809 } 1810 1811 static int 1812 alc_shutdown(device_t dev) 1813 { 1814 1815 return (alc_suspend(dev)); 1816 } 1817 1818 /* 1819 * Note, this driver resets the link speed to 10/100Mbps by 1820 * restarting auto-negotiation in suspend/shutdown phase but we 1821 * don't know whether that auto-negotiation would succeed or not 1822 * as driver has no control after powering off/suspend operation. 1823 * If the renegotiation fail WOL may not work. Running at 1Gbps 1824 * will draw more power than 375mA at 3.3V which is specified in 1825 * PCI specification and that would result in complete 1826 * shutdowning power to ethernet controller. 1827 * 1828 * TODO 1829 * Save current negotiated media speed/duplex/flow-control to 1830 * softc and restore the same link again after resuming. PHY 1831 * handling such as power down/resetting to 100Mbps may be better 1832 * handled in suspend method in phy driver. 1833 */ 1834 static void 1835 alc_setlinkspeed(struct alc_softc *sc) 1836 { 1837 struct mii_data *mii; 1838 int aneg, i; 1839 1840 mii = device_get_softc(sc->alc_miibus); 1841 mii_pollstat(mii); 1842 aneg = 0; 1843 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1844 (IFM_ACTIVE | IFM_AVALID)) { 1845 switch IFM_SUBTYPE(mii->mii_media_active) { 1846 case IFM_10_T: 1847 case IFM_100_TX: 1848 return; 1849 case IFM_1000_T: 1850 aneg++; 1851 break; 1852 default: 1853 break; 1854 } 1855 } 1856 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1857 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1858 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1859 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1860 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1861 DELAY(1000); 1862 if (aneg != 0) { 1863 /* 1864 * Poll link state until alc(4) get a 10/100Mbps link. 1865 */ 1866 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1867 mii_pollstat(mii); 1868 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1869 == (IFM_ACTIVE | IFM_AVALID)) { 1870 switch (IFM_SUBTYPE( 1871 mii->mii_media_active)) { 1872 case IFM_10_T: 1873 case IFM_100_TX: 1874 alc_mac_config(sc); 1875 return; 1876 default: 1877 break; 1878 } 1879 } 1880 ALC_UNLOCK(sc); 1881 pause("alclnk", hz); 1882 ALC_LOCK(sc); 1883 } 1884 if (i == MII_ANEGTICKS_GIGE) 1885 device_printf(sc->alc_dev, 1886 "establishing a link failed, WOL may not work!"); 1887 } 1888 /* 1889 * No link, force MAC to have 100Mbps, full-duplex link. 1890 * This is the last resort and may/may not work. 1891 */ 1892 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1893 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1894 alc_mac_config(sc); 1895 } 1896 1897 static void 1898 alc_setwol(struct alc_softc *sc) 1899 { 1900 struct ifnet *ifp; 1901 uint32_t reg, pmcs; 1902 uint16_t pmstat; 1903 1904 ALC_LOCK_ASSERT(sc); 1905 1906 alc_disable_l0s_l1(sc); 1907 ifp = sc->alc_ifp; 1908 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1909 /* Disable WOL. */ 1910 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1911 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1912 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1913 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1914 /* Force PHY power down. */ 1915 alc_phy_down(sc); 1916 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1917 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1918 return; 1919 } 1920 1921 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1922 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1923 alc_setlinkspeed(sc); 1924 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1925 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1926 } 1927 1928 pmcs = 0; 1929 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1930 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1931 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1932 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1933 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1934 MAC_CFG_BCAST); 1935 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1936 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1937 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1938 reg |= MAC_CFG_RX_ENB; 1939 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1940 1941 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1942 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1943 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1944 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1945 /* WOL disabled, PHY power down. */ 1946 alc_phy_down(sc); 1947 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1948 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1949 } 1950 /* Request PME. */ 1951 pmstat = pci_read_config(sc->alc_dev, 1952 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1953 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1954 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1955 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1956 pci_write_config(sc->alc_dev, 1957 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1958 } 1959 1960 static int 1961 alc_suspend(device_t dev) 1962 { 1963 struct alc_softc *sc; 1964 1965 sc = device_get_softc(dev); 1966 1967 ALC_LOCK(sc); 1968 alc_stop(sc); 1969 alc_setwol(sc); 1970 ALC_UNLOCK(sc); 1971 1972 return (0); 1973 } 1974 1975 static int 1976 alc_resume(device_t dev) 1977 { 1978 struct alc_softc *sc; 1979 struct ifnet *ifp; 1980 uint16_t pmstat; 1981 1982 sc = device_get_softc(dev); 1983 1984 ALC_LOCK(sc); 1985 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1986 /* Disable PME and clear PME status. */ 1987 pmstat = pci_read_config(sc->alc_dev, 1988 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1989 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1990 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1991 pci_write_config(sc->alc_dev, 1992 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1993 } 1994 } 1995 /* Reset PHY. */ 1996 alc_phy_reset(sc); 1997 ifp = sc->alc_ifp; 1998 if ((ifp->if_flags & IFF_UP) != 0) { 1999 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2000 alc_init_locked(sc); 2001 } 2002 ALC_UNLOCK(sc); 2003 2004 return (0); 2005 } 2006 2007 static int 2008 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2009 { 2010 struct alc_txdesc *txd, *txd_last; 2011 struct tx_desc *desc; 2012 struct mbuf *m; 2013 struct ip *ip; 2014 struct tcphdr *tcp; 2015 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2016 bus_dmamap_t map; 2017 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2018 int error, idx, nsegs, prod; 2019 2020 ALC_LOCK_ASSERT(sc); 2021 2022 M_ASSERTPKTHDR((*m_head)); 2023 2024 m = *m_head; 2025 ip = NULL; 2026 tcp = NULL; 2027 ip_off = poff = 0; 2028 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2029 /* 2030 * AR813x/AR815x requires offset of TCP/UDP header in its 2031 * Tx descriptor to perform Tx checksum offloading. TSO 2032 * also requires TCP header offset and modification of 2033 * IP/TCP header. This kind of operation takes many CPU 2034 * cycles on FreeBSD so fast host CPU is required to get 2035 * smooth TSO performance. 2036 */ 2037 struct ether_header *eh; 2038 2039 if (M_WRITABLE(m) == 0) { 2040 /* Get a writable copy. */ 2041 m = m_dup(*m_head, M_DONTWAIT); 2042 /* Release original mbufs. */ 2043 m_freem(*m_head); 2044 if (m == NULL) { 2045 *m_head = NULL; 2046 return (ENOBUFS); 2047 } 2048 *m_head = m; 2049 } 2050 2051 ip_off = sizeof(struct ether_header); 2052 m = m_pullup(m, ip_off); 2053 if (m == NULL) { 2054 *m_head = NULL; 2055 return (ENOBUFS); 2056 } 2057 eh = mtod(m, struct ether_header *); 2058 /* 2059 * Check if hardware VLAN insertion is off. 2060 * Additional check for LLC/SNAP frame? 2061 */ 2062 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2063 ip_off = sizeof(struct ether_vlan_header); 2064 m = m_pullup(m, ip_off); 2065 if (m == NULL) { 2066 *m_head = NULL; 2067 return (ENOBUFS); 2068 } 2069 } 2070 m = m_pullup(m, ip_off + sizeof(struct ip)); 2071 if (m == NULL) { 2072 *m_head = NULL; 2073 return (ENOBUFS); 2074 } 2075 ip = (struct ip *)(mtod(m, char *) + ip_off); 2076 poff = ip_off + (ip->ip_hl << 2); 2077 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2078 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2079 if (m == NULL) { 2080 *m_head = NULL; 2081 return (ENOBUFS); 2082 } 2083 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2084 m = m_pullup(m, poff + (tcp->th_off << 2)); 2085 if (m == NULL) { 2086 *m_head = NULL; 2087 return (ENOBUFS); 2088 } 2089 /* 2090 * Due to strict adherence of Microsoft NDIS 2091 * Large Send specification, hardware expects 2092 * a pseudo TCP checksum inserted by upper 2093 * stack. Unfortunately the pseudo TCP 2094 * checksum that NDIS refers to does not include 2095 * TCP payload length so driver should recompute 2096 * the pseudo checksum here. Hopefully this 2097 * wouldn't be much burden on modern CPUs. 2098 * 2099 * Reset IP checksum and recompute TCP pseudo 2100 * checksum as NDIS specification said. 2101 */ 2102 ip = (struct ip *)(mtod(m, char *) + ip_off); 2103 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2104 ip->ip_sum = 0; 2105 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2106 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2107 } 2108 *m_head = m; 2109 } 2110 2111 prod = sc->alc_cdata.alc_tx_prod; 2112 txd = &sc->alc_cdata.alc_txdesc[prod]; 2113 txd_last = txd; 2114 map = txd->tx_dmamap; 2115 2116 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2117 *m_head, txsegs, &nsegs, 0); 2118 if (error == EFBIG) { 2119 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 2120 if (m == NULL) { 2121 m_freem(*m_head); 2122 *m_head = NULL; 2123 return (ENOMEM); 2124 } 2125 *m_head = m; 2126 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2127 *m_head, txsegs, &nsegs, 0); 2128 if (error != 0) { 2129 m_freem(*m_head); 2130 *m_head = NULL; 2131 return (error); 2132 } 2133 } else if (error != 0) 2134 return (error); 2135 if (nsegs == 0) { 2136 m_freem(*m_head); 2137 *m_head = NULL; 2138 return (EIO); 2139 } 2140 2141 /* Check descriptor overrun. */ 2142 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2143 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2144 return (ENOBUFS); 2145 } 2146 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2147 2148 m = *m_head; 2149 cflags = TD_ETHERNET; 2150 vtag = 0; 2151 desc = NULL; 2152 idx = 0; 2153 /* Configure VLAN hardware tag insertion. */ 2154 if ((m->m_flags & M_VLANTAG) != 0) { 2155 vtag = htons(m->m_pkthdr.ether_vtag); 2156 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2157 cflags |= TD_INS_VLAN_TAG; 2158 } 2159 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2160 /* Request TSO and set MSS. */ 2161 cflags |= TD_TSO | TD_TSO_DESCV1; 2162 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2163 TD_MSS_MASK; 2164 /* Set TCP header offset. */ 2165 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2166 TD_TCPHDR_OFFSET_MASK; 2167 /* 2168 * AR813x/AR815x requires the first buffer should 2169 * only hold IP/TCP header data. Payload should 2170 * be handled in other descriptors. 2171 */ 2172 hdrlen = poff + (tcp->th_off << 2); 2173 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2174 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2175 desc->flags = htole32(cflags); 2176 desc->addr = htole64(txsegs[0].ds_addr); 2177 sc->alc_cdata.alc_tx_cnt++; 2178 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2179 if (m->m_len - hdrlen > 0) { 2180 /* Handle remaining payload of the first fragment. */ 2181 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2182 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2183 vtag)); 2184 desc->flags = htole32(cflags); 2185 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2186 sc->alc_cdata.alc_tx_cnt++; 2187 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2188 } 2189 /* Handle remaining fragments. */ 2190 idx = 1; 2191 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2192 /* Configure Tx checksum offload. */ 2193 #ifdef ALC_USE_CUSTOM_CSUM 2194 cflags |= TD_CUSTOM_CSUM; 2195 /* Set checksum start offset. */ 2196 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2197 TD_PLOAD_OFFSET_MASK; 2198 /* Set checksum insertion position of TCP/UDP. */ 2199 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2200 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2201 #else 2202 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2203 cflags |= TD_IPCSUM; 2204 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2205 cflags |= TD_TCPCSUM; 2206 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2207 cflags |= TD_UDPCSUM; 2208 /* Set TCP/UDP header offset. */ 2209 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2210 TD_L4HDR_OFFSET_MASK; 2211 #endif 2212 } 2213 for (; idx < nsegs; idx++) { 2214 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2215 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2216 desc->flags = htole32(cflags); 2217 desc->addr = htole64(txsegs[idx].ds_addr); 2218 sc->alc_cdata.alc_tx_cnt++; 2219 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2220 } 2221 /* Update producer index. */ 2222 sc->alc_cdata.alc_tx_prod = prod; 2223 2224 /* Finally set EOP on the last descriptor. */ 2225 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2226 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2227 desc->flags |= htole32(TD_EOP); 2228 2229 /* Swap dmamap of the first and the last. */ 2230 txd = &sc->alc_cdata.alc_txdesc[prod]; 2231 map = txd_last->tx_dmamap; 2232 txd_last->tx_dmamap = txd->tx_dmamap; 2233 txd->tx_dmamap = map; 2234 txd->tx_m = m; 2235 2236 return (0); 2237 } 2238 2239 static void 2240 alc_tx_task(void *arg, int pending) 2241 { 2242 struct ifnet *ifp; 2243 2244 ifp = (struct ifnet *)arg; 2245 alc_start(ifp); 2246 } 2247 2248 static void 2249 alc_start(struct ifnet *ifp) 2250 { 2251 struct alc_softc *sc; 2252 struct mbuf *m_head; 2253 int enq; 2254 2255 sc = ifp->if_softc; 2256 2257 ALC_LOCK(sc); 2258 2259 /* Reclaim transmitted frames. */ 2260 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2261 alc_txeof(sc); 2262 2263 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2264 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2265 ALC_UNLOCK(sc); 2266 return; 2267 } 2268 2269 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2270 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2271 if (m_head == NULL) 2272 break; 2273 /* 2274 * Pack the data into the transmit ring. If we 2275 * don't have room, set the OACTIVE flag and wait 2276 * for the NIC to drain the ring. 2277 */ 2278 if (alc_encap(sc, &m_head)) { 2279 if (m_head == NULL) 2280 break; 2281 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2282 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2283 break; 2284 } 2285 2286 enq++; 2287 /* 2288 * If there's a BPF listener, bounce a copy of this frame 2289 * to him. 2290 */ 2291 ETHER_BPF_MTAP(ifp, m_head); 2292 } 2293 2294 if (enq > 0) { 2295 /* Sync descriptors. */ 2296 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2297 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2298 /* Kick. Assume we're using normal Tx priority queue. */ 2299 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2300 (sc->alc_cdata.alc_tx_prod << 2301 MBOX_TD_PROD_LO_IDX_SHIFT) & 2302 MBOX_TD_PROD_LO_IDX_MASK); 2303 /* Set a timeout in case the chip goes out to lunch. */ 2304 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2305 } 2306 2307 ALC_UNLOCK(sc); 2308 } 2309 2310 static void 2311 alc_watchdog(struct alc_softc *sc) 2312 { 2313 struct ifnet *ifp; 2314 2315 ALC_LOCK_ASSERT(sc); 2316 2317 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2318 return; 2319 2320 ifp = sc->alc_ifp; 2321 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2322 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2323 ifp->if_oerrors++; 2324 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2325 alc_init_locked(sc); 2326 return; 2327 } 2328 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2329 ifp->if_oerrors++; 2330 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2331 alc_init_locked(sc); 2332 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2333 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2334 } 2335 2336 static int 2337 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2338 { 2339 struct alc_softc *sc; 2340 struct ifreq *ifr; 2341 struct mii_data *mii; 2342 int error, mask; 2343 2344 sc = ifp->if_softc; 2345 ifr = (struct ifreq *)data; 2346 error = 0; 2347 switch (cmd) { 2348 case SIOCSIFMTU: 2349 if (ifr->ifr_mtu < ETHERMIN || 2350 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2351 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2352 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2353 ifr->ifr_mtu > ETHERMTU)) 2354 error = EINVAL; 2355 else if (ifp->if_mtu != ifr->ifr_mtu) { 2356 ALC_LOCK(sc); 2357 ifp->if_mtu = ifr->ifr_mtu; 2358 /* AR813x/AR815x has 13 bits MSS field. */ 2359 if (ifp->if_mtu > ALC_TSO_MTU && 2360 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2361 ifp->if_capenable &= ~IFCAP_TSO4; 2362 ifp->if_hwassist &= ~CSUM_TSO; 2363 VLAN_CAPABILITIES(ifp); 2364 } 2365 ALC_UNLOCK(sc); 2366 } 2367 break; 2368 case SIOCSIFFLAGS: 2369 ALC_LOCK(sc); 2370 if ((ifp->if_flags & IFF_UP) != 0) { 2371 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2372 ((ifp->if_flags ^ sc->alc_if_flags) & 2373 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2374 alc_rxfilter(sc); 2375 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2376 alc_init_locked(sc); 2377 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2378 alc_stop(sc); 2379 sc->alc_if_flags = ifp->if_flags; 2380 ALC_UNLOCK(sc); 2381 break; 2382 case SIOCADDMULTI: 2383 case SIOCDELMULTI: 2384 ALC_LOCK(sc); 2385 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2386 alc_rxfilter(sc); 2387 ALC_UNLOCK(sc); 2388 break; 2389 case SIOCSIFMEDIA: 2390 case SIOCGIFMEDIA: 2391 mii = device_get_softc(sc->alc_miibus); 2392 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2393 break; 2394 case SIOCSIFCAP: 2395 ALC_LOCK(sc); 2396 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2397 if ((mask & IFCAP_TXCSUM) != 0 && 2398 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2399 ifp->if_capenable ^= IFCAP_TXCSUM; 2400 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2401 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2402 else 2403 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2404 } 2405 if ((mask & IFCAP_TSO4) != 0 && 2406 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2407 ifp->if_capenable ^= IFCAP_TSO4; 2408 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2409 /* AR813x/AR815x has 13 bits MSS field. */ 2410 if (ifp->if_mtu > ALC_TSO_MTU) { 2411 ifp->if_capenable &= ~IFCAP_TSO4; 2412 ifp->if_hwassist &= ~CSUM_TSO; 2413 } else 2414 ifp->if_hwassist |= CSUM_TSO; 2415 } else 2416 ifp->if_hwassist &= ~CSUM_TSO; 2417 } 2418 if ((mask & IFCAP_WOL_MCAST) != 0 && 2419 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2420 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2421 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2422 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2423 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2424 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2425 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2426 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2427 alc_rxvlan(sc); 2428 } 2429 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2430 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2431 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2432 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2433 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2434 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2435 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2436 ifp->if_capenable &= 2437 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2438 ALC_UNLOCK(sc); 2439 VLAN_CAPABILITIES(ifp); 2440 break; 2441 default: 2442 error = ether_ioctl(ifp, cmd, data); 2443 break; 2444 } 2445 2446 return (error); 2447 } 2448 2449 static void 2450 alc_mac_config(struct alc_softc *sc) 2451 { 2452 struct mii_data *mii; 2453 uint32_t reg; 2454 2455 ALC_LOCK_ASSERT(sc); 2456 2457 mii = device_get_softc(sc->alc_miibus); 2458 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2459 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2460 MAC_CFG_SPEED_MASK); 2461 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2462 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2463 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2464 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2465 /* Reprogram MAC with resolved speed/duplex. */ 2466 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2467 case IFM_10_T: 2468 case IFM_100_TX: 2469 reg |= MAC_CFG_SPEED_10_100; 2470 break; 2471 case IFM_1000_T: 2472 reg |= MAC_CFG_SPEED_1000; 2473 break; 2474 } 2475 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2476 reg |= MAC_CFG_FULL_DUPLEX; 2477 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2478 reg |= MAC_CFG_TX_FC; 2479 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2480 reg |= MAC_CFG_RX_FC; 2481 } 2482 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2483 } 2484 2485 static void 2486 alc_stats_clear(struct alc_softc *sc) 2487 { 2488 struct smb sb, *smb; 2489 uint32_t *reg; 2490 int i; 2491 2492 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2493 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2494 sc->alc_cdata.alc_smb_map, 2495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2496 smb = sc->alc_rdata.alc_smb; 2497 /* Update done, clear. */ 2498 smb->updated = 0; 2499 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2500 sc->alc_cdata.alc_smb_map, 2501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2502 } else { 2503 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2504 reg++) { 2505 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2506 i += sizeof(uint32_t); 2507 } 2508 /* Read Tx statistics. */ 2509 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2510 reg++) { 2511 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2512 i += sizeof(uint32_t); 2513 } 2514 } 2515 } 2516 2517 static void 2518 alc_stats_update(struct alc_softc *sc) 2519 { 2520 struct alc_hw_stats *stat; 2521 struct smb sb, *smb; 2522 struct ifnet *ifp; 2523 uint32_t *reg; 2524 int i; 2525 2526 ALC_LOCK_ASSERT(sc); 2527 2528 ifp = sc->alc_ifp; 2529 stat = &sc->alc_stats; 2530 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2531 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2532 sc->alc_cdata.alc_smb_map, 2533 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2534 smb = sc->alc_rdata.alc_smb; 2535 if (smb->updated == 0) 2536 return; 2537 } else { 2538 smb = &sb; 2539 /* Read Rx statistics. */ 2540 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2541 reg++) { 2542 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2543 i += sizeof(uint32_t); 2544 } 2545 /* Read Tx statistics. */ 2546 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2547 reg++) { 2548 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2549 i += sizeof(uint32_t); 2550 } 2551 } 2552 2553 /* Rx stats. */ 2554 stat->rx_frames += smb->rx_frames; 2555 stat->rx_bcast_frames += smb->rx_bcast_frames; 2556 stat->rx_mcast_frames += smb->rx_mcast_frames; 2557 stat->rx_pause_frames += smb->rx_pause_frames; 2558 stat->rx_control_frames += smb->rx_control_frames; 2559 stat->rx_crcerrs += smb->rx_crcerrs; 2560 stat->rx_lenerrs += smb->rx_lenerrs; 2561 stat->rx_bytes += smb->rx_bytes; 2562 stat->rx_runts += smb->rx_runts; 2563 stat->rx_fragments += smb->rx_fragments; 2564 stat->rx_pkts_64 += smb->rx_pkts_64; 2565 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2566 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2567 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2568 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2569 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2570 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2571 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2572 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2573 stat->rx_rrs_errs += smb->rx_rrs_errs; 2574 stat->rx_alignerrs += smb->rx_alignerrs; 2575 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2576 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2577 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2578 2579 /* Tx stats. */ 2580 stat->tx_frames += smb->tx_frames; 2581 stat->tx_bcast_frames += smb->tx_bcast_frames; 2582 stat->tx_mcast_frames += smb->tx_mcast_frames; 2583 stat->tx_pause_frames += smb->tx_pause_frames; 2584 stat->tx_excess_defer += smb->tx_excess_defer; 2585 stat->tx_control_frames += smb->tx_control_frames; 2586 stat->tx_deferred += smb->tx_deferred; 2587 stat->tx_bytes += smb->tx_bytes; 2588 stat->tx_pkts_64 += smb->tx_pkts_64; 2589 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2590 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2591 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2592 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2593 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2594 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2595 stat->tx_single_colls += smb->tx_single_colls; 2596 stat->tx_multi_colls += smb->tx_multi_colls; 2597 stat->tx_late_colls += smb->tx_late_colls; 2598 stat->tx_excess_colls += smb->tx_excess_colls; 2599 stat->tx_abort += smb->tx_abort; 2600 stat->tx_underrun += smb->tx_underrun; 2601 stat->tx_desc_underrun += smb->tx_desc_underrun; 2602 stat->tx_lenerrs += smb->tx_lenerrs; 2603 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2604 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2605 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2606 2607 /* Update counters in ifnet. */ 2608 ifp->if_opackets += smb->tx_frames; 2609 2610 ifp->if_collisions += smb->tx_single_colls + 2611 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2612 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2613 2614 /* 2615 * XXX 2616 * tx_pkts_truncated counter looks suspicious. It constantly 2617 * increments with no sign of Tx errors. This may indicate 2618 * the counter name is not correct one so I've removed the 2619 * counter in output errors. 2620 */ 2621 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2622 smb->tx_underrun; 2623 2624 ifp->if_ipackets += smb->rx_frames; 2625 2626 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2627 smb->rx_runts + smb->rx_pkts_truncated + 2628 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2629 smb->rx_alignerrs; 2630 2631 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2632 /* Update done, clear. */ 2633 smb->updated = 0; 2634 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2635 sc->alc_cdata.alc_smb_map, 2636 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2637 } 2638 } 2639 2640 static int 2641 alc_intr(void *arg) 2642 { 2643 struct alc_softc *sc; 2644 uint32_t status; 2645 2646 sc = (struct alc_softc *)arg; 2647 2648 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2649 if ((status & ALC_INTRS) == 0) 2650 return (FILTER_STRAY); 2651 /* Disable interrupts. */ 2652 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2653 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2654 2655 return (FILTER_HANDLED); 2656 } 2657 2658 static void 2659 alc_int_task(void *arg, int pending) 2660 { 2661 struct alc_softc *sc; 2662 struct ifnet *ifp; 2663 uint32_t status; 2664 int more; 2665 2666 sc = (struct alc_softc *)arg; 2667 ifp = sc->alc_ifp; 2668 2669 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2670 if (sc->alc_morework != 0) { 2671 sc->alc_morework = 0; 2672 status |= INTR_RX_PKT; 2673 } 2674 if ((status & ALC_INTRS) == 0) 2675 goto done; 2676 2677 /* Acknowledge interrupts but still disable interrupts. */ 2678 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2679 2680 more = 0; 2681 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2682 if ((status & INTR_RX_PKT) != 0) { 2683 more = alc_rxintr(sc, sc->alc_process_limit); 2684 if (more == EAGAIN) 2685 sc->alc_morework = 1; 2686 else if (more == EIO) { 2687 ALC_LOCK(sc); 2688 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2689 alc_init_locked(sc); 2690 ALC_UNLOCK(sc); 2691 return; 2692 } 2693 } 2694 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2695 INTR_TXQ_TO_RST)) != 0) { 2696 if ((status & INTR_DMA_RD_TO_RST) != 0) 2697 device_printf(sc->alc_dev, 2698 "DMA read error! -- resetting\n"); 2699 if ((status & INTR_DMA_WR_TO_RST) != 0) 2700 device_printf(sc->alc_dev, 2701 "DMA write error! -- resetting\n"); 2702 if ((status & INTR_TXQ_TO_RST) != 0) 2703 device_printf(sc->alc_dev, 2704 "TxQ reset! -- resetting\n"); 2705 ALC_LOCK(sc); 2706 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2707 alc_init_locked(sc); 2708 ALC_UNLOCK(sc); 2709 return; 2710 } 2711 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2712 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2713 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2714 } 2715 2716 if (more == EAGAIN || 2717 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2718 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2719 return; 2720 } 2721 2722 done: 2723 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2724 /* Re-enable interrupts if we're running. */ 2725 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2726 } 2727 } 2728 2729 static void 2730 alc_txeof(struct alc_softc *sc) 2731 { 2732 struct ifnet *ifp; 2733 struct alc_txdesc *txd; 2734 uint32_t cons, prod; 2735 int prog; 2736 2737 ALC_LOCK_ASSERT(sc); 2738 2739 ifp = sc->alc_ifp; 2740 2741 if (sc->alc_cdata.alc_tx_cnt == 0) 2742 return; 2743 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2744 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2745 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2746 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2747 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2748 prod = sc->alc_rdata.alc_cmb->cons; 2749 } else 2750 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2751 /* Assume we're using normal Tx priority queue. */ 2752 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2753 MBOX_TD_CONS_LO_IDX_SHIFT; 2754 cons = sc->alc_cdata.alc_tx_cons; 2755 /* 2756 * Go through our Tx list and free mbufs for those 2757 * frames which have been transmitted. 2758 */ 2759 for (prog = 0; cons != prod; prog++, 2760 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2761 if (sc->alc_cdata.alc_tx_cnt <= 0) 2762 break; 2763 prog++; 2764 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2765 sc->alc_cdata.alc_tx_cnt--; 2766 txd = &sc->alc_cdata.alc_txdesc[cons]; 2767 if (txd->tx_m != NULL) { 2768 /* Reclaim transmitted mbufs. */ 2769 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2770 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2771 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2772 txd->tx_dmamap); 2773 m_freem(txd->tx_m); 2774 txd->tx_m = NULL; 2775 } 2776 } 2777 2778 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2779 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2780 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2781 sc->alc_cdata.alc_tx_cons = cons; 2782 /* 2783 * Unarm watchdog timer only when there is no pending 2784 * frames in Tx queue. 2785 */ 2786 if (sc->alc_cdata.alc_tx_cnt == 0) 2787 sc->alc_watchdog_timer = 0; 2788 } 2789 2790 static int 2791 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2792 { 2793 struct mbuf *m; 2794 bus_dma_segment_t segs[1]; 2795 bus_dmamap_t map; 2796 int nsegs; 2797 2798 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2799 if (m == NULL) 2800 return (ENOBUFS); 2801 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2802 #ifndef __NO_STRICT_ALIGNMENT 2803 m_adj(m, sizeof(uint64_t)); 2804 #endif 2805 2806 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2807 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2808 m_freem(m); 2809 return (ENOBUFS); 2810 } 2811 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2812 2813 if (rxd->rx_m != NULL) { 2814 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2815 BUS_DMASYNC_POSTREAD); 2816 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2817 } 2818 map = rxd->rx_dmamap; 2819 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2820 sc->alc_cdata.alc_rx_sparemap = map; 2821 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2822 BUS_DMASYNC_PREREAD); 2823 rxd->rx_m = m; 2824 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2825 return (0); 2826 } 2827 2828 static int 2829 alc_rxintr(struct alc_softc *sc, int count) 2830 { 2831 struct ifnet *ifp; 2832 struct rx_rdesc *rrd; 2833 uint32_t nsegs, status; 2834 int rr_cons, prog; 2835 2836 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2837 sc->alc_cdata.alc_rr_ring_map, 2838 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2839 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2840 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2841 rr_cons = sc->alc_cdata.alc_rr_cons; 2842 ifp = sc->alc_ifp; 2843 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2844 if (count-- <= 0) 2845 break; 2846 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2847 status = le32toh(rrd->status); 2848 if ((status & RRD_VALID) == 0) 2849 break; 2850 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2851 if (nsegs == 0) { 2852 /* This should not happen! */ 2853 device_printf(sc->alc_dev, 2854 "unexpected segment count -- resetting\n"); 2855 return (EIO); 2856 } 2857 alc_rxeof(sc, rrd); 2858 /* Clear Rx return status. */ 2859 rrd->status = 0; 2860 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2861 sc->alc_cdata.alc_rx_cons += nsegs; 2862 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2863 prog += nsegs; 2864 } 2865 2866 if (prog > 0) { 2867 /* Update the consumer index. */ 2868 sc->alc_cdata.alc_rr_cons = rr_cons; 2869 /* Sync Rx return descriptors. */ 2870 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2871 sc->alc_cdata.alc_rr_ring_map, 2872 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2873 /* 2874 * Sync updated Rx descriptors such that controller see 2875 * modified buffer addresses. 2876 */ 2877 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2878 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2879 /* 2880 * Let controller know availability of new Rx buffers. 2881 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2882 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2883 * only when Rx buffer pre-fetching is required. In 2884 * addition we already set ALC_RX_RD_FREE_THRESH to 2885 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2886 * it still seems that pre-fetching needs more 2887 * experimentation. 2888 */ 2889 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2890 sc->alc_cdata.alc_rx_cons); 2891 } 2892 2893 return (count > 0 ? 0 : EAGAIN); 2894 } 2895 2896 #ifndef __NO_STRICT_ALIGNMENT 2897 static struct mbuf * 2898 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2899 { 2900 struct mbuf *n; 2901 int i; 2902 uint16_t *src, *dst; 2903 2904 src = mtod(m, uint16_t *); 2905 dst = src - 3; 2906 2907 if (m->m_next == NULL) { 2908 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2909 *dst++ = *src++; 2910 m->m_data -= 6; 2911 return (m); 2912 } 2913 /* 2914 * Append a new mbuf to received mbuf chain and copy ethernet 2915 * header from the mbuf chain. This can save lots of CPU 2916 * cycles for jumbo frame. 2917 */ 2918 MGETHDR(n, M_DONTWAIT, MT_DATA); 2919 if (n == NULL) { 2920 ifp->if_iqdrops++; 2921 m_freem(m); 2922 return (NULL); 2923 } 2924 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2925 m->m_data += ETHER_HDR_LEN; 2926 m->m_len -= ETHER_HDR_LEN; 2927 n->m_len = ETHER_HDR_LEN; 2928 M_MOVE_PKTHDR(n, m); 2929 n->m_next = m; 2930 return (n); 2931 } 2932 #endif 2933 2934 /* Receive a frame. */ 2935 static void 2936 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2937 { 2938 struct alc_rxdesc *rxd; 2939 struct ifnet *ifp; 2940 struct mbuf *mp, *m; 2941 uint32_t rdinfo, status, vtag; 2942 int count, nsegs, rx_cons; 2943 2944 ifp = sc->alc_ifp; 2945 status = le32toh(rrd->status); 2946 rdinfo = le32toh(rrd->rdinfo); 2947 rx_cons = RRD_RD_IDX(rdinfo); 2948 nsegs = RRD_RD_CNT(rdinfo); 2949 2950 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2951 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2952 /* 2953 * We want to pass the following frames to upper 2954 * layer regardless of error status of Rx return 2955 * ring. 2956 * 2957 * o IP/TCP/UDP checksum is bad. 2958 * o frame length and protocol specific length 2959 * does not match. 2960 * 2961 * Force network stack compute checksum for 2962 * errored frames. 2963 */ 2964 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2965 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2966 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2967 return; 2968 } 2969 2970 for (count = 0; count < nsegs; count++, 2971 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2972 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2973 mp = rxd->rx_m; 2974 /* Add a new receive buffer to the ring. */ 2975 if (alc_newbuf(sc, rxd) != 0) { 2976 ifp->if_iqdrops++; 2977 /* Reuse Rx buffers. */ 2978 if (sc->alc_cdata.alc_rxhead != NULL) 2979 m_freem(sc->alc_cdata.alc_rxhead); 2980 break; 2981 } 2982 2983 /* 2984 * Assume we've received a full sized frame. 2985 * Actual size is fixed when we encounter the end of 2986 * multi-segmented frame. 2987 */ 2988 mp->m_len = sc->alc_buf_size; 2989 2990 /* Chain received mbufs. */ 2991 if (sc->alc_cdata.alc_rxhead == NULL) { 2992 sc->alc_cdata.alc_rxhead = mp; 2993 sc->alc_cdata.alc_rxtail = mp; 2994 } else { 2995 mp->m_flags &= ~M_PKTHDR; 2996 sc->alc_cdata.alc_rxprev_tail = 2997 sc->alc_cdata.alc_rxtail; 2998 sc->alc_cdata.alc_rxtail->m_next = mp; 2999 sc->alc_cdata.alc_rxtail = mp; 3000 } 3001 3002 if (count == nsegs - 1) { 3003 /* Last desc. for this frame. */ 3004 m = sc->alc_cdata.alc_rxhead; 3005 m->m_flags |= M_PKTHDR; 3006 /* 3007 * It seems that L1C/L2C controller has no way 3008 * to tell hardware to strip CRC bytes. 3009 */ 3010 m->m_pkthdr.len = 3011 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3012 if (nsegs > 1) { 3013 /* Set last mbuf size. */ 3014 mp->m_len = sc->alc_cdata.alc_rxlen - 3015 (nsegs - 1) * sc->alc_buf_size; 3016 /* Remove the CRC bytes in chained mbufs. */ 3017 if (mp->m_len <= ETHER_CRC_LEN) { 3018 sc->alc_cdata.alc_rxtail = 3019 sc->alc_cdata.alc_rxprev_tail; 3020 sc->alc_cdata.alc_rxtail->m_len -= 3021 (ETHER_CRC_LEN - mp->m_len); 3022 sc->alc_cdata.alc_rxtail->m_next = NULL; 3023 m_freem(mp); 3024 } else { 3025 mp->m_len -= ETHER_CRC_LEN; 3026 } 3027 } else 3028 m->m_len = m->m_pkthdr.len; 3029 m->m_pkthdr.rcvif = ifp; 3030 /* 3031 * Due to hardware bugs, Rx checksum offloading 3032 * was intentionally disabled. 3033 */ 3034 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3035 (status & RRD_VLAN_TAG) != 0) { 3036 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3037 m->m_pkthdr.ether_vtag = ntohs(vtag); 3038 m->m_flags |= M_VLANTAG; 3039 } 3040 #ifndef __NO_STRICT_ALIGNMENT 3041 m = alc_fixup_rx(ifp, m); 3042 if (m != NULL) 3043 #endif 3044 { 3045 /* Pass it on. */ 3046 (*ifp->if_input)(ifp, m); 3047 } 3048 } 3049 } 3050 /* Reset mbuf chains. */ 3051 ALC_RXCHAIN_RESET(sc); 3052 } 3053 3054 static void 3055 alc_tick(void *arg) 3056 { 3057 struct alc_softc *sc; 3058 struct mii_data *mii; 3059 3060 sc = (struct alc_softc *)arg; 3061 3062 ALC_LOCK_ASSERT(sc); 3063 3064 mii = device_get_softc(sc->alc_miibus); 3065 mii_tick(mii); 3066 alc_stats_update(sc); 3067 /* 3068 * alc(4) does not rely on Tx completion interrupts to reclaim 3069 * transferred buffers. Instead Tx completion interrupts are 3070 * used to hint for scheduling Tx task. So it's necessary to 3071 * release transmitted buffers by kicking Tx completion 3072 * handler. This limits the maximum reclamation delay to a hz. 3073 */ 3074 alc_txeof(sc); 3075 alc_watchdog(sc); 3076 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3077 } 3078 3079 static void 3080 alc_reset(struct alc_softc *sc) 3081 { 3082 uint32_t reg; 3083 int i; 3084 3085 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3086 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3087 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3088 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3089 DELAY(10); 3090 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3091 break; 3092 } 3093 if (i == 0) 3094 device_printf(sc->alc_dev, "master reset timeout!\n"); 3095 3096 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3097 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3098 break; 3099 DELAY(10); 3100 } 3101 3102 if (i == 0) 3103 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3104 } 3105 3106 static void 3107 alc_init(void *xsc) 3108 { 3109 struct alc_softc *sc; 3110 3111 sc = (struct alc_softc *)xsc; 3112 ALC_LOCK(sc); 3113 alc_init_locked(sc); 3114 ALC_UNLOCK(sc); 3115 } 3116 3117 static void 3118 alc_init_locked(struct alc_softc *sc) 3119 { 3120 struct ifnet *ifp; 3121 struct mii_data *mii; 3122 uint8_t eaddr[ETHER_ADDR_LEN]; 3123 bus_addr_t paddr; 3124 uint32_t reg, rxf_hi, rxf_lo; 3125 3126 ALC_LOCK_ASSERT(sc); 3127 3128 ifp = sc->alc_ifp; 3129 mii = device_get_softc(sc->alc_miibus); 3130 3131 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3132 return; 3133 /* 3134 * Cancel any pending I/O. 3135 */ 3136 alc_stop(sc); 3137 /* 3138 * Reset the chip to a known state. 3139 */ 3140 alc_reset(sc); 3141 3142 /* Initialize Rx descriptors. */ 3143 if (alc_init_rx_ring(sc) != 0) { 3144 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3145 alc_stop(sc); 3146 return; 3147 } 3148 alc_init_rr_ring(sc); 3149 alc_init_tx_ring(sc); 3150 alc_init_cmb(sc); 3151 alc_init_smb(sc); 3152 3153 /* Reprogram the station address. */ 3154 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3155 CSR_WRITE_4(sc, ALC_PAR0, 3156 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3157 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3158 /* 3159 * Clear WOL status and disable all WOL feature as WOL 3160 * would interfere Rx operation under normal environments. 3161 */ 3162 CSR_READ_4(sc, ALC_WOL_CFG); 3163 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3164 /* Set Tx descriptor base addresses. */ 3165 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3166 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3167 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3168 /* We don't use high priority ring. */ 3169 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3170 /* Set Tx descriptor counter. */ 3171 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3172 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3173 /* Set Rx descriptor base addresses. */ 3174 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3175 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3176 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3177 /* We use one Rx ring. */ 3178 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3179 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3180 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3181 /* Set Rx descriptor counter. */ 3182 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3183 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3184 3185 /* 3186 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3187 * if it do not fit the buffer size. Rx return descriptor holds 3188 * a counter that indicates how many fragments were made by the 3189 * hardware. The buffer size should be multiple of 8 bytes. 3190 * Since hardware has limit on the size of buffer size, always 3191 * use the maximum value. 3192 * For strict-alignment architectures make sure to reduce buffer 3193 * size by 8 bytes to make room for alignment fixup. 3194 */ 3195 #ifndef __NO_STRICT_ALIGNMENT 3196 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3197 #else 3198 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3199 #endif 3200 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3201 3202 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3203 /* Set Rx return descriptor base addresses. */ 3204 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3205 /* We use one Rx return ring. */ 3206 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3207 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3208 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3209 /* Set Rx return descriptor counter. */ 3210 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3211 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3212 paddr = sc->alc_rdata.alc_cmb_paddr; 3213 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3214 paddr = sc->alc_rdata.alc_smb_paddr; 3215 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3216 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3217 3218 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3219 /* Reconfigure SRAM - Vendor magic. */ 3220 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3221 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3222 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3223 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3224 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3225 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3226 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3227 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3228 } 3229 3230 /* Tell hardware that we're ready to load DMA blocks. */ 3231 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3232 3233 /* Configure interrupt moderation timer. */ 3234 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3235 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3236 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3237 /* 3238 * We don't want to automatic interrupt clear as task queue 3239 * for the interrupt should know interrupt status. 3240 */ 3241 reg = MASTER_SA_TIMER_ENB; 3242 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3243 reg |= MASTER_IM_RX_TIMER_ENB; 3244 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3245 reg |= MASTER_IM_TX_TIMER_ENB; 3246 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3247 /* 3248 * Disable interrupt re-trigger timer. We don't want automatic 3249 * re-triggering of un-ACKed interrupts. 3250 */ 3251 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3252 /* Configure CMB. */ 3253 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3254 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3255 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3256 } else 3257 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3258 /* 3259 * Hardware can be configured to issue SMB interrupt based 3260 * on programmed interval. Since there is a callout that is 3261 * invoked for every hz in driver we use that instead of 3262 * relying on periodic SMB interrupt. 3263 */ 3264 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3265 /* Clear MAC statistics. */ 3266 alc_stats_clear(sc); 3267 3268 /* 3269 * Always use maximum frame size that controller can support. 3270 * Otherwise received frames that has larger frame length 3271 * than alc(4) MTU would be silently dropped in hardware. This 3272 * would make path-MTU discovery hard as sender wouldn't get 3273 * any responses from receiver. alc(4) supports 3274 * multi-fragmented frames on Rx path so it has no issue on 3275 * assembling fragmented frames. Using maximum frame size also 3276 * removes the need to reinitialize hardware when interface 3277 * MTU configuration was changed. 3278 * 3279 * Be conservative in what you do, be liberal in what you 3280 * accept from others - RFC 793. 3281 */ 3282 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3283 3284 /* Disable header split(?) */ 3285 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3286 3287 /* Configure IPG/IFG parameters. */ 3288 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3289 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3290 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3291 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3292 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3293 /* Set parameters for half-duplex media. */ 3294 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3295 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3296 HDPX_CFG_LCOL_MASK) | 3297 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3298 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3299 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3300 HDPX_CFG_ABEBT_MASK) | 3301 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3302 HDPX_CFG_JAMIPG_MASK)); 3303 /* 3304 * Set TSO/checksum offload threshold. For frames that is 3305 * larger than this threshold, hardware wouldn't do 3306 * TSO/checksum offloading. 3307 */ 3308 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3309 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3310 TSO_OFFLOAD_THRESH_MASK); 3311 /* Configure TxQ. */ 3312 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3313 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3314 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3315 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3316 reg >>= 1; 3317 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3318 TXQ_CFG_TD_BURST_MASK; 3319 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3320 3321 /* Configure Rx free descriptor pre-fetching. */ 3322 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3323 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3324 RX_RD_FREE_THRESH_HI_MASK) | 3325 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3326 RX_RD_FREE_THRESH_LO_MASK)); 3327 3328 /* 3329 * Configure flow control parameters. 3330 * XON : 80% of Rx FIFO 3331 * XOFF : 30% of Rx FIFO 3332 */ 3333 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3334 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3335 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3336 rxf_hi = (reg * 8) / 10; 3337 rxf_lo = (reg * 3) / 10; 3338 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3339 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3340 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3341 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3342 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3343 } 3344 3345 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3346 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3347 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3348 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3349 SERDES_PHY_CLK_SLOWDOWN); 3350 3351 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3352 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3353 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3354 3355 /* Configure RxQ. */ 3356 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3357 RXQ_CFG_RD_BURST_MASK; 3358 reg |= RXQ_CFG_RSS_MODE_DIS; 3359 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3360 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3361 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3362 3363 /* Configure DMA parameters. */ 3364 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3365 reg |= sc->alc_rcb; 3366 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3367 reg |= DMA_CFG_CMB_ENB; 3368 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3369 reg |= DMA_CFG_SMB_ENB; 3370 else 3371 reg |= DMA_CFG_SMB_DIS; 3372 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3373 DMA_CFG_RD_BURST_SHIFT; 3374 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3375 DMA_CFG_WR_BURST_SHIFT; 3376 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3377 DMA_CFG_RD_DELAY_CNT_MASK; 3378 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3379 DMA_CFG_WR_DELAY_CNT_MASK; 3380 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3381 3382 /* 3383 * Configure Tx/Rx MACs. 3384 * - Auto-padding for short frames. 3385 * - Enable CRC generation. 3386 * Actual reconfiguration of MAC for resolved speed/duplex 3387 * is followed after detection of link establishment. 3388 * AR813x/AR815x always does checksum computation regardless 3389 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3390 * have bug in protocol field in Rx return structure so 3391 * these controllers can't handle fragmented frames. Disable 3392 * Rx checksum offloading until there is a newer controller 3393 * that has sane implementation. 3394 */ 3395 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3396 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3397 MAC_CFG_PREAMBLE_MASK); 3398 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3399 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3400 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3401 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3402 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3403 reg |= MAC_CFG_SPEED_10_100; 3404 else 3405 reg |= MAC_CFG_SPEED_1000; 3406 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3407 3408 /* Set up the receive filter. */ 3409 alc_rxfilter(sc); 3410 alc_rxvlan(sc); 3411 3412 /* Acknowledge all pending interrupts and clear it. */ 3413 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3414 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3415 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3416 3417 sc->alc_flags &= ~ALC_FLAG_LINK; 3418 /* Switch to the current media. */ 3419 mii_mediachg(mii); 3420 3421 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3422 3423 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3424 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3425 } 3426 3427 static void 3428 alc_stop(struct alc_softc *sc) 3429 { 3430 struct ifnet *ifp; 3431 struct alc_txdesc *txd; 3432 struct alc_rxdesc *rxd; 3433 uint32_t reg; 3434 int i; 3435 3436 ALC_LOCK_ASSERT(sc); 3437 /* 3438 * Mark the interface down and cancel the watchdog timer. 3439 */ 3440 ifp = sc->alc_ifp; 3441 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3442 sc->alc_flags &= ~ALC_FLAG_LINK; 3443 callout_stop(&sc->alc_tick_ch); 3444 sc->alc_watchdog_timer = 0; 3445 alc_stats_update(sc); 3446 /* Disable interrupts. */ 3447 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3448 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3449 alc_stop_queue(sc); 3450 /* Disable DMA. */ 3451 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3452 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3453 reg |= DMA_CFG_SMB_DIS; 3454 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3455 DELAY(1000); 3456 /* Stop Rx/Tx MACs. */ 3457 alc_stop_mac(sc); 3458 /* Disable interrupts which might be touched in taskq handler. */ 3459 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3460 3461 /* Reclaim Rx buffers that have been processed. */ 3462 if (sc->alc_cdata.alc_rxhead != NULL) 3463 m_freem(sc->alc_cdata.alc_rxhead); 3464 ALC_RXCHAIN_RESET(sc); 3465 /* 3466 * Free Tx/Rx mbufs still in the queues. 3467 */ 3468 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3469 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3470 if (rxd->rx_m != NULL) { 3471 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3472 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3473 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3474 rxd->rx_dmamap); 3475 m_freem(rxd->rx_m); 3476 rxd->rx_m = NULL; 3477 } 3478 } 3479 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3480 txd = &sc->alc_cdata.alc_txdesc[i]; 3481 if (txd->tx_m != NULL) { 3482 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3483 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3484 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3485 txd->tx_dmamap); 3486 m_freem(txd->tx_m); 3487 txd->tx_m = NULL; 3488 } 3489 } 3490 } 3491 3492 static void 3493 alc_stop_mac(struct alc_softc *sc) 3494 { 3495 uint32_t reg; 3496 int i; 3497 3498 ALC_LOCK_ASSERT(sc); 3499 3500 /* Disable Rx/Tx MAC. */ 3501 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3502 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3503 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3504 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3505 } 3506 for (i = ALC_TIMEOUT; i > 0; i--) { 3507 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3508 if (reg == 0) 3509 break; 3510 DELAY(10); 3511 } 3512 if (i == 0) 3513 device_printf(sc->alc_dev, 3514 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3515 } 3516 3517 static void 3518 alc_start_queue(struct alc_softc *sc) 3519 { 3520 uint32_t qcfg[] = { 3521 0, 3522 RXQ_CFG_QUEUE0_ENB, 3523 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3524 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3525 RXQ_CFG_ENB 3526 }; 3527 uint32_t cfg; 3528 3529 ALC_LOCK_ASSERT(sc); 3530 3531 /* Enable RxQ. */ 3532 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3533 cfg &= ~RXQ_CFG_ENB; 3534 cfg |= qcfg[1]; 3535 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3536 /* Enable TxQ. */ 3537 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3538 cfg |= TXQ_CFG_ENB; 3539 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3540 } 3541 3542 static void 3543 alc_stop_queue(struct alc_softc *sc) 3544 { 3545 uint32_t reg; 3546 int i; 3547 3548 ALC_LOCK_ASSERT(sc); 3549 3550 /* Disable RxQ. */ 3551 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3552 if ((reg & RXQ_CFG_ENB) != 0) { 3553 reg &= ~RXQ_CFG_ENB; 3554 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3555 } 3556 /* Disable TxQ. */ 3557 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3558 if ((reg & TXQ_CFG_ENB) == 0) { 3559 reg &= ~TXQ_CFG_ENB; 3560 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3561 } 3562 for (i = ALC_TIMEOUT; i > 0; i--) { 3563 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3564 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3565 break; 3566 DELAY(10); 3567 } 3568 if (i == 0) 3569 device_printf(sc->alc_dev, 3570 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3571 } 3572 3573 static void 3574 alc_init_tx_ring(struct alc_softc *sc) 3575 { 3576 struct alc_ring_data *rd; 3577 struct alc_txdesc *txd; 3578 int i; 3579 3580 ALC_LOCK_ASSERT(sc); 3581 3582 sc->alc_cdata.alc_tx_prod = 0; 3583 sc->alc_cdata.alc_tx_cons = 0; 3584 sc->alc_cdata.alc_tx_cnt = 0; 3585 3586 rd = &sc->alc_rdata; 3587 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3588 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3589 txd = &sc->alc_cdata.alc_txdesc[i]; 3590 txd->tx_m = NULL; 3591 } 3592 3593 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3594 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3595 } 3596 3597 static int 3598 alc_init_rx_ring(struct alc_softc *sc) 3599 { 3600 struct alc_ring_data *rd; 3601 struct alc_rxdesc *rxd; 3602 int i; 3603 3604 ALC_LOCK_ASSERT(sc); 3605 3606 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3607 sc->alc_morework = 0; 3608 rd = &sc->alc_rdata; 3609 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3610 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3611 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3612 rxd->rx_m = NULL; 3613 rxd->rx_desc = &rd->alc_rx_ring[i]; 3614 if (alc_newbuf(sc, rxd) != 0) 3615 return (ENOBUFS); 3616 } 3617 3618 /* 3619 * Since controller does not update Rx descriptors, driver 3620 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3621 * is enough to ensure coherence. 3622 */ 3623 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3624 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3625 /* Let controller know availability of new Rx buffers. */ 3626 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3627 3628 return (0); 3629 } 3630 3631 static void 3632 alc_init_rr_ring(struct alc_softc *sc) 3633 { 3634 struct alc_ring_data *rd; 3635 3636 ALC_LOCK_ASSERT(sc); 3637 3638 sc->alc_cdata.alc_rr_cons = 0; 3639 ALC_RXCHAIN_RESET(sc); 3640 3641 rd = &sc->alc_rdata; 3642 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3643 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3644 sc->alc_cdata.alc_rr_ring_map, 3645 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3646 } 3647 3648 static void 3649 alc_init_cmb(struct alc_softc *sc) 3650 { 3651 struct alc_ring_data *rd; 3652 3653 ALC_LOCK_ASSERT(sc); 3654 3655 rd = &sc->alc_rdata; 3656 bzero(rd->alc_cmb, ALC_CMB_SZ); 3657 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3659 } 3660 3661 static void 3662 alc_init_smb(struct alc_softc *sc) 3663 { 3664 struct alc_ring_data *rd; 3665 3666 ALC_LOCK_ASSERT(sc); 3667 3668 rd = &sc->alc_rdata; 3669 bzero(rd->alc_smb, ALC_SMB_SZ); 3670 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3672 } 3673 3674 static void 3675 alc_rxvlan(struct alc_softc *sc) 3676 { 3677 struct ifnet *ifp; 3678 uint32_t reg; 3679 3680 ALC_LOCK_ASSERT(sc); 3681 3682 ifp = sc->alc_ifp; 3683 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3684 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3685 reg |= MAC_CFG_VLAN_TAG_STRIP; 3686 else 3687 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3688 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3689 } 3690 3691 static void 3692 alc_rxfilter(struct alc_softc *sc) 3693 { 3694 struct ifnet *ifp; 3695 struct ifmultiaddr *ifma; 3696 uint32_t crc; 3697 uint32_t mchash[2]; 3698 uint32_t rxcfg; 3699 3700 ALC_LOCK_ASSERT(sc); 3701 3702 ifp = sc->alc_ifp; 3703 3704 bzero(mchash, sizeof(mchash)); 3705 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3706 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3707 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3708 rxcfg |= MAC_CFG_BCAST; 3709 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3710 if ((ifp->if_flags & IFF_PROMISC) != 0) 3711 rxcfg |= MAC_CFG_PROMISC; 3712 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3713 rxcfg |= MAC_CFG_ALLMULTI; 3714 mchash[0] = 0xFFFFFFFF; 3715 mchash[1] = 0xFFFFFFFF; 3716 goto chipit; 3717 } 3718 3719 if_maddr_rlock(ifp); 3720 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3721 if (ifma->ifma_addr->sa_family != AF_LINK) 3722 continue; 3723 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3724 ifma->ifma_addr), ETHER_ADDR_LEN); 3725 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3726 } 3727 if_maddr_runlock(ifp); 3728 3729 chipit: 3730 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3731 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3732 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3733 } 3734 3735 static int 3736 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3737 { 3738 int error, value; 3739 3740 if (arg1 == NULL) 3741 return (EINVAL); 3742 value = *(int *)arg1; 3743 error = sysctl_handle_int(oidp, &value, 0, req); 3744 if (error || req->newptr == NULL) 3745 return (error); 3746 if (value < low || value > high) 3747 return (EINVAL); 3748 *(int *)arg1 = value; 3749 3750 return (0); 3751 } 3752 3753 static int 3754 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3755 { 3756 return (sysctl_int_range(oidp, arg1, arg2, req, 3757 ALC_PROC_MIN, ALC_PROC_MAX)); 3758 } 3759 3760 static int 3761 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3762 { 3763 3764 return (sysctl_int_range(oidp, arg1, arg2, req, 3765 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3766 } 3767