1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/debugnet.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/alc/if_alcreg.h> 76 #include <dev/alc/if_alcvar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 #undef ALC_USE_CUSTOM_CSUM 81 82 #ifdef ALC_USE_CUSTOM_CSUM 83 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84 #else 85 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 #endif 87 88 MODULE_DEPEND(alc, pci, 1, 1, 1); 89 MODULE_DEPEND(alc, ether, 1, 1, 1); 90 MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92 /* Tunables. */ 93 static int msi_disable = 0; 94 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95 96 /* 97 * The default value of msix_disable is 2, which means to decide whether to 98 * enable MSI-X in alc_attach() depending on the card type. The operator can 99 * set this to 0 or 1 to override the default. 100 */ 101 static int msix_disable = 2; 102 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 103 104 /* 105 * Devices supported by this driver. 106 */ 107 static struct alc_ident alc_ident_table[] = { 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 109 "Atheros AR8131 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 111 "Atheros AR8132 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 117 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 121 "Atheros AR8161 PCIe Gigabit Ethernet" }, 122 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 123 "Atheros AR8162 PCIe Fast Ethernet" }, 124 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 125 "Atheros AR8171 PCIe Gigabit Ethernet" }, 126 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 127 "Atheros AR8172 PCIe Fast Ethernet" }, 128 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 129 "Killer E2200 Gigabit Ethernet" }, 130 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 131 "Killer E2400 Gigabit Ethernet" }, 132 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 133 "Killer E2500 Gigabit Ethernet" }, 134 { 0, 0, 0, NULL} 135 }; 136 137 static void alc_aspm(struct alc_softc *, int, int); 138 static void alc_aspm_813x(struct alc_softc *, int); 139 static void alc_aspm_816x(struct alc_softc *, int); 140 static int alc_attach(device_t); 141 static int alc_check_boundary(struct alc_softc *); 142 static void alc_config_msi(struct alc_softc *); 143 static int alc_detach(device_t); 144 static void alc_disable_l0s_l1(struct alc_softc *); 145 static int alc_dma_alloc(struct alc_softc *); 146 static void alc_dma_free(struct alc_softc *); 147 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 148 static void alc_dsp_fixup(struct alc_softc *, int); 149 static int alc_encap(struct alc_softc *, struct mbuf **); 150 static struct alc_ident * 151 alc_find_ident(device_t); 152 #ifndef __NO_STRICT_ALIGNMENT 153 static struct mbuf * 154 alc_fixup_rx(if_t, struct mbuf *); 155 #endif 156 static void alc_get_macaddr(struct alc_softc *); 157 static void alc_get_macaddr_813x(struct alc_softc *); 158 static void alc_get_macaddr_816x(struct alc_softc *); 159 static void alc_get_macaddr_par(struct alc_softc *); 160 static void alc_init(void *); 161 static void alc_init_cmb(struct alc_softc *); 162 static void alc_init_locked(struct alc_softc *); 163 static void alc_init_rr_ring(struct alc_softc *); 164 static int alc_init_rx_ring(struct alc_softc *); 165 static void alc_init_smb(struct alc_softc *); 166 static void alc_init_tx_ring(struct alc_softc *); 167 static void alc_int_task(void *, int); 168 static int alc_intr(void *); 169 static int alc_ioctl(if_t, u_long, caddr_t); 170 static void alc_mac_config(struct alc_softc *); 171 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 172 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 173 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 174 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 175 static int alc_miibus_readreg(device_t, int, int); 176 static void alc_miibus_statchg(device_t); 177 static int alc_miibus_writereg(device_t, int, int, int); 178 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 179 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 180 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 181 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 182 static int alc_mediachange(if_t); 183 static int alc_mediachange_locked(struct alc_softc *); 184 static void alc_mediastatus(if_t, struct ifmediareq *); 185 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 186 static void alc_osc_reset(struct alc_softc *); 187 static void alc_phy_down(struct alc_softc *); 188 static void alc_phy_reset(struct alc_softc *); 189 static void alc_phy_reset_813x(struct alc_softc *); 190 static void alc_phy_reset_816x(struct alc_softc *); 191 static int alc_probe(device_t); 192 static void alc_reset(struct alc_softc *); 193 static int alc_resume(device_t); 194 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 195 static int alc_rxintr(struct alc_softc *, int); 196 static void alc_rxfilter(struct alc_softc *); 197 static void alc_rxvlan(struct alc_softc *); 198 static void alc_setlinkspeed(struct alc_softc *); 199 static void alc_setwol(struct alc_softc *); 200 static void alc_setwol_813x(struct alc_softc *); 201 static void alc_setwol_816x(struct alc_softc *); 202 static int alc_shutdown(device_t); 203 static void alc_start(if_t); 204 static void alc_start_locked(if_t); 205 static void alc_start_queue(struct alc_softc *); 206 static void alc_start_tx(struct alc_softc *); 207 static void alc_stats_clear(struct alc_softc *); 208 static void alc_stats_update(struct alc_softc *); 209 static void alc_stop(struct alc_softc *); 210 static void alc_stop_mac(struct alc_softc *); 211 static void alc_stop_queue(struct alc_softc *); 212 static int alc_suspend(device_t); 213 static void alc_sysctl_node(struct alc_softc *); 214 static void alc_tick(void *); 215 static void alc_txeof(struct alc_softc *); 216 static void alc_watchdog(struct alc_softc *); 217 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 218 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 219 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 220 221 DEBUGNET_DEFINE(alc); 222 223 static device_method_t alc_methods[] = { 224 /* Device interface. */ 225 DEVMETHOD(device_probe, alc_probe), 226 DEVMETHOD(device_attach, alc_attach), 227 DEVMETHOD(device_detach, alc_detach), 228 DEVMETHOD(device_shutdown, alc_shutdown), 229 DEVMETHOD(device_suspend, alc_suspend), 230 DEVMETHOD(device_resume, alc_resume), 231 232 /* MII interface. */ 233 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 234 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 235 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 236 237 DEVMETHOD_END 238 }; 239 240 static driver_t alc_driver = { 241 "alc", 242 alc_methods, 243 sizeof(struct alc_softc) 244 }; 245 246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0); 247 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 248 nitems(alc_ident_table) - 1); 249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0); 250 251 static struct resource_spec alc_res_spec_mem[] = { 252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 253 { -1, 0, 0 } 254 }; 255 256 static struct resource_spec alc_irq_spec_legacy[] = { 257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 258 { -1, 0, 0 } 259 }; 260 261 static struct resource_spec alc_irq_spec_msi[] = { 262 { SYS_RES_IRQ, 1, RF_ACTIVE }, 263 { -1, 0, 0 } 264 }; 265 266 static struct resource_spec alc_irq_spec_msix[] = { 267 { SYS_RES_IRQ, 1, RF_ACTIVE }, 268 { -1, 0, 0 } 269 }; 270 271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 272 273 static int 274 alc_miibus_readreg(device_t dev, int phy, int reg) 275 { 276 struct alc_softc *sc; 277 int v; 278 279 sc = device_get_softc(dev); 280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 281 v = alc_mii_readreg_816x(sc, phy, reg); 282 else 283 v = alc_mii_readreg_813x(sc, phy, reg); 284 return (v); 285 } 286 287 static uint32_t 288 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 289 { 290 uint32_t v; 291 int i; 292 293 /* 294 * For AR8132 fast ethernet controller, do not report 1000baseT 295 * capability to mii(4). Even though AR8132 uses the same 296 * model/revision number of F1 gigabit PHY, the PHY has no 297 * ability to establish 1000baseT link. 298 */ 299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 300 reg == MII_EXTSR) 301 return (0); 302 303 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 304 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 306 DELAY(5); 307 v = CSR_READ_4(sc, ALC_MDIO); 308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 309 break; 310 } 311 312 if (i == 0) { 313 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 314 return (0); 315 } 316 317 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 318 } 319 320 static uint32_t 321 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 322 { 323 uint32_t clk, v; 324 int i; 325 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 327 clk = MDIO_CLK_25_128; 328 else 329 clk = MDIO_CLK_25_4; 330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 331 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 333 DELAY(5); 334 v = CSR_READ_4(sc, ALC_MDIO); 335 if ((v & MDIO_OP_BUSY) == 0) 336 break; 337 } 338 339 if (i == 0) { 340 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 341 return (0); 342 } 343 344 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 345 } 346 347 static int 348 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 349 { 350 struct alc_softc *sc; 351 int v; 352 353 sc = device_get_softc(dev); 354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 355 v = alc_mii_writereg_816x(sc, phy, reg, val); 356 else 357 v = alc_mii_writereg_813x(sc, phy, reg, val); 358 return (v); 359 } 360 361 static uint32_t 362 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 363 { 364 uint32_t v; 365 int i; 366 367 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 368 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 369 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 v = CSR_READ_4(sc, ALC_MDIO); 373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 374 break; 375 } 376 377 if (i == 0) 378 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 379 380 return (0); 381 } 382 383 static uint32_t 384 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 385 { 386 uint32_t clk, v; 387 int i; 388 389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 390 clk = MDIO_CLK_25_128; 391 else 392 clk = MDIO_CLK_25_4; 393 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 394 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 395 MDIO_SUP_PREAMBLE | clk); 396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 397 DELAY(5); 398 v = CSR_READ_4(sc, ALC_MDIO); 399 if ((v & MDIO_OP_BUSY) == 0) 400 break; 401 } 402 403 if (i == 0) 404 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 405 406 return (0); 407 } 408 409 static void 410 alc_miibus_statchg(device_t dev) 411 { 412 struct alc_softc *sc; 413 struct mii_data *mii; 414 if_t ifp; 415 uint32_t reg; 416 417 sc = device_get_softc(dev); 418 419 mii = device_get_softc(sc->alc_miibus); 420 ifp = sc->alc_ifp; 421 if (mii == NULL || ifp == NULL || 422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 423 return; 424 425 sc->alc_flags &= ~ALC_FLAG_LINK; 426 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 427 (IFM_ACTIVE | IFM_AVALID)) { 428 switch (IFM_SUBTYPE(mii->mii_media_active)) { 429 case IFM_10_T: 430 case IFM_100_TX: 431 sc->alc_flags |= ALC_FLAG_LINK; 432 break; 433 case IFM_1000_T: 434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 435 sc->alc_flags |= ALC_FLAG_LINK; 436 break; 437 default: 438 break; 439 } 440 } 441 /* Stop Rx/Tx MACs. */ 442 alc_stop_mac(sc); 443 444 /* Program MACs with resolved speed/duplex/flow-control. */ 445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 446 alc_start_queue(sc); 447 alc_mac_config(sc); 448 /* Re-enable Tx/Rx MACs. */ 449 reg = CSR_READ_4(sc, ALC_MAC_CFG); 450 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 451 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 452 } 453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 454 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 455 } 456 457 static uint32_t 458 alc_miidbg_readreg(struct alc_softc *sc, int reg) 459 { 460 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 462 reg); 463 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA)); 465 } 466 467 static uint32_t 468 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 469 { 470 471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 472 reg); 473 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 474 ALC_MII_DBG_DATA, val)); 475 } 476 477 static uint32_t 478 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 479 { 480 uint32_t clk, v; 481 int i; 482 483 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 484 EXT_MDIO_DEVADDR(devaddr)); 485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 486 clk = MDIO_CLK_25_128; 487 else 488 clk = MDIO_CLK_25_4; 489 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 490 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 492 DELAY(5); 493 v = CSR_READ_4(sc, ALC_MDIO); 494 if ((v & MDIO_OP_BUSY) == 0) 495 break; 496 } 497 498 if (i == 0) { 499 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 500 devaddr, reg); 501 return (0); 502 } 503 504 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 505 } 506 507 static uint32_t 508 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 509 { 510 uint32_t clk, v; 511 int i; 512 513 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 514 EXT_MDIO_DEVADDR(devaddr)); 515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 516 clk = MDIO_CLK_25_128; 517 else 518 clk = MDIO_CLK_25_4; 519 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 520 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 521 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 523 DELAY(5); 524 v = CSR_READ_4(sc, ALC_MDIO); 525 if ((v & MDIO_OP_BUSY) == 0) 526 break; 527 } 528 529 if (i == 0) 530 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 531 devaddr, reg); 532 533 return (0); 534 } 535 536 static void 537 alc_dsp_fixup(struct alc_softc *sc, int media) 538 { 539 uint16_t agc, len, val; 540 541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 542 return; 543 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 544 return; 545 546 /* 547 * Vendor PHY magic. 548 * 1000BT/AZ, wrong cable length 549 */ 550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 551 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 552 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 553 EXT_CLDCTL6_CAB_LEN_MASK; 554 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 555 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 556 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 557 agc > DBG_AGC_LONG1G_LIMT) || 558 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 559 agc > DBG_AGC_LONG1G_LIMT)) { 560 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 561 DBG_AZ_ANADECT_LONG); 562 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 563 MII_EXT_ANEG_AFE); 564 val |= ANEG_AFEE_10BT_100M_TH; 565 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 566 val); 567 } else { 568 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 569 DBG_AZ_ANADECT_DEFAULT); 570 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 571 MII_EXT_ANEG_AFE); 572 val &= ~ANEG_AFEE_10BT_100M_TH; 573 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 574 val); 575 } 576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 577 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 578 if (media == IFM_1000_T) { 579 /* 580 * Giga link threshold, raise the tolerance of 581 * noise 50%. 582 */ 583 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 584 val &= ~DBG_MSE20DB_TH_MASK; 585 val |= (DBG_MSE20DB_TH_HI << 586 DBG_MSE20DB_TH_SHIFT); 587 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 588 } else if (media == IFM_100_TX) 589 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 590 DBG_MSE16DB_UP); 591 } 592 } else { 593 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 594 val &= ~ANEG_AFEE_10BT_100M_TH; 595 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 597 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 598 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 599 DBG_MSE16DB_DOWN); 600 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 601 val &= ~DBG_MSE20DB_TH_MASK; 602 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 603 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 604 } 605 } 606 } 607 608 static void 609 alc_mediastatus(if_t ifp, struct ifmediareq *ifmr) 610 { 611 struct alc_softc *sc; 612 struct mii_data *mii; 613 614 sc = if_getsoftc(ifp); 615 ALC_LOCK(sc); 616 if ((if_getflags(ifp) & IFF_UP) == 0) { 617 ALC_UNLOCK(sc); 618 return; 619 } 620 mii = device_get_softc(sc->alc_miibus); 621 622 mii_pollstat(mii); 623 ifmr->ifm_status = mii->mii_media_status; 624 ifmr->ifm_active = mii->mii_media_active; 625 ALC_UNLOCK(sc); 626 } 627 628 static int 629 alc_mediachange(if_t ifp) 630 { 631 struct alc_softc *sc; 632 int error; 633 634 sc = if_getsoftc(ifp); 635 ALC_LOCK(sc); 636 error = alc_mediachange_locked(sc); 637 ALC_UNLOCK(sc); 638 639 return (error); 640 } 641 642 static int 643 alc_mediachange_locked(struct alc_softc *sc) 644 { 645 struct mii_data *mii; 646 struct mii_softc *miisc; 647 int error; 648 649 ALC_LOCK_ASSERT(sc); 650 651 mii = device_get_softc(sc->alc_miibus); 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 PHY_RESET(miisc); 654 error = mii_mediachg(mii); 655 656 return (error); 657 } 658 659 static struct alc_ident * 660 alc_find_ident(device_t dev) 661 { 662 struct alc_ident *ident; 663 uint16_t vendor, devid; 664 665 vendor = pci_get_vendor(dev); 666 devid = pci_get_device(dev); 667 for (ident = alc_ident_table; ident->name != NULL; ident++) { 668 if (vendor == ident->vendorid && devid == ident->deviceid) 669 return (ident); 670 } 671 672 return (NULL); 673 } 674 675 static int 676 alc_probe(device_t dev) 677 { 678 struct alc_ident *ident; 679 680 ident = alc_find_ident(dev); 681 if (ident != NULL) { 682 device_set_desc(dev, ident->name); 683 return (BUS_PROBE_DEFAULT); 684 } 685 686 return (ENXIO); 687 } 688 689 static void 690 alc_get_macaddr(struct alc_softc *sc) 691 { 692 693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 694 alc_get_macaddr_816x(sc); 695 else 696 alc_get_macaddr_813x(sc); 697 } 698 699 static void 700 alc_get_macaddr_813x(struct alc_softc *sc) 701 { 702 uint32_t opt; 703 uint16_t val; 704 int eeprom, i; 705 706 eeprom = 0; 707 opt = CSR_READ_4(sc, ALC_OPT_CFG); 708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 710 /* 711 * EEPROM found, let TWSI reload EEPROM configuration. 712 * This will set ethernet address of controller. 713 */ 714 eeprom++; 715 switch (sc->alc_ident->deviceid) { 716 case DEVICEID_ATHEROS_AR8131: 717 case DEVICEID_ATHEROS_AR8132: 718 if ((opt & OPT_CFG_CLK_ENB) == 0) { 719 opt |= OPT_CFG_CLK_ENB; 720 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 721 CSR_READ_4(sc, ALC_OPT_CFG); 722 DELAY(1000); 723 } 724 break; 725 case DEVICEID_ATHEROS_AR8151: 726 case DEVICEID_ATHEROS_AR8151_V2: 727 case DEVICEID_ATHEROS_AR8152_B: 728 case DEVICEID_ATHEROS_AR8152_B2: 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_ADDR, 0x00); 731 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 732 ALC_MII_DBG_DATA); 733 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 734 ALC_MII_DBG_DATA, val & 0xFF7F); 735 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 736 ALC_MII_DBG_ADDR, 0x3B); 737 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 738 ALC_MII_DBG_DATA); 739 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 740 ALC_MII_DBG_DATA, val | 0x0008); 741 DELAY(20); 742 break; 743 } 744 745 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 748 CSR_READ_4(sc, ALC_WOL_CFG); 749 750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 751 TWSI_CFG_SW_LD_START); 752 for (i = 100; i > 0; i--) { 753 DELAY(1000); 754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 755 TWSI_CFG_SW_LD_START) == 0) 756 break; 757 } 758 if (i == 0) 759 device_printf(sc->alc_dev, 760 "reloading EEPROM timeout!\n"); 761 } else { 762 if (bootverbose) 763 device_printf(sc->alc_dev, "EEPROM not found!\n"); 764 } 765 if (eeprom != 0) { 766 switch (sc->alc_ident->deviceid) { 767 case DEVICEID_ATHEROS_AR8131: 768 case DEVICEID_ATHEROS_AR8132: 769 if ((opt & OPT_CFG_CLK_ENB) != 0) { 770 opt &= ~OPT_CFG_CLK_ENB; 771 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 772 CSR_READ_4(sc, ALC_OPT_CFG); 773 DELAY(1000); 774 } 775 break; 776 case DEVICEID_ATHEROS_AR8151: 777 case DEVICEID_ATHEROS_AR8151_V2: 778 case DEVICEID_ATHEROS_AR8152_B: 779 case DEVICEID_ATHEROS_AR8152_B2: 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_ADDR, 0x00); 782 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 783 ALC_MII_DBG_DATA); 784 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 785 ALC_MII_DBG_DATA, val | 0x0080); 786 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x3B); 788 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA); 790 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 791 ALC_MII_DBG_DATA, val & 0xFFF7); 792 DELAY(20); 793 break; 794 } 795 } 796 797 alc_get_macaddr_par(sc); 798 } 799 800 static void 801 alc_get_macaddr_816x(struct alc_softc *sc) 802 { 803 uint32_t reg; 804 int i, reloaded; 805 806 reloaded = 0; 807 /* Try to reload station address via TWSI. */ 808 for (i = 100; i > 0; i--) { 809 reg = CSR_READ_4(sc, ALC_SLD); 810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 811 break; 812 DELAY(1000); 813 } 814 if (i != 0) { 815 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 816 for (i = 100; i > 0; i--) { 817 DELAY(1000); 818 reg = CSR_READ_4(sc, ALC_SLD); 819 if ((reg & SLD_START) == 0) 820 break; 821 } 822 if (i != 0) 823 reloaded++; 824 else if (bootverbose) 825 device_printf(sc->alc_dev, 826 "reloading station address via TWSI timed out!\n"); 827 } 828 829 /* Try to reload station address from EEPROM or FLASH. */ 830 if (reloaded == 0) { 831 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 832 if ((reg & (EEPROM_LD_EEPROM_EXIST | 833 EEPROM_LD_FLASH_EXIST)) != 0) { 834 for (i = 100; i > 0; i--) { 835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 836 if ((reg & (EEPROM_LD_PROGRESS | 837 EEPROM_LD_START)) == 0) 838 break; 839 DELAY(1000); 840 } 841 if (i != 0) { 842 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 843 EEPROM_LD_START); 844 for (i = 100; i > 0; i--) { 845 DELAY(1000); 846 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 847 if ((reg & EEPROM_LD_START) == 0) 848 break; 849 } 850 } else if (bootverbose) 851 device_printf(sc->alc_dev, 852 "reloading EEPROM/FLASH timed out!\n"); 853 } 854 } 855 856 alc_get_macaddr_par(sc); 857 } 858 859 static void 860 alc_get_macaddr_par(struct alc_softc *sc) 861 { 862 uint32_t ea[2]; 863 864 ea[0] = CSR_READ_4(sc, ALC_PAR0); 865 ea[1] = CSR_READ_4(sc, ALC_PAR1); 866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 872 } 873 874 static void 875 alc_disable_l0s_l1(struct alc_softc *sc) 876 { 877 uint32_t pmcfg; 878 879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 880 /* Another magic from vendor. */ 881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 882 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 883 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 884 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 885 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 886 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 887 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 888 } 889 } 890 891 static void 892 alc_phy_reset(struct alc_softc *sc) 893 { 894 895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 896 alc_phy_reset_816x(sc); 897 else 898 alc_phy_reset_813x(sc); 899 } 900 901 static void 902 alc_phy_reset_813x(struct alc_softc *sc) 903 { 904 uint16_t data; 905 906 /* Reset magic from Linux. */ 907 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 908 CSR_READ_2(sc, ALC_GPHY_CFG); 909 DELAY(10 * 1000); 910 911 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 912 GPHY_CFG_SEL_ANA_RESET); 913 CSR_READ_2(sc, ALC_GPHY_CFG); 914 DELAY(10 * 1000); 915 916 /* DSP fixup, Vendor magic. */ 917 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, 0x000A); 920 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA); 922 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 923 ALC_MII_DBG_DATA, data & 0xDFFF); 924 } 925 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 929 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 930 ALC_MII_DBG_ADDR, 0x003B); 931 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 932 ALC_MII_DBG_DATA); 933 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 934 ALC_MII_DBG_DATA, data & 0xFFF7); 935 DELAY(20 * 1000); 936 } 937 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_ADDR, 0x0029); 940 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 941 ALC_MII_DBG_DATA, 0x929D); 942 } 943 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 946 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_ADDR, 0x0029); 949 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 950 ALC_MII_DBG_DATA, 0xB6DD); 951 } 952 953 /* Load DSP codes, vendor magic. */ 954 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 955 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 957 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 958 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 959 ALC_MII_DBG_DATA, data); 960 961 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 962 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 963 ANA_SERDES_EN_LCKDT; 964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 965 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 967 ALC_MII_DBG_DATA, data); 968 969 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 970 ANA_LONG_CABLE_TH_100_MASK) | 971 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 972 ANA_SHORT_CABLE_TH_100_SHIFT) | 973 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 974 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 975 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 976 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 977 ALC_MII_DBG_DATA, data); 978 979 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 980 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 981 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 982 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 984 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 985 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 986 ALC_MII_DBG_DATA, data); 987 988 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 989 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 990 ANA_OEN_125M; 991 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 992 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 994 ALC_MII_DBG_DATA, data); 995 DELAY(1000); 996 997 /* Disable hibernation. */ 998 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 999 0x0029); 1000 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1001 ALC_MII_DBG_DATA); 1002 data &= ~0x8000; 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1004 data); 1005 1006 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1007 0x000B); 1008 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1009 ALC_MII_DBG_DATA); 1010 data &= ~0x8000; 1011 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1012 data); 1013 } 1014 1015 static void 1016 alc_phy_reset_816x(struct alc_softc *sc) 1017 { 1018 uint32_t val; 1019 1020 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1021 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1022 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1023 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1024 val |= GPHY_CFG_SEL_ANA_RESET; 1025 #ifdef notyet 1026 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1027 #else 1028 /* Disable PHY hibernation. */ 1029 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1030 #endif 1031 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1032 DELAY(10); 1033 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1034 DELAY(800); 1035 1036 /* Vendor PHY magic. */ 1037 #ifdef notyet 1038 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1039 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1040 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1041 EXT_VDRVBIAS_DEFAULT); 1042 #else 1043 /* Disable PHY hibernation. */ 1044 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1045 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1046 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1047 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1048 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1049 #endif 1050 1051 /* XXX Disable EEE. */ 1052 val = CSR_READ_4(sc, ALC_LPI_CTL); 1053 val &= ~LPI_CTL_ENB; 1054 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1056 1057 /* PHY power saving. */ 1058 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1061 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1062 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1063 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1064 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1065 1066 /* RTL8139C, 120m issue. */ 1067 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1068 ANEG_NLP78_120M_DEFAULT); 1069 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1070 ANEG_S3DIG10_DEFAULT); 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1073 /* Turn off half amplitude. */ 1074 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1075 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1076 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1077 /* Turn off Green feature. */ 1078 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1079 val |= DBG_GREENCFG2_BP_GREEN; 1080 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1081 /* Turn off half bias. */ 1082 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1083 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1084 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1085 } 1086 } 1087 1088 static void 1089 alc_phy_down(struct alc_softc *sc) 1090 { 1091 uint32_t gphy; 1092 1093 switch (sc->alc_ident->deviceid) { 1094 case DEVICEID_ATHEROS_AR8161: 1095 case DEVICEID_ATHEROS_E2200: 1096 case DEVICEID_ATHEROS_E2400: 1097 case DEVICEID_ATHEROS_E2500: 1098 case DEVICEID_ATHEROS_AR8162: 1099 case DEVICEID_ATHEROS_AR8171: 1100 case DEVICEID_ATHEROS_AR8172: 1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1102 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1103 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1104 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1105 GPHY_CFG_SEL_ANA_RESET; 1106 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1107 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1108 break; 1109 case DEVICEID_ATHEROS_AR8151: 1110 case DEVICEID_ATHEROS_AR8151_V2: 1111 case DEVICEID_ATHEROS_AR8152_B: 1112 case DEVICEID_ATHEROS_AR8152_B2: 1113 /* 1114 * GPHY power down caused more problems on AR8151 v2.0. 1115 * When driver is reloaded after GPHY power down, 1116 * accesses to PHY/MAC registers hung the system. Only 1117 * cold boot recovered from it. I'm not sure whether 1118 * AR8151 v1.0 also requires this one though. I don't 1119 * have AR8151 v1.0 controller in hand. 1120 * The only option left is to isolate the PHY and 1121 * initiates power down the PHY which in turn saves 1122 * more power when driver is unloaded. 1123 */ 1124 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1125 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1126 break; 1127 default: 1128 /* Force PHY down. */ 1129 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1130 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1131 GPHY_CFG_PWDOWN_HW); 1132 DELAY(1000); 1133 break; 1134 } 1135 } 1136 1137 static void 1138 alc_aspm(struct alc_softc *sc, int init, int media) 1139 { 1140 1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1142 alc_aspm_816x(sc, init); 1143 else 1144 alc_aspm_813x(sc, media); 1145 } 1146 1147 static void 1148 alc_aspm_813x(struct alc_softc *sc, int media) 1149 { 1150 uint32_t pmcfg; 1151 uint16_t linkcfg; 1152 1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1154 return; 1155 1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1157 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1158 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1159 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1160 PCIER_LINK_CTL); 1161 else 1162 linkcfg = 0; 1163 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1164 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1165 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1166 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1167 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1168 1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1170 /* Disable extended sync except AR8152 B v1.0 */ 1171 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1173 sc->alc_rev == ATHEROS_AR8152_B_V10) 1174 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1175 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1176 linkcfg); 1177 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1178 PM_CFG_HOTRST); 1179 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1180 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1181 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1182 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1183 PM_CFG_PM_REQ_TIMER_SHIFT); 1184 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1185 } 1186 1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1189 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1191 pmcfg |= PM_CFG_ASPM_L1_ENB; 1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1193 if (sc->alc_ident->deviceid == 1194 DEVICEID_ATHEROS_AR8152_B) 1195 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1196 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1197 PM_CFG_SERDES_PLL_L1_ENB | 1198 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1199 pmcfg |= PM_CFG_CLK_SWH_L1; 1200 if (media == IFM_100_TX || media == IFM_1000_T) { 1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1202 switch (sc->alc_ident->deviceid) { 1203 case DEVICEID_ATHEROS_AR8152_B: 1204 pmcfg |= (7 << 1205 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1206 break; 1207 case DEVICEID_ATHEROS_AR8152_B2: 1208 case DEVICEID_ATHEROS_AR8151_V2: 1209 pmcfg |= (4 << 1210 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1211 break; 1212 default: 1213 pmcfg |= (15 << 1214 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1215 break; 1216 } 1217 } 1218 } else { 1219 pmcfg |= PM_CFG_SERDES_L1_ENB | 1220 PM_CFG_SERDES_PLL_L1_ENB | 1221 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1222 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1223 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1224 } 1225 } else { 1226 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1227 PM_CFG_SERDES_PLL_L1_ENB); 1228 pmcfg |= PM_CFG_CLK_SWH_L1; 1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1230 pmcfg |= PM_CFG_ASPM_L1_ENB; 1231 } 1232 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1233 } 1234 1235 static void 1236 alc_aspm_816x(struct alc_softc *sc, int init) 1237 { 1238 uint32_t pmcfg; 1239 1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1241 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1242 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1243 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1244 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1245 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1246 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1247 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1248 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1249 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1250 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1251 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1252 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1253 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1254 (sc->alc_rev & 0x01) != 0) 1255 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1257 /* Link up, enable both L0s, L1s. */ 1258 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1259 PM_CFG_MAC_ASPM_CHK; 1260 } else { 1261 if (init != 0) 1262 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1263 PM_CFG_MAC_ASPM_CHK; 1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0) 1265 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1266 } 1267 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1268 } 1269 1270 static void 1271 alc_init_pcie(struct alc_softc *sc) 1272 { 1273 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1274 uint32_t cap, ctl, val; 1275 int state; 1276 1277 /* Clear data link and flow-control protocol error. */ 1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1279 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1280 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1281 1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1283 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1287 PCIE_PHYMISC_FORCE_RCV_DET); 1288 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1289 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1291 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1292 PCIE_PHYMISC2_SERDES_TH_MASK); 1293 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1294 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1295 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1296 } 1297 /* Disable ASPM L0S and L1. */ 1298 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1300 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1302 sc->alc_rcb = DMA_CFG_RCB_128; 1303 if (bootverbose) 1304 device_printf(sc->alc_dev, "RCB %u bytes\n", 1305 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1306 state = ctl & PCIEM_LINK_CTL_ASPMC; 1307 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1308 sc->alc_flags |= ALC_FLAG_L0S; 1309 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1310 sc->alc_flags |= ALC_FLAG_L1S; 1311 if (bootverbose) 1312 device_printf(sc->alc_dev, "ASPM %s %s\n", 1313 aspm_state[state], 1314 state == 0 ? "disabled" : "enabled"); 1315 alc_disable_l0s_l1(sc); 1316 } else { 1317 if (bootverbose) 1318 device_printf(sc->alc_dev, 1319 "no ASPM support\n"); 1320 } 1321 } else { 1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1323 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1324 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1325 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1326 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1327 (sc->alc_rev & 0x01) != 0) { 1328 if ((val & MASTER_WAKEN_25M) == 0 || 1329 (val & MASTER_CLK_SEL_DIS) == 0) { 1330 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1331 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1332 } 1333 } else { 1334 if ((val & MASTER_WAKEN_25M) == 0 || 1335 (val & MASTER_CLK_SEL_DIS) != 0) { 1336 val |= MASTER_WAKEN_25M; 1337 val &= ~MASTER_CLK_SEL_DIS; 1338 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1339 } 1340 } 1341 } 1342 alc_aspm(sc, 1, IFM_UNKNOWN); 1343 } 1344 1345 static void 1346 alc_config_msi(struct alc_softc *sc) 1347 { 1348 uint32_t ctl, mod; 1349 1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1351 /* 1352 * It seems interrupt moderation is controlled by 1353 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1354 * Driver uses RX interrupt moderation parameter to 1355 * program ALC_MSI_RETRANS_TIMER register. 1356 */ 1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1358 ctl &= ~MSI_RETRANS_TIMER_MASK; 1359 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1360 mod = ALC_USECS(sc->alc_int_rx_mod); 1361 if (mod == 0) 1362 mod = 1; 1363 ctl |= mod; 1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_STD); 1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1369 MSI_RETRANS_MASK_SEL_LINE); 1370 else 1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1372 } 1373 } 1374 1375 static int 1376 alc_attach(device_t dev) 1377 { 1378 struct alc_softc *sc; 1379 if_t ifp; 1380 int base, error, i, msic, msixc; 1381 uint16_t burst; 1382 1383 error = 0; 1384 sc = device_get_softc(dev); 1385 sc->alc_dev = dev; 1386 sc->alc_rev = pci_get_revid(dev); 1387 1388 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1389 MTX_DEF); 1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1392 sc->alc_ident = alc_find_ident(dev); 1393 1394 /* Map the device. */ 1395 pci_enable_busmaster(dev); 1396 sc->alc_res_spec = alc_res_spec_mem; 1397 sc->alc_irq_spec = alc_irq_spec_legacy; 1398 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1399 if (error != 0) { 1400 device_printf(dev, "cannot allocate memory resources.\n"); 1401 goto fail; 1402 } 1403 1404 /* Set PHY address. */ 1405 sc->alc_phyaddr = ALC_PHY_ADDR; 1406 1407 /* 1408 * One odd thing is AR8132 uses the same PHY hardware(F1 1409 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1410 * the PHY supports 1000Mbps but that's not true. The PHY 1411 * used in AR8132 can't establish gigabit link even if it 1412 * shows the same PHY model/revision number of AR8131. 1413 */ 1414 switch (sc->alc_ident->deviceid) { 1415 case DEVICEID_ATHEROS_E2200: 1416 case DEVICEID_ATHEROS_E2400: 1417 case DEVICEID_ATHEROS_E2500: 1418 sc->alc_flags |= ALC_FLAG_E2X00; 1419 1420 /* 1421 * Disable MSI-X by default on Killer devices, since this is 1422 * reported by several users to not work well. 1423 */ 1424 if (msix_disable == 2) 1425 msix_disable = 1; 1426 1427 /* FALLTHROUGH */ 1428 case DEVICEID_ATHEROS_AR8161: 1429 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1431 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8171: 1434 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1435 break; 1436 case DEVICEID_ATHEROS_AR8162: 1437 case DEVICEID_ATHEROS_AR8172: 1438 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1439 break; 1440 case DEVICEID_ATHEROS_AR8152_B: 1441 case DEVICEID_ATHEROS_AR8152_B2: 1442 sc->alc_flags |= ALC_FLAG_APS; 1443 /* FALLTHROUGH */ 1444 case DEVICEID_ATHEROS_AR8132: 1445 sc->alc_flags |= ALC_FLAG_FASTETHER; 1446 break; 1447 case DEVICEID_ATHEROS_AR8151: 1448 case DEVICEID_ATHEROS_AR8151_V2: 1449 sc->alc_flags |= ALC_FLAG_APS; 1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1451 sc->alc_flags |= ALC_FLAG_MT; 1452 /* FALLTHROUGH */ 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * The default value of msix_disable is 2, which means auto-detect. If 1459 * we didn't auto-detect it, default to enabling it. 1460 */ 1461 if (msix_disable == 2) 1462 msix_disable = 0; 1463 1464 sc->alc_flags |= ALC_FLAG_JUMBO; 1465 1466 /* 1467 * It seems that AR813x/AR815x has silicon bug for SMB. In 1468 * addition, Atheros said that enabling SMB wouldn't improve 1469 * performance. However I think it's bad to access lots of 1470 * registers to extract MAC statistics. 1471 */ 1472 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1473 /* 1474 * Don't use Tx CMB. It is known to have silicon bug. 1475 */ 1476 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1478 MASTER_CHIP_REV_SHIFT; 1479 if (bootverbose) { 1480 device_printf(dev, "PCI device revision : 0x%04x\n", 1481 sc->alc_rev); 1482 device_printf(dev, "Chip id/revision : 0x%04x\n", 1483 sc->alc_chip_rev); 1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1485 device_printf(dev, "AR816x revision : 0x%x\n", 1486 AR816X_REV(sc->alc_rev)); 1487 } 1488 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1491 1492 /* Initialize DMA parameters. */ 1493 sc->alc_dma_rd_burst = 0; 1494 sc->alc_dma_wr_burst = 0; 1495 sc->alc_rcb = DMA_CFG_RCB_64; 1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1497 sc->alc_flags |= ALC_FLAG_PCIE; 1498 sc->alc_expcap = base; 1499 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1500 sc->alc_dma_rd_burst = 1501 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1502 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1503 if (bootverbose) { 1504 device_printf(dev, "Read request size : %u bytes.\n", 1505 alc_dma_burst[sc->alc_dma_rd_burst]); 1506 device_printf(dev, "TLP payload size : %u bytes.\n", 1507 alc_dma_burst[sc->alc_dma_wr_burst]); 1508 } 1509 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1510 sc->alc_dma_rd_burst = 3; 1511 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1512 sc->alc_dma_wr_burst = 3; 1513 /* 1514 * Force maximum payload size to 128 bytes for 1515 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1516 * Otherwise it triggers DMA write error. 1517 */ 1518 if ((sc->alc_flags & 1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1520 sc->alc_dma_wr_burst = 0; 1521 alc_init_pcie(sc); 1522 } 1523 1524 /* Reset PHY. */ 1525 alc_phy_reset(sc); 1526 1527 /* Reset the ethernet controller. */ 1528 alc_stop_mac(sc); 1529 alc_reset(sc); 1530 1531 /* Allocate IRQ resources. */ 1532 msixc = pci_msix_count(dev); 1533 msic = pci_msi_count(dev); 1534 if (bootverbose) { 1535 device_printf(dev, "MSIX count : %d\n", msixc); 1536 device_printf(dev, "MSI count : %d\n", msic); 1537 } 1538 if (msixc > 1) 1539 msixc = 1; 1540 if (msic > 1) 1541 msic = 1; 1542 /* 1543 * Prefer MSIX over MSI. 1544 * AR816x controller has a silicon bug that MSI interrupt 1545 * does not assert if PCIM_CMD_INTxDIS bit of command 1546 * register is set. pci(4) was taught to handle that case. 1547 */ 1548 if (msix_disable == 0 || msi_disable == 0) { 1549 if (msix_disable == 0 && msixc > 0 && 1550 pci_alloc_msix(dev, &msixc) == 0) { 1551 if (msic == 1) { 1552 device_printf(dev, 1553 "Using %d MSIX message(s).\n", msixc); 1554 sc->alc_flags |= ALC_FLAG_MSIX; 1555 sc->alc_irq_spec = alc_irq_spec_msix; 1556 } else 1557 pci_release_msi(dev); 1558 } 1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1561 if (msic == 1) { 1562 device_printf(dev, 1563 "Using %d MSI message(s).\n", msic); 1564 sc->alc_flags |= ALC_FLAG_MSI; 1565 sc->alc_irq_spec = alc_irq_spec_msi; 1566 } else 1567 pci_release_msi(dev); 1568 } 1569 } 1570 1571 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1572 if (error != 0) { 1573 device_printf(dev, "cannot allocate IRQ resources.\n"); 1574 goto fail; 1575 } 1576 1577 /* Create device sysctl node. */ 1578 alc_sysctl_node(sc); 1579 1580 if ((error = alc_dma_alloc(sc)) != 0) 1581 goto fail; 1582 1583 /* Load station address. */ 1584 alc_get_macaddr(sc); 1585 1586 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1587 if (ifp == NULL) { 1588 device_printf(dev, "cannot allocate ifnet structure.\n"); 1589 error = ENXIO; 1590 goto fail; 1591 } 1592 1593 if_setsoftc(ifp, sc); 1594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1596 if_setioctlfn(ifp, alc_ioctl); 1597 if_setstartfn(ifp, alc_start); 1598 if_setinitfn(ifp, alc_init); 1599 if_setsendqlen(ifp, ALC_TX_RING_CNT - 1); 1600 if_setsendqready(ifp); 1601 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1602 if_sethwassist(ifp, ALC_CSUM_FEATURES | CSUM_TSO); 1603 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1604 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 1605 sc->alc_flags |= ALC_FLAG_PM; 1606 sc->alc_pmcap = base; 1607 } 1608 if_setcapenable(ifp, if_getcapabilities(ifp)); 1609 1610 /* Set up MII bus. */ 1611 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1612 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1613 MIIF_DOPAUSE); 1614 if (error != 0) { 1615 device_printf(dev, "attaching PHYs failed\n"); 1616 goto fail; 1617 } 1618 1619 ether_ifattach(ifp, sc->alc_eaddr); 1620 1621 /* VLAN capability setup. */ 1622 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1623 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 1624 if_setcapenable(ifp, if_getcapabilities(ifp)); 1625 /* 1626 * XXX 1627 * It seems enabling Tx checksum offloading makes more trouble. 1628 * Sometimes the controller does not receive any frames when 1629 * Tx checksum offloading is enabled. I'm not sure whether this 1630 * is a bug in Tx checksum offloading logic or I got broken 1631 * sample boards. To safety, don't enable Tx checksum offloading 1632 * by default but give chance to users to toggle it if they know 1633 * their controllers work without problems. 1634 * Fortunately, Tx checksum offloading for AR816x family 1635 * seems to work. 1636 */ 1637 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1638 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1639 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 1640 } 1641 1642 /* Tell the upper layer(s) we support long frames. */ 1643 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1644 1645 /* Create local taskq. */ 1646 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1647 taskqueue_thread_enqueue, &sc->alc_tq); 1648 if (sc->alc_tq == NULL) { 1649 device_printf(dev, "could not create taskqueue.\n"); 1650 ether_ifdetach(ifp); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1655 device_get_nameunit(sc->alc_dev)); 1656 1657 alc_config_msi(sc); 1658 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1659 msic = ALC_MSIX_MESSAGES; 1660 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1661 msic = ALC_MSI_MESSAGES; 1662 else 1663 msic = 1; 1664 for (i = 0; i < msic; i++) { 1665 error = bus_setup_intr(dev, sc->alc_irq[i], 1666 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1667 &sc->alc_intrhand[i]); 1668 if (error != 0) 1669 break; 1670 } 1671 if (error != 0) { 1672 device_printf(dev, "could not set up interrupt handler.\n"); 1673 taskqueue_free(sc->alc_tq); 1674 sc->alc_tq = NULL; 1675 ether_ifdetach(ifp); 1676 goto fail; 1677 } 1678 1679 /* Attach driver debugnet methods. */ 1680 DEBUGNET_SET(ifp, alc); 1681 1682 fail: 1683 if (error != 0) 1684 alc_detach(dev); 1685 1686 return (error); 1687 } 1688 1689 static int 1690 alc_detach(device_t dev) 1691 { 1692 struct alc_softc *sc; 1693 if_t ifp; 1694 int i, msic; 1695 1696 sc = device_get_softc(dev); 1697 1698 ifp = sc->alc_ifp; 1699 if (device_is_attached(dev)) { 1700 ether_ifdetach(ifp); 1701 ALC_LOCK(sc); 1702 alc_stop(sc); 1703 ALC_UNLOCK(sc); 1704 callout_drain(&sc->alc_tick_ch); 1705 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1706 } 1707 1708 if (sc->alc_tq != NULL) { 1709 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1710 taskqueue_free(sc->alc_tq); 1711 sc->alc_tq = NULL; 1712 } 1713 1714 if (sc->alc_miibus != NULL) { 1715 device_delete_child(dev, sc->alc_miibus); 1716 sc->alc_miibus = NULL; 1717 } 1718 bus_generic_detach(dev); 1719 alc_dma_free(sc); 1720 1721 if (ifp != NULL) { 1722 if_free(ifp); 1723 sc->alc_ifp = NULL; 1724 } 1725 1726 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1727 msic = ALC_MSIX_MESSAGES; 1728 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1729 msic = ALC_MSI_MESSAGES; 1730 else 1731 msic = 1; 1732 for (i = 0; i < msic; i++) { 1733 if (sc->alc_intrhand[i] != NULL) { 1734 bus_teardown_intr(dev, sc->alc_irq[i], 1735 sc->alc_intrhand[i]); 1736 sc->alc_intrhand[i] = NULL; 1737 } 1738 } 1739 if (sc->alc_res[0] != NULL) 1740 alc_phy_down(sc); 1741 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1742 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1743 pci_release_msi(dev); 1744 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1745 mtx_destroy(&sc->alc_mtx); 1746 1747 return (0); 1748 } 1749 1750 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1751 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1752 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1753 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1754 1755 static void 1756 alc_sysctl_node(struct alc_softc *sc) 1757 { 1758 struct sysctl_ctx_list *ctx; 1759 struct sysctl_oid_list *child, *parent; 1760 struct sysctl_oid *tree; 1761 struct alc_hw_stats *stats; 1762 int error; 1763 1764 stats = &sc->alc_stats; 1765 ctx = device_get_sysctl_ctx(sc->alc_dev); 1766 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1767 1768 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1769 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1770 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1771 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1772 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1773 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1774 /* Pull in device tunables. */ 1775 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1776 error = resource_int_value(device_get_name(sc->alc_dev), 1777 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1778 if (error == 0) { 1779 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1780 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1781 device_printf(sc->alc_dev, "int_rx_mod value out of " 1782 "range; using default: %d\n", 1783 ALC_IM_RX_TIMER_DEFAULT); 1784 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1785 } 1786 } 1787 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1788 error = resource_int_value(device_get_name(sc->alc_dev), 1789 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1790 if (error == 0) { 1791 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1792 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1793 device_printf(sc->alc_dev, "int_tx_mod value out of " 1794 "range; using default: %d\n", 1795 ALC_IM_TX_TIMER_DEFAULT); 1796 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1797 } 1798 } 1799 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1800 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1801 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1802 "max number of Rx events to process"); 1803 /* Pull in device tunables. */ 1804 sc->alc_process_limit = ALC_PROC_DEFAULT; 1805 error = resource_int_value(device_get_name(sc->alc_dev), 1806 device_get_unit(sc->alc_dev), "process_limit", 1807 &sc->alc_process_limit); 1808 if (error == 0) { 1809 if (sc->alc_process_limit < ALC_PROC_MIN || 1810 sc->alc_process_limit > ALC_PROC_MAX) { 1811 device_printf(sc->alc_dev, 1812 "process_limit value out of range; " 1813 "using default: %d\n", ALC_PROC_DEFAULT); 1814 sc->alc_process_limit = ALC_PROC_DEFAULT; 1815 } 1816 } 1817 1818 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1819 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1820 parent = SYSCTL_CHILDREN(tree); 1821 1822 /* Rx statistics. */ 1823 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1824 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1825 child = SYSCTL_CHILDREN(tree); 1826 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1827 &stats->rx_frames, "Good frames"); 1828 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1829 &stats->rx_bcast_frames, "Good broadcast frames"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1831 &stats->rx_mcast_frames, "Good multicast frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1833 &stats->rx_pause_frames, "Pause control frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1835 &stats->rx_control_frames, "Control frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1837 &stats->rx_crcerrs, "CRC errors"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1839 &stats->rx_lenerrs, "Frames with length mismatched"); 1840 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1841 &stats->rx_bytes, "Good octets"); 1842 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1843 &stats->rx_bcast_bytes, "Good broadcast octets"); 1844 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1845 &stats->rx_mcast_bytes, "Good multicast octets"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1847 &stats->rx_runts, "Too short frames"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1849 &stats->rx_fragments, "Fragmented frames"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1851 &stats->rx_pkts_64, "64 bytes frames"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1853 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1855 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1857 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1858 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1859 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1860 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1861 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1862 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1863 &stats->rx_pkts_1519_max, "1519 to max frames"); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1865 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1867 &stats->rx_fifo_oflows, "FIFO overflows"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1869 &stats->rx_rrs_errs, "Return status write-back errors"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1871 &stats->rx_alignerrs, "Alignment errors"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1873 &stats->rx_pkts_filtered, 1874 "Frames dropped due to address filtering"); 1875 1876 /* Tx statistics. */ 1877 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1878 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1879 child = SYSCTL_CHILDREN(tree); 1880 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1881 &stats->tx_frames, "Good frames"); 1882 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1883 &stats->tx_bcast_frames, "Good broadcast frames"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1885 &stats->tx_mcast_frames, "Good multicast frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1887 &stats->tx_pause_frames, "Pause control frames"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1889 &stats->tx_control_frames, "Control frames"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1891 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1893 &stats->tx_excess_defer, "Frames with derferrals"); 1894 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1895 &stats->tx_bytes, "Good octets"); 1896 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1897 &stats->tx_bcast_bytes, "Good broadcast octets"); 1898 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1899 &stats->tx_mcast_bytes, "Good multicast octets"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1901 &stats->tx_pkts_64, "64 bytes frames"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1903 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1905 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1907 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1909 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1911 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1912 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1913 &stats->tx_pkts_1519_max, "1519 to max frames"); 1914 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1915 &stats->tx_single_colls, "Single collisions"); 1916 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1917 &stats->tx_multi_colls, "Multiple collisions"); 1918 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1919 &stats->tx_late_colls, "Late collisions"); 1920 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1921 &stats->tx_excess_colls, "Excessive collisions"); 1922 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1923 &stats->tx_underrun, "FIFO underruns"); 1924 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1925 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1926 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1927 &stats->tx_lenerrs, "Frames with length mismatched"); 1928 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1929 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1930 } 1931 1932 #undef ALC_SYSCTL_STAT_ADD32 1933 #undef ALC_SYSCTL_STAT_ADD64 1934 1935 struct alc_dmamap_arg { 1936 bus_addr_t alc_busaddr; 1937 }; 1938 1939 static void 1940 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1941 { 1942 struct alc_dmamap_arg *ctx; 1943 1944 if (error != 0) 1945 return; 1946 1947 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1948 1949 ctx = (struct alc_dmamap_arg *)arg; 1950 ctx->alc_busaddr = segs[0].ds_addr; 1951 } 1952 1953 /* 1954 * Normal and high Tx descriptors shares single Tx high address. 1955 * Four Rx descriptor/return rings and CMB shares the same Rx 1956 * high address. 1957 */ 1958 static int 1959 alc_check_boundary(struct alc_softc *sc) 1960 { 1961 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1962 1963 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1964 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1965 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1966 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1967 1968 /* 4GB boundary crossing is not allowed. */ 1969 if ((ALC_ADDR_HI(rx_ring_end) != 1970 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1971 (ALC_ADDR_HI(rr_ring_end) != 1972 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1973 (ALC_ADDR_HI(cmb_end) != 1974 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1975 (ALC_ADDR_HI(tx_ring_end) != 1976 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1977 return (EFBIG); 1978 /* 1979 * Make sure Rx return descriptor/Rx descriptor/CMB use 1980 * the same high address. 1981 */ 1982 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1983 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1984 return (EFBIG); 1985 1986 return (0); 1987 } 1988 1989 static int 1990 alc_dma_alloc(struct alc_softc *sc) 1991 { 1992 struct alc_txdesc *txd; 1993 struct alc_rxdesc *rxd; 1994 bus_addr_t lowaddr; 1995 struct alc_dmamap_arg ctx; 1996 int error, i; 1997 1998 lowaddr = BUS_SPACE_MAXADDR; 1999 if (sc->alc_flags & ALC_FLAG_MT) 2000 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 2001 again: 2002 /* Create parent DMA tag. */ 2003 error = bus_dma_tag_create( 2004 bus_get_dma_tag(sc->alc_dev), /* parent */ 2005 1, 0, /* alignment, boundary */ 2006 lowaddr, /* lowaddr */ 2007 BUS_SPACE_MAXADDR, /* highaddr */ 2008 NULL, NULL, /* filter, filterarg */ 2009 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2010 0, /* nsegments */ 2011 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2012 0, /* flags */ 2013 NULL, NULL, /* lockfunc, lockarg */ 2014 &sc->alc_cdata.alc_parent_tag); 2015 if (error != 0) { 2016 device_printf(sc->alc_dev, 2017 "could not create parent DMA tag.\n"); 2018 goto fail; 2019 } 2020 2021 /* Create DMA tag for Tx descriptor ring. */ 2022 error = bus_dma_tag_create( 2023 sc->alc_cdata.alc_parent_tag, /* parent */ 2024 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2025 BUS_SPACE_MAXADDR, /* lowaddr */ 2026 BUS_SPACE_MAXADDR, /* highaddr */ 2027 NULL, NULL, /* filter, filterarg */ 2028 ALC_TX_RING_SZ, /* maxsize */ 2029 1, /* nsegments */ 2030 ALC_TX_RING_SZ, /* maxsegsize */ 2031 0, /* flags */ 2032 NULL, NULL, /* lockfunc, lockarg */ 2033 &sc->alc_cdata.alc_tx_ring_tag); 2034 if (error != 0) { 2035 device_printf(sc->alc_dev, 2036 "could not create Tx ring DMA tag.\n"); 2037 goto fail; 2038 } 2039 2040 /* Create DMA tag for Rx free descriptor ring. */ 2041 error = bus_dma_tag_create( 2042 sc->alc_cdata.alc_parent_tag, /* parent */ 2043 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2044 BUS_SPACE_MAXADDR, /* lowaddr */ 2045 BUS_SPACE_MAXADDR, /* highaddr */ 2046 NULL, NULL, /* filter, filterarg */ 2047 ALC_RX_RING_SZ, /* maxsize */ 2048 1, /* nsegments */ 2049 ALC_RX_RING_SZ, /* maxsegsize */ 2050 0, /* flags */ 2051 NULL, NULL, /* lockfunc, lockarg */ 2052 &sc->alc_cdata.alc_rx_ring_tag); 2053 if (error != 0) { 2054 device_printf(sc->alc_dev, 2055 "could not create Rx ring DMA tag.\n"); 2056 goto fail; 2057 } 2058 /* Create DMA tag for Rx return descriptor ring. */ 2059 error = bus_dma_tag_create( 2060 sc->alc_cdata.alc_parent_tag, /* parent */ 2061 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2062 BUS_SPACE_MAXADDR, /* lowaddr */ 2063 BUS_SPACE_MAXADDR, /* highaddr */ 2064 NULL, NULL, /* filter, filterarg */ 2065 ALC_RR_RING_SZ, /* maxsize */ 2066 1, /* nsegments */ 2067 ALC_RR_RING_SZ, /* maxsegsize */ 2068 0, /* flags */ 2069 NULL, NULL, /* lockfunc, lockarg */ 2070 &sc->alc_cdata.alc_rr_ring_tag); 2071 if (error != 0) { 2072 device_printf(sc->alc_dev, 2073 "could not create Rx return ring DMA tag.\n"); 2074 goto fail; 2075 } 2076 2077 /* Create DMA tag for coalescing message block. */ 2078 error = bus_dma_tag_create( 2079 sc->alc_cdata.alc_parent_tag, /* parent */ 2080 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2081 BUS_SPACE_MAXADDR, /* lowaddr */ 2082 BUS_SPACE_MAXADDR, /* highaddr */ 2083 NULL, NULL, /* filter, filterarg */ 2084 ALC_CMB_SZ, /* maxsize */ 2085 1, /* nsegments */ 2086 ALC_CMB_SZ, /* maxsegsize */ 2087 0, /* flags */ 2088 NULL, NULL, /* lockfunc, lockarg */ 2089 &sc->alc_cdata.alc_cmb_tag); 2090 if (error != 0) { 2091 device_printf(sc->alc_dev, 2092 "could not create CMB DMA tag.\n"); 2093 goto fail; 2094 } 2095 /* Create DMA tag for status message block. */ 2096 error = bus_dma_tag_create( 2097 sc->alc_cdata.alc_parent_tag, /* parent */ 2098 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2099 BUS_SPACE_MAXADDR, /* lowaddr */ 2100 BUS_SPACE_MAXADDR, /* highaddr */ 2101 NULL, NULL, /* filter, filterarg */ 2102 ALC_SMB_SZ, /* maxsize */ 2103 1, /* nsegments */ 2104 ALC_SMB_SZ, /* maxsegsize */ 2105 0, /* flags */ 2106 NULL, NULL, /* lockfunc, lockarg */ 2107 &sc->alc_cdata.alc_smb_tag); 2108 if (error != 0) { 2109 device_printf(sc->alc_dev, 2110 "could not create SMB DMA tag.\n"); 2111 goto fail; 2112 } 2113 2114 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2115 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2116 (void **)&sc->alc_rdata.alc_tx_ring, 2117 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2118 &sc->alc_cdata.alc_tx_ring_map); 2119 if (error != 0) { 2120 device_printf(sc->alc_dev, 2121 "could not allocate DMA'able memory for Tx ring.\n"); 2122 goto fail; 2123 } 2124 ctx.alc_busaddr = 0; 2125 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2126 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2127 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2128 if (error != 0 || ctx.alc_busaddr == 0) { 2129 device_printf(sc->alc_dev, 2130 "could not load DMA'able memory for Tx ring.\n"); 2131 goto fail; 2132 } 2133 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2134 2135 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2136 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2137 (void **)&sc->alc_rdata.alc_rx_ring, 2138 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2139 &sc->alc_cdata.alc_rx_ring_map); 2140 if (error != 0) { 2141 device_printf(sc->alc_dev, 2142 "could not allocate DMA'able memory for Rx ring.\n"); 2143 goto fail; 2144 } 2145 ctx.alc_busaddr = 0; 2146 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2147 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2148 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2149 if (error != 0 || ctx.alc_busaddr == 0) { 2150 device_printf(sc->alc_dev, 2151 "could not load DMA'able memory for Rx ring.\n"); 2152 goto fail; 2153 } 2154 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2155 2156 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2157 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2158 (void **)&sc->alc_rdata.alc_rr_ring, 2159 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2160 &sc->alc_cdata.alc_rr_ring_map); 2161 if (error != 0) { 2162 device_printf(sc->alc_dev, 2163 "could not allocate DMA'able memory for Rx return ring.\n"); 2164 goto fail; 2165 } 2166 ctx.alc_busaddr = 0; 2167 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2168 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2169 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2170 if (error != 0 || ctx.alc_busaddr == 0) { 2171 device_printf(sc->alc_dev, 2172 "could not load DMA'able memory for Tx ring.\n"); 2173 goto fail; 2174 } 2175 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2176 2177 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2178 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2179 (void **)&sc->alc_rdata.alc_cmb, 2180 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2181 &sc->alc_cdata.alc_cmb_map); 2182 if (error != 0) { 2183 device_printf(sc->alc_dev, 2184 "could not allocate DMA'able memory for CMB.\n"); 2185 goto fail; 2186 } 2187 ctx.alc_busaddr = 0; 2188 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2189 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2190 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2191 if (error != 0 || ctx.alc_busaddr == 0) { 2192 device_printf(sc->alc_dev, 2193 "could not load DMA'able memory for CMB.\n"); 2194 goto fail; 2195 } 2196 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2197 2198 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2199 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2200 (void **)&sc->alc_rdata.alc_smb, 2201 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2202 &sc->alc_cdata.alc_smb_map); 2203 if (error != 0) { 2204 device_printf(sc->alc_dev, 2205 "could not allocate DMA'able memory for SMB.\n"); 2206 goto fail; 2207 } 2208 ctx.alc_busaddr = 0; 2209 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2210 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2211 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2212 if (error != 0 || ctx.alc_busaddr == 0) { 2213 device_printf(sc->alc_dev, 2214 "could not load DMA'able memory for CMB.\n"); 2215 goto fail; 2216 } 2217 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2218 2219 /* Make sure we've not crossed 4GB boundary. */ 2220 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2221 (error = alc_check_boundary(sc)) != 0) { 2222 device_printf(sc->alc_dev, "4GB boundary crossed, " 2223 "switching to 32bit DMA addressing mode.\n"); 2224 alc_dma_free(sc); 2225 /* 2226 * Limit max allowable DMA address space to 32bit 2227 * and try again. 2228 */ 2229 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2230 goto again; 2231 } 2232 2233 /* 2234 * Create Tx buffer parent tag. 2235 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2236 * so it needs separate parent DMA tag as parent DMA address 2237 * space could be restricted to be within 32bit address space 2238 * by 4GB boundary crossing. 2239 */ 2240 error = bus_dma_tag_create( 2241 bus_get_dma_tag(sc->alc_dev), /* parent */ 2242 1, 0, /* alignment, boundary */ 2243 lowaddr, /* lowaddr */ 2244 BUS_SPACE_MAXADDR, /* highaddr */ 2245 NULL, NULL, /* filter, filterarg */ 2246 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2247 0, /* nsegments */ 2248 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2249 0, /* flags */ 2250 NULL, NULL, /* lockfunc, lockarg */ 2251 &sc->alc_cdata.alc_buffer_tag); 2252 if (error != 0) { 2253 device_printf(sc->alc_dev, 2254 "could not create parent buffer DMA tag.\n"); 2255 goto fail; 2256 } 2257 2258 /* Create DMA tag for Tx buffers. */ 2259 error = bus_dma_tag_create( 2260 sc->alc_cdata.alc_buffer_tag, /* parent */ 2261 1, 0, /* alignment, boundary */ 2262 BUS_SPACE_MAXADDR, /* lowaddr */ 2263 BUS_SPACE_MAXADDR, /* highaddr */ 2264 NULL, NULL, /* filter, filterarg */ 2265 ALC_TSO_MAXSIZE, /* maxsize */ 2266 ALC_MAXTXSEGS, /* nsegments */ 2267 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2268 0, /* flags */ 2269 NULL, NULL, /* lockfunc, lockarg */ 2270 &sc->alc_cdata.alc_tx_tag); 2271 if (error != 0) { 2272 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2273 goto fail; 2274 } 2275 2276 /* Create DMA tag for Rx buffers. */ 2277 error = bus_dma_tag_create( 2278 sc->alc_cdata.alc_buffer_tag, /* parent */ 2279 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2280 BUS_SPACE_MAXADDR, /* lowaddr */ 2281 BUS_SPACE_MAXADDR, /* highaddr */ 2282 NULL, NULL, /* filter, filterarg */ 2283 MCLBYTES, /* maxsize */ 2284 1, /* nsegments */ 2285 MCLBYTES, /* maxsegsize */ 2286 0, /* flags */ 2287 NULL, NULL, /* lockfunc, lockarg */ 2288 &sc->alc_cdata.alc_rx_tag); 2289 if (error != 0) { 2290 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2291 goto fail; 2292 } 2293 /* Create DMA maps for Tx buffers. */ 2294 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2295 txd = &sc->alc_cdata.alc_txdesc[i]; 2296 txd->tx_m = NULL; 2297 txd->tx_dmamap = NULL; 2298 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2299 &txd->tx_dmamap); 2300 if (error != 0) { 2301 device_printf(sc->alc_dev, 2302 "could not create Tx dmamap.\n"); 2303 goto fail; 2304 } 2305 } 2306 /* Create DMA maps for Rx buffers. */ 2307 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2308 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2309 device_printf(sc->alc_dev, 2310 "could not create spare Rx dmamap.\n"); 2311 goto fail; 2312 } 2313 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2314 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2315 rxd->rx_m = NULL; 2316 rxd->rx_dmamap = NULL; 2317 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2318 &rxd->rx_dmamap); 2319 if (error != 0) { 2320 device_printf(sc->alc_dev, 2321 "could not create Rx dmamap.\n"); 2322 goto fail; 2323 } 2324 } 2325 2326 fail: 2327 return (error); 2328 } 2329 2330 static void 2331 alc_dma_free(struct alc_softc *sc) 2332 { 2333 struct alc_txdesc *txd; 2334 struct alc_rxdesc *rxd; 2335 int i; 2336 2337 /* Tx buffers. */ 2338 if (sc->alc_cdata.alc_tx_tag != NULL) { 2339 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2340 txd = &sc->alc_cdata.alc_txdesc[i]; 2341 if (txd->tx_dmamap != NULL) { 2342 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2343 txd->tx_dmamap); 2344 txd->tx_dmamap = NULL; 2345 } 2346 } 2347 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2348 sc->alc_cdata.alc_tx_tag = NULL; 2349 } 2350 /* Rx buffers */ 2351 if (sc->alc_cdata.alc_rx_tag != NULL) { 2352 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2353 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2354 if (rxd->rx_dmamap != NULL) { 2355 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2356 rxd->rx_dmamap); 2357 rxd->rx_dmamap = NULL; 2358 } 2359 } 2360 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2361 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2362 sc->alc_cdata.alc_rx_sparemap); 2363 sc->alc_cdata.alc_rx_sparemap = NULL; 2364 } 2365 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2366 sc->alc_cdata.alc_rx_tag = NULL; 2367 } 2368 /* Tx descriptor ring. */ 2369 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2370 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2371 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2372 sc->alc_cdata.alc_tx_ring_map); 2373 if (sc->alc_rdata.alc_tx_ring != NULL) 2374 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2375 sc->alc_rdata.alc_tx_ring, 2376 sc->alc_cdata.alc_tx_ring_map); 2377 sc->alc_rdata.alc_tx_ring_paddr = 0; 2378 sc->alc_rdata.alc_tx_ring = NULL; 2379 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2380 sc->alc_cdata.alc_tx_ring_tag = NULL; 2381 } 2382 /* Rx ring. */ 2383 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2384 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2385 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2386 sc->alc_cdata.alc_rx_ring_map); 2387 if (sc->alc_rdata.alc_rx_ring != NULL) 2388 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2389 sc->alc_rdata.alc_rx_ring, 2390 sc->alc_cdata.alc_rx_ring_map); 2391 sc->alc_rdata.alc_rx_ring_paddr = 0; 2392 sc->alc_rdata.alc_rx_ring = NULL; 2393 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2394 sc->alc_cdata.alc_rx_ring_tag = NULL; 2395 } 2396 /* Rx return ring. */ 2397 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2398 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2399 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2400 sc->alc_cdata.alc_rr_ring_map); 2401 if (sc->alc_rdata.alc_rr_ring != NULL) 2402 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2403 sc->alc_rdata.alc_rr_ring, 2404 sc->alc_cdata.alc_rr_ring_map); 2405 sc->alc_rdata.alc_rr_ring_paddr = 0; 2406 sc->alc_rdata.alc_rr_ring = NULL; 2407 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2408 sc->alc_cdata.alc_rr_ring_tag = NULL; 2409 } 2410 /* CMB block */ 2411 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2412 if (sc->alc_rdata.alc_cmb_paddr != 0) 2413 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2414 sc->alc_cdata.alc_cmb_map); 2415 if (sc->alc_rdata.alc_cmb != NULL) 2416 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2417 sc->alc_rdata.alc_cmb, 2418 sc->alc_cdata.alc_cmb_map); 2419 sc->alc_rdata.alc_cmb_paddr = 0; 2420 sc->alc_rdata.alc_cmb = NULL; 2421 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2422 sc->alc_cdata.alc_cmb_tag = NULL; 2423 } 2424 /* SMB block */ 2425 if (sc->alc_cdata.alc_smb_tag != NULL) { 2426 if (sc->alc_rdata.alc_smb_paddr != 0) 2427 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2428 sc->alc_cdata.alc_smb_map); 2429 if (sc->alc_rdata.alc_smb != NULL) 2430 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2431 sc->alc_rdata.alc_smb, 2432 sc->alc_cdata.alc_smb_map); 2433 sc->alc_rdata.alc_smb_paddr = 0; 2434 sc->alc_rdata.alc_smb = NULL; 2435 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2436 sc->alc_cdata.alc_smb_tag = NULL; 2437 } 2438 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2439 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2440 sc->alc_cdata.alc_buffer_tag = NULL; 2441 } 2442 if (sc->alc_cdata.alc_parent_tag != NULL) { 2443 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2444 sc->alc_cdata.alc_parent_tag = NULL; 2445 } 2446 } 2447 2448 static int 2449 alc_shutdown(device_t dev) 2450 { 2451 2452 return (alc_suspend(dev)); 2453 } 2454 2455 /* 2456 * Note, this driver resets the link speed to 10/100Mbps by 2457 * restarting auto-negotiation in suspend/shutdown phase but we 2458 * don't know whether that auto-negotiation would succeed or not 2459 * as driver has no control after powering off/suspend operation. 2460 * If the renegotiation fail WOL may not work. Running at 1Gbps 2461 * will draw more power than 375mA at 3.3V which is specified in 2462 * PCI specification and that would result in complete 2463 * shutdowning power to ethernet controller. 2464 * 2465 * TODO 2466 * Save current negotiated media speed/duplex/flow-control to 2467 * softc and restore the same link again after resuming. PHY 2468 * handling such as power down/resetting to 100Mbps may be better 2469 * handled in suspend method in phy driver. 2470 */ 2471 static void 2472 alc_setlinkspeed(struct alc_softc *sc) 2473 { 2474 struct mii_data *mii; 2475 int aneg, i; 2476 2477 mii = device_get_softc(sc->alc_miibus); 2478 mii_pollstat(mii); 2479 aneg = 0; 2480 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2481 (IFM_ACTIVE | IFM_AVALID)) { 2482 switch IFM_SUBTYPE(mii->mii_media_active) { 2483 case IFM_10_T: 2484 case IFM_100_TX: 2485 return; 2486 case IFM_1000_T: 2487 aneg++; 2488 break; 2489 default: 2490 break; 2491 } 2492 } 2493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2494 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2495 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2496 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2497 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2498 DELAY(1000); 2499 if (aneg != 0) { 2500 /* 2501 * Poll link state until alc(4) get a 10/100Mbps link. 2502 */ 2503 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2504 mii_pollstat(mii); 2505 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2506 == (IFM_ACTIVE | IFM_AVALID)) { 2507 switch (IFM_SUBTYPE( 2508 mii->mii_media_active)) { 2509 case IFM_10_T: 2510 case IFM_100_TX: 2511 alc_mac_config(sc); 2512 return; 2513 default: 2514 break; 2515 } 2516 } 2517 ALC_UNLOCK(sc); 2518 pause("alclnk", hz); 2519 ALC_LOCK(sc); 2520 } 2521 if (i == MII_ANEGTICKS_GIGE) 2522 device_printf(sc->alc_dev, 2523 "establishing a link failed, WOL may not work!"); 2524 } 2525 /* 2526 * No link, force MAC to have 100Mbps, full-duplex link. 2527 * This is the last resort and may/may not work. 2528 */ 2529 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2530 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2531 alc_mac_config(sc); 2532 } 2533 2534 static void 2535 alc_setwol(struct alc_softc *sc) 2536 { 2537 2538 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2539 alc_setwol_816x(sc); 2540 else 2541 alc_setwol_813x(sc); 2542 } 2543 2544 static void 2545 alc_setwol_813x(struct alc_softc *sc) 2546 { 2547 if_t ifp; 2548 uint32_t reg, pmcs; 2549 uint16_t pmstat; 2550 2551 ALC_LOCK_ASSERT(sc); 2552 2553 alc_disable_l0s_l1(sc); 2554 ifp = sc->alc_ifp; 2555 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2556 /* Disable WOL. */ 2557 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2558 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2559 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2560 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2561 /* Force PHY power down. */ 2562 alc_phy_down(sc); 2563 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2564 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2565 return; 2566 } 2567 2568 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2569 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2570 alc_setlinkspeed(sc); 2571 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2572 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2573 } 2574 2575 pmcs = 0; 2576 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2577 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2578 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2579 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2580 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2581 MAC_CFG_BCAST); 2582 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2583 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2584 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2585 reg |= MAC_CFG_RX_ENB; 2586 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2587 2588 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2589 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2590 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2591 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2592 /* WOL disabled, PHY power down. */ 2593 alc_phy_down(sc); 2594 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2595 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2596 } 2597 /* Request PME. */ 2598 pmstat = pci_read_config(sc->alc_dev, 2599 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2600 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2601 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2602 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2603 pci_write_config(sc->alc_dev, 2604 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2605 } 2606 2607 static void 2608 alc_setwol_816x(struct alc_softc *sc) 2609 { 2610 if_t ifp; 2611 uint32_t gphy, mac, master, pmcs, reg; 2612 uint16_t pmstat; 2613 2614 ALC_LOCK_ASSERT(sc); 2615 2616 ifp = sc->alc_ifp; 2617 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2618 master &= ~MASTER_CLK_SEL_DIS; 2619 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2620 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2621 GPHY_CFG_PHY_PLL_ON); 2622 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2623 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2624 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2625 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2626 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2627 } else { 2628 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2629 gphy |= GPHY_CFG_EXT_RESET; 2630 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2631 alc_setlinkspeed(sc); 2632 } 2633 pmcs = 0; 2634 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2635 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2636 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2637 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2638 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2639 MAC_CFG_BCAST); 2640 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2641 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2642 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2643 mac |= MAC_CFG_RX_ENB; 2644 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2645 ANEG_S3DIG10_SL); 2646 } 2647 2648 /* Enable OSC. */ 2649 reg = CSR_READ_4(sc, ALC_MISC); 2650 reg &= ~MISC_INTNLOSC_OPEN; 2651 CSR_WRITE_4(sc, ALC_MISC, reg); 2652 reg |= MISC_INTNLOSC_OPEN; 2653 CSR_WRITE_4(sc, ALC_MISC, reg); 2654 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2655 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2656 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2657 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2658 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2659 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2660 2661 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2662 /* Request PME. */ 2663 pmstat = pci_read_config(sc->alc_dev, 2664 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2665 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2666 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2667 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2668 pci_write_config(sc->alc_dev, 2669 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2670 } 2671 } 2672 2673 static int 2674 alc_suspend(device_t dev) 2675 { 2676 struct alc_softc *sc; 2677 2678 sc = device_get_softc(dev); 2679 2680 ALC_LOCK(sc); 2681 alc_stop(sc); 2682 alc_setwol(sc); 2683 ALC_UNLOCK(sc); 2684 2685 return (0); 2686 } 2687 2688 static int 2689 alc_resume(device_t dev) 2690 { 2691 struct alc_softc *sc; 2692 if_t ifp; 2693 uint16_t pmstat; 2694 2695 sc = device_get_softc(dev); 2696 2697 ALC_LOCK(sc); 2698 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2699 /* Disable PME and clear PME status. */ 2700 pmstat = pci_read_config(sc->alc_dev, 2701 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2702 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2703 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2704 pci_write_config(sc->alc_dev, 2705 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2706 } 2707 } 2708 /* Reset PHY. */ 2709 alc_phy_reset(sc); 2710 ifp = sc->alc_ifp; 2711 if ((if_getflags(ifp) & IFF_UP) != 0) { 2712 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2713 alc_init_locked(sc); 2714 } 2715 ALC_UNLOCK(sc); 2716 2717 return (0); 2718 } 2719 2720 static int 2721 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2722 { 2723 struct alc_txdesc *txd, *txd_last; 2724 struct tx_desc *desc; 2725 struct mbuf *m; 2726 struct ip *ip; 2727 struct tcphdr *tcp; 2728 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2729 bus_dmamap_t map; 2730 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2731 int error, idx, nsegs, prod; 2732 2733 ALC_LOCK_ASSERT(sc); 2734 2735 M_ASSERTPKTHDR((*m_head)); 2736 2737 m = *m_head; 2738 ip = NULL; 2739 tcp = NULL; 2740 ip_off = poff = 0; 2741 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2742 /* 2743 * AR81[3567]x requires offset of TCP/UDP header in its 2744 * Tx descriptor to perform Tx checksum offloading. TSO 2745 * also requires TCP header offset and modification of 2746 * IP/TCP header. This kind of operation takes many CPU 2747 * cycles on FreeBSD so fast host CPU is required to get 2748 * smooth TSO performance. 2749 */ 2750 struct ether_header *eh; 2751 2752 if (M_WRITABLE(m) == 0) { 2753 /* Get a writable copy. */ 2754 m = m_dup(*m_head, M_NOWAIT); 2755 /* Release original mbufs. */ 2756 m_freem(*m_head); 2757 if (m == NULL) { 2758 *m_head = NULL; 2759 return (ENOBUFS); 2760 } 2761 *m_head = m; 2762 } 2763 2764 ip_off = sizeof(struct ether_header); 2765 m = m_pullup(m, ip_off); 2766 if (m == NULL) { 2767 *m_head = NULL; 2768 return (ENOBUFS); 2769 } 2770 eh = mtod(m, struct ether_header *); 2771 /* 2772 * Check if hardware VLAN insertion is off. 2773 * Additional check for LLC/SNAP frame? 2774 */ 2775 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2776 ip_off = sizeof(struct ether_vlan_header); 2777 m = m_pullup(m, ip_off); 2778 if (m == NULL) { 2779 *m_head = NULL; 2780 return (ENOBUFS); 2781 } 2782 } 2783 m = m_pullup(m, ip_off + sizeof(struct ip)); 2784 if (m == NULL) { 2785 *m_head = NULL; 2786 return (ENOBUFS); 2787 } 2788 ip = (struct ip *)(mtod(m, char *) + ip_off); 2789 poff = ip_off + (ip->ip_hl << 2); 2790 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2791 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2792 if (m == NULL) { 2793 *m_head = NULL; 2794 return (ENOBUFS); 2795 } 2796 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2797 m = m_pullup(m, poff + (tcp->th_off << 2)); 2798 if (m == NULL) { 2799 *m_head = NULL; 2800 return (ENOBUFS); 2801 } 2802 /* 2803 * Due to strict adherence of Microsoft NDIS 2804 * Large Send specification, hardware expects 2805 * a pseudo TCP checksum inserted by upper 2806 * stack. Unfortunately the pseudo TCP 2807 * checksum that NDIS refers to does not include 2808 * TCP payload length so driver should recompute 2809 * the pseudo checksum here. Hopefully this 2810 * wouldn't be much burden on modern CPUs. 2811 * 2812 * Reset IP checksum and recompute TCP pseudo 2813 * checksum as NDIS specification said. 2814 */ 2815 ip = (struct ip *)(mtod(m, char *) + ip_off); 2816 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2817 ip->ip_sum = 0; 2818 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2819 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2820 } 2821 *m_head = m; 2822 } 2823 2824 prod = sc->alc_cdata.alc_tx_prod; 2825 txd = &sc->alc_cdata.alc_txdesc[prod]; 2826 txd_last = txd; 2827 map = txd->tx_dmamap; 2828 2829 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2830 *m_head, txsegs, &nsegs, 0); 2831 if (error == EFBIG) { 2832 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2833 if (m == NULL) { 2834 m_freem(*m_head); 2835 *m_head = NULL; 2836 return (ENOMEM); 2837 } 2838 *m_head = m; 2839 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2840 *m_head, txsegs, &nsegs, 0); 2841 if (error != 0) { 2842 m_freem(*m_head); 2843 *m_head = NULL; 2844 return (error); 2845 } 2846 } else if (error != 0) 2847 return (error); 2848 if (nsegs == 0) { 2849 m_freem(*m_head); 2850 *m_head = NULL; 2851 return (EIO); 2852 } 2853 2854 /* Check descriptor overrun. */ 2855 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2856 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2857 return (ENOBUFS); 2858 } 2859 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2860 2861 m = *m_head; 2862 cflags = TD_ETHERNET; 2863 vtag = 0; 2864 desc = NULL; 2865 idx = 0; 2866 /* Configure VLAN hardware tag insertion. */ 2867 if ((m->m_flags & M_VLANTAG) != 0) { 2868 vtag = htons(m->m_pkthdr.ether_vtag); 2869 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2870 cflags |= TD_INS_VLAN_TAG; 2871 } 2872 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2873 /* Request TSO and set MSS. */ 2874 cflags |= TD_TSO | TD_TSO_DESCV1; 2875 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2876 TD_MSS_MASK; 2877 /* Set TCP header offset. */ 2878 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2879 TD_TCPHDR_OFFSET_MASK; 2880 /* 2881 * AR81[3567]x requires the first buffer should 2882 * only hold IP/TCP header data. Payload should 2883 * be handled in other descriptors. 2884 */ 2885 hdrlen = poff + (tcp->th_off << 2); 2886 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2887 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2888 desc->flags = htole32(cflags); 2889 desc->addr = htole64(txsegs[0].ds_addr); 2890 sc->alc_cdata.alc_tx_cnt++; 2891 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2892 if (m->m_len - hdrlen > 0) { 2893 /* Handle remaining payload of the first fragment. */ 2894 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2895 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2896 vtag)); 2897 desc->flags = htole32(cflags); 2898 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2899 sc->alc_cdata.alc_tx_cnt++; 2900 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2901 } 2902 /* Handle remaining fragments. */ 2903 idx = 1; 2904 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2905 /* Configure Tx checksum offload. */ 2906 #ifdef ALC_USE_CUSTOM_CSUM 2907 cflags |= TD_CUSTOM_CSUM; 2908 /* Set checksum start offset. */ 2909 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2910 TD_PLOAD_OFFSET_MASK; 2911 /* Set checksum insertion position of TCP/UDP. */ 2912 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2913 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2914 #else 2915 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2916 cflags |= TD_IPCSUM; 2917 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2918 cflags |= TD_TCPCSUM; 2919 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2920 cflags |= TD_UDPCSUM; 2921 /* Set TCP/UDP header offset. */ 2922 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2923 TD_L4HDR_OFFSET_MASK; 2924 #endif 2925 } 2926 for (; idx < nsegs; idx++) { 2927 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2928 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2929 desc->flags = htole32(cflags); 2930 desc->addr = htole64(txsegs[idx].ds_addr); 2931 sc->alc_cdata.alc_tx_cnt++; 2932 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2933 } 2934 /* Update producer index. */ 2935 sc->alc_cdata.alc_tx_prod = prod; 2936 2937 /* Finally set EOP on the last descriptor. */ 2938 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2939 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2940 desc->flags |= htole32(TD_EOP); 2941 2942 /* Swap dmamap of the first and the last. */ 2943 txd = &sc->alc_cdata.alc_txdesc[prod]; 2944 map = txd_last->tx_dmamap; 2945 txd_last->tx_dmamap = txd->tx_dmamap; 2946 txd->tx_dmamap = map; 2947 txd->tx_m = m; 2948 2949 return (0); 2950 } 2951 2952 static void 2953 alc_start(if_t ifp) 2954 { 2955 struct alc_softc *sc; 2956 2957 sc = if_getsoftc(ifp); 2958 ALC_LOCK(sc); 2959 alc_start_locked(ifp); 2960 ALC_UNLOCK(sc); 2961 } 2962 2963 static void 2964 alc_start_locked(if_t ifp) 2965 { 2966 struct alc_softc *sc; 2967 struct mbuf *m_head; 2968 int enq; 2969 2970 sc = if_getsoftc(ifp); 2971 2972 ALC_LOCK_ASSERT(sc); 2973 2974 /* Reclaim transmitted frames. */ 2975 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2976 alc_txeof(sc); 2977 2978 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2979 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2980 return; 2981 2982 for (enq = 0; !if_sendq_empty(ifp); ) { 2983 m_head = if_dequeue(ifp); 2984 if (m_head == NULL) 2985 break; 2986 /* 2987 * Pack the data into the transmit ring. If we 2988 * don't have room, set the OACTIVE flag and wait 2989 * for the NIC to drain the ring. 2990 */ 2991 if (alc_encap(sc, &m_head)) { 2992 if (m_head == NULL) 2993 break; 2994 if_sendq_prepend(ifp, m_head); 2995 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2996 break; 2997 } 2998 2999 enq++; 3000 /* 3001 * If there's a BPF listener, bounce a copy of this frame 3002 * to him. 3003 */ 3004 ETHER_BPF_MTAP(ifp, m_head); 3005 } 3006 3007 if (enq > 0) 3008 alc_start_tx(sc); 3009 } 3010 3011 static void 3012 alc_start_tx(struct alc_softc *sc) 3013 { 3014 3015 /* Sync descriptors. */ 3016 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3017 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3018 /* Kick. Assume we're using normal Tx priority queue. */ 3019 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3020 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3021 (uint16_t)sc->alc_cdata.alc_tx_prod); 3022 else 3023 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3024 (sc->alc_cdata.alc_tx_prod << 3025 MBOX_TD_PROD_LO_IDX_SHIFT) & 3026 MBOX_TD_PROD_LO_IDX_MASK); 3027 /* Set a timeout in case the chip goes out to lunch. */ 3028 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3029 } 3030 3031 static void 3032 alc_watchdog(struct alc_softc *sc) 3033 { 3034 if_t ifp; 3035 3036 ALC_LOCK_ASSERT(sc); 3037 3038 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3039 return; 3040 3041 ifp = sc->alc_ifp; 3042 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3043 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3044 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3045 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3046 alc_init_locked(sc); 3047 return; 3048 } 3049 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3050 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3051 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3052 alc_init_locked(sc); 3053 if (!if_sendq_empty(ifp)) 3054 alc_start_locked(ifp); 3055 } 3056 3057 static int 3058 alc_ioctl(if_t ifp, u_long cmd, caddr_t data) 3059 { 3060 struct alc_softc *sc; 3061 struct ifreq *ifr; 3062 struct mii_data *mii; 3063 int error, mask; 3064 3065 sc = if_getsoftc(ifp); 3066 ifr = (struct ifreq *)data; 3067 error = 0; 3068 switch (cmd) { 3069 case SIOCSIFMTU: 3070 if (ifr->ifr_mtu < ETHERMIN || 3071 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3072 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3073 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3074 ifr->ifr_mtu > ETHERMTU)) 3075 error = EINVAL; 3076 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 3077 ALC_LOCK(sc); 3078 if_setmtu(ifp, ifr->ifr_mtu); 3079 /* AR81[3567]x has 13 bits MSS field. */ 3080 if (if_getmtu(ifp) > ALC_TSO_MTU && 3081 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3082 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3083 if_sethwassistbits(ifp, 0, CSUM_TSO); 3084 VLAN_CAPABILITIES(ifp); 3085 } 3086 ALC_UNLOCK(sc); 3087 } 3088 break; 3089 case SIOCSIFFLAGS: 3090 ALC_LOCK(sc); 3091 if ((if_getflags(ifp) & IFF_UP) != 0) { 3092 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3093 ((if_getflags(ifp) ^ sc->alc_if_flags) & 3094 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3095 alc_rxfilter(sc); 3096 else 3097 alc_init_locked(sc); 3098 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3099 alc_stop(sc); 3100 sc->alc_if_flags = if_getflags(ifp); 3101 ALC_UNLOCK(sc); 3102 break; 3103 case SIOCADDMULTI: 3104 case SIOCDELMULTI: 3105 ALC_LOCK(sc); 3106 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3107 alc_rxfilter(sc); 3108 ALC_UNLOCK(sc); 3109 break; 3110 case SIOCSIFMEDIA: 3111 case SIOCGIFMEDIA: 3112 mii = device_get_softc(sc->alc_miibus); 3113 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3114 break; 3115 case SIOCSIFCAP: 3116 ALC_LOCK(sc); 3117 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3118 if ((mask & IFCAP_TXCSUM) != 0 && 3119 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3120 if_togglecapenable(ifp, IFCAP_TXCSUM); 3121 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3122 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0); 3123 else 3124 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES); 3125 } 3126 if ((mask & IFCAP_TSO4) != 0 && 3127 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3128 if_togglecapenable(ifp, IFCAP_TSO4); 3129 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3130 /* AR81[3567]x has 13 bits MSS field. */ 3131 if (if_getmtu(ifp) > ALC_TSO_MTU) { 3132 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3133 if_sethwassistbits(ifp, 0, CSUM_TSO); 3134 } else 3135 if_sethwassistbits(ifp, CSUM_TSO, 0); 3136 } else 3137 if_sethwassistbits(ifp, 0, CSUM_TSO); 3138 } 3139 if ((mask & IFCAP_WOL_MCAST) != 0 && 3140 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 3141 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3142 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3143 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3144 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3145 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3146 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3147 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3148 alc_rxvlan(sc); 3149 } 3150 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3151 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3152 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3153 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3154 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3155 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3156 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3157 if_setcapenablebit(ifp, 0, 3158 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3159 ALC_UNLOCK(sc); 3160 VLAN_CAPABILITIES(ifp); 3161 break; 3162 default: 3163 error = ether_ioctl(ifp, cmd, data); 3164 break; 3165 } 3166 3167 return (error); 3168 } 3169 3170 static void 3171 alc_mac_config(struct alc_softc *sc) 3172 { 3173 struct mii_data *mii; 3174 uint32_t reg; 3175 3176 ALC_LOCK_ASSERT(sc); 3177 3178 mii = device_get_softc(sc->alc_miibus); 3179 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3180 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3181 MAC_CFG_SPEED_MASK); 3182 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3183 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3184 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3185 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3186 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3187 /* Reprogram MAC with resolved speed/duplex. */ 3188 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3189 case IFM_10_T: 3190 case IFM_100_TX: 3191 reg |= MAC_CFG_SPEED_10_100; 3192 break; 3193 case IFM_1000_T: 3194 reg |= MAC_CFG_SPEED_1000; 3195 break; 3196 } 3197 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3198 reg |= MAC_CFG_FULL_DUPLEX; 3199 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3200 reg |= MAC_CFG_TX_FC; 3201 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3202 reg |= MAC_CFG_RX_FC; 3203 } 3204 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3205 } 3206 3207 static void 3208 alc_stats_clear(struct alc_softc *sc) 3209 { 3210 struct smb sb, *smb; 3211 uint32_t *reg; 3212 int i; 3213 3214 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3215 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3216 sc->alc_cdata.alc_smb_map, 3217 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3218 smb = sc->alc_rdata.alc_smb; 3219 /* Update done, clear. */ 3220 smb->updated = 0; 3221 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3222 sc->alc_cdata.alc_smb_map, 3223 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3224 } else { 3225 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3226 reg++) { 3227 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3228 i += sizeof(uint32_t); 3229 } 3230 /* Read Tx statistics. */ 3231 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3232 reg++) { 3233 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3234 i += sizeof(uint32_t); 3235 } 3236 } 3237 } 3238 3239 static void 3240 alc_stats_update(struct alc_softc *sc) 3241 { 3242 struct alc_hw_stats *stat; 3243 struct smb sb, *smb; 3244 if_t ifp; 3245 uint32_t *reg; 3246 int i; 3247 3248 ALC_LOCK_ASSERT(sc); 3249 3250 ifp = sc->alc_ifp; 3251 stat = &sc->alc_stats; 3252 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3253 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3254 sc->alc_cdata.alc_smb_map, 3255 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3256 smb = sc->alc_rdata.alc_smb; 3257 if (smb->updated == 0) 3258 return; 3259 } else { 3260 smb = &sb; 3261 /* Read Rx statistics. */ 3262 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3263 reg++) { 3264 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3265 i += sizeof(uint32_t); 3266 } 3267 /* Read Tx statistics. */ 3268 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3269 reg++) { 3270 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3271 i += sizeof(uint32_t); 3272 } 3273 } 3274 3275 /* Rx stats. */ 3276 stat->rx_frames += smb->rx_frames; 3277 stat->rx_bcast_frames += smb->rx_bcast_frames; 3278 stat->rx_mcast_frames += smb->rx_mcast_frames; 3279 stat->rx_pause_frames += smb->rx_pause_frames; 3280 stat->rx_control_frames += smb->rx_control_frames; 3281 stat->rx_crcerrs += smb->rx_crcerrs; 3282 stat->rx_lenerrs += smb->rx_lenerrs; 3283 stat->rx_bytes += smb->rx_bytes; 3284 stat->rx_runts += smb->rx_runts; 3285 stat->rx_fragments += smb->rx_fragments; 3286 stat->rx_pkts_64 += smb->rx_pkts_64; 3287 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3288 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3289 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3290 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3291 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3292 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3293 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3294 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3295 stat->rx_rrs_errs += smb->rx_rrs_errs; 3296 stat->rx_alignerrs += smb->rx_alignerrs; 3297 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3298 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3299 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3300 3301 /* Tx stats. */ 3302 stat->tx_frames += smb->tx_frames; 3303 stat->tx_bcast_frames += smb->tx_bcast_frames; 3304 stat->tx_mcast_frames += smb->tx_mcast_frames; 3305 stat->tx_pause_frames += smb->tx_pause_frames; 3306 stat->tx_excess_defer += smb->tx_excess_defer; 3307 stat->tx_control_frames += smb->tx_control_frames; 3308 stat->tx_deferred += smb->tx_deferred; 3309 stat->tx_bytes += smb->tx_bytes; 3310 stat->tx_pkts_64 += smb->tx_pkts_64; 3311 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3312 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3313 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3314 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3315 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3316 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3317 stat->tx_single_colls += smb->tx_single_colls; 3318 stat->tx_multi_colls += smb->tx_multi_colls; 3319 stat->tx_late_colls += smb->tx_late_colls; 3320 stat->tx_excess_colls += smb->tx_excess_colls; 3321 stat->tx_underrun += smb->tx_underrun; 3322 stat->tx_desc_underrun += smb->tx_desc_underrun; 3323 stat->tx_lenerrs += smb->tx_lenerrs; 3324 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3325 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3326 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3327 3328 /* Update counters in ifnet. */ 3329 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3330 3331 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3332 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3333 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3334 3335 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3336 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3337 3338 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3339 3340 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3341 smb->rx_crcerrs + smb->rx_lenerrs + 3342 smb->rx_runts + smb->rx_pkts_truncated + 3343 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3344 smb->rx_alignerrs); 3345 3346 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3347 /* Update done, clear. */ 3348 smb->updated = 0; 3349 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3350 sc->alc_cdata.alc_smb_map, 3351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3352 } 3353 } 3354 3355 static int 3356 alc_intr(void *arg) 3357 { 3358 struct alc_softc *sc; 3359 uint32_t status; 3360 3361 sc = (struct alc_softc *)arg; 3362 3363 if (sc->alc_flags & ALC_FLAG_MT) { 3364 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3365 return (FILTER_HANDLED); 3366 } 3367 3368 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3369 if ((status & ALC_INTRS) == 0) 3370 return (FILTER_STRAY); 3371 /* Disable interrupts. */ 3372 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3373 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3374 3375 return (FILTER_HANDLED); 3376 } 3377 3378 static void 3379 alc_int_task(void *arg, int pending) 3380 { 3381 struct alc_softc *sc; 3382 if_t ifp; 3383 uint32_t status; 3384 int more; 3385 3386 sc = (struct alc_softc *)arg; 3387 ifp = sc->alc_ifp; 3388 3389 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3390 ALC_LOCK(sc); 3391 if (sc->alc_morework != 0) { 3392 sc->alc_morework = 0; 3393 status |= INTR_RX_PKT; 3394 } 3395 if ((status & ALC_INTRS) == 0) 3396 goto done; 3397 3398 /* Acknowledge interrupts but still disable interrupts. */ 3399 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3400 3401 more = 0; 3402 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3403 if ((status & INTR_RX_PKT) != 0) { 3404 more = alc_rxintr(sc, sc->alc_process_limit); 3405 if (more == EAGAIN) 3406 sc->alc_morework = 1; 3407 else if (more == EIO) { 3408 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3409 alc_init_locked(sc); 3410 ALC_UNLOCK(sc); 3411 return; 3412 } 3413 } 3414 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3415 INTR_TXQ_TO_RST)) != 0) { 3416 if ((status & INTR_DMA_RD_TO_RST) != 0) 3417 device_printf(sc->alc_dev, 3418 "DMA read error! -- resetting\n"); 3419 if ((status & INTR_DMA_WR_TO_RST) != 0) 3420 device_printf(sc->alc_dev, 3421 "DMA write error! -- resetting\n"); 3422 if ((status & INTR_TXQ_TO_RST) != 0) 3423 device_printf(sc->alc_dev, 3424 "TxQ reset! -- resetting\n"); 3425 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3426 alc_init_locked(sc); 3427 ALC_UNLOCK(sc); 3428 return; 3429 } 3430 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 3431 !if_sendq_empty(ifp)) 3432 alc_start_locked(ifp); 3433 } 3434 3435 if (more == EAGAIN || 3436 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3437 ALC_UNLOCK(sc); 3438 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3439 return; 3440 } 3441 3442 done: 3443 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3444 /* Re-enable interrupts if we're running. */ 3445 if (sc->alc_flags & ALC_FLAG_MT) 3446 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3447 else 3448 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3449 } 3450 ALC_UNLOCK(sc); 3451 } 3452 3453 static void 3454 alc_txeof(struct alc_softc *sc) 3455 { 3456 if_t ifp; 3457 struct alc_txdesc *txd; 3458 uint32_t cons, prod; 3459 3460 ALC_LOCK_ASSERT(sc); 3461 3462 ifp = sc->alc_ifp; 3463 3464 if (sc->alc_cdata.alc_tx_cnt == 0) 3465 return; 3466 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3467 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3468 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3469 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3470 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3471 prod = sc->alc_rdata.alc_cmb->cons; 3472 } else { 3473 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3474 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3475 else { 3476 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3477 /* Assume we're using normal Tx priority queue. */ 3478 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3479 MBOX_TD_CONS_LO_IDX_SHIFT; 3480 } 3481 } 3482 cons = sc->alc_cdata.alc_tx_cons; 3483 /* 3484 * Go through our Tx list and free mbufs for those 3485 * frames which have been transmitted. 3486 */ 3487 for (; cons != prod; ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3488 if (sc->alc_cdata.alc_tx_cnt <= 0) 3489 break; 3490 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3491 sc->alc_cdata.alc_tx_cnt--; 3492 txd = &sc->alc_cdata.alc_txdesc[cons]; 3493 if (txd->tx_m != NULL) { 3494 /* Reclaim transmitted mbufs. */ 3495 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3496 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3497 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3498 txd->tx_dmamap); 3499 m_freem(txd->tx_m); 3500 txd->tx_m = NULL; 3501 } 3502 } 3503 3504 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3505 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3506 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3507 sc->alc_cdata.alc_tx_cons = cons; 3508 /* 3509 * Unarm watchdog timer only when there is no pending 3510 * frames in Tx queue. 3511 */ 3512 if (sc->alc_cdata.alc_tx_cnt == 0) 3513 sc->alc_watchdog_timer = 0; 3514 } 3515 3516 static int 3517 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3518 { 3519 struct mbuf *m; 3520 bus_dma_segment_t segs[1]; 3521 bus_dmamap_t map; 3522 int nsegs; 3523 3524 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3525 if (m == NULL) 3526 return (ENOBUFS); 3527 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3528 #ifndef __NO_STRICT_ALIGNMENT 3529 m_adj(m, sizeof(uint64_t)); 3530 #endif 3531 3532 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3533 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3534 m_freem(m); 3535 return (ENOBUFS); 3536 } 3537 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3538 3539 if (rxd->rx_m != NULL) { 3540 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3541 BUS_DMASYNC_POSTREAD); 3542 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3543 } 3544 map = rxd->rx_dmamap; 3545 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3546 sc->alc_cdata.alc_rx_sparemap = map; 3547 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3548 BUS_DMASYNC_PREREAD); 3549 rxd->rx_m = m; 3550 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3551 return (0); 3552 } 3553 3554 static int 3555 alc_rxintr(struct alc_softc *sc, int count) 3556 { 3557 if_t ifp; 3558 struct rx_rdesc *rrd; 3559 uint32_t nsegs, status; 3560 int rr_cons, prog; 3561 3562 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3563 sc->alc_cdata.alc_rr_ring_map, 3564 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3565 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3566 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3567 rr_cons = sc->alc_cdata.alc_rr_cons; 3568 ifp = sc->alc_ifp; 3569 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) { 3570 if (count-- <= 0) 3571 break; 3572 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3573 status = le32toh(rrd->status); 3574 if ((status & RRD_VALID) == 0) 3575 break; 3576 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3577 if (nsegs == 0) { 3578 /* This should not happen! */ 3579 device_printf(sc->alc_dev, 3580 "unexpected segment count -- resetting\n"); 3581 return (EIO); 3582 } 3583 alc_rxeof(sc, rrd); 3584 /* Clear Rx return status. */ 3585 rrd->status = 0; 3586 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3587 sc->alc_cdata.alc_rx_cons += nsegs; 3588 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3589 prog += nsegs; 3590 } 3591 3592 if (prog > 0) { 3593 /* Update the consumer index. */ 3594 sc->alc_cdata.alc_rr_cons = rr_cons; 3595 /* Sync Rx return descriptors. */ 3596 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3597 sc->alc_cdata.alc_rr_ring_map, 3598 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3599 /* 3600 * Sync updated Rx descriptors such that controller see 3601 * modified buffer addresses. 3602 */ 3603 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3604 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3605 /* 3606 * Let controller know availability of new Rx buffers. 3607 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3608 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3609 * only when Rx buffer pre-fetching is required. In 3610 * addition we already set ALC_RX_RD_FREE_THRESH to 3611 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3612 * it still seems that pre-fetching needs more 3613 * experimentation. 3614 */ 3615 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3616 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3617 (uint16_t)sc->alc_cdata.alc_rx_cons); 3618 else 3619 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3620 sc->alc_cdata.alc_rx_cons); 3621 } 3622 3623 return (count > 0 ? 0 : EAGAIN); 3624 } 3625 3626 #ifndef __NO_STRICT_ALIGNMENT 3627 static struct mbuf * 3628 alc_fixup_rx(if_t ifp, struct mbuf *m) 3629 { 3630 struct mbuf *n; 3631 int i; 3632 uint16_t *src, *dst; 3633 3634 src = mtod(m, uint16_t *); 3635 dst = src - 3; 3636 3637 if (m->m_next == NULL) { 3638 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3639 *dst++ = *src++; 3640 m->m_data -= 6; 3641 return (m); 3642 } 3643 /* 3644 * Append a new mbuf to received mbuf chain and copy ethernet 3645 * header from the mbuf chain. This can save lots of CPU 3646 * cycles for jumbo frame. 3647 */ 3648 MGETHDR(n, M_NOWAIT, MT_DATA); 3649 if (n == NULL) { 3650 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3651 m_freem(m); 3652 return (NULL); 3653 } 3654 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3655 m->m_data += ETHER_HDR_LEN; 3656 m->m_len -= ETHER_HDR_LEN; 3657 n->m_len = ETHER_HDR_LEN; 3658 M_MOVE_PKTHDR(n, m); 3659 n->m_next = m; 3660 return (n); 3661 } 3662 #endif 3663 3664 /* Receive a frame. */ 3665 static void 3666 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3667 { 3668 struct alc_rxdesc *rxd; 3669 if_t ifp; 3670 struct mbuf *mp, *m; 3671 uint32_t rdinfo, status, vtag; 3672 int count, nsegs, rx_cons; 3673 3674 ifp = sc->alc_ifp; 3675 status = le32toh(rrd->status); 3676 rdinfo = le32toh(rrd->rdinfo); 3677 rx_cons = RRD_RD_IDX(rdinfo); 3678 nsegs = RRD_RD_CNT(rdinfo); 3679 3680 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3681 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3682 /* 3683 * We want to pass the following frames to upper 3684 * layer regardless of error status of Rx return 3685 * ring. 3686 * 3687 * o IP/TCP/UDP checksum is bad. 3688 * o frame length and protocol specific length 3689 * does not match. 3690 * 3691 * Force network stack compute checksum for 3692 * errored frames. 3693 */ 3694 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3695 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3696 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3697 return; 3698 } 3699 3700 for (count = 0; count < nsegs; count++, 3701 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3702 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3703 mp = rxd->rx_m; 3704 /* Add a new receive buffer to the ring. */ 3705 if (alc_newbuf(sc, rxd) != 0) { 3706 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3707 /* Reuse Rx buffers. */ 3708 if (sc->alc_cdata.alc_rxhead != NULL) 3709 m_freem(sc->alc_cdata.alc_rxhead); 3710 break; 3711 } 3712 3713 /* 3714 * Assume we've received a full sized frame. 3715 * Actual size is fixed when we encounter the end of 3716 * multi-segmented frame. 3717 */ 3718 mp->m_len = sc->alc_buf_size; 3719 3720 /* Chain received mbufs. */ 3721 if (sc->alc_cdata.alc_rxhead == NULL) { 3722 sc->alc_cdata.alc_rxhead = mp; 3723 sc->alc_cdata.alc_rxtail = mp; 3724 } else { 3725 mp->m_flags &= ~M_PKTHDR; 3726 sc->alc_cdata.alc_rxprev_tail = 3727 sc->alc_cdata.alc_rxtail; 3728 sc->alc_cdata.alc_rxtail->m_next = mp; 3729 sc->alc_cdata.alc_rxtail = mp; 3730 } 3731 3732 if (count == nsegs - 1) { 3733 /* Last desc. for this frame. */ 3734 m = sc->alc_cdata.alc_rxhead; 3735 m->m_flags |= M_PKTHDR; 3736 /* 3737 * It seems that L1C/L2C controller has no way 3738 * to tell hardware to strip CRC bytes. 3739 */ 3740 m->m_pkthdr.len = 3741 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3742 if (nsegs > 1) { 3743 /* Set last mbuf size. */ 3744 mp->m_len = sc->alc_cdata.alc_rxlen - 3745 (nsegs - 1) * sc->alc_buf_size; 3746 /* Remove the CRC bytes in chained mbufs. */ 3747 if (mp->m_len <= ETHER_CRC_LEN) { 3748 sc->alc_cdata.alc_rxtail = 3749 sc->alc_cdata.alc_rxprev_tail; 3750 sc->alc_cdata.alc_rxtail->m_len -= 3751 (ETHER_CRC_LEN - mp->m_len); 3752 sc->alc_cdata.alc_rxtail->m_next = NULL; 3753 m_freem(mp); 3754 } else { 3755 mp->m_len -= ETHER_CRC_LEN; 3756 } 3757 } else 3758 m->m_len = m->m_pkthdr.len; 3759 m->m_pkthdr.rcvif = ifp; 3760 /* 3761 * Due to hardware bugs, Rx checksum offloading 3762 * was intentionally disabled. 3763 */ 3764 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 3765 (status & RRD_VLAN_TAG) != 0) { 3766 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3767 m->m_pkthdr.ether_vtag = ntohs(vtag); 3768 m->m_flags |= M_VLANTAG; 3769 } 3770 #ifndef __NO_STRICT_ALIGNMENT 3771 m = alc_fixup_rx(ifp, m); 3772 if (m != NULL) 3773 #endif 3774 { 3775 /* Pass it on. */ 3776 ALC_UNLOCK(sc); 3777 if_input(ifp, m); 3778 ALC_LOCK(sc); 3779 } 3780 } 3781 } 3782 /* Reset mbuf chains. */ 3783 ALC_RXCHAIN_RESET(sc); 3784 } 3785 3786 static void 3787 alc_tick(void *arg) 3788 { 3789 struct alc_softc *sc; 3790 struct mii_data *mii; 3791 3792 sc = (struct alc_softc *)arg; 3793 3794 ALC_LOCK_ASSERT(sc); 3795 3796 mii = device_get_softc(sc->alc_miibus); 3797 mii_tick(mii); 3798 alc_stats_update(sc); 3799 /* 3800 * alc(4) does not rely on Tx completion interrupts to reclaim 3801 * transferred buffers. Instead Tx completion interrupts are 3802 * used to hint for scheduling Tx task. So it's necessary to 3803 * release transmitted buffers by kicking Tx completion 3804 * handler. This limits the maximum reclamation delay to a hz. 3805 */ 3806 alc_txeof(sc); 3807 alc_watchdog(sc); 3808 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3809 } 3810 3811 static void 3812 alc_osc_reset(struct alc_softc *sc) 3813 { 3814 uint32_t reg; 3815 3816 reg = CSR_READ_4(sc, ALC_MISC3); 3817 reg &= ~MISC3_25M_BY_SW; 3818 reg |= MISC3_25M_NOTO_INTNL; 3819 CSR_WRITE_4(sc, ALC_MISC3, reg); 3820 3821 reg = CSR_READ_4(sc, ALC_MISC); 3822 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3823 /* 3824 * Restore over-current protection default value. 3825 * This value could be reset by MAC reset. 3826 */ 3827 reg &= ~MISC_PSW_OCP_MASK; 3828 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3829 reg &= ~MISC_INTNLOSC_OPEN; 3830 CSR_WRITE_4(sc, ALC_MISC, reg); 3831 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3832 reg = CSR_READ_4(sc, ALC_MISC2); 3833 reg &= ~MISC2_CALB_START; 3834 CSR_WRITE_4(sc, ALC_MISC2, reg); 3835 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3836 3837 } else { 3838 reg &= ~MISC_INTNLOSC_OPEN; 3839 /* Disable isolate for revision A devices. */ 3840 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3841 reg &= ~MISC_ISO_ENB; 3842 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3843 CSR_WRITE_4(sc, ALC_MISC, reg); 3844 } 3845 3846 DELAY(20); 3847 } 3848 3849 static void 3850 alc_reset(struct alc_softc *sc) 3851 { 3852 uint32_t pmcfg, reg; 3853 int i; 3854 3855 pmcfg = 0; 3856 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3857 /* Reset workaround. */ 3858 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3859 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3860 (sc->alc_rev & 0x01) != 0) { 3861 /* Disable L0s/L1s before reset. */ 3862 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3863 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3864 != 0) { 3865 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3866 PM_CFG_ASPM_L1_ENB); 3867 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3868 } 3869 } 3870 } 3871 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3872 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3873 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3874 3875 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3876 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3877 DELAY(10); 3878 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3879 break; 3880 } 3881 if (i == 0) 3882 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3883 } 3884 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3885 DELAY(10); 3886 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3887 break; 3888 } 3889 if (i == 0) 3890 device_printf(sc->alc_dev, "master reset timeout!\n"); 3891 3892 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3893 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3894 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3895 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3896 break; 3897 DELAY(10); 3898 } 3899 if (i == 0) 3900 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3901 3902 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3903 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3904 (sc->alc_rev & 0x01) != 0) { 3905 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3906 reg |= MASTER_CLK_SEL_DIS; 3907 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3908 /* Restore L0s/L1s config. */ 3909 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3910 != 0) 3911 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3912 } 3913 3914 alc_osc_reset(sc); 3915 reg = CSR_READ_4(sc, ALC_MISC3); 3916 reg &= ~MISC3_25M_BY_SW; 3917 reg |= MISC3_25M_NOTO_INTNL; 3918 CSR_WRITE_4(sc, ALC_MISC3, reg); 3919 reg = CSR_READ_4(sc, ALC_MISC); 3920 reg &= ~MISC_INTNLOSC_OPEN; 3921 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3922 reg &= ~MISC_ISO_ENB; 3923 CSR_WRITE_4(sc, ALC_MISC, reg); 3924 DELAY(20); 3925 } 3926 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3928 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3929 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3930 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3931 SERDES_PHY_CLK_SLOWDOWN); 3932 } 3933 3934 static void 3935 alc_init(void *xsc) 3936 { 3937 struct alc_softc *sc; 3938 3939 sc = (struct alc_softc *)xsc; 3940 ALC_LOCK(sc); 3941 alc_init_locked(sc); 3942 ALC_UNLOCK(sc); 3943 } 3944 3945 static void 3946 alc_init_locked(struct alc_softc *sc) 3947 { 3948 if_t ifp; 3949 uint8_t eaddr[ETHER_ADDR_LEN]; 3950 bus_addr_t paddr; 3951 uint32_t reg, rxf_hi, rxf_lo; 3952 3953 ALC_LOCK_ASSERT(sc); 3954 3955 ifp = sc->alc_ifp; 3956 3957 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3958 return; 3959 /* 3960 * Cancel any pending I/O. 3961 */ 3962 alc_stop(sc); 3963 /* 3964 * Reset the chip to a known state. 3965 */ 3966 alc_reset(sc); 3967 3968 /* Initialize Rx descriptors. */ 3969 if (alc_init_rx_ring(sc) != 0) { 3970 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3971 alc_stop(sc); 3972 return; 3973 } 3974 alc_init_rr_ring(sc); 3975 alc_init_tx_ring(sc); 3976 alc_init_cmb(sc); 3977 alc_init_smb(sc); 3978 3979 /* Enable all clocks. */ 3980 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3981 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3982 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3983 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3984 CLK_GATING_RXMAC_ENB); 3985 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3986 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3987 IDLE_DECISN_TIMER_DEFAULT_1MS); 3988 } else 3989 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3990 3991 /* Reprogram the station address. */ 3992 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 3993 CSR_WRITE_4(sc, ALC_PAR0, 3994 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3995 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3996 /* 3997 * Clear WOL status and disable all WOL feature as WOL 3998 * would interfere Rx operation under normal environments. 3999 */ 4000 CSR_READ_4(sc, ALC_WOL_CFG); 4001 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 4002 /* Set Tx descriptor base addresses. */ 4003 paddr = sc->alc_rdata.alc_tx_ring_paddr; 4004 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4005 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4006 /* We don't use high priority ring. */ 4007 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 4008 /* Set Tx descriptor counter. */ 4009 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 4010 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 4011 /* Set Rx descriptor base addresses. */ 4012 paddr = sc->alc_rdata.alc_rx_ring_paddr; 4013 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4014 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4015 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4016 /* We use one Rx ring. */ 4017 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4018 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4019 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4020 } 4021 /* Set Rx descriptor counter. */ 4022 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4023 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4024 4025 /* 4026 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4027 * if it do not fit the buffer size. Rx return descriptor holds 4028 * a counter that indicates how many fragments were made by the 4029 * hardware. The buffer size should be multiple of 8 bytes. 4030 * Since hardware has limit on the size of buffer size, always 4031 * use the maximum value. 4032 * For strict-alignment architectures make sure to reduce buffer 4033 * size by 8 bytes to make room for alignment fixup. 4034 */ 4035 #ifndef __NO_STRICT_ALIGNMENT 4036 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4037 #else 4038 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4039 #endif 4040 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4041 4042 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4043 /* Set Rx return descriptor base addresses. */ 4044 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4045 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4046 /* We use one Rx return ring. */ 4047 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4048 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4049 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4050 } 4051 /* Set Rx return descriptor counter. */ 4052 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4053 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4054 paddr = sc->alc_rdata.alc_cmb_paddr; 4055 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4056 paddr = sc->alc_rdata.alc_smb_paddr; 4057 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4058 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4059 4060 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4061 /* Reconfigure SRAM - Vendor magic. */ 4062 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4063 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4064 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4065 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4066 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4067 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4068 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4069 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4070 } 4071 4072 /* Tell hardware that we're ready to load DMA blocks. */ 4073 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4074 4075 /* Configure interrupt moderation timer. */ 4076 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4077 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4078 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4079 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4080 /* 4081 * We don't want to automatic interrupt clear as task queue 4082 * for the interrupt should know interrupt status. 4083 */ 4084 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4085 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4086 reg |= MASTER_SA_TIMER_ENB; 4087 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4088 reg |= MASTER_IM_RX_TIMER_ENB; 4089 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4090 ALC_USECS(sc->alc_int_tx_mod) != 0) 4091 reg |= MASTER_IM_TX_TIMER_ENB; 4092 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4093 /* 4094 * Disable interrupt re-trigger timer. We don't want automatic 4095 * re-triggering of un-ACKed interrupts. 4096 */ 4097 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4098 /* Configure CMB. */ 4099 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4100 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4101 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4102 ALC_USECS(sc->alc_int_tx_mod)); 4103 } else { 4104 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4105 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4106 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4107 } else 4108 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4109 } 4110 /* 4111 * Hardware can be configured to issue SMB interrupt based 4112 * on programmed interval. Since there is a callout that is 4113 * invoked for every hz in driver we use that instead of 4114 * relying on periodic SMB interrupt. 4115 */ 4116 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4117 /* Clear MAC statistics. */ 4118 alc_stats_clear(sc); 4119 4120 /* 4121 * Always use maximum frame size that controller can support. 4122 * Otherwise received frames that has larger frame length 4123 * than alc(4) MTU would be silently dropped in hardware. This 4124 * would make path-MTU discovery hard as sender wouldn't get 4125 * any responses from receiver. alc(4) supports 4126 * multi-fragmented frames on Rx path so it has no issue on 4127 * assembling fragmented frames. Using maximum frame size also 4128 * removes the need to reinitialize hardware when interface 4129 * MTU configuration was changed. 4130 * 4131 * Be conservative in what you do, be liberal in what you 4132 * accept from others - RFC 793. 4133 */ 4134 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4135 4136 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4137 /* Disable header split(?) */ 4138 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4139 4140 /* Configure IPG/IFG parameters. */ 4141 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4142 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4143 IPG_IFG_IPGT_MASK) | 4144 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4145 IPG_IFG_MIFG_MASK) | 4146 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4147 IPG_IFG_IPG1_MASK) | 4148 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4149 IPG_IFG_IPG2_MASK)); 4150 /* Set parameters for half-duplex media. */ 4151 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4152 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4153 HDPX_CFG_LCOL_MASK) | 4154 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4155 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4156 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4157 HDPX_CFG_ABEBT_MASK) | 4158 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4159 HDPX_CFG_JAMIPG_MASK)); 4160 } 4161 4162 /* 4163 * Set TSO/checksum offload threshold. For frames that is 4164 * larger than this threshold, hardware wouldn't do 4165 * TSO/checksum offloading. 4166 */ 4167 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4168 TSO_OFFLOAD_THRESH_MASK; 4169 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4170 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4171 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4172 /* Configure TxQ. */ 4173 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4174 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4175 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4176 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4177 reg >>= 1; 4178 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4179 TXQ_CFG_TD_BURST_MASK; 4180 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4181 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4182 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4183 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4184 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4185 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4186 HQTD_CFG_BURST_ENB); 4187 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4188 reg = WRR_PRI_RESTRICT_NONE; 4189 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4190 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4191 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4192 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4193 CSR_WRITE_4(sc, ALC_WRR, reg); 4194 } else { 4195 /* Configure Rx free descriptor pre-fetching. */ 4196 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4197 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4198 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4199 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4200 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4201 } 4202 4203 /* 4204 * Configure flow control parameters. 4205 * XON : 80% of Rx FIFO 4206 * XOFF : 30% of Rx FIFO 4207 */ 4208 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4209 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4210 reg &= SRAM_RX_FIFO_LEN_MASK; 4211 reg *= 8; 4212 if (reg > 8 * 1024) 4213 reg -= RX_FIFO_PAUSE_816X_RSVD; 4214 else 4215 reg -= RX_BUF_SIZE_MAX; 4216 reg /= 8; 4217 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4218 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4219 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4220 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4221 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4222 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4223 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4224 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4225 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4226 rxf_hi = (reg * 8) / 10; 4227 rxf_lo = (reg * 3) / 10; 4228 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4229 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4230 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4231 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4232 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4233 } 4234 4235 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4236 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4237 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4238 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4239 } 4240 4241 /* Configure RxQ. */ 4242 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4243 RXQ_CFG_RD_BURST_MASK; 4244 reg |= RXQ_CFG_RSS_MODE_DIS; 4245 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4246 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4247 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4248 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4249 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4250 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4251 } else { 4252 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4253 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4254 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4255 } 4256 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4257 4258 /* Configure DMA parameters. */ 4259 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4260 reg |= sc->alc_rcb; 4261 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4262 reg |= DMA_CFG_CMB_ENB; 4263 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4264 reg |= DMA_CFG_SMB_ENB; 4265 else 4266 reg |= DMA_CFG_SMB_DIS; 4267 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4268 DMA_CFG_RD_BURST_SHIFT; 4269 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4270 DMA_CFG_WR_BURST_SHIFT; 4271 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4272 DMA_CFG_RD_DELAY_CNT_MASK; 4273 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4274 DMA_CFG_WR_DELAY_CNT_MASK; 4275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4276 switch (AR816X_REV(sc->alc_rev)) { 4277 case AR816X_REV_A0: 4278 case AR816X_REV_A1: 4279 reg |= DMA_CFG_RD_CHNL_SEL_2; 4280 break; 4281 case AR816X_REV_B0: 4282 /* FALLTHROUGH */ 4283 default: 4284 reg |= DMA_CFG_RD_CHNL_SEL_4; 4285 break; 4286 } 4287 } 4288 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4289 4290 /* 4291 * Configure Tx/Rx MACs. 4292 * - Auto-padding for short frames. 4293 * - Enable CRC generation. 4294 * Actual reconfiguration of MAC for resolved speed/duplex 4295 * is followed after detection of link establishment. 4296 * AR813x/AR815x always does checksum computation regardless 4297 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4298 * have bug in protocol field in Rx return structure so 4299 * these controllers can't handle fragmented frames. Disable 4300 * Rx checksum offloading until there is a newer controller 4301 * that has sane implementation. 4302 */ 4303 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4304 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4305 MAC_CFG_PREAMBLE_MASK); 4306 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4307 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4308 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4309 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4310 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4311 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4312 reg |= MAC_CFG_SPEED_10_100; 4313 else 4314 reg |= MAC_CFG_SPEED_1000; 4315 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4316 4317 /* Set up the receive filter. */ 4318 alc_rxfilter(sc); 4319 alc_rxvlan(sc); 4320 4321 /* Acknowledge all pending interrupts and clear it. */ 4322 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4323 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4324 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4325 4326 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4327 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4328 4329 sc->alc_flags &= ~ALC_FLAG_LINK; 4330 /* Switch to the current media. */ 4331 alc_mediachange_locked(sc); 4332 4333 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4334 } 4335 4336 static void 4337 alc_stop(struct alc_softc *sc) 4338 { 4339 if_t ifp; 4340 struct alc_txdesc *txd; 4341 struct alc_rxdesc *rxd; 4342 uint32_t reg; 4343 int i; 4344 4345 ALC_LOCK_ASSERT(sc); 4346 /* 4347 * Mark the interface down and cancel the watchdog timer. 4348 */ 4349 ifp = sc->alc_ifp; 4350 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4351 sc->alc_flags &= ~ALC_FLAG_LINK; 4352 callout_stop(&sc->alc_tick_ch); 4353 sc->alc_watchdog_timer = 0; 4354 alc_stats_update(sc); 4355 /* Disable interrupts. */ 4356 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4357 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4358 /* Disable DMA. */ 4359 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4360 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4361 reg |= DMA_CFG_SMB_DIS; 4362 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4363 DELAY(1000); 4364 /* Stop Rx/Tx MACs. */ 4365 alc_stop_mac(sc); 4366 /* Disable interrupts which might be touched in taskq handler. */ 4367 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4368 /* Disable L0s/L1s */ 4369 alc_aspm(sc, 0, IFM_UNKNOWN); 4370 /* Reclaim Rx buffers that have been processed. */ 4371 if (sc->alc_cdata.alc_rxhead != NULL) 4372 m_freem(sc->alc_cdata.alc_rxhead); 4373 ALC_RXCHAIN_RESET(sc); 4374 /* 4375 * Free Tx/Rx mbufs still in the queues. 4376 */ 4377 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4378 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4379 if (rxd->rx_m != NULL) { 4380 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4381 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4382 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4383 rxd->rx_dmamap); 4384 m_freem(rxd->rx_m); 4385 rxd->rx_m = NULL; 4386 } 4387 } 4388 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4389 txd = &sc->alc_cdata.alc_txdesc[i]; 4390 if (txd->tx_m != NULL) { 4391 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4392 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4393 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4394 txd->tx_dmamap); 4395 m_freem(txd->tx_m); 4396 txd->tx_m = NULL; 4397 } 4398 } 4399 } 4400 4401 static void 4402 alc_stop_mac(struct alc_softc *sc) 4403 { 4404 uint32_t reg; 4405 int i; 4406 4407 alc_stop_queue(sc); 4408 /* Disable Rx/Tx MAC. */ 4409 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4410 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4411 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4412 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4413 } 4414 for (i = ALC_TIMEOUT; i > 0; i--) { 4415 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4416 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4417 break; 4418 DELAY(10); 4419 } 4420 if (i == 0) 4421 device_printf(sc->alc_dev, 4422 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4423 } 4424 4425 static void 4426 alc_start_queue(struct alc_softc *sc) 4427 { 4428 uint32_t qcfg[] = { 4429 0, 4430 RXQ_CFG_QUEUE0_ENB, 4431 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4432 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4433 RXQ_CFG_ENB 4434 }; 4435 uint32_t cfg; 4436 4437 ALC_LOCK_ASSERT(sc); 4438 4439 /* Enable RxQ. */ 4440 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4441 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4442 cfg &= ~RXQ_CFG_ENB; 4443 cfg |= qcfg[1]; 4444 } else 4445 cfg |= RXQ_CFG_QUEUE0_ENB; 4446 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4447 /* Enable TxQ. */ 4448 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4449 cfg |= TXQ_CFG_ENB; 4450 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4451 } 4452 4453 static void 4454 alc_stop_queue(struct alc_softc *sc) 4455 { 4456 uint32_t reg; 4457 int i; 4458 4459 /* Disable RxQ. */ 4460 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4461 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4462 if ((reg & RXQ_CFG_ENB) != 0) { 4463 reg &= ~RXQ_CFG_ENB; 4464 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4465 } 4466 } else { 4467 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4468 reg &= ~RXQ_CFG_QUEUE0_ENB; 4469 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4470 } 4471 } 4472 /* Disable TxQ. */ 4473 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4474 if ((reg & TXQ_CFG_ENB) != 0) { 4475 reg &= ~TXQ_CFG_ENB; 4476 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4477 } 4478 DELAY(40); 4479 for (i = ALC_TIMEOUT; i > 0; i--) { 4480 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4481 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4482 break; 4483 DELAY(10); 4484 } 4485 if (i == 0) 4486 device_printf(sc->alc_dev, 4487 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4488 } 4489 4490 static void 4491 alc_init_tx_ring(struct alc_softc *sc) 4492 { 4493 struct alc_ring_data *rd; 4494 struct alc_txdesc *txd; 4495 int i; 4496 4497 ALC_LOCK_ASSERT(sc); 4498 4499 sc->alc_cdata.alc_tx_prod = 0; 4500 sc->alc_cdata.alc_tx_cons = 0; 4501 sc->alc_cdata.alc_tx_cnt = 0; 4502 4503 rd = &sc->alc_rdata; 4504 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4505 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4506 txd = &sc->alc_cdata.alc_txdesc[i]; 4507 txd->tx_m = NULL; 4508 } 4509 4510 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4511 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4512 } 4513 4514 static int 4515 alc_init_rx_ring(struct alc_softc *sc) 4516 { 4517 struct alc_ring_data *rd; 4518 struct alc_rxdesc *rxd; 4519 int i; 4520 4521 ALC_LOCK_ASSERT(sc); 4522 4523 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4524 sc->alc_morework = 0; 4525 rd = &sc->alc_rdata; 4526 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4527 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4528 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4529 rxd->rx_m = NULL; 4530 rxd->rx_desc = &rd->alc_rx_ring[i]; 4531 if (alc_newbuf(sc, rxd) != 0) 4532 return (ENOBUFS); 4533 } 4534 4535 /* 4536 * Since controller does not update Rx descriptors, driver 4537 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4538 * is enough to ensure coherence. 4539 */ 4540 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4541 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4542 /* Let controller know availability of new Rx buffers. */ 4543 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4544 4545 return (0); 4546 } 4547 4548 static void 4549 alc_init_rr_ring(struct alc_softc *sc) 4550 { 4551 struct alc_ring_data *rd; 4552 4553 ALC_LOCK_ASSERT(sc); 4554 4555 sc->alc_cdata.alc_rr_cons = 0; 4556 ALC_RXCHAIN_RESET(sc); 4557 4558 rd = &sc->alc_rdata; 4559 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4560 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4561 sc->alc_cdata.alc_rr_ring_map, 4562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4563 } 4564 4565 static void 4566 alc_init_cmb(struct alc_softc *sc) 4567 { 4568 struct alc_ring_data *rd; 4569 4570 ALC_LOCK_ASSERT(sc); 4571 4572 rd = &sc->alc_rdata; 4573 bzero(rd->alc_cmb, ALC_CMB_SZ); 4574 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4576 } 4577 4578 static void 4579 alc_init_smb(struct alc_softc *sc) 4580 { 4581 struct alc_ring_data *rd; 4582 4583 ALC_LOCK_ASSERT(sc); 4584 4585 rd = &sc->alc_rdata; 4586 bzero(rd->alc_smb, ALC_SMB_SZ); 4587 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4588 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4589 } 4590 4591 static void 4592 alc_rxvlan(struct alc_softc *sc) 4593 { 4594 if_t ifp; 4595 uint32_t reg; 4596 4597 ALC_LOCK_ASSERT(sc); 4598 4599 ifp = sc->alc_ifp; 4600 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4601 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 4602 reg |= MAC_CFG_VLAN_TAG_STRIP; 4603 else 4604 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4605 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4606 } 4607 4608 static u_int 4609 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4610 { 4611 uint32_t *mchash = arg; 4612 uint32_t crc; 4613 4614 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4615 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4616 4617 return (1); 4618 } 4619 4620 static void 4621 alc_rxfilter(struct alc_softc *sc) 4622 { 4623 if_t ifp; 4624 uint32_t mchash[2]; 4625 uint32_t rxcfg; 4626 4627 ALC_LOCK_ASSERT(sc); 4628 4629 ifp = sc->alc_ifp; 4630 4631 bzero(mchash, sizeof(mchash)); 4632 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4633 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4634 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 4635 rxcfg |= MAC_CFG_BCAST; 4636 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4637 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 4638 rxcfg |= MAC_CFG_PROMISC; 4639 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 4640 rxcfg |= MAC_CFG_ALLMULTI; 4641 mchash[0] = 0xFFFFFFFF; 4642 mchash[1] = 0xFFFFFFFF; 4643 goto chipit; 4644 } 4645 4646 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4647 4648 chipit: 4649 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4650 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4651 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4652 } 4653 4654 static int 4655 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4656 { 4657 int error, value; 4658 4659 if (arg1 == NULL) 4660 return (EINVAL); 4661 value = *(int *)arg1; 4662 error = sysctl_handle_int(oidp, &value, 0, req); 4663 if (error || req->newptr == NULL) 4664 return (error); 4665 if (value < low || value > high) 4666 return (EINVAL); 4667 *(int *)arg1 = value; 4668 4669 return (0); 4670 } 4671 4672 static int 4673 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4674 { 4675 return (sysctl_int_range(oidp, arg1, arg2, req, 4676 ALC_PROC_MIN, ALC_PROC_MAX)); 4677 } 4678 4679 static int 4680 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4681 { 4682 4683 return (sysctl_int_range(oidp, arg1, arg2, req, 4684 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4685 } 4686 4687 #ifdef DEBUGNET 4688 static void 4689 alc_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4690 { 4691 struct alc_softc *sc __diagused; 4692 4693 sc = if_getsoftc(ifp); 4694 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4695 4696 *nrxr = ALC_RX_RING_CNT; 4697 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4698 *clsize = MCLBYTES; 4699 } 4700 4701 static void 4702 alc_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4703 { 4704 } 4705 4706 static int 4707 alc_debugnet_transmit(if_t ifp, struct mbuf *m) 4708 { 4709 struct alc_softc *sc; 4710 int error; 4711 4712 sc = if_getsoftc(ifp); 4713 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4714 IFF_DRV_RUNNING) 4715 return (EBUSY); 4716 4717 error = alc_encap(sc, &m); 4718 if (error == 0) 4719 alc_start_tx(sc); 4720 return (error); 4721 } 4722 4723 static int 4724 alc_debugnet_poll(if_t ifp, int count) 4725 { 4726 struct alc_softc *sc; 4727 4728 sc = if_getsoftc(ifp); 4729 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4730 IFF_DRV_RUNNING) 4731 return (EBUSY); 4732 4733 alc_txeof(sc); 4734 return (alc_rxintr(sc, count)); 4735 } 4736 #endif /* DEBUGNET */ 4737