1d68875ebSPyun YongHyeon /*- 2d68875ebSPyun YongHyeon * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3d68875ebSPyun YongHyeon * All rights reserved. 4d68875ebSPyun YongHyeon * 5d68875ebSPyun YongHyeon * Redistribution and use in source and binary forms, with or without 6d68875ebSPyun YongHyeon * modification, are permitted provided that the following conditions 7d68875ebSPyun YongHyeon * are met: 8d68875ebSPyun YongHyeon * 1. Redistributions of source code must retain the above copyright 9d68875ebSPyun YongHyeon * notice unmodified, this list of conditions, and the following 10d68875ebSPyun YongHyeon * disclaimer. 11d68875ebSPyun YongHyeon * 2. Redistributions in binary form must reproduce the above copyright 12d68875ebSPyun YongHyeon * notice, this list of conditions and the following disclaimer in the 13d68875ebSPyun YongHyeon * documentation and/or other materials provided with the distribution. 14d68875ebSPyun YongHyeon * 15d68875ebSPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16d68875ebSPyun YongHyeon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17d68875ebSPyun YongHyeon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18d68875ebSPyun YongHyeon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19d68875ebSPyun YongHyeon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20d68875ebSPyun YongHyeon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21d68875ebSPyun YongHyeon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22d68875ebSPyun YongHyeon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23d68875ebSPyun YongHyeon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24d68875ebSPyun YongHyeon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25d68875ebSPyun YongHyeon * SUCH DAMAGE. 26d68875ebSPyun YongHyeon */ 27d68875ebSPyun YongHyeon 282f70cceaSPyun YongHyeon /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29d68875ebSPyun YongHyeon 30d68875ebSPyun YongHyeon #include <sys/cdefs.h> 31d68875ebSPyun YongHyeon __FBSDID("$FreeBSD$"); 32d68875ebSPyun YongHyeon 33d68875ebSPyun YongHyeon #include <sys/param.h> 34d68875ebSPyun YongHyeon #include <sys/systm.h> 35d68875ebSPyun YongHyeon #include <sys/bus.h> 36d68875ebSPyun YongHyeon #include <sys/endian.h> 37d68875ebSPyun YongHyeon #include <sys/kernel.h> 38d68875ebSPyun YongHyeon #include <sys/lock.h> 39d68875ebSPyun YongHyeon #include <sys/malloc.h> 40d68875ebSPyun YongHyeon #include <sys/mbuf.h> 41d68875ebSPyun YongHyeon #include <sys/module.h> 42d68875ebSPyun YongHyeon #include <sys/mutex.h> 43d68875ebSPyun YongHyeon #include <sys/rman.h> 44d68875ebSPyun YongHyeon #include <sys/queue.h> 45d68875ebSPyun YongHyeon #include <sys/socket.h> 46d68875ebSPyun YongHyeon #include <sys/sockio.h> 47d68875ebSPyun YongHyeon #include <sys/sysctl.h> 48d68875ebSPyun YongHyeon #include <sys/taskqueue.h> 49d68875ebSPyun YongHyeon 50d68875ebSPyun YongHyeon #include <net/bpf.h> 51d68875ebSPyun YongHyeon #include <net/if.h> 52d68875ebSPyun YongHyeon #include <net/if_arp.h> 53d68875ebSPyun YongHyeon #include <net/ethernet.h> 54d68875ebSPyun YongHyeon #include <net/if_dl.h> 55d68875ebSPyun YongHyeon #include <net/if_llc.h> 56d68875ebSPyun YongHyeon #include <net/if_media.h> 57d68875ebSPyun YongHyeon #include <net/if_types.h> 58d68875ebSPyun YongHyeon #include <net/if_vlan_var.h> 59d68875ebSPyun YongHyeon 60d68875ebSPyun YongHyeon #include <netinet/in.h> 61d68875ebSPyun YongHyeon #include <netinet/in_systm.h> 62d68875ebSPyun YongHyeon #include <netinet/ip.h> 63d68875ebSPyun YongHyeon #include <netinet/tcp.h> 64d68875ebSPyun YongHyeon 65d68875ebSPyun YongHyeon #include <dev/mii/mii.h> 66d68875ebSPyun YongHyeon #include <dev/mii/miivar.h> 67d68875ebSPyun YongHyeon 68d68875ebSPyun YongHyeon #include <dev/pci/pcireg.h> 69d68875ebSPyun YongHyeon #include <dev/pci/pcivar.h> 70d68875ebSPyun YongHyeon 71d68875ebSPyun YongHyeon #include <machine/bus.h> 72d68875ebSPyun YongHyeon #include <machine/in_cksum.h> 73d68875ebSPyun YongHyeon 74d68875ebSPyun YongHyeon #include <dev/alc/if_alcreg.h> 75d68875ebSPyun YongHyeon #include <dev/alc/if_alcvar.h> 76d68875ebSPyun YongHyeon 77d68875ebSPyun YongHyeon /* "device miibus" required. See GENERIC if you get errors here. */ 78d68875ebSPyun YongHyeon #include "miibus_if.h" 79d68875ebSPyun YongHyeon #undef ALC_USE_CUSTOM_CSUM 80d68875ebSPyun YongHyeon 81d68875ebSPyun YongHyeon #ifdef ALC_USE_CUSTOM_CSUM 82d68875ebSPyun YongHyeon #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83d68875ebSPyun YongHyeon #else 84d68875ebSPyun YongHyeon #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85d68875ebSPyun YongHyeon #endif 86d68875ebSPyun YongHyeon 87d68875ebSPyun YongHyeon MODULE_DEPEND(alc, pci, 1, 1, 1); 88d68875ebSPyun YongHyeon MODULE_DEPEND(alc, ether, 1, 1, 1); 89d68875ebSPyun YongHyeon MODULE_DEPEND(alc, miibus, 1, 1, 1); 90d68875ebSPyun YongHyeon 91d68875ebSPyun YongHyeon /* Tunables. */ 92d68875ebSPyun YongHyeon static int msi_disable = 0; 93d68875ebSPyun YongHyeon static int msix_disable = 0; 94d68875ebSPyun YongHyeon TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95d68875ebSPyun YongHyeon TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96d68875ebSPyun YongHyeon 97d68875ebSPyun YongHyeon /* 98d68875ebSPyun YongHyeon * Devices supported by this driver. 99d68875ebSPyun YongHyeon */ 1002f70cceaSPyun YongHyeon static struct alc_ident alc_ident_table[] = { 1012f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102d68875ebSPyun YongHyeon "Atheros AR8131 PCIe Gigabit Ethernet" }, 1032f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 1042f70cceaSPyun YongHyeon "Atheros AR8132 PCIe Fast Ethernet" }, 1052f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 1062f70cceaSPyun YongHyeon "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 1072f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 1082f70cceaSPyun YongHyeon "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 1092f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 1102f70cceaSPyun YongHyeon "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 1112f70cceaSPyun YongHyeon { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 1122f70cceaSPyun YongHyeon "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 1132f70cceaSPyun YongHyeon { 0, 0, 0, NULL} 114d68875ebSPyun YongHyeon }; 115d68875ebSPyun YongHyeon 1162f70cceaSPyun YongHyeon static void alc_aspm(struct alc_softc *, int); 117d68875ebSPyun YongHyeon static int alc_attach(device_t); 118d68875ebSPyun YongHyeon static int alc_check_boundary(struct alc_softc *); 119d68875ebSPyun YongHyeon static int alc_detach(device_t); 120d68875ebSPyun YongHyeon static void alc_disable_l0s_l1(struct alc_softc *); 121d68875ebSPyun YongHyeon static int alc_dma_alloc(struct alc_softc *); 122d68875ebSPyun YongHyeon static void alc_dma_free(struct alc_softc *); 123d68875ebSPyun YongHyeon static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 124d68875ebSPyun YongHyeon static int alc_encap(struct alc_softc *, struct mbuf **); 1252f70cceaSPyun YongHyeon static struct alc_ident * 1262f70cceaSPyun YongHyeon alc_find_ident(device_t); 127d68875ebSPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 128d68875ebSPyun YongHyeon static struct mbuf * 129d68875ebSPyun YongHyeon alc_fixup_rx(struct ifnet *, struct mbuf *); 130d68875ebSPyun YongHyeon #endif 131d68875ebSPyun YongHyeon static void alc_get_macaddr(struct alc_softc *); 132d68875ebSPyun YongHyeon static void alc_init(void *); 133d68875ebSPyun YongHyeon static void alc_init_cmb(struct alc_softc *); 134d68875ebSPyun YongHyeon static void alc_init_locked(struct alc_softc *); 135d68875ebSPyun YongHyeon static void alc_init_rr_ring(struct alc_softc *); 136d68875ebSPyun YongHyeon static int alc_init_rx_ring(struct alc_softc *); 137d68875ebSPyun YongHyeon static void alc_init_smb(struct alc_softc *); 138d68875ebSPyun YongHyeon static void alc_init_tx_ring(struct alc_softc *); 139d68875ebSPyun YongHyeon static void alc_int_task(void *, int); 140d68875ebSPyun YongHyeon static int alc_intr(void *); 141d68875ebSPyun YongHyeon static int alc_ioctl(struct ifnet *, u_long, caddr_t); 142d68875ebSPyun YongHyeon static void alc_mac_config(struct alc_softc *); 143d68875ebSPyun YongHyeon static int alc_miibus_readreg(device_t, int, int); 144d68875ebSPyun YongHyeon static void alc_miibus_statchg(device_t); 145d68875ebSPyun YongHyeon static int alc_miibus_writereg(device_t, int, int, int); 146d68875ebSPyun YongHyeon static int alc_mediachange(struct ifnet *); 147d68875ebSPyun YongHyeon static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 148d68875ebSPyun YongHyeon static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 149d68875ebSPyun YongHyeon static void alc_phy_down(struct alc_softc *); 150d68875ebSPyun YongHyeon static void alc_phy_reset(struct alc_softc *); 151d68875ebSPyun YongHyeon static int alc_probe(device_t); 152d68875ebSPyun YongHyeon static void alc_reset(struct alc_softc *); 153d68875ebSPyun YongHyeon static int alc_resume(device_t); 154d68875ebSPyun YongHyeon static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 155d68875ebSPyun YongHyeon static int alc_rxintr(struct alc_softc *, int); 156d68875ebSPyun YongHyeon static void alc_rxfilter(struct alc_softc *); 157d68875ebSPyun YongHyeon static void alc_rxvlan(struct alc_softc *); 158d68875ebSPyun YongHyeon static void alc_setlinkspeed(struct alc_softc *); 159d68875ebSPyun YongHyeon static void alc_setwol(struct alc_softc *); 160d68875ebSPyun YongHyeon static int alc_shutdown(device_t); 161d68875ebSPyun YongHyeon static void alc_start(struct ifnet *); 162d68875ebSPyun YongHyeon static void alc_start_queue(struct alc_softc *); 163d68875ebSPyun YongHyeon static void alc_stats_clear(struct alc_softc *); 164d68875ebSPyun YongHyeon static void alc_stats_update(struct alc_softc *); 165d68875ebSPyun YongHyeon static void alc_stop(struct alc_softc *); 166d68875ebSPyun YongHyeon static void alc_stop_mac(struct alc_softc *); 167d68875ebSPyun YongHyeon static void alc_stop_queue(struct alc_softc *); 168d68875ebSPyun YongHyeon static int alc_suspend(device_t); 169d68875ebSPyun YongHyeon static void alc_sysctl_node(struct alc_softc *); 170d68875ebSPyun YongHyeon static void alc_tick(void *); 171d68875ebSPyun YongHyeon static void alc_tx_task(void *, int); 172d68875ebSPyun YongHyeon static void alc_txeof(struct alc_softc *); 173d68875ebSPyun YongHyeon static void alc_watchdog(struct alc_softc *); 174d68875ebSPyun YongHyeon static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 175d68875ebSPyun YongHyeon static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 176d68875ebSPyun YongHyeon static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 177d68875ebSPyun YongHyeon 178d68875ebSPyun YongHyeon static device_method_t alc_methods[] = { 179d68875ebSPyun YongHyeon /* Device interface. */ 180d68875ebSPyun YongHyeon DEVMETHOD(device_probe, alc_probe), 181d68875ebSPyun YongHyeon DEVMETHOD(device_attach, alc_attach), 182d68875ebSPyun YongHyeon DEVMETHOD(device_detach, alc_detach), 183d68875ebSPyun YongHyeon DEVMETHOD(device_shutdown, alc_shutdown), 184d68875ebSPyun YongHyeon DEVMETHOD(device_suspend, alc_suspend), 185d68875ebSPyun YongHyeon DEVMETHOD(device_resume, alc_resume), 186d68875ebSPyun YongHyeon 187d68875ebSPyun YongHyeon /* MII interface. */ 188d68875ebSPyun YongHyeon DEVMETHOD(miibus_readreg, alc_miibus_readreg), 189d68875ebSPyun YongHyeon DEVMETHOD(miibus_writereg, alc_miibus_writereg), 190d68875ebSPyun YongHyeon DEVMETHOD(miibus_statchg, alc_miibus_statchg), 191d68875ebSPyun YongHyeon 192d68875ebSPyun YongHyeon { NULL, NULL } 193d68875ebSPyun YongHyeon }; 194d68875ebSPyun YongHyeon 195d68875ebSPyun YongHyeon static driver_t alc_driver = { 196d68875ebSPyun YongHyeon "alc", 197d68875ebSPyun YongHyeon alc_methods, 198d68875ebSPyun YongHyeon sizeof(struct alc_softc) 199d68875ebSPyun YongHyeon }; 200d68875ebSPyun YongHyeon 201d68875ebSPyun YongHyeon static devclass_t alc_devclass; 202d68875ebSPyun YongHyeon 203d68875ebSPyun YongHyeon DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 204d68875ebSPyun YongHyeon DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 205d68875ebSPyun YongHyeon 206d68875ebSPyun YongHyeon static struct resource_spec alc_res_spec_mem[] = { 207d68875ebSPyun YongHyeon { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 208d68875ebSPyun YongHyeon { -1, 0, 0 } 209d68875ebSPyun YongHyeon }; 210d68875ebSPyun YongHyeon 211d68875ebSPyun YongHyeon static struct resource_spec alc_irq_spec_legacy[] = { 212d68875ebSPyun YongHyeon { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 213d68875ebSPyun YongHyeon { -1, 0, 0 } 214d68875ebSPyun YongHyeon }; 215d68875ebSPyun YongHyeon 216d68875ebSPyun YongHyeon static struct resource_spec alc_irq_spec_msi[] = { 217d68875ebSPyun YongHyeon { SYS_RES_IRQ, 1, RF_ACTIVE }, 218d68875ebSPyun YongHyeon { -1, 0, 0 } 219d68875ebSPyun YongHyeon }; 220d68875ebSPyun YongHyeon 221d68875ebSPyun YongHyeon static struct resource_spec alc_irq_spec_msix[] = { 222d68875ebSPyun YongHyeon { SYS_RES_IRQ, 1, RF_ACTIVE }, 223d68875ebSPyun YongHyeon { -1, 0, 0 } 224d68875ebSPyun YongHyeon }; 225d68875ebSPyun YongHyeon 226d68875ebSPyun YongHyeon static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 227d68875ebSPyun YongHyeon 228d68875ebSPyun YongHyeon static int 229d68875ebSPyun YongHyeon alc_miibus_readreg(device_t dev, int phy, int reg) 230d68875ebSPyun YongHyeon { 231d68875ebSPyun YongHyeon struct alc_softc *sc; 232d68875ebSPyun YongHyeon uint32_t v; 233d68875ebSPyun YongHyeon int i; 234d68875ebSPyun YongHyeon 235d68875ebSPyun YongHyeon sc = device_get_softc(dev); 236d68875ebSPyun YongHyeon 237e3413501SPyun YongHyeon /* 238e3413501SPyun YongHyeon * For AR8132 fast ethernet controller, do not report 1000baseT 239e3413501SPyun YongHyeon * capability to mii(4). Even though AR8132 uses the same 240e3413501SPyun YongHyeon * model/revision number of F1 gigabit PHY, the PHY has no 241e3413501SPyun YongHyeon * ability to establish 1000baseT link. 242e3413501SPyun YongHyeon */ 243e3413501SPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 244e3413501SPyun YongHyeon reg == MII_EXTSR) 245e3413501SPyun YongHyeon return (0); 246e3413501SPyun YongHyeon 247d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248d68875ebSPyun YongHyeon MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249d68875ebSPyun YongHyeon for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250d68875ebSPyun YongHyeon DELAY(5); 251d68875ebSPyun YongHyeon v = CSR_READ_4(sc, ALC_MDIO); 252d68875ebSPyun YongHyeon if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253d68875ebSPyun YongHyeon break; 254d68875ebSPyun YongHyeon } 255d68875ebSPyun YongHyeon 256d68875ebSPyun YongHyeon if (i == 0) { 257d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 258d68875ebSPyun YongHyeon return (0); 259d68875ebSPyun YongHyeon } 260d68875ebSPyun YongHyeon 261d68875ebSPyun YongHyeon return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262d68875ebSPyun YongHyeon } 263d68875ebSPyun YongHyeon 264d68875ebSPyun YongHyeon static int 265d68875ebSPyun YongHyeon alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266d68875ebSPyun YongHyeon { 267d68875ebSPyun YongHyeon struct alc_softc *sc; 268d68875ebSPyun YongHyeon uint32_t v; 269d68875ebSPyun YongHyeon int i; 270d68875ebSPyun YongHyeon 271d68875ebSPyun YongHyeon sc = device_get_softc(dev); 272d68875ebSPyun YongHyeon 273d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274d68875ebSPyun YongHyeon (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275d68875ebSPyun YongHyeon MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276d68875ebSPyun YongHyeon for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277d68875ebSPyun YongHyeon DELAY(5); 278d68875ebSPyun YongHyeon v = CSR_READ_4(sc, ALC_MDIO); 279d68875ebSPyun YongHyeon if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280d68875ebSPyun YongHyeon break; 281d68875ebSPyun YongHyeon } 282d68875ebSPyun YongHyeon 283d68875ebSPyun YongHyeon if (i == 0) 284d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285d68875ebSPyun YongHyeon 286d68875ebSPyun YongHyeon return (0); 287d68875ebSPyun YongHyeon } 288d68875ebSPyun YongHyeon 289d68875ebSPyun YongHyeon static void 290d68875ebSPyun YongHyeon alc_miibus_statchg(device_t dev) 291d68875ebSPyun YongHyeon { 292d68875ebSPyun YongHyeon struct alc_softc *sc; 293d68875ebSPyun YongHyeon struct mii_data *mii; 294d68875ebSPyun YongHyeon struct ifnet *ifp; 295d68875ebSPyun YongHyeon uint32_t reg; 296d68875ebSPyun YongHyeon 297d68875ebSPyun YongHyeon sc = device_get_softc(dev); 298d68875ebSPyun YongHyeon 299d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 300d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 301d68875ebSPyun YongHyeon if (mii == NULL || ifp == NULL || 302d68875ebSPyun YongHyeon (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303d68875ebSPyun YongHyeon return; 304d68875ebSPyun YongHyeon 305d68875ebSPyun YongHyeon sc->alc_flags &= ~ALC_FLAG_LINK; 306d68875ebSPyun YongHyeon if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307d68875ebSPyun YongHyeon (IFM_ACTIVE | IFM_AVALID)) { 308d68875ebSPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 309d68875ebSPyun YongHyeon case IFM_10_T: 310d68875ebSPyun YongHyeon case IFM_100_TX: 311d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_LINK; 312d68875ebSPyun YongHyeon break; 313d68875ebSPyun YongHyeon case IFM_1000_T: 314d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_LINK; 316d68875ebSPyun YongHyeon break; 317d68875ebSPyun YongHyeon default: 318d68875ebSPyun YongHyeon break; 319d68875ebSPyun YongHyeon } 320d68875ebSPyun YongHyeon } 321d68875ebSPyun YongHyeon alc_stop_queue(sc); 322d68875ebSPyun YongHyeon /* Stop Rx/Tx MACs. */ 323d68875ebSPyun YongHyeon alc_stop_mac(sc); 324d68875ebSPyun YongHyeon 325d68875ebSPyun YongHyeon /* Program MACs with resolved speed/duplex/flow-control. */ 326d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327d68875ebSPyun YongHyeon alc_start_queue(sc); 328d68875ebSPyun YongHyeon alc_mac_config(sc); 329d68875ebSPyun YongHyeon /* Re-enable Tx/Rx MACs. */ 330d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MAC_CFG); 331d68875ebSPyun YongHyeon reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3332f70cceaSPyun YongHyeon alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 334d68875ebSPyun YongHyeon } 335d0b2f7efSPyun YongHyeon } 336d68875ebSPyun YongHyeon 337d68875ebSPyun YongHyeon static void 338d68875ebSPyun YongHyeon alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339d68875ebSPyun YongHyeon { 340d68875ebSPyun YongHyeon struct alc_softc *sc; 341d68875ebSPyun YongHyeon struct mii_data *mii; 342d68875ebSPyun YongHyeon 343d68875ebSPyun YongHyeon sc = ifp->if_softc; 344d68875ebSPyun YongHyeon ALC_LOCK(sc); 345d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_UP) == 0) { 346d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 347d68875ebSPyun YongHyeon return; 348d68875ebSPyun YongHyeon } 349d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 350d68875ebSPyun YongHyeon 351d68875ebSPyun YongHyeon mii_pollstat(mii); 352d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 353d68875ebSPyun YongHyeon ifmr->ifm_status = mii->mii_media_status; 354d68875ebSPyun YongHyeon ifmr->ifm_active = mii->mii_media_active; 355d68875ebSPyun YongHyeon } 356d68875ebSPyun YongHyeon 357d68875ebSPyun YongHyeon static int 358d68875ebSPyun YongHyeon alc_mediachange(struct ifnet *ifp) 359d68875ebSPyun YongHyeon { 360d68875ebSPyun YongHyeon struct alc_softc *sc; 361d68875ebSPyun YongHyeon struct mii_data *mii; 362d68875ebSPyun YongHyeon struct mii_softc *miisc; 363d68875ebSPyun YongHyeon int error; 364d68875ebSPyun YongHyeon 365d68875ebSPyun YongHyeon sc = ifp->if_softc; 366d68875ebSPyun YongHyeon ALC_LOCK(sc); 367d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 368d68875ebSPyun YongHyeon if (mii->mii_instance != 0) { 369d68875ebSPyun YongHyeon LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 370d68875ebSPyun YongHyeon mii_phy_reset(miisc); 371d68875ebSPyun YongHyeon } 372d68875ebSPyun YongHyeon error = mii_mediachg(mii); 373d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 374d68875ebSPyun YongHyeon 375d68875ebSPyun YongHyeon return (error); 376d68875ebSPyun YongHyeon } 377d68875ebSPyun YongHyeon 3782f70cceaSPyun YongHyeon static struct alc_ident * 3792f70cceaSPyun YongHyeon alc_find_ident(device_t dev) 380d68875ebSPyun YongHyeon { 3812f70cceaSPyun YongHyeon struct alc_ident *ident; 382d68875ebSPyun YongHyeon uint16_t vendor, devid; 383d68875ebSPyun YongHyeon 384d68875ebSPyun YongHyeon vendor = pci_get_vendor(dev); 385d68875ebSPyun YongHyeon devid = pci_get_device(dev); 3862f70cceaSPyun YongHyeon for (ident = alc_ident_table; ident->name != NULL; ident++) { 3872f70cceaSPyun YongHyeon if (vendor == ident->vendorid && devid == ident->deviceid) 3882f70cceaSPyun YongHyeon return (ident); 389d68875ebSPyun YongHyeon } 3902f70cceaSPyun YongHyeon 3912f70cceaSPyun YongHyeon return (NULL); 3922f70cceaSPyun YongHyeon } 3932f70cceaSPyun YongHyeon 3942f70cceaSPyun YongHyeon static int 3952f70cceaSPyun YongHyeon alc_probe(device_t dev) 3962f70cceaSPyun YongHyeon { 3972f70cceaSPyun YongHyeon struct alc_ident *ident; 3982f70cceaSPyun YongHyeon 3992f70cceaSPyun YongHyeon ident = alc_find_ident(dev); 4002f70cceaSPyun YongHyeon if (ident != NULL) { 4012f70cceaSPyun YongHyeon device_set_desc(dev, ident->name); 4022f70cceaSPyun YongHyeon return (BUS_PROBE_DEFAULT); 403d68875ebSPyun YongHyeon } 404d68875ebSPyun YongHyeon 405d68875ebSPyun YongHyeon return (ENXIO); 406d68875ebSPyun YongHyeon } 407d68875ebSPyun YongHyeon 408d68875ebSPyun YongHyeon static void 409d68875ebSPyun YongHyeon alc_get_macaddr(struct alc_softc *sc) 410d68875ebSPyun YongHyeon { 411d68875ebSPyun YongHyeon uint32_t ea[2], opt; 4122f70cceaSPyun YongHyeon uint16_t val; 4132f70cceaSPyun YongHyeon int eeprom, i; 414d68875ebSPyun YongHyeon 4152f70cceaSPyun YongHyeon eeprom = 0; 416d68875ebSPyun YongHyeon opt = CSR_READ_4(sc, ALC_OPT_CFG); 4172f70cceaSPyun YongHyeon if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 4182f70cceaSPyun YongHyeon (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 419d68875ebSPyun YongHyeon /* 420d68875ebSPyun YongHyeon * EEPROM found, let TWSI reload EEPROM configuration. 421d68875ebSPyun YongHyeon * This will set ethernet address of controller. 422d68875ebSPyun YongHyeon */ 4232f70cceaSPyun YongHyeon eeprom++; 4242f70cceaSPyun YongHyeon switch (sc->alc_ident->deviceid) { 4252f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8131: 4262f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8132: 427d68875ebSPyun YongHyeon if ((opt & OPT_CFG_CLK_ENB) == 0) { 428d68875ebSPyun YongHyeon opt |= OPT_CFG_CLK_ENB; 429d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 430d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_OPT_CFG); 431d68875ebSPyun YongHyeon DELAY(1000); 432d68875ebSPyun YongHyeon } 4332f70cceaSPyun YongHyeon break; 4342f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151: 4352f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151_V2: 4362f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B: 4372f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B2: 4382f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4392f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x00); 4402f70cceaSPyun YongHyeon val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 4412f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 4422f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4432f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, val & 0xFF7F); 4442f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4452f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x3B); 4462f70cceaSPyun YongHyeon val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 4472f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 4482f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4492f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, val | 0x0008); 4502f70cceaSPyun YongHyeon DELAY(20); 4512f70cceaSPyun YongHyeon break; 4522f70cceaSPyun YongHyeon } 4532f70cceaSPyun YongHyeon 4542f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 4552f70cceaSPyun YongHyeon CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 4562f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 4572f70cceaSPyun YongHyeon CSR_READ_4(sc, ALC_WOL_CFG); 4582f70cceaSPyun YongHyeon 459d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 460d68875ebSPyun YongHyeon TWSI_CFG_SW_LD_START); 461d68875ebSPyun YongHyeon for (i = 100; i > 0; i--) { 462d68875ebSPyun YongHyeon DELAY(1000); 463d68875ebSPyun YongHyeon if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 464d68875ebSPyun YongHyeon TWSI_CFG_SW_LD_START) == 0) 465d68875ebSPyun YongHyeon break; 466d68875ebSPyun YongHyeon } 467d68875ebSPyun YongHyeon if (i == 0) 468d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 469d68875ebSPyun YongHyeon "reloading EEPROM timeout!\n"); 470d68875ebSPyun YongHyeon } else { 471d68875ebSPyun YongHyeon if (bootverbose) 472d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "EEPROM not found!\n"); 473d68875ebSPyun YongHyeon } 4742f70cceaSPyun YongHyeon if (eeprom != 0) { 4752f70cceaSPyun YongHyeon switch (sc->alc_ident->deviceid) { 4762f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8131: 4772f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8132: 478d68875ebSPyun YongHyeon if ((opt & OPT_CFG_CLK_ENB) != 0) { 479d68875ebSPyun YongHyeon opt &= ~OPT_CFG_CLK_ENB; 480d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 481d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_OPT_CFG); 482d68875ebSPyun YongHyeon DELAY(1000); 483d68875ebSPyun YongHyeon } 4842f70cceaSPyun YongHyeon break; 4852f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151: 4862f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151_V2: 4872f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B: 4882f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B2: 4892f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4902f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x00); 4912f70cceaSPyun YongHyeon val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 4922f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 4932f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4942f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, val | 0x0080); 4952f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 4962f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x3B); 4972f70cceaSPyun YongHyeon val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 4982f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 4992f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5002f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, val & 0xFFF7); 5012f70cceaSPyun YongHyeon DELAY(20); 5022f70cceaSPyun YongHyeon break; 5032f70cceaSPyun YongHyeon } 5042f70cceaSPyun YongHyeon } 505d68875ebSPyun YongHyeon 506d68875ebSPyun YongHyeon ea[0] = CSR_READ_4(sc, ALC_PAR0); 507d68875ebSPyun YongHyeon ea[1] = CSR_READ_4(sc, ALC_PAR1); 508d68875ebSPyun YongHyeon sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 509d68875ebSPyun YongHyeon sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 510d68875ebSPyun YongHyeon sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 511d68875ebSPyun YongHyeon sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 512d68875ebSPyun YongHyeon sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 513d68875ebSPyun YongHyeon sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 514d68875ebSPyun YongHyeon } 515d68875ebSPyun YongHyeon 516d68875ebSPyun YongHyeon static void 517d68875ebSPyun YongHyeon alc_disable_l0s_l1(struct alc_softc *sc) 518d68875ebSPyun YongHyeon { 519d68875ebSPyun YongHyeon uint32_t pmcfg; 520d68875ebSPyun YongHyeon 521d68875ebSPyun YongHyeon /* Another magic from vendor. */ 522d68875ebSPyun YongHyeon pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 523d68875ebSPyun YongHyeon pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 524d68875ebSPyun YongHyeon PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 525d68875ebSPyun YongHyeon PM_CFG_SERDES_PD_EX_L1); 526d68875ebSPyun YongHyeon pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 527d68875ebSPyun YongHyeon PM_CFG_SERDES_L1_ENB; 528d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 529d68875ebSPyun YongHyeon } 530d68875ebSPyun YongHyeon 531d68875ebSPyun YongHyeon static void 532d68875ebSPyun YongHyeon alc_phy_reset(struct alc_softc *sc) 533d68875ebSPyun YongHyeon { 534d68875ebSPyun YongHyeon uint16_t data; 535d68875ebSPyun YongHyeon 536d68875ebSPyun YongHyeon /* Reset magic from Linux. */ 537d68875ebSPyun YongHyeon CSR_WRITE_2(sc, ALC_GPHY_CFG, 538d68875ebSPyun YongHyeon GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 539d68875ebSPyun YongHyeon CSR_READ_2(sc, ALC_GPHY_CFG); 540d68875ebSPyun YongHyeon DELAY(10 * 1000); 541d68875ebSPyun YongHyeon 542d68875ebSPyun YongHyeon CSR_WRITE_2(sc, ALC_GPHY_CFG, 543d68875ebSPyun YongHyeon GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 544d68875ebSPyun YongHyeon GPHY_CFG_SEL_ANA_RESET); 545d68875ebSPyun YongHyeon CSR_READ_2(sc, ALC_GPHY_CFG); 546d68875ebSPyun YongHyeon DELAY(10 * 1000); 547d68875ebSPyun YongHyeon 5482f70cceaSPyun YongHyeon /* DSP fixup, Vendor magic. */ 5492f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 5502f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5512f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x000A); 5522f70cceaSPyun YongHyeon data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 5532f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 5542f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5552f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, data & 0xDFFF); 5562f70cceaSPyun YongHyeon } 5572f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 5582f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 5592f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 5602f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 5612f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5622f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x003B); 5632f70cceaSPyun YongHyeon data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 5642f70cceaSPyun YongHyeon ALC_MII_DBG_DATA); 5652f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5662f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, data & 0xFFF7); 5672f70cceaSPyun YongHyeon DELAY(20 * 1000); 5682f70cceaSPyun YongHyeon } 5692f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 5702f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5712f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x0029); 5722f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5732f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, 0x929D); 5742f70cceaSPyun YongHyeon } 5752f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 5762f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 5772f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 5782f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 5792f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5802f70cceaSPyun YongHyeon ALC_MII_DBG_ADDR, 0x0029); 5812f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 5822f70cceaSPyun YongHyeon ALC_MII_DBG_DATA, 0xB6DD); 5832f70cceaSPyun YongHyeon } 5842f70cceaSPyun YongHyeon 585d68875ebSPyun YongHyeon /* Load DSP codes, vendor magic. */ 586d68875ebSPyun YongHyeon data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 587d68875ebSPyun YongHyeon ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 588d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589d68875ebSPyun YongHyeon ALC_MII_DBG_ADDR, MII_ANA_CFG18); 590d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 591d68875ebSPyun YongHyeon ALC_MII_DBG_DATA, data); 592d68875ebSPyun YongHyeon 593d68875ebSPyun YongHyeon data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 594d68875ebSPyun YongHyeon ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 595d68875ebSPyun YongHyeon ANA_SERDES_EN_LCKDT; 596d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 597d68875ebSPyun YongHyeon ALC_MII_DBG_ADDR, MII_ANA_CFG5); 598d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 599d68875ebSPyun YongHyeon ALC_MII_DBG_DATA, data); 600d68875ebSPyun YongHyeon 601d68875ebSPyun YongHyeon data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 602d68875ebSPyun YongHyeon ANA_LONG_CABLE_TH_100_MASK) | 603d68875ebSPyun YongHyeon ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 604d68875ebSPyun YongHyeon ANA_SHORT_CABLE_TH_100_SHIFT) | 605d68875ebSPyun YongHyeon ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 606d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 607d68875ebSPyun YongHyeon ALC_MII_DBG_ADDR, MII_ANA_CFG54); 608d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 609d68875ebSPyun YongHyeon ALC_MII_DBG_DATA, data); 610d68875ebSPyun YongHyeon 611d68875ebSPyun YongHyeon data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 612d68875ebSPyun YongHyeon ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 613d68875ebSPyun YongHyeon ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 614d68875ebSPyun YongHyeon ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 615d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616d68875ebSPyun YongHyeon ALC_MII_DBG_ADDR, MII_ANA_CFG4); 617d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 618d68875ebSPyun YongHyeon ALC_MII_DBG_DATA, data); 619d68875ebSPyun YongHyeon 620d68875ebSPyun YongHyeon data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 621d68875ebSPyun YongHyeon ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 622d68875ebSPyun YongHyeon ANA_OEN_125M; 623d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 624d68875ebSPyun YongHyeon ALC_MII_DBG_ADDR, MII_ANA_CFG0); 625d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 626d68875ebSPyun YongHyeon ALC_MII_DBG_DATA, data); 627d68875ebSPyun YongHyeon DELAY(1000); 628d68875ebSPyun YongHyeon } 629d68875ebSPyun YongHyeon 630d68875ebSPyun YongHyeon static void 631d68875ebSPyun YongHyeon alc_phy_down(struct alc_softc *sc) 632d68875ebSPyun YongHyeon { 633d68875ebSPyun YongHyeon 6342f70cceaSPyun YongHyeon switch (sc->alc_ident->deviceid) { 6352f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151: 6362f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151_V2: 6372f70cceaSPyun YongHyeon /* 6382f70cceaSPyun YongHyeon * GPHY power down caused more problems on AR8151 v2.0. 6392f70cceaSPyun YongHyeon * When driver is reloaded after GPHY power down, 6402f70cceaSPyun YongHyeon * accesses to PHY/MAC registers hung the system. Only 6412f70cceaSPyun YongHyeon * cold boot recovered from it. I'm not sure whether 6422f70cceaSPyun YongHyeon * AR8151 v1.0 also requires this one though. I don't 6432f70cceaSPyun YongHyeon * have AR8151 v1.0 controller in hand. 6442f70cceaSPyun YongHyeon * The only option left is to isolate the PHY and 6452f70cceaSPyun YongHyeon * initiates power down the PHY which in turn saves 6462f70cceaSPyun YongHyeon * more power when driver is unloaded. 6472f70cceaSPyun YongHyeon */ 6482f70cceaSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 6492f70cceaSPyun YongHyeon MII_BMCR, BMCR_ISO | BMCR_PDOWN); 6502f70cceaSPyun YongHyeon break; 6512f70cceaSPyun YongHyeon default: 652d68875ebSPyun YongHyeon /* Force PHY down. */ 653d68875ebSPyun YongHyeon CSR_WRITE_2(sc, ALC_GPHY_CFG, 654d68875ebSPyun YongHyeon GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 6552f70cceaSPyun YongHyeon GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 6562f70cceaSPyun YongHyeon GPHY_CFG_PWDOWN_HW); 657d68875ebSPyun YongHyeon DELAY(1000); 6582f70cceaSPyun YongHyeon break; 6592f70cceaSPyun YongHyeon } 660d68875ebSPyun YongHyeon } 661d68875ebSPyun YongHyeon 662d68875ebSPyun YongHyeon static void 6632f70cceaSPyun YongHyeon alc_aspm(struct alc_softc *sc, int media) 664d68875ebSPyun YongHyeon { 665d68875ebSPyun YongHyeon uint32_t pmcfg; 6662f70cceaSPyun YongHyeon uint16_t linkcfg; 667d68875ebSPyun YongHyeon 668d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 669d68875ebSPyun YongHyeon 670d68875ebSPyun YongHyeon pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 6712f70cceaSPyun YongHyeon if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 6722f70cceaSPyun YongHyeon (ALC_FLAG_APS | ALC_FLAG_PCIE)) 6732f70cceaSPyun YongHyeon linkcfg = CSR_READ_2(sc, sc->alc_expcap + 6742f70cceaSPyun YongHyeon PCIR_EXPRESS_LINK_CTL); 6752f70cceaSPyun YongHyeon else 6762f70cceaSPyun YongHyeon linkcfg = 0; 677d68875ebSPyun YongHyeon pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 6782f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 679d68875ebSPyun YongHyeon pmcfg |= PM_CFG_MAC_ASPM_CHK; 6802f70cceaSPyun YongHyeon pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 6812f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 6822f70cceaSPyun YongHyeon 6832f70cceaSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 6842f70cceaSPyun YongHyeon /* Disable extended sync except AR8152 B v1.0 */ 6852f70cceaSPyun YongHyeon linkcfg &= ~0x80; 6862f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 6872f70cceaSPyun YongHyeon sc->alc_rev == ATHEROS_AR8152_B_V10) 6882f70cceaSPyun YongHyeon linkcfg |= 0x80; 6892f70cceaSPyun YongHyeon CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 6902f70cceaSPyun YongHyeon linkcfg); 6912f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 6922f70cceaSPyun YongHyeon PM_CFG_HOTRST); 6932f70cceaSPyun YongHyeon pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 6942f70cceaSPyun YongHyeon PM_CFG_L1_ENTRY_TIMER_SHIFT); 6952f70cceaSPyun YongHyeon pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 6962f70cceaSPyun YongHyeon pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 6972f70cceaSPyun YongHyeon PM_CFG_PM_REQ_TIMER_SHIFT); 6982f70cceaSPyun YongHyeon pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 6992f70cceaSPyun YongHyeon } 7002f70cceaSPyun YongHyeon 701d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 7022f70cceaSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 7032f70cceaSPyun YongHyeon pmcfg |= PM_CFG_ASPM_L0S_ENB; 7042f70cceaSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 7052f70cceaSPyun YongHyeon pmcfg |= PM_CFG_ASPM_L1_ENB; 7062f70cceaSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 7072f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == 7082f70cceaSPyun YongHyeon DEVICEID_ATHEROS_AR8152_B) 709d68875ebSPyun YongHyeon pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 7102f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 7112f70cceaSPyun YongHyeon PM_CFG_SERDES_PLL_L1_ENB | 7122f70cceaSPyun YongHyeon PM_CFG_SERDES_BUDS_RX_L1_ENB); 713d68875ebSPyun YongHyeon pmcfg |= PM_CFG_CLK_SWH_L1; 7142f70cceaSPyun YongHyeon if (media == IFM_100_TX || media == IFM_1000_T) { 7152f70cceaSPyun YongHyeon pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 7162f70cceaSPyun YongHyeon switch (sc->alc_ident->deviceid) { 7172f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B: 7182f70cceaSPyun YongHyeon pmcfg |= (7 << 7192f70cceaSPyun YongHyeon PM_CFG_L1_ENTRY_TIMER_SHIFT); 7202f70cceaSPyun YongHyeon break; 7212f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B2: 7222f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151_V2: 7232f70cceaSPyun YongHyeon pmcfg |= (4 << 7242f70cceaSPyun YongHyeon PM_CFG_L1_ENTRY_TIMER_SHIFT); 7252f70cceaSPyun YongHyeon break; 7262f70cceaSPyun YongHyeon default: 7272f70cceaSPyun YongHyeon pmcfg |= (15 << 7282f70cceaSPyun YongHyeon PM_CFG_L1_ENTRY_TIMER_SHIFT); 7292f70cceaSPyun YongHyeon break; 7302f70cceaSPyun YongHyeon } 7312f70cceaSPyun YongHyeon } 7322f70cceaSPyun YongHyeon } else { 7332f70cceaSPyun YongHyeon pmcfg |= PM_CFG_SERDES_L1_ENB | 7342f70cceaSPyun YongHyeon PM_CFG_SERDES_PLL_L1_ENB | 7352f70cceaSPyun YongHyeon PM_CFG_SERDES_BUDS_RX_L1_ENB; 7362f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 7372f70cceaSPyun YongHyeon PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 7382f70cceaSPyun YongHyeon } 7392f70cceaSPyun YongHyeon } else { 7402f70cceaSPyun YongHyeon pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 7412f70cceaSPyun YongHyeon PM_CFG_SERDES_PLL_L1_ENB); 7422f70cceaSPyun YongHyeon pmcfg |= PM_CFG_CLK_SWH_L1; 7432f70cceaSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 7442f70cceaSPyun YongHyeon pmcfg |= PM_CFG_ASPM_L1_ENB; 745d68875ebSPyun YongHyeon } 746d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 747d68875ebSPyun YongHyeon } 748d68875ebSPyun YongHyeon 749d68875ebSPyun YongHyeon static int 750d68875ebSPyun YongHyeon alc_attach(device_t dev) 751d68875ebSPyun YongHyeon { 752d68875ebSPyun YongHyeon struct alc_softc *sc; 753d68875ebSPyun YongHyeon struct ifnet *ifp; 7542f70cceaSPyun YongHyeon char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 755d68875ebSPyun YongHyeon uint16_t burst; 756a4d3574cSPyun YongHyeon int base, error, i, msic, msixc, state; 757d68875ebSPyun YongHyeon uint32_t cap, ctl, val; 758d68875ebSPyun YongHyeon 759d68875ebSPyun YongHyeon error = 0; 760d68875ebSPyun YongHyeon sc = device_get_softc(dev); 761d68875ebSPyun YongHyeon sc->alc_dev = dev; 762d68875ebSPyun YongHyeon 763d68875ebSPyun YongHyeon mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 764d68875ebSPyun YongHyeon MTX_DEF); 765d68875ebSPyun YongHyeon callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 766d68875ebSPyun YongHyeon TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 7672f70cceaSPyun YongHyeon sc->alc_ident = alc_find_ident(dev); 768d68875ebSPyun YongHyeon 769d68875ebSPyun YongHyeon /* Map the device. */ 770d68875ebSPyun YongHyeon pci_enable_busmaster(dev); 771d68875ebSPyun YongHyeon sc->alc_res_spec = alc_res_spec_mem; 772d68875ebSPyun YongHyeon sc->alc_irq_spec = alc_irq_spec_legacy; 773d68875ebSPyun YongHyeon error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 774d68875ebSPyun YongHyeon if (error != 0) { 775d68875ebSPyun YongHyeon device_printf(dev, "cannot allocate memory resources.\n"); 776d68875ebSPyun YongHyeon goto fail; 777d68875ebSPyun YongHyeon } 778d68875ebSPyun YongHyeon 779d68875ebSPyun YongHyeon /* Set PHY address. */ 780d68875ebSPyun YongHyeon sc->alc_phyaddr = ALC_PHY_ADDR; 781d68875ebSPyun YongHyeon 782d68875ebSPyun YongHyeon /* Initialize DMA parameters. */ 783d68875ebSPyun YongHyeon sc->alc_dma_rd_burst = 0; 784d68875ebSPyun YongHyeon sc->alc_dma_wr_burst = 0; 785d68875ebSPyun YongHyeon sc->alc_rcb = DMA_CFG_RCB_64; 786d68875ebSPyun YongHyeon if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 787d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_PCIE; 788a4d3574cSPyun YongHyeon sc->alc_expcap = base; 789d68875ebSPyun YongHyeon burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 790d68875ebSPyun YongHyeon sc->alc_dma_rd_burst = 791d68875ebSPyun YongHyeon (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 792d68875ebSPyun YongHyeon sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 793d68875ebSPyun YongHyeon if (bootverbose) { 794d68875ebSPyun YongHyeon device_printf(dev, "Read request size : %u bytes.\n", 795d68875ebSPyun YongHyeon alc_dma_burst[sc->alc_dma_rd_burst]); 796d68875ebSPyun YongHyeon device_printf(dev, "TLP payload size : %u bytes.\n", 797d68875ebSPyun YongHyeon alc_dma_burst[sc->alc_dma_wr_burst]); 798d68875ebSPyun YongHyeon } 7991e77baedSPyun YongHyeon if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 8001e77baedSPyun YongHyeon sc->alc_dma_rd_burst = 3; 8011e77baedSPyun YongHyeon if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 8021e77baedSPyun YongHyeon sc->alc_dma_wr_burst = 3; 803d68875ebSPyun YongHyeon /* Clear data link and flow-control protocol error. */ 804d68875ebSPyun YongHyeon val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 805d68875ebSPyun YongHyeon val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 806d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 8072f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 8082f70cceaSPyun YongHyeon CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 8092f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 8102f70cceaSPyun YongHyeon CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 8112f70cceaSPyun YongHyeon PCIE_PHYMISC_FORCE_RCV_DET); 8122f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 8132f70cceaSPyun YongHyeon sc->alc_rev == ATHEROS_AR8152_B_V10) { 8142f70cceaSPyun YongHyeon val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 8152f70cceaSPyun YongHyeon val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 8162f70cceaSPyun YongHyeon PCIE_PHYMISC2_SERDES_TH_MASK); 8172f70cceaSPyun YongHyeon val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 8182f70cceaSPyun YongHyeon val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 8192f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 8202f70cceaSPyun YongHyeon } 821d68875ebSPyun YongHyeon /* Disable ASPM L0S and L1. */ 822d68875ebSPyun YongHyeon cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 823d68875ebSPyun YongHyeon if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 824d68875ebSPyun YongHyeon ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 825d68875ebSPyun YongHyeon if ((ctl & 0x08) != 0) 826d68875ebSPyun YongHyeon sc->alc_rcb = DMA_CFG_RCB_128; 827d68875ebSPyun YongHyeon if (bootverbose) 828d68875ebSPyun YongHyeon device_printf(dev, "RCB %u bytes\n", 829d68875ebSPyun YongHyeon sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 830d68875ebSPyun YongHyeon state = ctl & 0x03; 8312f70cceaSPyun YongHyeon if (state & 0x01) 8322f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_L0S; 8332f70cceaSPyun YongHyeon if (state & 0x02) 8342f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_L1S; 835d68875ebSPyun YongHyeon if (bootverbose) 836d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "ASPM %s %s\n", 837d68875ebSPyun YongHyeon aspm_state[state], 838d68875ebSPyun YongHyeon state == 0 ? "disabled" : "enabled"); 839d68875ebSPyun YongHyeon alc_disable_l0s_l1(sc); 8402f70cceaSPyun YongHyeon } else { 8412f70cceaSPyun YongHyeon if (bootverbose) 8422f70cceaSPyun YongHyeon device_printf(sc->alc_dev, 8432f70cceaSPyun YongHyeon "no ASPM support\n"); 844d68875ebSPyun YongHyeon } 845d68875ebSPyun YongHyeon } 846d68875ebSPyun YongHyeon 847d68875ebSPyun YongHyeon /* Reset PHY. */ 848d68875ebSPyun YongHyeon alc_phy_reset(sc); 849d68875ebSPyun YongHyeon 850d68875ebSPyun YongHyeon /* Reset the ethernet controller. */ 851d68875ebSPyun YongHyeon alc_reset(sc); 852d68875ebSPyun YongHyeon 853d68875ebSPyun YongHyeon /* 854d68875ebSPyun YongHyeon * One odd thing is AR8132 uses the same PHY hardware(F1 855d68875ebSPyun YongHyeon * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 856d68875ebSPyun YongHyeon * the PHY supports 1000Mbps but that's not true. The PHY 857d68875ebSPyun YongHyeon * used in AR8132 can't establish gigabit link even if it 858d68875ebSPyun YongHyeon * shows the same PHY model/revision number of AR8131. 859d68875ebSPyun YongHyeon */ 8602f70cceaSPyun YongHyeon switch (sc->alc_ident->deviceid) { 8612f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B: 8622f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8152_B2: 8632f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_APS; 8642f70cceaSPyun YongHyeon /* FALLTHROUGH */ 8652f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8132: 8662f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_FASTETHER; 8672f70cceaSPyun YongHyeon break; 8682f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151: 8692f70cceaSPyun YongHyeon case DEVICEID_ATHEROS_AR8151_V2: 8702f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_APS; 8712f70cceaSPyun YongHyeon /* FALLTHROUGH */ 8722f70cceaSPyun YongHyeon default: 8732f70cceaSPyun YongHyeon break; 8742f70cceaSPyun YongHyeon } 8752f70cceaSPyun YongHyeon sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 8762f70cceaSPyun YongHyeon 877d68875ebSPyun YongHyeon /* 8782f70cceaSPyun YongHyeon * It seems that AR813x/AR815x has silicon bug for SMB. In 879d68875ebSPyun YongHyeon * addition, Atheros said that enabling SMB wouldn't improve 880d68875ebSPyun YongHyeon * performance. However I think it's bad to access lots of 881d68875ebSPyun YongHyeon * registers to extract MAC statistics. 882d68875ebSPyun YongHyeon */ 883d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_SMB_BUG; 884d68875ebSPyun YongHyeon /* 885d68875ebSPyun YongHyeon * Don't use Tx CMB. It is known to have silicon bug. 886d68875ebSPyun YongHyeon */ 887d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_CMB_BUG; 888d68875ebSPyun YongHyeon sc->alc_rev = pci_get_revid(dev); 889d68875ebSPyun YongHyeon sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 890d68875ebSPyun YongHyeon MASTER_CHIP_REV_SHIFT; 891d68875ebSPyun YongHyeon if (bootverbose) { 892d68875ebSPyun YongHyeon device_printf(dev, "PCI device revision : 0x%04x\n", 893d68875ebSPyun YongHyeon sc->alc_rev); 894d68875ebSPyun YongHyeon device_printf(dev, "Chip id/revision : 0x%04x\n", 895d68875ebSPyun YongHyeon sc->alc_chip_rev); 896d68875ebSPyun YongHyeon } 897d68875ebSPyun YongHyeon device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 898d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 899d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 900d68875ebSPyun YongHyeon 901d68875ebSPyun YongHyeon /* Allocate IRQ resources. */ 902d68875ebSPyun YongHyeon msixc = pci_msix_count(dev); 903d68875ebSPyun YongHyeon msic = pci_msi_count(dev); 904d68875ebSPyun YongHyeon if (bootverbose) { 905d68875ebSPyun YongHyeon device_printf(dev, "MSIX count : %d\n", msixc); 906d68875ebSPyun YongHyeon device_printf(dev, "MSI count : %d\n", msic); 907d68875ebSPyun YongHyeon } 908d68875ebSPyun YongHyeon /* Prefer MSIX over MSI. */ 909d68875ebSPyun YongHyeon if (msix_disable == 0 || msi_disable == 0) { 910d68875ebSPyun YongHyeon if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 911d68875ebSPyun YongHyeon pci_alloc_msix(dev, &msixc) == 0) { 912d68875ebSPyun YongHyeon if (msic == ALC_MSIX_MESSAGES) { 913d68875ebSPyun YongHyeon device_printf(dev, 914d68875ebSPyun YongHyeon "Using %d MSIX message(s).\n", msixc); 915d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_MSIX; 916d68875ebSPyun YongHyeon sc->alc_irq_spec = alc_irq_spec_msix; 917d68875ebSPyun YongHyeon } else 918d68875ebSPyun YongHyeon pci_release_msi(dev); 919d68875ebSPyun YongHyeon } 920d68875ebSPyun YongHyeon if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 921d68875ebSPyun YongHyeon msic == ALC_MSI_MESSAGES && 922d68875ebSPyun YongHyeon pci_alloc_msi(dev, &msic) == 0) { 923d68875ebSPyun YongHyeon if (msic == ALC_MSI_MESSAGES) { 924d68875ebSPyun YongHyeon device_printf(dev, 925d68875ebSPyun YongHyeon "Using %d MSI message(s).\n", msic); 926d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_MSI; 927d68875ebSPyun YongHyeon sc->alc_irq_spec = alc_irq_spec_msi; 928d68875ebSPyun YongHyeon } else 929d68875ebSPyun YongHyeon pci_release_msi(dev); 930d68875ebSPyun YongHyeon } 931d68875ebSPyun YongHyeon } 932d68875ebSPyun YongHyeon 933d68875ebSPyun YongHyeon error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 934d68875ebSPyun YongHyeon if (error != 0) { 935d68875ebSPyun YongHyeon device_printf(dev, "cannot allocate IRQ resources.\n"); 936d68875ebSPyun YongHyeon goto fail; 937d68875ebSPyun YongHyeon } 938d68875ebSPyun YongHyeon 939d68875ebSPyun YongHyeon /* Create device sysctl node. */ 940d68875ebSPyun YongHyeon alc_sysctl_node(sc); 941d68875ebSPyun YongHyeon 942d68875ebSPyun YongHyeon if ((error = alc_dma_alloc(sc) != 0)) 943d68875ebSPyun YongHyeon goto fail; 944d68875ebSPyun YongHyeon 945d68875ebSPyun YongHyeon /* Load station address. */ 946d68875ebSPyun YongHyeon alc_get_macaddr(sc); 947d68875ebSPyun YongHyeon 948d68875ebSPyun YongHyeon ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 949d68875ebSPyun YongHyeon if (ifp == NULL) { 950d68875ebSPyun YongHyeon device_printf(dev, "cannot allocate ifnet structure.\n"); 951d68875ebSPyun YongHyeon error = ENXIO; 952d68875ebSPyun YongHyeon goto fail; 953d68875ebSPyun YongHyeon } 954d68875ebSPyun YongHyeon 955d68875ebSPyun YongHyeon ifp->if_softc = sc; 956d68875ebSPyun YongHyeon if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 957d68875ebSPyun YongHyeon ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 958d68875ebSPyun YongHyeon ifp->if_ioctl = alc_ioctl; 959d68875ebSPyun YongHyeon ifp->if_start = alc_start; 960d68875ebSPyun YongHyeon ifp->if_init = alc_init; 961d68875ebSPyun YongHyeon ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 962d68875ebSPyun YongHyeon IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 963d68875ebSPyun YongHyeon IFQ_SET_READY(&ifp->if_snd); 964d68875ebSPyun YongHyeon ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 965d68875ebSPyun YongHyeon ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 966a4d3574cSPyun YongHyeon if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { 967d68875ebSPyun YongHyeon ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 968a4d3574cSPyun YongHyeon sc->alc_flags |= ALC_FLAG_PM; 969a4d3574cSPyun YongHyeon sc->alc_pmcap = base; 970a4d3574cSPyun YongHyeon } 971d68875ebSPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 972d68875ebSPyun YongHyeon 973d68875ebSPyun YongHyeon /* Set up MII bus. */ 9748e5d93dbSMarius Strobl error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 9758e5d93dbSMarius Strobl alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 9769f4e8f46SPyun YongHyeon MIIF_DOPAUSE); 9778e5d93dbSMarius Strobl if (error != 0) { 9788e5d93dbSMarius Strobl device_printf(dev, "attaching PHYs failed\n"); 979d68875ebSPyun YongHyeon goto fail; 980d68875ebSPyun YongHyeon } 981d68875ebSPyun YongHyeon 982d68875ebSPyun YongHyeon ether_ifattach(ifp, sc->alc_eaddr); 983d68875ebSPyun YongHyeon 984d68875ebSPyun YongHyeon /* VLAN capability setup. */ 985e67344a3SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 986e67344a3SPyun YongHyeon IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 987d68875ebSPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 988d68875ebSPyun YongHyeon /* 989d68875ebSPyun YongHyeon * XXX 990d68875ebSPyun YongHyeon * It seems enabling Tx checksum offloading makes more trouble. 991d68875ebSPyun YongHyeon * Sometimes the controller does not receive any frames when 992d68875ebSPyun YongHyeon * Tx checksum offloading is enabled. I'm not sure whether this 993d68875ebSPyun YongHyeon * is a bug in Tx checksum offloading logic or I got broken 994d68875ebSPyun YongHyeon * sample boards. To safety, don't enable Tx checksum offloading 995d68875ebSPyun YongHyeon * by default but give chance to users to toggle it if they know 996d68875ebSPyun YongHyeon * their controllers work without problems. 997d68875ebSPyun YongHyeon */ 998d68875ebSPyun YongHyeon ifp->if_capenable &= ~IFCAP_TXCSUM; 999d68875ebSPyun YongHyeon ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1000d68875ebSPyun YongHyeon 1001d68875ebSPyun YongHyeon /* Tell the upper layer(s) we support long frames. */ 1002d68875ebSPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1003d68875ebSPyun YongHyeon 1004d68875ebSPyun YongHyeon /* Create local taskq. */ 1005d68875ebSPyun YongHyeon TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1006d68875ebSPyun YongHyeon sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1007d68875ebSPyun YongHyeon taskqueue_thread_enqueue, &sc->alc_tq); 1008d68875ebSPyun YongHyeon if (sc->alc_tq == NULL) { 1009d68875ebSPyun YongHyeon device_printf(dev, "could not create taskqueue.\n"); 1010d68875ebSPyun YongHyeon ether_ifdetach(ifp); 1011d68875ebSPyun YongHyeon error = ENXIO; 1012d68875ebSPyun YongHyeon goto fail; 1013d68875ebSPyun YongHyeon } 1014d68875ebSPyun YongHyeon taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1015d68875ebSPyun YongHyeon device_get_nameunit(sc->alc_dev)); 1016d68875ebSPyun YongHyeon 1017d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1018d68875ebSPyun YongHyeon msic = ALC_MSIX_MESSAGES; 1019d68875ebSPyun YongHyeon else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1020d68875ebSPyun YongHyeon msic = ALC_MSI_MESSAGES; 1021d68875ebSPyun YongHyeon else 1022d68875ebSPyun YongHyeon msic = 1; 1023d68875ebSPyun YongHyeon for (i = 0; i < msic; i++) { 1024d68875ebSPyun YongHyeon error = bus_setup_intr(dev, sc->alc_irq[i], 1025d68875ebSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1026d68875ebSPyun YongHyeon &sc->alc_intrhand[i]); 1027d68875ebSPyun YongHyeon if (error != 0) 1028d68875ebSPyun YongHyeon break; 1029d68875ebSPyun YongHyeon } 1030d68875ebSPyun YongHyeon if (error != 0) { 1031d68875ebSPyun YongHyeon device_printf(dev, "could not set up interrupt handler.\n"); 1032d68875ebSPyun YongHyeon taskqueue_free(sc->alc_tq); 1033d68875ebSPyun YongHyeon sc->alc_tq = NULL; 1034d68875ebSPyun YongHyeon ether_ifdetach(ifp); 1035d68875ebSPyun YongHyeon goto fail; 1036d68875ebSPyun YongHyeon } 1037d68875ebSPyun YongHyeon 1038d68875ebSPyun YongHyeon fail: 1039d68875ebSPyun YongHyeon if (error != 0) 1040d68875ebSPyun YongHyeon alc_detach(dev); 1041d68875ebSPyun YongHyeon 1042d68875ebSPyun YongHyeon return (error); 1043d68875ebSPyun YongHyeon } 1044d68875ebSPyun YongHyeon 1045d68875ebSPyun YongHyeon static int 1046d68875ebSPyun YongHyeon alc_detach(device_t dev) 1047d68875ebSPyun YongHyeon { 1048d68875ebSPyun YongHyeon struct alc_softc *sc; 1049d68875ebSPyun YongHyeon struct ifnet *ifp; 1050d68875ebSPyun YongHyeon int i, msic; 1051d68875ebSPyun YongHyeon 1052d68875ebSPyun YongHyeon sc = device_get_softc(dev); 1053d68875ebSPyun YongHyeon 1054d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 1055d68875ebSPyun YongHyeon if (device_is_attached(dev)) { 1056d68875ebSPyun YongHyeon ALC_LOCK(sc); 1057d68875ebSPyun YongHyeon sc->alc_flags |= ALC_FLAG_DETACH; 1058d68875ebSPyun YongHyeon alc_stop(sc); 1059d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 1060d68875ebSPyun YongHyeon callout_drain(&sc->alc_tick_ch); 1061d68875ebSPyun YongHyeon taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1062d68875ebSPyun YongHyeon taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1063d68875ebSPyun YongHyeon ether_ifdetach(ifp); 1064d68875ebSPyun YongHyeon } 1065d68875ebSPyun YongHyeon 1066d68875ebSPyun YongHyeon if (sc->alc_tq != NULL) { 1067d68875ebSPyun YongHyeon taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1068d68875ebSPyun YongHyeon taskqueue_free(sc->alc_tq); 1069d68875ebSPyun YongHyeon sc->alc_tq = NULL; 1070d68875ebSPyun YongHyeon } 1071d68875ebSPyun YongHyeon 1072d68875ebSPyun YongHyeon if (sc->alc_miibus != NULL) { 1073d68875ebSPyun YongHyeon device_delete_child(dev, sc->alc_miibus); 1074d68875ebSPyun YongHyeon sc->alc_miibus = NULL; 1075d68875ebSPyun YongHyeon } 1076d68875ebSPyun YongHyeon bus_generic_detach(dev); 1077d68875ebSPyun YongHyeon alc_dma_free(sc); 1078d68875ebSPyun YongHyeon 1079d68875ebSPyun YongHyeon if (ifp != NULL) { 1080d68875ebSPyun YongHyeon if_free(ifp); 1081d68875ebSPyun YongHyeon sc->alc_ifp = NULL; 1082d68875ebSPyun YongHyeon } 1083d68875ebSPyun YongHyeon 1084d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1085d68875ebSPyun YongHyeon msic = ALC_MSIX_MESSAGES; 1086d68875ebSPyun YongHyeon else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1087d68875ebSPyun YongHyeon msic = ALC_MSI_MESSAGES; 1088d68875ebSPyun YongHyeon else 1089d68875ebSPyun YongHyeon msic = 1; 1090d68875ebSPyun YongHyeon for (i = 0; i < msic; i++) { 1091d68875ebSPyun YongHyeon if (sc->alc_intrhand[i] != NULL) { 1092d68875ebSPyun YongHyeon bus_teardown_intr(dev, sc->alc_irq[i], 1093d68875ebSPyun YongHyeon sc->alc_intrhand[i]); 1094d68875ebSPyun YongHyeon sc->alc_intrhand[i] = NULL; 1095d68875ebSPyun YongHyeon } 1096d68875ebSPyun YongHyeon } 1097e4d5e248SPyun YongHyeon if (sc->alc_res[0] != NULL) 1098d68875ebSPyun YongHyeon alc_phy_down(sc); 1099d68875ebSPyun YongHyeon bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1100d68875ebSPyun YongHyeon if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1101d68875ebSPyun YongHyeon pci_release_msi(dev); 1102d68875ebSPyun YongHyeon bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1103d68875ebSPyun YongHyeon mtx_destroy(&sc->alc_mtx); 1104d68875ebSPyun YongHyeon 1105d68875ebSPyun YongHyeon return (0); 1106d68875ebSPyun YongHyeon } 1107d68875ebSPyun YongHyeon 1108d68875ebSPyun YongHyeon #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1109d68875ebSPyun YongHyeon SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1110d68875ebSPyun YongHyeon #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1111d68875ebSPyun YongHyeon SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1112d68875ebSPyun YongHyeon 1113d68875ebSPyun YongHyeon static void 1114d68875ebSPyun YongHyeon alc_sysctl_node(struct alc_softc *sc) 1115d68875ebSPyun YongHyeon { 1116d68875ebSPyun YongHyeon struct sysctl_ctx_list *ctx; 1117d68875ebSPyun YongHyeon struct sysctl_oid_list *child, *parent; 1118d68875ebSPyun YongHyeon struct sysctl_oid *tree; 1119d68875ebSPyun YongHyeon struct alc_hw_stats *stats; 1120d68875ebSPyun YongHyeon int error; 1121d68875ebSPyun YongHyeon 1122d68875ebSPyun YongHyeon stats = &sc->alc_stats; 1123d68875ebSPyun YongHyeon ctx = device_get_sysctl_ctx(sc->alc_dev); 1124d68875ebSPyun YongHyeon child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1125d68875ebSPyun YongHyeon 1126d68875ebSPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1127d68875ebSPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1128d68875ebSPyun YongHyeon sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1129d68875ebSPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1130d68875ebSPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1131d68875ebSPyun YongHyeon sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1132d68875ebSPyun YongHyeon /* Pull in device tunables. */ 1133d68875ebSPyun YongHyeon sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1134d68875ebSPyun YongHyeon error = resource_int_value(device_get_name(sc->alc_dev), 1135d68875ebSPyun YongHyeon device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1136d68875ebSPyun YongHyeon if (error == 0) { 1137d68875ebSPyun YongHyeon if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1138d68875ebSPyun YongHyeon sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1139d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "int_rx_mod value out of " 1140d68875ebSPyun YongHyeon "range; using default: %d\n", 1141d68875ebSPyun YongHyeon ALC_IM_RX_TIMER_DEFAULT); 1142d68875ebSPyun YongHyeon sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1143d68875ebSPyun YongHyeon } 1144d68875ebSPyun YongHyeon } 1145d68875ebSPyun YongHyeon sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1146d68875ebSPyun YongHyeon error = resource_int_value(device_get_name(sc->alc_dev), 1147d68875ebSPyun YongHyeon device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1148d68875ebSPyun YongHyeon if (error == 0) { 1149d68875ebSPyun YongHyeon if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1150d68875ebSPyun YongHyeon sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1151d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "int_tx_mod value out of " 1152d68875ebSPyun YongHyeon "range; using default: %d\n", 1153d68875ebSPyun YongHyeon ALC_IM_TX_TIMER_DEFAULT); 1154d68875ebSPyun YongHyeon sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1155d68875ebSPyun YongHyeon } 1156d68875ebSPyun YongHyeon } 1157d68875ebSPyun YongHyeon SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1158d68875ebSPyun YongHyeon CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1159d68875ebSPyun YongHyeon sysctl_hw_alc_proc_limit, "I", 1160d68875ebSPyun YongHyeon "max number of Rx events to process"); 1161d68875ebSPyun YongHyeon /* Pull in device tunables. */ 1162d68875ebSPyun YongHyeon sc->alc_process_limit = ALC_PROC_DEFAULT; 1163d68875ebSPyun YongHyeon error = resource_int_value(device_get_name(sc->alc_dev), 1164d68875ebSPyun YongHyeon device_get_unit(sc->alc_dev), "process_limit", 1165d68875ebSPyun YongHyeon &sc->alc_process_limit); 1166d68875ebSPyun YongHyeon if (error == 0) { 1167d68875ebSPyun YongHyeon if (sc->alc_process_limit < ALC_PROC_MIN || 1168d68875ebSPyun YongHyeon sc->alc_process_limit > ALC_PROC_MAX) { 1169d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1170d68875ebSPyun YongHyeon "process_limit value out of range; " 1171d68875ebSPyun YongHyeon "using default: %d\n", ALC_PROC_DEFAULT); 1172d68875ebSPyun YongHyeon sc->alc_process_limit = ALC_PROC_DEFAULT; 1173d68875ebSPyun YongHyeon } 1174d68875ebSPyun YongHyeon } 1175d68875ebSPyun YongHyeon 1176d68875ebSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1177d68875ebSPyun YongHyeon NULL, "ALC statistics"); 1178d68875ebSPyun YongHyeon parent = SYSCTL_CHILDREN(tree); 1179d68875ebSPyun YongHyeon 1180d68875ebSPyun YongHyeon /* Rx statistics. */ 1181d68875ebSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1182d68875ebSPyun YongHyeon NULL, "Rx MAC statistics"); 1183d68875ebSPyun YongHyeon child = SYSCTL_CHILDREN(tree); 1184d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1185d68875ebSPyun YongHyeon &stats->rx_frames, "Good frames"); 1186d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1187d68875ebSPyun YongHyeon &stats->rx_bcast_frames, "Good broadcast frames"); 1188d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1189d68875ebSPyun YongHyeon &stats->rx_mcast_frames, "Good multicast frames"); 1190d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1191d68875ebSPyun YongHyeon &stats->rx_pause_frames, "Pause control frames"); 1192d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1193d68875ebSPyun YongHyeon &stats->rx_control_frames, "Control frames"); 1194d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1195d68875ebSPyun YongHyeon &stats->rx_crcerrs, "CRC errors"); 1196d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1197d68875ebSPyun YongHyeon &stats->rx_lenerrs, "Frames with length mismatched"); 1198d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1199d68875ebSPyun YongHyeon &stats->rx_bytes, "Good octets"); 1200d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1201d68875ebSPyun YongHyeon &stats->rx_bcast_bytes, "Good broadcast octets"); 1202d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1203d68875ebSPyun YongHyeon &stats->rx_mcast_bytes, "Good multicast octets"); 1204d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1205d68875ebSPyun YongHyeon &stats->rx_runts, "Too short frames"); 1206d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1207d68875ebSPyun YongHyeon &stats->rx_fragments, "Fragmented frames"); 1208d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1209d68875ebSPyun YongHyeon &stats->rx_pkts_64, "64 bytes frames"); 1210d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1211d68875ebSPyun YongHyeon &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1212d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1213d68875ebSPyun YongHyeon &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1214d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1215d68875ebSPyun YongHyeon &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1216d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1217d68875ebSPyun YongHyeon &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1218d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1219d68875ebSPyun YongHyeon &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1220d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1221d68875ebSPyun YongHyeon &stats->rx_pkts_1519_max, "1519 to max frames"); 1222d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1223d68875ebSPyun YongHyeon &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1224d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1225d68875ebSPyun YongHyeon &stats->rx_fifo_oflows, "FIFO overflows"); 1226d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1227d68875ebSPyun YongHyeon &stats->rx_rrs_errs, "Return status write-back errors"); 1228d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1229d68875ebSPyun YongHyeon &stats->rx_alignerrs, "Alignment errors"); 1230d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1231d68875ebSPyun YongHyeon &stats->rx_pkts_filtered, 1232d68875ebSPyun YongHyeon "Frames dropped due to address filtering"); 1233d68875ebSPyun YongHyeon 1234d68875ebSPyun YongHyeon /* Tx statistics. */ 1235d68875ebSPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1236d68875ebSPyun YongHyeon NULL, "Tx MAC statistics"); 1237d68875ebSPyun YongHyeon child = SYSCTL_CHILDREN(tree); 1238d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1239d68875ebSPyun YongHyeon &stats->tx_frames, "Good frames"); 1240d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1241d68875ebSPyun YongHyeon &stats->tx_bcast_frames, "Good broadcast frames"); 1242d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1243d68875ebSPyun YongHyeon &stats->tx_mcast_frames, "Good multicast frames"); 1244d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1245d68875ebSPyun YongHyeon &stats->tx_pause_frames, "Pause control frames"); 1246d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1247d68875ebSPyun YongHyeon &stats->tx_control_frames, "Control frames"); 1248d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1249d68875ebSPyun YongHyeon &stats->tx_excess_defer, "Frames with excessive derferrals"); 1250d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1251d68875ebSPyun YongHyeon &stats->tx_excess_defer, "Frames with derferrals"); 1252d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1253d68875ebSPyun YongHyeon &stats->tx_bytes, "Good octets"); 1254d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1255d68875ebSPyun YongHyeon &stats->tx_bcast_bytes, "Good broadcast octets"); 1256d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1257d68875ebSPyun YongHyeon &stats->tx_mcast_bytes, "Good multicast octets"); 1258d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1259d68875ebSPyun YongHyeon &stats->tx_pkts_64, "64 bytes frames"); 1260d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1261d68875ebSPyun YongHyeon &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1262d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1263d68875ebSPyun YongHyeon &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1264d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1265d68875ebSPyun YongHyeon &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1266d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1267d68875ebSPyun YongHyeon &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1268d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1269d68875ebSPyun YongHyeon &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1270d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1271d68875ebSPyun YongHyeon &stats->tx_pkts_1519_max, "1519 to max frames"); 1272d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1273d68875ebSPyun YongHyeon &stats->tx_single_colls, "Single collisions"); 1274d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1275d68875ebSPyun YongHyeon &stats->tx_multi_colls, "Multiple collisions"); 1276d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1277d68875ebSPyun YongHyeon &stats->tx_late_colls, "Late collisions"); 1278d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1279d68875ebSPyun YongHyeon &stats->tx_excess_colls, "Excessive collisions"); 1280d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1281d68875ebSPyun YongHyeon &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1282d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1283d68875ebSPyun YongHyeon &stats->tx_underrun, "FIFO underruns"); 1284d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1285d68875ebSPyun YongHyeon &stats->tx_desc_underrun, "Descriptor write-back errors"); 1286d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1287d68875ebSPyun YongHyeon &stats->tx_lenerrs, "Frames with length mismatched"); 1288d68875ebSPyun YongHyeon ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1289d68875ebSPyun YongHyeon &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1290d68875ebSPyun YongHyeon } 1291d68875ebSPyun YongHyeon 1292d68875ebSPyun YongHyeon #undef ALC_SYSCTL_STAT_ADD32 1293d68875ebSPyun YongHyeon #undef ALC_SYSCTL_STAT_ADD64 1294d68875ebSPyun YongHyeon 1295d68875ebSPyun YongHyeon struct alc_dmamap_arg { 1296d68875ebSPyun YongHyeon bus_addr_t alc_busaddr; 1297d68875ebSPyun YongHyeon }; 1298d68875ebSPyun YongHyeon 1299d68875ebSPyun YongHyeon static void 1300d68875ebSPyun YongHyeon alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1301d68875ebSPyun YongHyeon { 1302d68875ebSPyun YongHyeon struct alc_dmamap_arg *ctx; 1303d68875ebSPyun YongHyeon 1304d68875ebSPyun YongHyeon if (error != 0) 1305d68875ebSPyun YongHyeon return; 1306d68875ebSPyun YongHyeon 1307d68875ebSPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1308d68875ebSPyun YongHyeon 1309d68875ebSPyun YongHyeon ctx = (struct alc_dmamap_arg *)arg; 1310d68875ebSPyun YongHyeon ctx->alc_busaddr = segs[0].ds_addr; 1311d68875ebSPyun YongHyeon } 1312d68875ebSPyun YongHyeon 1313d68875ebSPyun YongHyeon /* 1314d68875ebSPyun YongHyeon * Normal and high Tx descriptors shares single Tx high address. 1315d68875ebSPyun YongHyeon * Four Rx descriptor/return rings and CMB shares the same Rx 1316d68875ebSPyun YongHyeon * high address. 1317d68875ebSPyun YongHyeon */ 1318d68875ebSPyun YongHyeon static int 1319d68875ebSPyun YongHyeon alc_check_boundary(struct alc_softc *sc) 1320d68875ebSPyun YongHyeon { 1321d68875ebSPyun YongHyeon bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1322d68875ebSPyun YongHyeon 1323d68875ebSPyun YongHyeon rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1324d68875ebSPyun YongHyeon rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1325d68875ebSPyun YongHyeon cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1326d68875ebSPyun YongHyeon tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1327d68875ebSPyun YongHyeon 1328d68875ebSPyun YongHyeon /* 4GB boundary crossing is not allowed. */ 1329d68875ebSPyun YongHyeon if ((ALC_ADDR_HI(rx_ring_end) != 1330d68875ebSPyun YongHyeon ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1331d68875ebSPyun YongHyeon (ALC_ADDR_HI(rr_ring_end) != 1332d68875ebSPyun YongHyeon ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1333d68875ebSPyun YongHyeon (ALC_ADDR_HI(cmb_end) != 1334d68875ebSPyun YongHyeon ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1335d68875ebSPyun YongHyeon (ALC_ADDR_HI(tx_ring_end) != 1336d68875ebSPyun YongHyeon ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1337d68875ebSPyun YongHyeon return (EFBIG); 1338d68875ebSPyun YongHyeon /* 1339d68875ebSPyun YongHyeon * Make sure Rx return descriptor/Rx descriptor/CMB use 1340d68875ebSPyun YongHyeon * the same high address. 1341d68875ebSPyun YongHyeon */ 1342d68875ebSPyun YongHyeon if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1343d68875ebSPyun YongHyeon (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1344d68875ebSPyun YongHyeon return (EFBIG); 1345d68875ebSPyun YongHyeon 1346d68875ebSPyun YongHyeon return (0); 1347d68875ebSPyun YongHyeon } 1348d68875ebSPyun YongHyeon 1349d68875ebSPyun YongHyeon static int 1350d68875ebSPyun YongHyeon alc_dma_alloc(struct alc_softc *sc) 1351d68875ebSPyun YongHyeon { 1352d68875ebSPyun YongHyeon struct alc_txdesc *txd; 1353d68875ebSPyun YongHyeon struct alc_rxdesc *rxd; 1354d68875ebSPyun YongHyeon bus_addr_t lowaddr; 1355d68875ebSPyun YongHyeon struct alc_dmamap_arg ctx; 1356d68875ebSPyun YongHyeon int error, i; 1357d68875ebSPyun YongHyeon 1358d68875ebSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 1359d68875ebSPyun YongHyeon again: 1360d68875ebSPyun YongHyeon /* Create parent DMA tag. */ 1361d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1362d68875ebSPyun YongHyeon bus_get_dma_tag(sc->alc_dev), /* parent */ 1363d68875ebSPyun YongHyeon 1, 0, /* alignment, boundary */ 1364d68875ebSPyun YongHyeon lowaddr, /* lowaddr */ 1365d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1366d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1367d68875ebSPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1368d68875ebSPyun YongHyeon 0, /* nsegments */ 1369d68875ebSPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1370d68875ebSPyun YongHyeon 0, /* flags */ 1371d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1372d68875ebSPyun YongHyeon &sc->alc_cdata.alc_parent_tag); 1373d68875ebSPyun YongHyeon if (error != 0) { 1374d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1375d68875ebSPyun YongHyeon "could not create parent DMA tag.\n"); 1376d68875ebSPyun YongHyeon goto fail; 1377d68875ebSPyun YongHyeon } 1378d68875ebSPyun YongHyeon 1379d68875ebSPyun YongHyeon /* Create DMA tag for Tx descriptor ring. */ 1380d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1381d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag, /* parent */ 1382d68875ebSPyun YongHyeon ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1383d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1384d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1385d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1386d68875ebSPyun YongHyeon ALC_TX_RING_SZ, /* maxsize */ 1387d68875ebSPyun YongHyeon 1, /* nsegments */ 1388d68875ebSPyun YongHyeon ALC_TX_RING_SZ, /* maxsegsize */ 1389d68875ebSPyun YongHyeon 0, /* flags */ 1390d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1391d68875ebSPyun YongHyeon &sc->alc_cdata.alc_tx_ring_tag); 1392d68875ebSPyun YongHyeon if (error != 0) { 1393d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1394d68875ebSPyun YongHyeon "could not create Tx ring DMA tag.\n"); 1395d68875ebSPyun YongHyeon goto fail; 1396d68875ebSPyun YongHyeon } 1397d68875ebSPyun YongHyeon 1398d68875ebSPyun YongHyeon /* Create DMA tag for Rx free descriptor ring. */ 1399d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1400d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag, /* parent */ 1401d68875ebSPyun YongHyeon ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1402d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1403d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1404d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1405d68875ebSPyun YongHyeon ALC_RX_RING_SZ, /* maxsize */ 1406d68875ebSPyun YongHyeon 1, /* nsegments */ 1407d68875ebSPyun YongHyeon ALC_RX_RING_SZ, /* maxsegsize */ 1408d68875ebSPyun YongHyeon 0, /* flags */ 1409d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1410d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rx_ring_tag); 1411d68875ebSPyun YongHyeon if (error != 0) { 1412d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1413d68875ebSPyun YongHyeon "could not create Rx ring DMA tag.\n"); 1414d68875ebSPyun YongHyeon goto fail; 1415d68875ebSPyun YongHyeon } 1416d68875ebSPyun YongHyeon /* Create DMA tag for Rx return descriptor ring. */ 1417d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1418d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag, /* parent */ 1419d68875ebSPyun YongHyeon ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1420d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1421d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1422d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1423d68875ebSPyun YongHyeon ALC_RR_RING_SZ, /* maxsize */ 1424d68875ebSPyun YongHyeon 1, /* nsegments */ 1425d68875ebSPyun YongHyeon ALC_RR_RING_SZ, /* maxsegsize */ 1426d68875ebSPyun YongHyeon 0, /* flags */ 1427d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1428d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rr_ring_tag); 1429d68875ebSPyun YongHyeon if (error != 0) { 1430d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1431d68875ebSPyun YongHyeon "could not create Rx return ring DMA tag.\n"); 1432d68875ebSPyun YongHyeon goto fail; 1433d68875ebSPyun YongHyeon } 1434d68875ebSPyun YongHyeon 1435d68875ebSPyun YongHyeon /* Create DMA tag for coalescing message block. */ 1436d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1437d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag, /* parent */ 1438d68875ebSPyun YongHyeon ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1439d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1440d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1441d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1442d68875ebSPyun YongHyeon ALC_CMB_SZ, /* maxsize */ 1443d68875ebSPyun YongHyeon 1, /* nsegments */ 1444d68875ebSPyun YongHyeon ALC_CMB_SZ, /* maxsegsize */ 1445d68875ebSPyun YongHyeon 0, /* flags */ 1446d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1447d68875ebSPyun YongHyeon &sc->alc_cdata.alc_cmb_tag); 1448d68875ebSPyun YongHyeon if (error != 0) { 1449d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1450d68875ebSPyun YongHyeon "could not create CMB DMA tag.\n"); 1451d68875ebSPyun YongHyeon goto fail; 1452d68875ebSPyun YongHyeon } 1453d68875ebSPyun YongHyeon /* Create DMA tag for status message block. */ 1454d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1455d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag, /* parent */ 1456d68875ebSPyun YongHyeon ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1457d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1458d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1459d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1460d68875ebSPyun YongHyeon ALC_SMB_SZ, /* maxsize */ 1461d68875ebSPyun YongHyeon 1, /* nsegments */ 1462d68875ebSPyun YongHyeon ALC_SMB_SZ, /* maxsegsize */ 1463d68875ebSPyun YongHyeon 0, /* flags */ 1464d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1465d68875ebSPyun YongHyeon &sc->alc_cdata.alc_smb_tag); 1466d68875ebSPyun YongHyeon if (error != 0) { 1467d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1468d68875ebSPyun YongHyeon "could not create SMB DMA tag.\n"); 1469d68875ebSPyun YongHyeon goto fail; 1470d68875ebSPyun YongHyeon } 1471d68875ebSPyun YongHyeon 1472d68875ebSPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1473d68875ebSPyun YongHyeon error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1474d68875ebSPyun YongHyeon (void **)&sc->alc_rdata.alc_tx_ring, 1475d68875ebSPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1476d68875ebSPyun YongHyeon &sc->alc_cdata.alc_tx_ring_map); 1477d68875ebSPyun YongHyeon if (error != 0) { 1478d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1479d68875ebSPyun YongHyeon "could not allocate DMA'able memory for Tx ring.\n"); 1480d68875ebSPyun YongHyeon goto fail; 1481d68875ebSPyun YongHyeon } 1482d68875ebSPyun YongHyeon ctx.alc_busaddr = 0; 1483d68875ebSPyun YongHyeon error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1484d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1485d68875ebSPyun YongHyeon ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1486d68875ebSPyun YongHyeon if (error != 0 || ctx.alc_busaddr == 0) { 1487d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1488d68875ebSPyun YongHyeon "could not load DMA'able memory for Tx ring.\n"); 1489d68875ebSPyun YongHyeon goto fail; 1490d68875ebSPyun YongHyeon } 1491d68875ebSPyun YongHyeon sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1492d68875ebSPyun YongHyeon 1493d68875ebSPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1494d68875ebSPyun YongHyeon error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1495d68875ebSPyun YongHyeon (void **)&sc->alc_rdata.alc_rx_ring, 1496d68875ebSPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1497d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rx_ring_map); 1498d68875ebSPyun YongHyeon if (error != 0) { 1499d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1500d68875ebSPyun YongHyeon "could not allocate DMA'able memory for Rx ring.\n"); 1501d68875ebSPyun YongHyeon goto fail; 1502d68875ebSPyun YongHyeon } 1503d68875ebSPyun YongHyeon ctx.alc_busaddr = 0; 1504d68875ebSPyun YongHyeon error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1505d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1506d68875ebSPyun YongHyeon ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1507d68875ebSPyun YongHyeon if (error != 0 || ctx.alc_busaddr == 0) { 1508d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1509d68875ebSPyun YongHyeon "could not load DMA'able memory for Rx ring.\n"); 1510d68875ebSPyun YongHyeon goto fail; 1511d68875ebSPyun YongHyeon } 1512d68875ebSPyun YongHyeon sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1513d68875ebSPyun YongHyeon 1514d68875ebSPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1515d68875ebSPyun YongHyeon error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1516d68875ebSPyun YongHyeon (void **)&sc->alc_rdata.alc_rr_ring, 1517d68875ebSPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1518d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rr_ring_map); 1519d68875ebSPyun YongHyeon if (error != 0) { 1520d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1521d68875ebSPyun YongHyeon "could not allocate DMA'able memory for Rx return ring.\n"); 1522d68875ebSPyun YongHyeon goto fail; 1523d68875ebSPyun YongHyeon } 1524d68875ebSPyun YongHyeon ctx.alc_busaddr = 0; 1525d68875ebSPyun YongHyeon error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1526d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1527d68875ebSPyun YongHyeon ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1528d68875ebSPyun YongHyeon if (error != 0 || ctx.alc_busaddr == 0) { 1529d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1530d68875ebSPyun YongHyeon "could not load DMA'able memory for Tx ring.\n"); 1531d68875ebSPyun YongHyeon goto fail; 1532d68875ebSPyun YongHyeon } 1533d68875ebSPyun YongHyeon sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1534d68875ebSPyun YongHyeon 1535d68875ebSPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for CMB. */ 1536d68875ebSPyun YongHyeon error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1537d68875ebSPyun YongHyeon (void **)&sc->alc_rdata.alc_cmb, 1538d68875ebSPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1539d68875ebSPyun YongHyeon &sc->alc_cdata.alc_cmb_map); 1540d68875ebSPyun YongHyeon if (error != 0) { 1541d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1542d68875ebSPyun YongHyeon "could not allocate DMA'able memory for CMB.\n"); 1543d68875ebSPyun YongHyeon goto fail; 1544d68875ebSPyun YongHyeon } 1545d68875ebSPyun YongHyeon ctx.alc_busaddr = 0; 1546d68875ebSPyun YongHyeon error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1547d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1548d68875ebSPyun YongHyeon ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1549d68875ebSPyun YongHyeon if (error != 0 || ctx.alc_busaddr == 0) { 1550d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1551d68875ebSPyun YongHyeon "could not load DMA'able memory for CMB.\n"); 1552d68875ebSPyun YongHyeon goto fail; 1553d68875ebSPyun YongHyeon } 1554d68875ebSPyun YongHyeon sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1555d68875ebSPyun YongHyeon 1556d68875ebSPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for SMB. */ 1557d68875ebSPyun YongHyeon error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1558d68875ebSPyun YongHyeon (void **)&sc->alc_rdata.alc_smb, 1559d68875ebSPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1560d68875ebSPyun YongHyeon &sc->alc_cdata.alc_smb_map); 1561d68875ebSPyun YongHyeon if (error != 0) { 1562d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1563d68875ebSPyun YongHyeon "could not allocate DMA'able memory for SMB.\n"); 1564d68875ebSPyun YongHyeon goto fail; 1565d68875ebSPyun YongHyeon } 1566d68875ebSPyun YongHyeon ctx.alc_busaddr = 0; 1567d68875ebSPyun YongHyeon error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1568d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1569d68875ebSPyun YongHyeon ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1570d68875ebSPyun YongHyeon if (error != 0 || ctx.alc_busaddr == 0) { 1571d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1572d68875ebSPyun YongHyeon "could not load DMA'able memory for CMB.\n"); 1573d68875ebSPyun YongHyeon goto fail; 1574d68875ebSPyun YongHyeon } 1575d68875ebSPyun YongHyeon sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1576d68875ebSPyun YongHyeon 1577d68875ebSPyun YongHyeon /* Make sure we've not crossed 4GB boundary. */ 1578d68875ebSPyun YongHyeon if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1579d68875ebSPyun YongHyeon (error = alc_check_boundary(sc)) != 0) { 1580d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "4GB boundary crossed, " 1581d68875ebSPyun YongHyeon "switching to 32bit DMA addressing mode.\n"); 1582d68875ebSPyun YongHyeon alc_dma_free(sc); 1583d68875ebSPyun YongHyeon /* 1584d68875ebSPyun YongHyeon * Limit max allowable DMA address space to 32bit 1585d68875ebSPyun YongHyeon * and try again. 1586d68875ebSPyun YongHyeon */ 1587d68875ebSPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 1588d68875ebSPyun YongHyeon goto again; 1589d68875ebSPyun YongHyeon } 1590d68875ebSPyun YongHyeon 1591d68875ebSPyun YongHyeon /* 1592d68875ebSPyun YongHyeon * Create Tx buffer parent tag. 15932f70cceaSPyun YongHyeon * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1594d68875ebSPyun YongHyeon * so it needs separate parent DMA tag as parent DMA address 1595d68875ebSPyun YongHyeon * space could be restricted to be within 32bit address space 1596d68875ebSPyun YongHyeon * by 4GB boundary crossing. 1597d68875ebSPyun YongHyeon */ 1598d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1599d68875ebSPyun YongHyeon bus_get_dma_tag(sc->alc_dev), /* parent */ 1600d68875ebSPyun YongHyeon 1, 0, /* alignment, boundary */ 1601d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1602d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1603d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1604d68875ebSPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1605d68875ebSPyun YongHyeon 0, /* nsegments */ 1606d68875ebSPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1607d68875ebSPyun YongHyeon 0, /* flags */ 1608d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1609d68875ebSPyun YongHyeon &sc->alc_cdata.alc_buffer_tag); 1610d68875ebSPyun YongHyeon if (error != 0) { 1611d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1612d68875ebSPyun YongHyeon "could not create parent buffer DMA tag.\n"); 1613d68875ebSPyun YongHyeon goto fail; 1614d68875ebSPyun YongHyeon } 1615d68875ebSPyun YongHyeon 1616d68875ebSPyun YongHyeon /* Create DMA tag for Tx buffers. */ 1617d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1618d68875ebSPyun YongHyeon sc->alc_cdata.alc_buffer_tag, /* parent */ 1619d68875ebSPyun YongHyeon 1, 0, /* alignment, boundary */ 1620d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1621d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1622d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1623d68875ebSPyun YongHyeon ALC_TSO_MAXSIZE, /* maxsize */ 1624d68875ebSPyun YongHyeon ALC_MAXTXSEGS, /* nsegments */ 1625d68875ebSPyun YongHyeon ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1626d68875ebSPyun YongHyeon 0, /* flags */ 1627d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1628d68875ebSPyun YongHyeon &sc->alc_cdata.alc_tx_tag); 1629d68875ebSPyun YongHyeon if (error != 0) { 1630d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1631d68875ebSPyun YongHyeon goto fail; 1632d68875ebSPyun YongHyeon } 1633d68875ebSPyun YongHyeon 1634d68875ebSPyun YongHyeon /* Create DMA tag for Rx buffers. */ 1635d68875ebSPyun YongHyeon error = bus_dma_tag_create( 1636d68875ebSPyun YongHyeon sc->alc_cdata.alc_buffer_tag, /* parent */ 1637d68875ebSPyun YongHyeon ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1638d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 1639d68875ebSPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 1640d68875ebSPyun YongHyeon NULL, NULL, /* filter, filterarg */ 1641d68875ebSPyun YongHyeon MCLBYTES, /* maxsize */ 1642d68875ebSPyun YongHyeon 1, /* nsegments */ 1643d68875ebSPyun YongHyeon MCLBYTES, /* maxsegsize */ 1644d68875ebSPyun YongHyeon 0, /* flags */ 1645d68875ebSPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 1646d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rx_tag); 1647d68875ebSPyun YongHyeon if (error != 0) { 1648d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1649d68875ebSPyun YongHyeon goto fail; 1650d68875ebSPyun YongHyeon } 1651d68875ebSPyun YongHyeon /* Create DMA maps for Tx buffers. */ 1652d68875ebSPyun YongHyeon for (i = 0; i < ALC_TX_RING_CNT; i++) { 1653d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[i]; 1654d68875ebSPyun YongHyeon txd->tx_m = NULL; 1655d68875ebSPyun YongHyeon txd->tx_dmamap = NULL; 1656d68875ebSPyun YongHyeon error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1657d68875ebSPyun YongHyeon &txd->tx_dmamap); 1658d68875ebSPyun YongHyeon if (error != 0) { 1659d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1660d68875ebSPyun YongHyeon "could not create Tx dmamap.\n"); 1661d68875ebSPyun YongHyeon goto fail; 1662d68875ebSPyun YongHyeon } 1663d68875ebSPyun YongHyeon } 1664d68875ebSPyun YongHyeon /* Create DMA maps for Rx buffers. */ 1665d68875ebSPyun YongHyeon if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1666d68875ebSPyun YongHyeon &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1667d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1668d68875ebSPyun YongHyeon "could not create spare Rx dmamap.\n"); 1669d68875ebSPyun YongHyeon goto fail; 1670d68875ebSPyun YongHyeon } 1671d68875ebSPyun YongHyeon for (i = 0; i < ALC_RX_RING_CNT; i++) { 1672d68875ebSPyun YongHyeon rxd = &sc->alc_cdata.alc_rxdesc[i]; 1673d68875ebSPyun YongHyeon rxd->rx_m = NULL; 1674d68875ebSPyun YongHyeon rxd->rx_dmamap = NULL; 1675d68875ebSPyun YongHyeon error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1676d68875ebSPyun YongHyeon &rxd->rx_dmamap); 1677d68875ebSPyun YongHyeon if (error != 0) { 1678d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1679d68875ebSPyun YongHyeon "could not create Rx dmamap.\n"); 1680d68875ebSPyun YongHyeon goto fail; 1681d68875ebSPyun YongHyeon } 1682d68875ebSPyun YongHyeon } 1683d68875ebSPyun YongHyeon 1684d68875ebSPyun YongHyeon fail: 1685d68875ebSPyun YongHyeon return (error); 1686d68875ebSPyun YongHyeon } 1687d68875ebSPyun YongHyeon 1688d68875ebSPyun YongHyeon static void 1689d68875ebSPyun YongHyeon alc_dma_free(struct alc_softc *sc) 1690d68875ebSPyun YongHyeon { 1691d68875ebSPyun YongHyeon struct alc_txdesc *txd; 1692d68875ebSPyun YongHyeon struct alc_rxdesc *rxd; 1693d68875ebSPyun YongHyeon int i; 1694d68875ebSPyun YongHyeon 1695d68875ebSPyun YongHyeon /* Tx buffers. */ 1696d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_tag != NULL) { 1697d68875ebSPyun YongHyeon for (i = 0; i < ALC_TX_RING_CNT; i++) { 1698d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[i]; 1699d68875ebSPyun YongHyeon if (txd->tx_dmamap != NULL) { 1700d68875ebSPyun YongHyeon bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1701d68875ebSPyun YongHyeon txd->tx_dmamap); 1702d68875ebSPyun YongHyeon txd->tx_dmamap = NULL; 1703d68875ebSPyun YongHyeon } 1704d68875ebSPyun YongHyeon } 1705d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1706d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_tag = NULL; 1707d68875ebSPyun YongHyeon } 1708d68875ebSPyun YongHyeon /* Rx buffers */ 1709d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rx_tag != NULL) { 1710d68875ebSPyun YongHyeon for (i = 0; i < ALC_RX_RING_CNT; i++) { 1711d68875ebSPyun YongHyeon rxd = &sc->alc_cdata.alc_rxdesc[i]; 1712d68875ebSPyun YongHyeon if (rxd->rx_dmamap != NULL) { 1713d68875ebSPyun YongHyeon bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1714d68875ebSPyun YongHyeon rxd->rx_dmamap); 1715d68875ebSPyun YongHyeon rxd->rx_dmamap = NULL; 1716d68875ebSPyun YongHyeon } 1717d68875ebSPyun YongHyeon } 1718d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1719d68875ebSPyun YongHyeon bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1720d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_sparemap); 1721d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_sparemap = NULL; 1722d68875ebSPyun YongHyeon } 1723d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1724d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_tag = NULL; 1725d68875ebSPyun YongHyeon } 1726d68875ebSPyun YongHyeon /* Tx descriptor ring. */ 1727d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1728d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_ring_map != NULL) 1729d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1730d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map); 1731d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_ring_map != NULL && 1732d68875ebSPyun YongHyeon sc->alc_rdata.alc_tx_ring != NULL) 1733d68875ebSPyun YongHyeon bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1734d68875ebSPyun YongHyeon sc->alc_rdata.alc_tx_ring, 1735d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map); 1736d68875ebSPyun YongHyeon sc->alc_rdata.alc_tx_ring = NULL; 1737d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map = NULL; 1738d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1739d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_tag = NULL; 1740d68875ebSPyun YongHyeon } 17416ece67d8SKevin Lo /* Rx ring. */ 17426ece67d8SKevin Lo if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 17436ece67d8SKevin Lo if (sc->alc_cdata.alc_rx_ring_map != NULL) 17446ece67d8SKevin Lo bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 17456ece67d8SKevin Lo sc->alc_cdata.alc_rx_ring_map); 17466ece67d8SKevin Lo if (sc->alc_cdata.alc_rx_ring_map != NULL && 17476ece67d8SKevin Lo sc->alc_rdata.alc_rx_ring != NULL) 17486ece67d8SKevin Lo bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 17496ece67d8SKevin Lo sc->alc_rdata.alc_rx_ring, 17506ece67d8SKevin Lo sc->alc_cdata.alc_rx_ring_map); 17516ece67d8SKevin Lo sc->alc_rdata.alc_rx_ring = NULL; 17526ece67d8SKevin Lo sc->alc_cdata.alc_rx_ring_map = NULL; 17536ece67d8SKevin Lo bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 17546ece67d8SKevin Lo sc->alc_cdata.alc_rx_ring_tag = NULL; 17556ece67d8SKevin Lo } 1756d68875ebSPyun YongHyeon /* Rx return ring. */ 1757d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1758d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rr_ring_map != NULL) 1759d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1760d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map); 1761d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rr_ring_map != NULL && 1762d68875ebSPyun YongHyeon sc->alc_rdata.alc_rr_ring != NULL) 1763d68875ebSPyun YongHyeon bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1764d68875ebSPyun YongHyeon sc->alc_rdata.alc_rr_ring, 1765d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map); 1766d68875ebSPyun YongHyeon sc->alc_rdata.alc_rr_ring = NULL; 1767d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map = NULL; 1768d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1769d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_tag = NULL; 1770d68875ebSPyun YongHyeon } 1771d68875ebSPyun YongHyeon /* CMB block */ 1772d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_cmb_tag != NULL) { 1773d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_cmb_map != NULL) 1774d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1775d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map); 1776d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_cmb_map != NULL && 1777d68875ebSPyun YongHyeon sc->alc_rdata.alc_cmb != NULL) 1778d68875ebSPyun YongHyeon bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1779d68875ebSPyun YongHyeon sc->alc_rdata.alc_cmb, 1780d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map); 1781d68875ebSPyun YongHyeon sc->alc_rdata.alc_cmb = NULL; 1782d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map = NULL; 1783d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1784d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_tag = NULL; 1785d68875ebSPyun YongHyeon } 1786d68875ebSPyun YongHyeon /* SMB block */ 1787d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_smb_tag != NULL) { 1788d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_smb_map != NULL) 1789d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1790d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map); 1791d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_smb_map != NULL && 1792d68875ebSPyun YongHyeon sc->alc_rdata.alc_smb != NULL) 1793d68875ebSPyun YongHyeon bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1794d68875ebSPyun YongHyeon sc->alc_rdata.alc_smb, 1795d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map); 1796d68875ebSPyun YongHyeon sc->alc_rdata.alc_smb = NULL; 1797d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map = NULL; 1798d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1799d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_tag = NULL; 1800d68875ebSPyun YongHyeon } 1801d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_buffer_tag != NULL) { 1802d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1803d68875ebSPyun YongHyeon sc->alc_cdata.alc_buffer_tag = NULL; 1804d68875ebSPyun YongHyeon } 1805d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_parent_tag != NULL) { 1806d68875ebSPyun YongHyeon bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1807d68875ebSPyun YongHyeon sc->alc_cdata.alc_parent_tag = NULL; 1808d68875ebSPyun YongHyeon } 1809d68875ebSPyun YongHyeon } 1810d68875ebSPyun YongHyeon 1811d68875ebSPyun YongHyeon static int 1812d68875ebSPyun YongHyeon alc_shutdown(device_t dev) 1813d68875ebSPyun YongHyeon { 1814d68875ebSPyun YongHyeon 1815d68875ebSPyun YongHyeon return (alc_suspend(dev)); 1816d68875ebSPyun YongHyeon } 1817d68875ebSPyun YongHyeon 1818d68875ebSPyun YongHyeon /* 1819d68875ebSPyun YongHyeon * Note, this driver resets the link speed to 10/100Mbps by 1820d68875ebSPyun YongHyeon * restarting auto-negotiation in suspend/shutdown phase but we 1821d68875ebSPyun YongHyeon * don't know whether that auto-negotiation would succeed or not 1822d68875ebSPyun YongHyeon * as driver has no control after powering off/suspend operation. 1823d68875ebSPyun YongHyeon * If the renegotiation fail WOL may not work. Running at 1Gbps 1824d68875ebSPyun YongHyeon * will draw more power than 375mA at 3.3V which is specified in 1825d68875ebSPyun YongHyeon * PCI specification and that would result in complete 1826d68875ebSPyun YongHyeon * shutdowning power to ethernet controller. 1827d68875ebSPyun YongHyeon * 1828d68875ebSPyun YongHyeon * TODO 1829d68875ebSPyun YongHyeon * Save current negotiated media speed/duplex/flow-control to 1830d68875ebSPyun YongHyeon * softc and restore the same link again after resuming. PHY 1831d68875ebSPyun YongHyeon * handling such as power down/resetting to 100Mbps may be better 1832d68875ebSPyun YongHyeon * handled in suspend method in phy driver. 1833d68875ebSPyun YongHyeon */ 1834d68875ebSPyun YongHyeon static void 1835d68875ebSPyun YongHyeon alc_setlinkspeed(struct alc_softc *sc) 1836d68875ebSPyun YongHyeon { 1837d68875ebSPyun YongHyeon struct mii_data *mii; 1838d68875ebSPyun YongHyeon int aneg, i; 1839d68875ebSPyun YongHyeon 1840d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 1841d68875ebSPyun YongHyeon mii_pollstat(mii); 1842d68875ebSPyun YongHyeon aneg = 0; 1843d68875ebSPyun YongHyeon if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1844d68875ebSPyun YongHyeon (IFM_ACTIVE | IFM_AVALID)) { 1845d68875ebSPyun YongHyeon switch IFM_SUBTYPE(mii->mii_media_active) { 1846d68875ebSPyun YongHyeon case IFM_10_T: 1847d68875ebSPyun YongHyeon case IFM_100_TX: 1848d68875ebSPyun YongHyeon return; 1849d68875ebSPyun YongHyeon case IFM_1000_T: 1850d68875ebSPyun YongHyeon aneg++; 1851d68875ebSPyun YongHyeon break; 1852d68875ebSPyun YongHyeon default: 1853d68875ebSPyun YongHyeon break; 1854d68875ebSPyun YongHyeon } 1855d68875ebSPyun YongHyeon } 1856d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1857d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1858d68875ebSPyun YongHyeon MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1859d68875ebSPyun YongHyeon alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1860d68875ebSPyun YongHyeon MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1861d68875ebSPyun YongHyeon DELAY(1000); 1862d68875ebSPyun YongHyeon if (aneg != 0) { 1863d68875ebSPyun YongHyeon /* 1864d68875ebSPyun YongHyeon * Poll link state until alc(4) get a 10/100Mbps link. 1865d68875ebSPyun YongHyeon */ 1866d68875ebSPyun YongHyeon for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1867d68875ebSPyun YongHyeon mii_pollstat(mii); 1868d68875ebSPyun YongHyeon if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1869d68875ebSPyun YongHyeon == (IFM_ACTIVE | IFM_AVALID)) { 1870d68875ebSPyun YongHyeon switch (IFM_SUBTYPE( 1871d68875ebSPyun YongHyeon mii->mii_media_active)) { 1872d68875ebSPyun YongHyeon case IFM_10_T: 1873d68875ebSPyun YongHyeon case IFM_100_TX: 1874d68875ebSPyun YongHyeon alc_mac_config(sc); 1875d68875ebSPyun YongHyeon return; 1876d68875ebSPyun YongHyeon default: 1877d68875ebSPyun YongHyeon break; 1878d68875ebSPyun YongHyeon } 1879d68875ebSPyun YongHyeon } 1880d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 1881d68875ebSPyun YongHyeon pause("alclnk", hz); 1882d68875ebSPyun YongHyeon ALC_LOCK(sc); 1883d68875ebSPyun YongHyeon } 1884d68875ebSPyun YongHyeon if (i == MII_ANEGTICKS_GIGE) 1885d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 1886d68875ebSPyun YongHyeon "establishing a link failed, WOL may not work!"); 1887d68875ebSPyun YongHyeon } 1888d68875ebSPyun YongHyeon /* 1889d68875ebSPyun YongHyeon * No link, force MAC to have 100Mbps, full-duplex link. 1890d68875ebSPyun YongHyeon * This is the last resort and may/may not work. 1891d68875ebSPyun YongHyeon */ 1892d68875ebSPyun YongHyeon mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1893d68875ebSPyun YongHyeon mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1894d68875ebSPyun YongHyeon alc_mac_config(sc); 1895d68875ebSPyun YongHyeon } 1896d68875ebSPyun YongHyeon 1897d68875ebSPyun YongHyeon static void 1898d68875ebSPyun YongHyeon alc_setwol(struct alc_softc *sc) 1899d68875ebSPyun YongHyeon { 1900d68875ebSPyun YongHyeon struct ifnet *ifp; 190147ae892cSPyun YongHyeon uint32_t reg, pmcs; 1902d68875ebSPyun YongHyeon uint16_t pmstat; 1903d68875ebSPyun YongHyeon 1904d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 1905d68875ebSPyun YongHyeon 1906d68875ebSPyun YongHyeon alc_disable_l0s_l1(sc); 190747ae892cSPyun YongHyeon ifp = sc->alc_ifp; 1908a4d3574cSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1909d68875ebSPyun YongHyeon /* Disable WOL. */ 1910d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1911d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1912d68875ebSPyun YongHyeon reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1913d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1914d68875ebSPyun YongHyeon /* Force PHY power down. */ 1915d68875ebSPyun YongHyeon alc_phy_down(sc); 191647ae892cSPyun YongHyeon CSR_WRITE_4(sc, ALC_MASTER_CFG, 191747ae892cSPyun YongHyeon CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1918d68875ebSPyun YongHyeon return; 1919d68875ebSPyun YongHyeon } 1920d68875ebSPyun YongHyeon 1921d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1922d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1923d68875ebSPyun YongHyeon alc_setlinkspeed(sc); 192447ae892cSPyun YongHyeon CSR_WRITE_4(sc, ALC_MASTER_CFG, 192547ae892cSPyun YongHyeon CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1926d68875ebSPyun YongHyeon } 1927d68875ebSPyun YongHyeon 1928d68875ebSPyun YongHyeon pmcs = 0; 1929d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1930d68875ebSPyun YongHyeon pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1931d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1932d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MAC_CFG); 1933d68875ebSPyun YongHyeon reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1934d68875ebSPyun YongHyeon MAC_CFG_BCAST); 1935d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1936d68875ebSPyun YongHyeon reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1937d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 1938d68875ebSPyun YongHyeon reg |= MAC_CFG_RX_ENB; 1939d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1940d68875ebSPyun YongHyeon 1941d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1942d68875ebSPyun YongHyeon reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1943d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1944d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1945d68875ebSPyun YongHyeon /* WOL disabled, PHY power down. */ 1946d68875ebSPyun YongHyeon alc_phy_down(sc); 194747ae892cSPyun YongHyeon CSR_WRITE_4(sc, ALC_MASTER_CFG, 194847ae892cSPyun YongHyeon CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1949d68875ebSPyun YongHyeon } 1950d68875ebSPyun YongHyeon /* Request PME. */ 1951a4d3574cSPyun YongHyeon pmstat = pci_read_config(sc->alc_dev, 1952a4d3574cSPyun YongHyeon sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1953d68875ebSPyun YongHyeon pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1954d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 1955d68875ebSPyun YongHyeon pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1956a4d3574cSPyun YongHyeon pci_write_config(sc->alc_dev, 1957a4d3574cSPyun YongHyeon sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1958d68875ebSPyun YongHyeon } 1959d68875ebSPyun YongHyeon 1960d68875ebSPyun YongHyeon static int 1961d68875ebSPyun YongHyeon alc_suspend(device_t dev) 1962d68875ebSPyun YongHyeon { 1963d68875ebSPyun YongHyeon struct alc_softc *sc; 1964d68875ebSPyun YongHyeon 1965d68875ebSPyun YongHyeon sc = device_get_softc(dev); 1966d68875ebSPyun YongHyeon 1967d68875ebSPyun YongHyeon ALC_LOCK(sc); 1968d68875ebSPyun YongHyeon alc_stop(sc); 1969d68875ebSPyun YongHyeon alc_setwol(sc); 1970d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 1971d68875ebSPyun YongHyeon 1972d68875ebSPyun YongHyeon return (0); 1973d68875ebSPyun YongHyeon } 1974d68875ebSPyun YongHyeon 1975d68875ebSPyun YongHyeon static int 1976d68875ebSPyun YongHyeon alc_resume(device_t dev) 1977d68875ebSPyun YongHyeon { 1978d68875ebSPyun YongHyeon struct alc_softc *sc; 1979d68875ebSPyun YongHyeon struct ifnet *ifp; 1980d68875ebSPyun YongHyeon uint16_t pmstat; 1981d68875ebSPyun YongHyeon 1982d68875ebSPyun YongHyeon sc = device_get_softc(dev); 1983d68875ebSPyun YongHyeon 1984d68875ebSPyun YongHyeon ALC_LOCK(sc); 1985a4d3574cSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1986d68875ebSPyun YongHyeon /* Disable PME and clear PME status. */ 1987d68875ebSPyun YongHyeon pmstat = pci_read_config(sc->alc_dev, 1988a4d3574cSPyun YongHyeon sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1989d68875ebSPyun YongHyeon if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1990d68875ebSPyun YongHyeon pmstat &= ~PCIM_PSTAT_PMEENABLE; 1991d68875ebSPyun YongHyeon pci_write_config(sc->alc_dev, 1992a4d3574cSPyun YongHyeon sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1993d68875ebSPyun YongHyeon } 1994d68875ebSPyun YongHyeon } 1995d68875ebSPyun YongHyeon /* Reset PHY. */ 1996d68875ebSPyun YongHyeon alc_phy_reset(sc); 1997d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 1998d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 1999d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2000d68875ebSPyun YongHyeon alc_init_locked(sc); 2001d68875ebSPyun YongHyeon } 2002d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2003d68875ebSPyun YongHyeon 2004d68875ebSPyun YongHyeon return (0); 2005d68875ebSPyun YongHyeon } 2006d68875ebSPyun YongHyeon 2007d68875ebSPyun YongHyeon static int 2008d68875ebSPyun YongHyeon alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2009d68875ebSPyun YongHyeon { 2010d68875ebSPyun YongHyeon struct alc_txdesc *txd, *txd_last; 2011d68875ebSPyun YongHyeon struct tx_desc *desc; 2012d68875ebSPyun YongHyeon struct mbuf *m; 2013d68875ebSPyun YongHyeon struct ip *ip; 2014d68875ebSPyun YongHyeon struct tcphdr *tcp; 2015d68875ebSPyun YongHyeon bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2016d68875ebSPyun YongHyeon bus_dmamap_t map; 2017cb2f3e7fSPyun YongHyeon uint32_t cflags, hdrlen, ip_off, poff, vtag; 2018d68875ebSPyun YongHyeon int error, idx, nsegs, prod; 2019d68875ebSPyun YongHyeon 2020d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 2021d68875ebSPyun YongHyeon 2022d68875ebSPyun YongHyeon M_ASSERTPKTHDR((*m_head)); 2023d68875ebSPyun YongHyeon 2024d68875ebSPyun YongHyeon m = *m_head; 2025d68875ebSPyun YongHyeon ip = NULL; 2026d68875ebSPyun YongHyeon tcp = NULL; 2027cb2f3e7fSPyun YongHyeon ip_off = poff = 0; 2028d68875ebSPyun YongHyeon if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2029d68875ebSPyun YongHyeon /* 20302f70cceaSPyun YongHyeon * AR813x/AR815x requires offset of TCP/UDP header in its 2031d68875ebSPyun YongHyeon * Tx descriptor to perform Tx checksum offloading. TSO 2032d68875ebSPyun YongHyeon * also requires TCP header offset and modification of 2033d68875ebSPyun YongHyeon * IP/TCP header. This kind of operation takes many CPU 2034d68875ebSPyun YongHyeon * cycles on FreeBSD so fast host CPU is required to get 2035d68875ebSPyun YongHyeon * smooth TSO performance. 2036d68875ebSPyun YongHyeon */ 2037cb2f3e7fSPyun YongHyeon struct ether_header *eh; 2038d68875ebSPyun YongHyeon 2039d68875ebSPyun YongHyeon if (M_WRITABLE(m) == 0) { 2040d68875ebSPyun YongHyeon /* Get a writable copy. */ 2041d68875ebSPyun YongHyeon m = m_dup(*m_head, M_DONTWAIT); 2042d68875ebSPyun YongHyeon /* Release original mbufs. */ 2043d68875ebSPyun YongHyeon m_freem(*m_head); 2044d68875ebSPyun YongHyeon if (m == NULL) { 2045d68875ebSPyun YongHyeon *m_head = NULL; 2046d68875ebSPyun YongHyeon return (ENOBUFS); 2047d68875ebSPyun YongHyeon } 2048d68875ebSPyun YongHyeon *m_head = m; 2049d68875ebSPyun YongHyeon } 2050d68875ebSPyun YongHyeon 2051cb2f3e7fSPyun YongHyeon ip_off = sizeof(struct ether_header); 2052cb2f3e7fSPyun YongHyeon m = m_pullup(m, ip_off); 2053d68875ebSPyun YongHyeon if (m == NULL) { 2054d68875ebSPyun YongHyeon *m_head = NULL; 2055d68875ebSPyun YongHyeon return (ENOBUFS); 2056d68875ebSPyun YongHyeon } 2057cb2f3e7fSPyun YongHyeon eh = mtod(m, struct ether_header *); 2058cb2f3e7fSPyun YongHyeon /* 2059cb2f3e7fSPyun YongHyeon * Check if hardware VLAN insertion is off. 2060cb2f3e7fSPyun YongHyeon * Additional check for LLC/SNAP frame? 2061cb2f3e7fSPyun YongHyeon */ 2062cb2f3e7fSPyun YongHyeon if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2063cb2f3e7fSPyun YongHyeon ip_off = sizeof(struct ether_vlan_header); 2064cb2f3e7fSPyun YongHyeon m = m_pullup(m, ip_off); 2065cb2f3e7fSPyun YongHyeon if (m == NULL) { 2066cb2f3e7fSPyun YongHyeon *m_head = NULL; 2067cb2f3e7fSPyun YongHyeon return (ENOBUFS); 2068cb2f3e7fSPyun YongHyeon } 2069cb2f3e7fSPyun YongHyeon } 2070cb2f3e7fSPyun YongHyeon m = m_pullup(m, ip_off + sizeof(struct ip)); 2071cb2f3e7fSPyun YongHyeon if (m == NULL) { 2072cb2f3e7fSPyun YongHyeon *m_head = NULL; 2073cb2f3e7fSPyun YongHyeon return (ENOBUFS); 2074cb2f3e7fSPyun YongHyeon } 2075cb2f3e7fSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + ip_off); 2076cb2f3e7fSPyun YongHyeon poff = ip_off + (ip->ip_hl << 2); 2077d68875ebSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2078d68875ebSPyun YongHyeon m = m_pullup(m, poff + sizeof(struct tcphdr)); 2079d68875ebSPyun YongHyeon if (m == NULL) { 2080d68875ebSPyun YongHyeon *m_head = NULL; 2081d68875ebSPyun YongHyeon return (ENOBUFS); 2082d68875ebSPyun YongHyeon } 2083d68875ebSPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2084d68875ebSPyun YongHyeon m = m_pullup(m, poff + (tcp->th_off << 2)); 2085d68875ebSPyun YongHyeon if (m == NULL) { 2086d68875ebSPyun YongHyeon *m_head = NULL; 2087d68875ebSPyun YongHyeon return (ENOBUFS); 2088d68875ebSPyun YongHyeon } 2089d68875ebSPyun YongHyeon /* 2090d68875ebSPyun YongHyeon * Due to strict adherence of Microsoft NDIS 2091d68875ebSPyun YongHyeon * Large Send specification, hardware expects 2092d68875ebSPyun YongHyeon * a pseudo TCP checksum inserted by upper 2093d68875ebSPyun YongHyeon * stack. Unfortunately the pseudo TCP 2094d68875ebSPyun YongHyeon * checksum that NDIS refers to does not include 2095d68875ebSPyun YongHyeon * TCP payload length so driver should recompute 2096d68875ebSPyun YongHyeon * the pseudo checksum here. Hopefully this 2097d68875ebSPyun YongHyeon * wouldn't be much burden on modern CPUs. 2098d68875ebSPyun YongHyeon * 2099d68875ebSPyun YongHyeon * Reset IP checksum and recompute TCP pseudo 2100d68875ebSPyun YongHyeon * checksum as NDIS specification said. 2101d68875ebSPyun YongHyeon */ 210296486faaSPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + ip_off); 210396486faaSPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2104d68875ebSPyun YongHyeon ip->ip_sum = 0; 2105d68875ebSPyun YongHyeon tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2106d68875ebSPyun YongHyeon ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2107d68875ebSPyun YongHyeon } 2108d68875ebSPyun YongHyeon *m_head = m; 2109d68875ebSPyun YongHyeon } 2110d68875ebSPyun YongHyeon 2111d68875ebSPyun YongHyeon prod = sc->alc_cdata.alc_tx_prod; 2112d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[prod]; 2113d68875ebSPyun YongHyeon txd_last = txd; 2114d68875ebSPyun YongHyeon map = txd->tx_dmamap; 2115d68875ebSPyun YongHyeon 2116d68875ebSPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2117d68875ebSPyun YongHyeon *m_head, txsegs, &nsegs, 0); 2118d68875ebSPyun YongHyeon if (error == EFBIG) { 2119d68875ebSPyun YongHyeon m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 2120d68875ebSPyun YongHyeon if (m == NULL) { 2121d68875ebSPyun YongHyeon m_freem(*m_head); 2122d68875ebSPyun YongHyeon *m_head = NULL; 2123d68875ebSPyun YongHyeon return (ENOMEM); 2124d68875ebSPyun YongHyeon } 2125d68875ebSPyun YongHyeon *m_head = m; 2126d68875ebSPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2127d68875ebSPyun YongHyeon *m_head, txsegs, &nsegs, 0); 2128d68875ebSPyun YongHyeon if (error != 0) { 2129d68875ebSPyun YongHyeon m_freem(*m_head); 2130d68875ebSPyun YongHyeon *m_head = NULL; 2131d68875ebSPyun YongHyeon return (error); 2132d68875ebSPyun YongHyeon } 2133d68875ebSPyun YongHyeon } else if (error != 0) 2134d68875ebSPyun YongHyeon return (error); 2135d68875ebSPyun YongHyeon if (nsegs == 0) { 2136d68875ebSPyun YongHyeon m_freem(*m_head); 2137d68875ebSPyun YongHyeon *m_head = NULL; 2138d68875ebSPyun YongHyeon return (EIO); 2139d68875ebSPyun YongHyeon } 2140d68875ebSPyun YongHyeon 2141d68875ebSPyun YongHyeon /* Check descriptor overrun. */ 2142d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2143d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2144d68875ebSPyun YongHyeon return (ENOBUFS); 2145d68875ebSPyun YongHyeon } 2146d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2147d68875ebSPyun YongHyeon 2148d68875ebSPyun YongHyeon m = *m_head; 2149d68875ebSPyun YongHyeon cflags = TD_ETHERNET; 2150d68875ebSPyun YongHyeon vtag = 0; 2151d68875ebSPyun YongHyeon desc = NULL; 2152d68875ebSPyun YongHyeon idx = 0; 2153d68875ebSPyun YongHyeon /* Configure VLAN hardware tag insertion. */ 2154d68875ebSPyun YongHyeon if ((m->m_flags & M_VLANTAG) != 0) { 2155d68875ebSPyun YongHyeon vtag = htons(m->m_pkthdr.ether_vtag); 2156d68875ebSPyun YongHyeon vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2157d68875ebSPyun YongHyeon cflags |= TD_INS_VLAN_TAG; 2158d68875ebSPyun YongHyeon } 21596da6d0a9SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2160d68875ebSPyun YongHyeon /* Request TSO and set MSS. */ 2161d68875ebSPyun YongHyeon cflags |= TD_TSO | TD_TSO_DESCV1; 2162d68875ebSPyun YongHyeon cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2163d68875ebSPyun YongHyeon TD_MSS_MASK; 2164d68875ebSPyun YongHyeon /* Set TCP header offset. */ 2165d68875ebSPyun YongHyeon cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2166d68875ebSPyun YongHyeon TD_TCPHDR_OFFSET_MASK; 2167d68875ebSPyun YongHyeon /* 21682f70cceaSPyun YongHyeon * AR813x/AR815x requires the first buffer should 2169d68875ebSPyun YongHyeon * only hold IP/TCP header data. Payload should 2170d68875ebSPyun YongHyeon * be handled in other descriptors. 2171d68875ebSPyun YongHyeon */ 2172d68875ebSPyun YongHyeon hdrlen = poff + (tcp->th_off << 2); 2173d68875ebSPyun YongHyeon desc = &sc->alc_rdata.alc_tx_ring[prod]; 2174d68875ebSPyun YongHyeon desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2175d68875ebSPyun YongHyeon desc->flags = htole32(cflags); 2176d68875ebSPyun YongHyeon desc->addr = htole64(txsegs[0].ds_addr); 2177d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cnt++; 2178d68875ebSPyun YongHyeon ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2179d68875ebSPyun YongHyeon if (m->m_len - hdrlen > 0) { 2180d68875ebSPyun YongHyeon /* Handle remaining payload of the first fragment. */ 2181d68875ebSPyun YongHyeon desc = &sc->alc_rdata.alc_tx_ring[prod]; 2182d68875ebSPyun YongHyeon desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2183d68875ebSPyun YongHyeon vtag)); 2184d68875ebSPyun YongHyeon desc->flags = htole32(cflags); 2185d68875ebSPyun YongHyeon desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2186d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cnt++; 2187d68875ebSPyun YongHyeon ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2188d68875ebSPyun YongHyeon } 2189d68875ebSPyun YongHyeon /* Handle remaining fragments. */ 2190d68875ebSPyun YongHyeon idx = 1; 21916da6d0a9SPyun YongHyeon } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 21926da6d0a9SPyun YongHyeon /* Configure Tx checksum offload. */ 21936da6d0a9SPyun YongHyeon #ifdef ALC_USE_CUSTOM_CSUM 21946da6d0a9SPyun YongHyeon cflags |= TD_CUSTOM_CSUM; 21956da6d0a9SPyun YongHyeon /* Set checksum start offset. */ 21966da6d0a9SPyun YongHyeon cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 21976da6d0a9SPyun YongHyeon TD_PLOAD_OFFSET_MASK; 21986da6d0a9SPyun YongHyeon /* Set checksum insertion position of TCP/UDP. */ 21996da6d0a9SPyun YongHyeon cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 22006da6d0a9SPyun YongHyeon TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 22016da6d0a9SPyun YongHyeon #else 22026da6d0a9SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 22036da6d0a9SPyun YongHyeon cflags |= TD_IPCSUM; 22046da6d0a9SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 22056da6d0a9SPyun YongHyeon cflags |= TD_TCPCSUM; 22066da6d0a9SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 22076da6d0a9SPyun YongHyeon cflags |= TD_UDPCSUM; 22086da6d0a9SPyun YongHyeon /* Set TCP/UDP header offset. */ 22096da6d0a9SPyun YongHyeon cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 22106da6d0a9SPyun YongHyeon TD_L4HDR_OFFSET_MASK; 22116da6d0a9SPyun YongHyeon #endif 2212d68875ebSPyun YongHyeon } 2213d68875ebSPyun YongHyeon for (; idx < nsegs; idx++) { 2214d68875ebSPyun YongHyeon desc = &sc->alc_rdata.alc_tx_ring[prod]; 2215d68875ebSPyun YongHyeon desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2216d68875ebSPyun YongHyeon desc->flags = htole32(cflags); 2217d68875ebSPyun YongHyeon desc->addr = htole64(txsegs[idx].ds_addr); 2218d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cnt++; 2219d68875ebSPyun YongHyeon ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2220d68875ebSPyun YongHyeon } 2221d68875ebSPyun YongHyeon /* Update producer index. */ 2222d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_prod = prod; 2223d68875ebSPyun YongHyeon 2224d68875ebSPyun YongHyeon /* Finally set EOP on the last descriptor. */ 2225d68875ebSPyun YongHyeon prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2226d68875ebSPyun YongHyeon desc = &sc->alc_rdata.alc_tx_ring[prod]; 2227d68875ebSPyun YongHyeon desc->flags |= htole32(TD_EOP); 2228d68875ebSPyun YongHyeon 2229d68875ebSPyun YongHyeon /* Swap dmamap of the first and the last. */ 2230d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[prod]; 2231d68875ebSPyun YongHyeon map = txd_last->tx_dmamap; 2232d68875ebSPyun YongHyeon txd_last->tx_dmamap = txd->tx_dmamap; 2233d68875ebSPyun YongHyeon txd->tx_dmamap = map; 2234d68875ebSPyun YongHyeon txd->tx_m = m; 2235d68875ebSPyun YongHyeon 2236d68875ebSPyun YongHyeon return (0); 2237d68875ebSPyun YongHyeon } 2238d68875ebSPyun YongHyeon 2239d68875ebSPyun YongHyeon static void 2240d68875ebSPyun YongHyeon alc_tx_task(void *arg, int pending) 2241d68875ebSPyun YongHyeon { 2242d68875ebSPyun YongHyeon struct ifnet *ifp; 2243d68875ebSPyun YongHyeon 2244d68875ebSPyun YongHyeon ifp = (struct ifnet *)arg; 2245d68875ebSPyun YongHyeon alc_start(ifp); 2246d68875ebSPyun YongHyeon } 2247d68875ebSPyun YongHyeon 2248d68875ebSPyun YongHyeon static void 2249d68875ebSPyun YongHyeon alc_start(struct ifnet *ifp) 2250d68875ebSPyun YongHyeon { 2251d68875ebSPyun YongHyeon struct alc_softc *sc; 2252d68875ebSPyun YongHyeon struct mbuf *m_head; 2253d68875ebSPyun YongHyeon int enq; 2254d68875ebSPyun YongHyeon 2255d68875ebSPyun YongHyeon sc = ifp->if_softc; 2256d68875ebSPyun YongHyeon 2257d68875ebSPyun YongHyeon ALC_LOCK(sc); 2258d68875ebSPyun YongHyeon 2259d68875ebSPyun YongHyeon /* Reclaim transmitted frames. */ 2260d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2261d68875ebSPyun YongHyeon alc_txeof(sc); 2262d68875ebSPyun YongHyeon 2263d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2264d68875ebSPyun YongHyeon IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2265d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2266d68875ebSPyun YongHyeon return; 2267d68875ebSPyun YongHyeon } 2268d68875ebSPyun YongHyeon 2269d68875ebSPyun YongHyeon for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2270d68875ebSPyun YongHyeon IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2271d68875ebSPyun YongHyeon if (m_head == NULL) 2272d68875ebSPyun YongHyeon break; 2273d68875ebSPyun YongHyeon /* 2274d68875ebSPyun YongHyeon * Pack the data into the transmit ring. If we 2275d68875ebSPyun YongHyeon * don't have room, set the OACTIVE flag and wait 2276d68875ebSPyun YongHyeon * for the NIC to drain the ring. 2277d68875ebSPyun YongHyeon */ 2278d68875ebSPyun YongHyeon if (alc_encap(sc, &m_head)) { 2279d68875ebSPyun YongHyeon if (m_head == NULL) 2280d68875ebSPyun YongHyeon break; 2281d68875ebSPyun YongHyeon IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2282d68875ebSPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2283d68875ebSPyun YongHyeon break; 2284d68875ebSPyun YongHyeon } 2285d68875ebSPyun YongHyeon 2286d68875ebSPyun YongHyeon enq++; 2287d68875ebSPyun YongHyeon /* 2288d68875ebSPyun YongHyeon * If there's a BPF listener, bounce a copy of this frame 2289d68875ebSPyun YongHyeon * to him. 2290d68875ebSPyun YongHyeon */ 2291d68875ebSPyun YongHyeon ETHER_BPF_MTAP(ifp, m_head); 2292d68875ebSPyun YongHyeon } 2293d68875ebSPyun YongHyeon 2294d68875ebSPyun YongHyeon if (enq > 0) { 2295d68875ebSPyun YongHyeon /* Sync descriptors. */ 2296d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2297d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2298d68875ebSPyun YongHyeon /* Kick. Assume we're using normal Tx priority queue. */ 2299d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2300d68875ebSPyun YongHyeon (sc->alc_cdata.alc_tx_prod << 2301d68875ebSPyun YongHyeon MBOX_TD_PROD_LO_IDX_SHIFT) & 2302d68875ebSPyun YongHyeon MBOX_TD_PROD_LO_IDX_MASK); 2303d68875ebSPyun YongHyeon /* Set a timeout in case the chip goes out to lunch. */ 2304d68875ebSPyun YongHyeon sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2305d68875ebSPyun YongHyeon } 2306d68875ebSPyun YongHyeon 2307d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2308d68875ebSPyun YongHyeon } 2309d68875ebSPyun YongHyeon 2310d68875ebSPyun YongHyeon static void 2311d68875ebSPyun YongHyeon alc_watchdog(struct alc_softc *sc) 2312d68875ebSPyun YongHyeon { 2313d68875ebSPyun YongHyeon struct ifnet *ifp; 2314d68875ebSPyun YongHyeon 2315d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 2316d68875ebSPyun YongHyeon 2317d68875ebSPyun YongHyeon if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2318d68875ebSPyun YongHyeon return; 2319d68875ebSPyun YongHyeon 2320d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2321d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2322d68875ebSPyun YongHyeon if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2323d68875ebSPyun YongHyeon ifp->if_oerrors++; 2324d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2325d68875ebSPyun YongHyeon alc_init_locked(sc); 2326d68875ebSPyun YongHyeon return; 2327d68875ebSPyun YongHyeon } 2328d68875ebSPyun YongHyeon if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2329d68875ebSPyun YongHyeon ifp->if_oerrors++; 2330d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2331d68875ebSPyun YongHyeon alc_init_locked(sc); 2332d68875ebSPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2333d68875ebSPyun YongHyeon taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2334d68875ebSPyun YongHyeon } 2335d68875ebSPyun YongHyeon 2336d68875ebSPyun YongHyeon static int 2337d68875ebSPyun YongHyeon alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2338d68875ebSPyun YongHyeon { 2339d68875ebSPyun YongHyeon struct alc_softc *sc; 2340d68875ebSPyun YongHyeon struct ifreq *ifr; 2341d68875ebSPyun YongHyeon struct mii_data *mii; 2342d68875ebSPyun YongHyeon int error, mask; 2343d68875ebSPyun YongHyeon 2344d68875ebSPyun YongHyeon sc = ifp->if_softc; 2345d68875ebSPyun YongHyeon ifr = (struct ifreq *)data; 2346d68875ebSPyun YongHyeon error = 0; 2347d68875ebSPyun YongHyeon switch (cmd) { 2348d68875ebSPyun YongHyeon case SIOCSIFMTU: 23492f70cceaSPyun YongHyeon if (ifr->ifr_mtu < ETHERMIN || 23502f70cceaSPyun YongHyeon ifr->ifr_mtu > (sc->alc_ident->max_framelen - 23512f70cceaSPyun YongHyeon sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2352d68875ebSPyun YongHyeon ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2353d68875ebSPyun YongHyeon ifr->ifr_mtu > ETHERMTU)) 2354d68875ebSPyun YongHyeon error = EINVAL; 2355d68875ebSPyun YongHyeon else if (ifp->if_mtu != ifr->ifr_mtu) { 2356d68875ebSPyun YongHyeon ALC_LOCK(sc); 2357d68875ebSPyun YongHyeon ifp->if_mtu = ifr->ifr_mtu; 23582f70cceaSPyun YongHyeon /* AR813x/AR815x has 13 bits MSS field. */ 2359d68875ebSPyun YongHyeon if (ifp->if_mtu > ALC_TSO_MTU && 2360d68875ebSPyun YongHyeon (ifp->if_capenable & IFCAP_TSO4) != 0) { 2361d68875ebSPyun YongHyeon ifp->if_capenable &= ~IFCAP_TSO4; 2362d68875ebSPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 2363e67344a3SPyun YongHyeon VLAN_CAPABILITIES(ifp); 2364d68875ebSPyun YongHyeon } 2365d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2366d68875ebSPyun YongHyeon } 2367d68875ebSPyun YongHyeon break; 2368d68875ebSPyun YongHyeon case SIOCSIFFLAGS: 2369d68875ebSPyun YongHyeon ALC_LOCK(sc); 2370d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 2371d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2372d68875ebSPyun YongHyeon ((ifp->if_flags ^ sc->alc_if_flags) & 2373d68875ebSPyun YongHyeon (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2374d68875ebSPyun YongHyeon alc_rxfilter(sc); 2375d68875ebSPyun YongHyeon else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2376d68875ebSPyun YongHyeon alc_init_locked(sc); 2377d68875ebSPyun YongHyeon } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2378d68875ebSPyun YongHyeon alc_stop(sc); 2379d68875ebSPyun YongHyeon sc->alc_if_flags = ifp->if_flags; 2380d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2381d68875ebSPyun YongHyeon break; 2382d68875ebSPyun YongHyeon case SIOCADDMULTI: 2383d68875ebSPyun YongHyeon case SIOCDELMULTI: 2384d68875ebSPyun YongHyeon ALC_LOCK(sc); 2385d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2386d68875ebSPyun YongHyeon alc_rxfilter(sc); 2387d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2388d68875ebSPyun YongHyeon break; 2389d68875ebSPyun YongHyeon case SIOCSIFMEDIA: 2390d68875ebSPyun YongHyeon case SIOCGIFMEDIA: 2391d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 2392d68875ebSPyun YongHyeon error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2393d68875ebSPyun YongHyeon break; 2394d68875ebSPyun YongHyeon case SIOCSIFCAP: 2395d68875ebSPyun YongHyeon ALC_LOCK(sc); 2396d68875ebSPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2397d68875ebSPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 2398d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2399d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 2400d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2401d68875ebSPyun YongHyeon ifp->if_hwassist |= ALC_CSUM_FEATURES; 2402d68875ebSPyun YongHyeon else 2403d68875ebSPyun YongHyeon ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2404d68875ebSPyun YongHyeon } 2405d68875ebSPyun YongHyeon if ((mask & IFCAP_TSO4) != 0 && 2406d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2407d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_TSO4; 2408d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 24092f70cceaSPyun YongHyeon /* AR813x/AR815x has 13 bits MSS field. */ 2410d68875ebSPyun YongHyeon if (ifp->if_mtu > ALC_TSO_MTU) { 2411d68875ebSPyun YongHyeon ifp->if_capenable &= ~IFCAP_TSO4; 2412d68875ebSPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 2413d68875ebSPyun YongHyeon } else 2414d68875ebSPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 2415d68875ebSPyun YongHyeon } else 2416d68875ebSPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 2417d68875ebSPyun YongHyeon } 2418d68875ebSPyun YongHyeon if ((mask & IFCAP_WOL_MCAST) != 0 && 2419d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2420d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_MCAST; 2421d68875ebSPyun YongHyeon if ((mask & IFCAP_WOL_MAGIC) != 0 && 2422d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2423d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2424d68875ebSPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2425d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2426d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2427d68875ebSPyun YongHyeon alc_rxvlan(sc); 2428d68875ebSPyun YongHyeon } 2429d68875ebSPyun YongHyeon if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2430d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2431d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2432d68875ebSPyun YongHyeon if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2433d68875ebSPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2434d68875ebSPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2435d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2436d68875ebSPyun YongHyeon ifp->if_capenable &= 2437d68875ebSPyun YongHyeon ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2438d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2439d68875ebSPyun YongHyeon VLAN_CAPABILITIES(ifp); 2440d68875ebSPyun YongHyeon break; 2441d68875ebSPyun YongHyeon default: 2442d68875ebSPyun YongHyeon error = ether_ioctl(ifp, cmd, data); 2443d68875ebSPyun YongHyeon break; 2444d68875ebSPyun YongHyeon } 2445d68875ebSPyun YongHyeon 2446d68875ebSPyun YongHyeon return (error); 2447d68875ebSPyun YongHyeon } 2448d68875ebSPyun YongHyeon 2449d68875ebSPyun YongHyeon static void 2450d68875ebSPyun YongHyeon alc_mac_config(struct alc_softc *sc) 2451d68875ebSPyun YongHyeon { 2452d68875ebSPyun YongHyeon struct mii_data *mii; 2453d68875ebSPyun YongHyeon uint32_t reg; 2454d68875ebSPyun YongHyeon 2455d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 2456d68875ebSPyun YongHyeon 2457d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 2458d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MAC_CFG); 2459d68875ebSPyun YongHyeon reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2460d68875ebSPyun YongHyeon MAC_CFG_SPEED_MASK); 24612f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 24622f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 24632f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 24642f70cceaSPyun YongHyeon reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2465d68875ebSPyun YongHyeon /* Reprogram MAC with resolved speed/duplex. */ 2466d68875ebSPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 2467d68875ebSPyun YongHyeon case IFM_10_T: 2468d68875ebSPyun YongHyeon case IFM_100_TX: 2469d68875ebSPyun YongHyeon reg |= MAC_CFG_SPEED_10_100; 2470d68875ebSPyun YongHyeon break; 2471d68875ebSPyun YongHyeon case IFM_1000_T: 2472d68875ebSPyun YongHyeon reg |= MAC_CFG_SPEED_1000; 2473d68875ebSPyun YongHyeon break; 2474d68875ebSPyun YongHyeon } 2475d68875ebSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2476d68875ebSPyun YongHyeon reg |= MAC_CFG_FULL_DUPLEX; 2477d68875ebSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2478d68875ebSPyun YongHyeon reg |= MAC_CFG_TX_FC; 2479d68875ebSPyun YongHyeon if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2480d68875ebSPyun YongHyeon reg |= MAC_CFG_RX_FC; 2481d68875ebSPyun YongHyeon } 2482d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2483d68875ebSPyun YongHyeon } 2484d68875ebSPyun YongHyeon 2485d68875ebSPyun YongHyeon static void 2486d68875ebSPyun YongHyeon alc_stats_clear(struct alc_softc *sc) 2487d68875ebSPyun YongHyeon { 2488d68875ebSPyun YongHyeon struct smb sb, *smb; 2489d68875ebSPyun YongHyeon uint32_t *reg; 2490d68875ebSPyun YongHyeon int i; 2491d68875ebSPyun YongHyeon 2492d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2493d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2494d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map, 2495d68875ebSPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2496d68875ebSPyun YongHyeon smb = sc->alc_rdata.alc_smb; 2497d68875ebSPyun YongHyeon /* Update done, clear. */ 2498d68875ebSPyun YongHyeon smb->updated = 0; 2499d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2500d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map, 2501d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2502d68875ebSPyun YongHyeon } else { 2503d68875ebSPyun YongHyeon for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2504d68875ebSPyun YongHyeon reg++) { 2505d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2506d68875ebSPyun YongHyeon i += sizeof(uint32_t); 2507d68875ebSPyun YongHyeon } 2508d68875ebSPyun YongHyeon /* Read Tx statistics. */ 2509d68875ebSPyun YongHyeon for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2510d68875ebSPyun YongHyeon reg++) { 2511d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2512d68875ebSPyun YongHyeon i += sizeof(uint32_t); 2513d68875ebSPyun YongHyeon } 2514d68875ebSPyun YongHyeon } 2515d68875ebSPyun YongHyeon } 2516d68875ebSPyun YongHyeon 2517d68875ebSPyun YongHyeon static void 2518d68875ebSPyun YongHyeon alc_stats_update(struct alc_softc *sc) 2519d68875ebSPyun YongHyeon { 2520d68875ebSPyun YongHyeon struct alc_hw_stats *stat; 2521d68875ebSPyun YongHyeon struct smb sb, *smb; 2522d68875ebSPyun YongHyeon struct ifnet *ifp; 2523d68875ebSPyun YongHyeon uint32_t *reg; 2524d68875ebSPyun YongHyeon int i; 2525d68875ebSPyun YongHyeon 2526d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 2527d68875ebSPyun YongHyeon 2528d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2529d68875ebSPyun YongHyeon stat = &sc->alc_stats; 2530d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2531d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2532d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map, 2533d68875ebSPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2534d68875ebSPyun YongHyeon smb = sc->alc_rdata.alc_smb; 2535d68875ebSPyun YongHyeon if (smb->updated == 0) 2536d68875ebSPyun YongHyeon return; 2537d68875ebSPyun YongHyeon } else { 2538d68875ebSPyun YongHyeon smb = &sb; 2539d68875ebSPyun YongHyeon /* Read Rx statistics. */ 2540d68875ebSPyun YongHyeon for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2541d68875ebSPyun YongHyeon reg++) { 2542d68875ebSPyun YongHyeon *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2543d68875ebSPyun YongHyeon i += sizeof(uint32_t); 2544d68875ebSPyun YongHyeon } 2545d68875ebSPyun YongHyeon /* Read Tx statistics. */ 2546d68875ebSPyun YongHyeon for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2547d68875ebSPyun YongHyeon reg++) { 2548d68875ebSPyun YongHyeon *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2549d68875ebSPyun YongHyeon i += sizeof(uint32_t); 2550d68875ebSPyun YongHyeon } 2551d68875ebSPyun YongHyeon } 2552d68875ebSPyun YongHyeon 2553d68875ebSPyun YongHyeon /* Rx stats. */ 2554d68875ebSPyun YongHyeon stat->rx_frames += smb->rx_frames; 2555d68875ebSPyun YongHyeon stat->rx_bcast_frames += smb->rx_bcast_frames; 2556d68875ebSPyun YongHyeon stat->rx_mcast_frames += smb->rx_mcast_frames; 2557d68875ebSPyun YongHyeon stat->rx_pause_frames += smb->rx_pause_frames; 2558d68875ebSPyun YongHyeon stat->rx_control_frames += smb->rx_control_frames; 2559d68875ebSPyun YongHyeon stat->rx_crcerrs += smb->rx_crcerrs; 2560d68875ebSPyun YongHyeon stat->rx_lenerrs += smb->rx_lenerrs; 2561d68875ebSPyun YongHyeon stat->rx_bytes += smb->rx_bytes; 2562d68875ebSPyun YongHyeon stat->rx_runts += smb->rx_runts; 2563d68875ebSPyun YongHyeon stat->rx_fragments += smb->rx_fragments; 2564d68875ebSPyun YongHyeon stat->rx_pkts_64 += smb->rx_pkts_64; 2565d68875ebSPyun YongHyeon stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2566d68875ebSPyun YongHyeon stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2567d68875ebSPyun YongHyeon stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2568d68875ebSPyun YongHyeon stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2569d68875ebSPyun YongHyeon stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2570d68875ebSPyun YongHyeon stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2571d68875ebSPyun YongHyeon stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2572d68875ebSPyun YongHyeon stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2573d68875ebSPyun YongHyeon stat->rx_rrs_errs += smb->rx_rrs_errs; 2574d68875ebSPyun YongHyeon stat->rx_alignerrs += smb->rx_alignerrs; 2575d68875ebSPyun YongHyeon stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2576d68875ebSPyun YongHyeon stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2577d68875ebSPyun YongHyeon stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2578d68875ebSPyun YongHyeon 2579d68875ebSPyun YongHyeon /* Tx stats. */ 2580d68875ebSPyun YongHyeon stat->tx_frames += smb->tx_frames; 2581d68875ebSPyun YongHyeon stat->tx_bcast_frames += smb->tx_bcast_frames; 2582d68875ebSPyun YongHyeon stat->tx_mcast_frames += smb->tx_mcast_frames; 2583d68875ebSPyun YongHyeon stat->tx_pause_frames += smb->tx_pause_frames; 2584d68875ebSPyun YongHyeon stat->tx_excess_defer += smb->tx_excess_defer; 2585d68875ebSPyun YongHyeon stat->tx_control_frames += smb->tx_control_frames; 2586d68875ebSPyun YongHyeon stat->tx_deferred += smb->tx_deferred; 2587d68875ebSPyun YongHyeon stat->tx_bytes += smb->tx_bytes; 2588d68875ebSPyun YongHyeon stat->tx_pkts_64 += smb->tx_pkts_64; 2589d68875ebSPyun YongHyeon stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2590d68875ebSPyun YongHyeon stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2591d68875ebSPyun YongHyeon stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2592d68875ebSPyun YongHyeon stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2593d68875ebSPyun YongHyeon stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2594d68875ebSPyun YongHyeon stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2595d68875ebSPyun YongHyeon stat->tx_single_colls += smb->tx_single_colls; 2596d68875ebSPyun YongHyeon stat->tx_multi_colls += smb->tx_multi_colls; 2597d68875ebSPyun YongHyeon stat->tx_late_colls += smb->tx_late_colls; 2598d68875ebSPyun YongHyeon stat->tx_excess_colls += smb->tx_excess_colls; 2599d68875ebSPyun YongHyeon stat->tx_abort += smb->tx_abort; 2600d68875ebSPyun YongHyeon stat->tx_underrun += smb->tx_underrun; 2601d68875ebSPyun YongHyeon stat->tx_desc_underrun += smb->tx_desc_underrun; 2602d68875ebSPyun YongHyeon stat->tx_lenerrs += smb->tx_lenerrs; 2603d68875ebSPyun YongHyeon stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2604d68875ebSPyun YongHyeon stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2605d68875ebSPyun YongHyeon stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2606d68875ebSPyun YongHyeon 2607d68875ebSPyun YongHyeon /* Update counters in ifnet. */ 2608d68875ebSPyun YongHyeon ifp->if_opackets += smb->tx_frames; 2609d68875ebSPyun YongHyeon 2610d68875ebSPyun YongHyeon ifp->if_collisions += smb->tx_single_colls + 2611d68875ebSPyun YongHyeon smb->tx_multi_colls * 2 + smb->tx_late_colls + 2612d68875ebSPyun YongHyeon smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2613d68875ebSPyun YongHyeon 2614d68875ebSPyun YongHyeon /* 2615d68875ebSPyun YongHyeon * XXX 2616d68875ebSPyun YongHyeon * tx_pkts_truncated counter looks suspicious. It constantly 2617d68875ebSPyun YongHyeon * increments with no sign of Tx errors. This may indicate 2618d68875ebSPyun YongHyeon * the counter name is not correct one so I've removed the 2619d68875ebSPyun YongHyeon * counter in output errors. 2620d68875ebSPyun YongHyeon */ 2621d68875ebSPyun YongHyeon ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2622d68875ebSPyun YongHyeon smb->tx_underrun; 2623d68875ebSPyun YongHyeon 2624d68875ebSPyun YongHyeon ifp->if_ipackets += smb->rx_frames; 2625d68875ebSPyun YongHyeon 2626d68875ebSPyun YongHyeon ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2627d68875ebSPyun YongHyeon smb->rx_runts + smb->rx_pkts_truncated + 2628d68875ebSPyun YongHyeon smb->rx_fifo_oflows + smb->rx_rrs_errs + 2629d68875ebSPyun YongHyeon smb->rx_alignerrs; 2630d68875ebSPyun YongHyeon 2631d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2632d68875ebSPyun YongHyeon /* Update done, clear. */ 2633d68875ebSPyun YongHyeon smb->updated = 0; 2634d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2635d68875ebSPyun YongHyeon sc->alc_cdata.alc_smb_map, 2636d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2637d68875ebSPyun YongHyeon } 2638d68875ebSPyun YongHyeon } 2639d68875ebSPyun YongHyeon 2640d68875ebSPyun YongHyeon static int 2641d68875ebSPyun YongHyeon alc_intr(void *arg) 2642d68875ebSPyun YongHyeon { 2643d68875ebSPyun YongHyeon struct alc_softc *sc; 2644d68875ebSPyun YongHyeon uint32_t status; 2645d68875ebSPyun YongHyeon 2646d68875ebSPyun YongHyeon sc = (struct alc_softc *)arg; 2647d68875ebSPyun YongHyeon 2648d68875ebSPyun YongHyeon status = CSR_READ_4(sc, ALC_INTR_STATUS); 2649d68875ebSPyun YongHyeon if ((status & ALC_INTRS) == 0) 2650d68875ebSPyun YongHyeon return (FILTER_STRAY); 2651d68875ebSPyun YongHyeon /* Disable interrupts. */ 2652d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2653d68875ebSPyun YongHyeon taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2654d68875ebSPyun YongHyeon 2655d68875ebSPyun YongHyeon return (FILTER_HANDLED); 2656d68875ebSPyun YongHyeon } 2657d68875ebSPyun YongHyeon 2658d68875ebSPyun YongHyeon static void 2659d68875ebSPyun YongHyeon alc_int_task(void *arg, int pending) 2660d68875ebSPyun YongHyeon { 2661d68875ebSPyun YongHyeon struct alc_softc *sc; 2662d68875ebSPyun YongHyeon struct ifnet *ifp; 2663d68875ebSPyun YongHyeon uint32_t status; 2664d68875ebSPyun YongHyeon int more; 2665d68875ebSPyun YongHyeon 2666d68875ebSPyun YongHyeon sc = (struct alc_softc *)arg; 2667d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2668d68875ebSPyun YongHyeon 2669d68875ebSPyun YongHyeon status = CSR_READ_4(sc, ALC_INTR_STATUS); 2670*7e86a37eSPyun YongHyeon if (sc->alc_morework != 0) { 2671*7e86a37eSPyun YongHyeon sc->alc_morework = 0; 2672d68875ebSPyun YongHyeon status |= INTR_RX_PKT; 2673*7e86a37eSPyun YongHyeon } 2674d68875ebSPyun YongHyeon if ((status & ALC_INTRS) == 0) 2675d68875ebSPyun YongHyeon goto done; 2676d68875ebSPyun YongHyeon 2677d68875ebSPyun YongHyeon /* Acknowledge interrupts but still disable interrupts. */ 2678d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2679d68875ebSPyun YongHyeon 2680d68875ebSPyun YongHyeon more = 0; 2681d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2682d68875ebSPyun YongHyeon if ((status & INTR_RX_PKT) != 0) { 2683d68875ebSPyun YongHyeon more = alc_rxintr(sc, sc->alc_process_limit); 2684d68875ebSPyun YongHyeon if (more == EAGAIN) 2685*7e86a37eSPyun YongHyeon sc->alc_morework = 1; 2686d68875ebSPyun YongHyeon else if (more == EIO) { 2687d68875ebSPyun YongHyeon ALC_LOCK(sc); 2688d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2689d68875ebSPyun YongHyeon alc_init_locked(sc); 2690d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2691d68875ebSPyun YongHyeon return; 2692d68875ebSPyun YongHyeon } 2693d68875ebSPyun YongHyeon } 2694d68875ebSPyun YongHyeon if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2695d68875ebSPyun YongHyeon INTR_TXQ_TO_RST)) != 0) { 2696d68875ebSPyun YongHyeon if ((status & INTR_DMA_RD_TO_RST) != 0) 2697d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 2698d68875ebSPyun YongHyeon "DMA read error! -- resetting\n"); 2699d68875ebSPyun YongHyeon if ((status & INTR_DMA_WR_TO_RST) != 0) 2700d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 2701d68875ebSPyun YongHyeon "DMA write error! -- resetting\n"); 2702d68875ebSPyun YongHyeon if ((status & INTR_TXQ_TO_RST) != 0) 2703d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 2704d68875ebSPyun YongHyeon "TxQ reset! -- resetting\n"); 2705d68875ebSPyun YongHyeon ALC_LOCK(sc); 2706d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2707d68875ebSPyun YongHyeon alc_init_locked(sc); 2708d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 2709d68875ebSPyun YongHyeon return; 2710d68875ebSPyun YongHyeon } 2711d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2712d68875ebSPyun YongHyeon !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2713d68875ebSPyun YongHyeon taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2714d68875ebSPyun YongHyeon } 2715d68875ebSPyun YongHyeon 2716d68875ebSPyun YongHyeon if (more == EAGAIN || 2717d68875ebSPyun YongHyeon (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2718d68875ebSPyun YongHyeon taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2719d68875ebSPyun YongHyeon return; 2720d68875ebSPyun YongHyeon } 2721d68875ebSPyun YongHyeon 2722d68875ebSPyun YongHyeon done: 2723d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2724d68875ebSPyun YongHyeon /* Re-enable interrupts if we're running. */ 2725d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2726d68875ebSPyun YongHyeon } 2727d68875ebSPyun YongHyeon } 2728d68875ebSPyun YongHyeon 2729d68875ebSPyun YongHyeon static void 2730d68875ebSPyun YongHyeon alc_txeof(struct alc_softc *sc) 2731d68875ebSPyun YongHyeon { 2732d68875ebSPyun YongHyeon struct ifnet *ifp; 2733d68875ebSPyun YongHyeon struct alc_txdesc *txd; 2734d68875ebSPyun YongHyeon uint32_t cons, prod; 2735d68875ebSPyun YongHyeon int prog; 2736d68875ebSPyun YongHyeon 2737d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 2738d68875ebSPyun YongHyeon 2739d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2740d68875ebSPyun YongHyeon 2741d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_cnt == 0) 2742d68875ebSPyun YongHyeon return; 2743d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2744d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2745d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2746d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2747d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2748d68875ebSPyun YongHyeon prod = sc->alc_rdata.alc_cmb->cons; 2749d68875ebSPyun YongHyeon } else 2750d68875ebSPyun YongHyeon prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2751d68875ebSPyun YongHyeon /* Assume we're using normal Tx priority queue. */ 2752d68875ebSPyun YongHyeon prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2753d68875ebSPyun YongHyeon MBOX_TD_CONS_LO_IDX_SHIFT; 2754d68875ebSPyun YongHyeon cons = sc->alc_cdata.alc_tx_cons; 2755d68875ebSPyun YongHyeon /* 2756d68875ebSPyun YongHyeon * Go through our Tx list and free mbufs for those 2757d68875ebSPyun YongHyeon * frames which have been transmitted. 2758d68875ebSPyun YongHyeon */ 2759d68875ebSPyun YongHyeon for (prog = 0; cons != prod; prog++, 2760d68875ebSPyun YongHyeon ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2761d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_cnt <= 0) 2762d68875ebSPyun YongHyeon break; 2763d68875ebSPyun YongHyeon prog++; 2764d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2765d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cnt--; 2766d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[cons]; 2767d68875ebSPyun YongHyeon if (txd->tx_m != NULL) { 2768d68875ebSPyun YongHyeon /* Reclaim transmitted mbufs. */ 2769d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2770d68875ebSPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2771d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2772d68875ebSPyun YongHyeon txd->tx_dmamap); 2773d68875ebSPyun YongHyeon m_freem(txd->tx_m); 2774d68875ebSPyun YongHyeon txd->tx_m = NULL; 2775d68875ebSPyun YongHyeon } 2776d68875ebSPyun YongHyeon } 2777d68875ebSPyun YongHyeon 2778d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2779d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2780d68875ebSPyun YongHyeon sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2781d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cons = cons; 2782d68875ebSPyun YongHyeon /* 2783d68875ebSPyun YongHyeon * Unarm watchdog timer only when there is no pending 2784d68875ebSPyun YongHyeon * frames in Tx queue. 2785d68875ebSPyun YongHyeon */ 2786d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_tx_cnt == 0) 2787d68875ebSPyun YongHyeon sc->alc_watchdog_timer = 0; 2788d68875ebSPyun YongHyeon } 2789d68875ebSPyun YongHyeon 2790d68875ebSPyun YongHyeon static int 2791d68875ebSPyun YongHyeon alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2792d68875ebSPyun YongHyeon { 2793d68875ebSPyun YongHyeon struct mbuf *m; 2794d68875ebSPyun YongHyeon bus_dma_segment_t segs[1]; 2795d68875ebSPyun YongHyeon bus_dmamap_t map; 2796d68875ebSPyun YongHyeon int nsegs; 2797d68875ebSPyun YongHyeon 2798d68875ebSPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2799d68875ebSPyun YongHyeon if (m == NULL) 2800d68875ebSPyun YongHyeon return (ENOBUFS); 2801d68875ebSPyun YongHyeon m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2802d68875ebSPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 2803d68875ebSPyun YongHyeon m_adj(m, sizeof(uint64_t)); 2804d68875ebSPyun YongHyeon #endif 2805d68875ebSPyun YongHyeon 2806d68875ebSPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2807d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2808d68875ebSPyun YongHyeon m_freem(m); 2809d68875ebSPyun YongHyeon return (ENOBUFS); 2810d68875ebSPyun YongHyeon } 2811d68875ebSPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2812d68875ebSPyun YongHyeon 2813d68875ebSPyun YongHyeon if (rxd->rx_m != NULL) { 2814d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2815d68875ebSPyun YongHyeon BUS_DMASYNC_POSTREAD); 2816d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2817d68875ebSPyun YongHyeon } 2818d68875ebSPyun YongHyeon map = rxd->rx_dmamap; 2819d68875ebSPyun YongHyeon rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2820d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_sparemap = map; 2821d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2822d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD); 2823d68875ebSPyun YongHyeon rxd->rx_m = m; 2824d68875ebSPyun YongHyeon rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2825d68875ebSPyun YongHyeon return (0); 2826d68875ebSPyun YongHyeon } 2827d68875ebSPyun YongHyeon 2828d68875ebSPyun YongHyeon static int 2829d68875ebSPyun YongHyeon alc_rxintr(struct alc_softc *sc, int count) 2830d68875ebSPyun YongHyeon { 2831d68875ebSPyun YongHyeon struct ifnet *ifp; 2832d68875ebSPyun YongHyeon struct rx_rdesc *rrd; 2833d68875ebSPyun YongHyeon uint32_t nsegs, status; 2834d68875ebSPyun YongHyeon int rr_cons, prog; 2835d68875ebSPyun YongHyeon 2836d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2837d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map, 2838d68875ebSPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2839d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2840d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2841d68875ebSPyun YongHyeon rr_cons = sc->alc_cdata.alc_rr_cons; 2842d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2843d68875ebSPyun YongHyeon for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2844d68875ebSPyun YongHyeon if (count-- <= 0) 2845d68875ebSPyun YongHyeon break; 2846d68875ebSPyun YongHyeon rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2847d68875ebSPyun YongHyeon status = le32toh(rrd->status); 2848d68875ebSPyun YongHyeon if ((status & RRD_VALID) == 0) 2849d68875ebSPyun YongHyeon break; 2850d68875ebSPyun YongHyeon nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2851d68875ebSPyun YongHyeon if (nsegs == 0) { 2852d68875ebSPyun YongHyeon /* This should not happen! */ 2853d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 2854d68875ebSPyun YongHyeon "unexpected segment count -- resetting\n"); 2855d68875ebSPyun YongHyeon return (EIO); 2856d68875ebSPyun YongHyeon } 2857d68875ebSPyun YongHyeon alc_rxeof(sc, rrd); 2858d68875ebSPyun YongHyeon /* Clear Rx return status. */ 2859d68875ebSPyun YongHyeon rrd->status = 0; 2860d68875ebSPyun YongHyeon ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2861d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_cons += nsegs; 2862d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2863d68875ebSPyun YongHyeon prog += nsegs; 2864d68875ebSPyun YongHyeon } 2865d68875ebSPyun YongHyeon 2866d68875ebSPyun YongHyeon if (prog > 0) { 2867d68875ebSPyun YongHyeon /* Update the consumer index. */ 2868d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_cons = rr_cons; 2869d68875ebSPyun YongHyeon /* Sync Rx return descriptors. */ 2870d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2871d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map, 2872d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2873d68875ebSPyun YongHyeon /* 2874d68875ebSPyun YongHyeon * Sync updated Rx descriptors such that controller see 2875d68875ebSPyun YongHyeon * modified buffer addresses. 2876d68875ebSPyun YongHyeon */ 2877d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2878d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2879d68875ebSPyun YongHyeon /* 2880d68875ebSPyun YongHyeon * Let controller know availability of new Rx buffers. 2881d68875ebSPyun YongHyeon * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2882d68875ebSPyun YongHyeon * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2883d68875ebSPyun YongHyeon * only when Rx buffer pre-fetching is required. In 2884d68875ebSPyun YongHyeon * addition we already set ALC_RX_RD_FREE_THRESH to 2885d68875ebSPyun YongHyeon * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2886d68875ebSPyun YongHyeon * it still seems that pre-fetching needs more 2887d68875ebSPyun YongHyeon * experimentation. 2888d68875ebSPyun YongHyeon */ 2889d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2890d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_cons); 2891d68875ebSPyun YongHyeon } 2892d68875ebSPyun YongHyeon 2893d68875ebSPyun YongHyeon return (count > 0 ? 0 : EAGAIN); 2894d68875ebSPyun YongHyeon } 2895d68875ebSPyun YongHyeon 2896d68875ebSPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 2897d68875ebSPyun YongHyeon static struct mbuf * 2898d68875ebSPyun YongHyeon alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2899d68875ebSPyun YongHyeon { 2900d68875ebSPyun YongHyeon struct mbuf *n; 2901d68875ebSPyun YongHyeon int i; 2902d68875ebSPyun YongHyeon uint16_t *src, *dst; 2903d68875ebSPyun YongHyeon 2904d68875ebSPyun YongHyeon src = mtod(m, uint16_t *); 2905d68875ebSPyun YongHyeon dst = src - 3; 2906d68875ebSPyun YongHyeon 2907d68875ebSPyun YongHyeon if (m->m_next == NULL) { 2908d68875ebSPyun YongHyeon for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2909d68875ebSPyun YongHyeon *dst++ = *src++; 2910d68875ebSPyun YongHyeon m->m_data -= 6; 2911d68875ebSPyun YongHyeon return (m); 2912d68875ebSPyun YongHyeon } 2913d68875ebSPyun YongHyeon /* 2914d68875ebSPyun YongHyeon * Append a new mbuf to received mbuf chain and copy ethernet 2915d68875ebSPyun YongHyeon * header from the mbuf chain. This can save lots of CPU 2916d68875ebSPyun YongHyeon * cycles for jumbo frame. 2917d68875ebSPyun YongHyeon */ 2918d68875ebSPyun YongHyeon MGETHDR(n, M_DONTWAIT, MT_DATA); 2919d68875ebSPyun YongHyeon if (n == NULL) { 2920d68875ebSPyun YongHyeon ifp->if_iqdrops++; 2921d68875ebSPyun YongHyeon m_freem(m); 2922d68875ebSPyun YongHyeon return (NULL); 2923d68875ebSPyun YongHyeon } 2924d68875ebSPyun YongHyeon bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2925d68875ebSPyun YongHyeon m->m_data += ETHER_HDR_LEN; 2926d68875ebSPyun YongHyeon m->m_len -= ETHER_HDR_LEN; 2927d68875ebSPyun YongHyeon n->m_len = ETHER_HDR_LEN; 2928d68875ebSPyun YongHyeon M_MOVE_PKTHDR(n, m); 2929d68875ebSPyun YongHyeon n->m_next = m; 2930d68875ebSPyun YongHyeon return (n); 2931d68875ebSPyun YongHyeon } 2932d68875ebSPyun YongHyeon #endif 2933d68875ebSPyun YongHyeon 2934d68875ebSPyun YongHyeon /* Receive a frame. */ 2935d68875ebSPyun YongHyeon static void 2936d68875ebSPyun YongHyeon alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2937d68875ebSPyun YongHyeon { 2938d68875ebSPyun YongHyeon struct alc_rxdesc *rxd; 2939d68875ebSPyun YongHyeon struct ifnet *ifp; 2940d68875ebSPyun YongHyeon struct mbuf *mp, *m; 2941d68875ebSPyun YongHyeon uint32_t rdinfo, status, vtag; 2942d68875ebSPyun YongHyeon int count, nsegs, rx_cons; 2943d68875ebSPyun YongHyeon 2944d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 2945d68875ebSPyun YongHyeon status = le32toh(rrd->status); 2946d68875ebSPyun YongHyeon rdinfo = le32toh(rrd->rdinfo); 2947d68875ebSPyun YongHyeon rx_cons = RRD_RD_IDX(rdinfo); 2948d68875ebSPyun YongHyeon nsegs = RRD_RD_CNT(rdinfo); 2949d68875ebSPyun YongHyeon 2950d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2951d68875ebSPyun YongHyeon if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2952d68875ebSPyun YongHyeon /* 2953d68875ebSPyun YongHyeon * We want to pass the following frames to upper 2954d68875ebSPyun YongHyeon * layer regardless of error status of Rx return 2955d68875ebSPyun YongHyeon * ring. 2956d68875ebSPyun YongHyeon * 2957d68875ebSPyun YongHyeon * o IP/TCP/UDP checksum is bad. 2958d68875ebSPyun YongHyeon * o frame length and protocol specific length 2959d68875ebSPyun YongHyeon * does not match. 2960d68875ebSPyun YongHyeon * 2961d68875ebSPyun YongHyeon * Force network stack compute checksum for 2962d68875ebSPyun YongHyeon * errored frames. 2963d68875ebSPyun YongHyeon */ 2964d68875ebSPyun YongHyeon status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 29659ed03f02SXin LI if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 29669ed03f02SXin LI RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2967d68875ebSPyun YongHyeon return; 2968d68875ebSPyun YongHyeon } 2969d68875ebSPyun YongHyeon 2970d68875ebSPyun YongHyeon for (count = 0; count < nsegs; count++, 2971d68875ebSPyun YongHyeon ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2972d68875ebSPyun YongHyeon rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2973d68875ebSPyun YongHyeon mp = rxd->rx_m; 2974d68875ebSPyun YongHyeon /* Add a new receive buffer to the ring. */ 2975d68875ebSPyun YongHyeon if (alc_newbuf(sc, rxd) != 0) { 2976d68875ebSPyun YongHyeon ifp->if_iqdrops++; 2977d68875ebSPyun YongHyeon /* Reuse Rx buffers. */ 2978d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rxhead != NULL) 2979d68875ebSPyun YongHyeon m_freem(sc->alc_cdata.alc_rxhead); 2980d68875ebSPyun YongHyeon break; 2981d68875ebSPyun YongHyeon } 2982d68875ebSPyun YongHyeon 2983d68875ebSPyun YongHyeon /* 2984d68875ebSPyun YongHyeon * Assume we've received a full sized frame. 2985d68875ebSPyun YongHyeon * Actual size is fixed when we encounter the end of 2986d68875ebSPyun YongHyeon * multi-segmented frame. 2987d68875ebSPyun YongHyeon */ 2988d68875ebSPyun YongHyeon mp->m_len = sc->alc_buf_size; 2989d68875ebSPyun YongHyeon 2990d68875ebSPyun YongHyeon /* Chain received mbufs. */ 2991d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rxhead == NULL) { 2992d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxhead = mp; 2993d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail = mp; 2994d68875ebSPyun YongHyeon } else { 2995d68875ebSPyun YongHyeon mp->m_flags &= ~M_PKTHDR; 2996d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxprev_tail = 2997d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail; 2998d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail->m_next = mp; 2999d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail = mp; 3000d68875ebSPyun YongHyeon } 3001d68875ebSPyun YongHyeon 3002d68875ebSPyun YongHyeon if (count == nsegs - 1) { 3003d68875ebSPyun YongHyeon /* Last desc. for this frame. */ 3004d68875ebSPyun YongHyeon m = sc->alc_cdata.alc_rxhead; 3005d68875ebSPyun YongHyeon m->m_flags |= M_PKTHDR; 3006d68875ebSPyun YongHyeon /* 3007d68875ebSPyun YongHyeon * It seems that L1C/L2C controller has no way 3008d68875ebSPyun YongHyeon * to tell hardware to strip CRC bytes. 3009d68875ebSPyun YongHyeon */ 3010d68875ebSPyun YongHyeon m->m_pkthdr.len = 3011d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3012d68875ebSPyun YongHyeon if (nsegs > 1) { 3013d68875ebSPyun YongHyeon /* Set last mbuf size. */ 3014d68875ebSPyun YongHyeon mp->m_len = sc->alc_cdata.alc_rxlen - 3015d68875ebSPyun YongHyeon (nsegs - 1) * sc->alc_buf_size; 3016d68875ebSPyun YongHyeon /* Remove the CRC bytes in chained mbufs. */ 3017d68875ebSPyun YongHyeon if (mp->m_len <= ETHER_CRC_LEN) { 3018d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail = 3019d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxprev_tail; 3020d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail->m_len -= 3021d68875ebSPyun YongHyeon (ETHER_CRC_LEN - mp->m_len); 3022d68875ebSPyun YongHyeon sc->alc_cdata.alc_rxtail->m_next = NULL; 3023d68875ebSPyun YongHyeon m_freem(mp); 3024d68875ebSPyun YongHyeon } else { 3025d68875ebSPyun YongHyeon mp->m_len -= ETHER_CRC_LEN; 3026d68875ebSPyun YongHyeon } 3027d68875ebSPyun YongHyeon } else 3028d68875ebSPyun YongHyeon m->m_len = m->m_pkthdr.len; 3029d68875ebSPyun YongHyeon m->m_pkthdr.rcvif = ifp; 3030d68875ebSPyun YongHyeon /* 3031d68875ebSPyun YongHyeon * Due to hardware bugs, Rx checksum offloading 3032d68875ebSPyun YongHyeon * was intentionally disabled. 3033d68875ebSPyun YongHyeon */ 3034d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3035d68875ebSPyun YongHyeon (status & RRD_VLAN_TAG) != 0) { 3036d68875ebSPyun YongHyeon vtag = RRD_VLAN(le32toh(rrd->vtag)); 3037d68875ebSPyun YongHyeon m->m_pkthdr.ether_vtag = ntohs(vtag); 3038d68875ebSPyun YongHyeon m->m_flags |= M_VLANTAG; 3039d68875ebSPyun YongHyeon } 3040d68875ebSPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 3041d68875ebSPyun YongHyeon m = alc_fixup_rx(ifp, m); 3042d68875ebSPyun YongHyeon if (m != NULL) 3043d68875ebSPyun YongHyeon #endif 3044d68875ebSPyun YongHyeon { 3045d68875ebSPyun YongHyeon /* Pass it on. */ 3046d68875ebSPyun YongHyeon (*ifp->if_input)(ifp, m); 3047d68875ebSPyun YongHyeon } 3048d68875ebSPyun YongHyeon } 3049d68875ebSPyun YongHyeon } 3050d68875ebSPyun YongHyeon /* Reset mbuf chains. */ 3051d68875ebSPyun YongHyeon ALC_RXCHAIN_RESET(sc); 3052d68875ebSPyun YongHyeon } 3053d68875ebSPyun YongHyeon 3054d68875ebSPyun YongHyeon static void 3055d68875ebSPyun YongHyeon alc_tick(void *arg) 3056d68875ebSPyun YongHyeon { 3057d68875ebSPyun YongHyeon struct alc_softc *sc; 3058d68875ebSPyun YongHyeon struct mii_data *mii; 3059d68875ebSPyun YongHyeon 3060d68875ebSPyun YongHyeon sc = (struct alc_softc *)arg; 3061d68875ebSPyun YongHyeon 3062d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3063d68875ebSPyun YongHyeon 3064d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 3065d68875ebSPyun YongHyeon mii_tick(mii); 3066d68875ebSPyun YongHyeon alc_stats_update(sc); 3067d68875ebSPyun YongHyeon /* 3068d68875ebSPyun YongHyeon * alc(4) does not rely on Tx completion interrupts to reclaim 3069d68875ebSPyun YongHyeon * transferred buffers. Instead Tx completion interrupts are 3070d68875ebSPyun YongHyeon * used to hint for scheduling Tx task. So it's necessary to 3071d68875ebSPyun YongHyeon * release transmitted buffers by kicking Tx completion 3072d68875ebSPyun YongHyeon * handler. This limits the maximum reclamation delay to a hz. 3073d68875ebSPyun YongHyeon */ 3074d68875ebSPyun YongHyeon alc_txeof(sc); 3075d68875ebSPyun YongHyeon alc_watchdog(sc); 3076d68875ebSPyun YongHyeon callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3077d68875ebSPyun YongHyeon } 3078d68875ebSPyun YongHyeon 3079d68875ebSPyun YongHyeon static void 3080d68875ebSPyun YongHyeon alc_reset(struct alc_softc *sc) 3081d68875ebSPyun YongHyeon { 3082d68875ebSPyun YongHyeon uint32_t reg; 3083d68875ebSPyun YongHyeon int i; 3084d68875ebSPyun YongHyeon 30852f70cceaSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 30862f70cceaSPyun YongHyeon reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 30872f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3088d68875ebSPyun YongHyeon for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3089d68875ebSPyun YongHyeon DELAY(10); 3090d68875ebSPyun YongHyeon if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3091d68875ebSPyun YongHyeon break; 3092d68875ebSPyun YongHyeon } 3093d68875ebSPyun YongHyeon if (i == 0) 3094d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "master reset timeout!\n"); 3095d68875ebSPyun YongHyeon 3096d68875ebSPyun YongHyeon for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3097d68875ebSPyun YongHyeon if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3098d68875ebSPyun YongHyeon break; 3099d68875ebSPyun YongHyeon DELAY(10); 3100d68875ebSPyun YongHyeon } 3101d68875ebSPyun YongHyeon 3102d68875ebSPyun YongHyeon if (i == 0) 3103d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3104d68875ebSPyun YongHyeon } 3105d68875ebSPyun YongHyeon 3106d68875ebSPyun YongHyeon static void 3107d68875ebSPyun YongHyeon alc_init(void *xsc) 3108d68875ebSPyun YongHyeon { 3109d68875ebSPyun YongHyeon struct alc_softc *sc; 3110d68875ebSPyun YongHyeon 3111d68875ebSPyun YongHyeon sc = (struct alc_softc *)xsc; 3112d68875ebSPyun YongHyeon ALC_LOCK(sc); 3113d68875ebSPyun YongHyeon alc_init_locked(sc); 3114d68875ebSPyun YongHyeon ALC_UNLOCK(sc); 3115d68875ebSPyun YongHyeon } 3116d68875ebSPyun YongHyeon 3117d68875ebSPyun YongHyeon static void 3118d68875ebSPyun YongHyeon alc_init_locked(struct alc_softc *sc) 3119d68875ebSPyun YongHyeon { 3120d68875ebSPyun YongHyeon struct ifnet *ifp; 3121d68875ebSPyun YongHyeon struct mii_data *mii; 3122d68875ebSPyun YongHyeon uint8_t eaddr[ETHER_ADDR_LEN]; 3123d68875ebSPyun YongHyeon bus_addr_t paddr; 3124d68875ebSPyun YongHyeon uint32_t reg, rxf_hi, rxf_lo; 3125d68875ebSPyun YongHyeon 3126d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3127d68875ebSPyun YongHyeon 3128d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 3129d68875ebSPyun YongHyeon mii = device_get_softc(sc->alc_miibus); 3130d68875ebSPyun YongHyeon 3131d68875ebSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3132d68875ebSPyun YongHyeon return; 3133d68875ebSPyun YongHyeon /* 3134d68875ebSPyun YongHyeon * Cancel any pending I/O. 3135d68875ebSPyun YongHyeon */ 3136d68875ebSPyun YongHyeon alc_stop(sc); 3137d68875ebSPyun YongHyeon /* 3138d68875ebSPyun YongHyeon * Reset the chip to a known state. 3139d68875ebSPyun YongHyeon */ 3140d68875ebSPyun YongHyeon alc_reset(sc); 3141d68875ebSPyun YongHyeon 3142d68875ebSPyun YongHyeon /* Initialize Rx descriptors. */ 3143d68875ebSPyun YongHyeon if (alc_init_rx_ring(sc) != 0) { 3144d68875ebSPyun YongHyeon device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3145d68875ebSPyun YongHyeon alc_stop(sc); 3146d68875ebSPyun YongHyeon return; 3147d68875ebSPyun YongHyeon } 3148d68875ebSPyun YongHyeon alc_init_rr_ring(sc); 3149d68875ebSPyun YongHyeon alc_init_tx_ring(sc); 3150d68875ebSPyun YongHyeon alc_init_cmb(sc); 3151d68875ebSPyun YongHyeon alc_init_smb(sc); 3152d68875ebSPyun YongHyeon 3153d68875ebSPyun YongHyeon /* Reprogram the station address. */ 3154d68875ebSPyun YongHyeon bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3155d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PAR0, 3156d68875ebSPyun YongHyeon eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3157d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3158d68875ebSPyun YongHyeon /* 3159d68875ebSPyun YongHyeon * Clear WOL status and disable all WOL feature as WOL 3160d68875ebSPyun YongHyeon * would interfere Rx operation under normal environments. 3161d68875ebSPyun YongHyeon */ 3162d68875ebSPyun YongHyeon CSR_READ_4(sc, ALC_WOL_CFG); 3163d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3164d68875ebSPyun YongHyeon /* Set Tx descriptor base addresses. */ 3165d68875ebSPyun YongHyeon paddr = sc->alc_rdata.alc_tx_ring_paddr; 3166d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3167d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3168d68875ebSPyun YongHyeon /* We don't use high priority ring. */ 3169d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3170d68875ebSPyun YongHyeon /* Set Tx descriptor counter. */ 3171d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3172d68875ebSPyun YongHyeon (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3173d68875ebSPyun YongHyeon /* Set Rx descriptor base addresses. */ 3174d68875ebSPyun YongHyeon paddr = sc->alc_rdata.alc_rx_ring_paddr; 3175d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3176d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3177d68875ebSPyun YongHyeon /* We use one Rx ring. */ 3178d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3179d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3180d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3181d68875ebSPyun YongHyeon /* Set Rx descriptor counter. */ 3182d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3183d68875ebSPyun YongHyeon (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3184d68875ebSPyun YongHyeon 3185d68875ebSPyun YongHyeon /* 3186d68875ebSPyun YongHyeon * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3187d68875ebSPyun YongHyeon * if it do not fit the buffer size. Rx return descriptor holds 3188d68875ebSPyun YongHyeon * a counter that indicates how many fragments were made by the 3189d68875ebSPyun YongHyeon * hardware. The buffer size should be multiple of 8 bytes. 3190d68875ebSPyun YongHyeon * Since hardware has limit on the size of buffer size, always 3191d68875ebSPyun YongHyeon * use the maximum value. 3192d68875ebSPyun YongHyeon * For strict-alignment architectures make sure to reduce buffer 3193d68875ebSPyun YongHyeon * size by 8 bytes to make room for alignment fixup. 3194d68875ebSPyun YongHyeon */ 3195d68875ebSPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 3196d68875ebSPyun YongHyeon sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3197d68875ebSPyun YongHyeon #else 3198d68875ebSPyun YongHyeon sc->alc_buf_size = RX_BUF_SIZE_MAX; 3199d68875ebSPyun YongHyeon #endif 3200d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3201d68875ebSPyun YongHyeon 3202d68875ebSPyun YongHyeon paddr = sc->alc_rdata.alc_rr_ring_paddr; 3203d68875ebSPyun YongHyeon /* Set Rx return descriptor base addresses. */ 3204d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3205d68875ebSPyun YongHyeon /* We use one Rx return ring. */ 3206d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3207d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3208d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3209d68875ebSPyun YongHyeon /* Set Rx return descriptor counter. */ 3210d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3211d68875ebSPyun YongHyeon (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3212d68875ebSPyun YongHyeon paddr = sc->alc_rdata.alc_cmb_paddr; 3213d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3214d68875ebSPyun YongHyeon paddr = sc->alc_rdata.alc_smb_paddr; 3215d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3216d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3217d68875ebSPyun YongHyeon 32182f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 32192f70cceaSPyun YongHyeon /* Reconfigure SRAM - Vendor magic. */ 32202f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 32212f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 32222f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 32232f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 32242f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 32252f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 32262f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 32272f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 32282f70cceaSPyun YongHyeon } 32292f70cceaSPyun YongHyeon 3230d68875ebSPyun YongHyeon /* Tell hardware that we're ready to load DMA blocks. */ 3231d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3232d68875ebSPyun YongHyeon 3233d68875ebSPyun YongHyeon /* Configure interrupt moderation timer. */ 3234d68875ebSPyun YongHyeon reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3235d68875ebSPyun YongHyeon reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3236d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3237d68875ebSPyun YongHyeon /* 3238d68875ebSPyun YongHyeon * We don't want to automatic interrupt clear as task queue 3239d68875ebSPyun YongHyeon * for the interrupt should know interrupt status. 3240d68875ebSPyun YongHyeon */ 32412f70cceaSPyun YongHyeon reg = MASTER_SA_TIMER_ENB; 3242d68875ebSPyun YongHyeon if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3243d68875ebSPyun YongHyeon reg |= MASTER_IM_RX_TIMER_ENB; 3244d68875ebSPyun YongHyeon if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3245d68875ebSPyun YongHyeon reg |= MASTER_IM_TX_TIMER_ENB; 3246d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3247d68875ebSPyun YongHyeon /* 3248d68875ebSPyun YongHyeon * Disable interrupt re-trigger timer. We don't want automatic 3249d68875ebSPyun YongHyeon * re-triggering of un-ACKed interrupts. 3250d68875ebSPyun YongHyeon */ 3251d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3252d68875ebSPyun YongHyeon /* Configure CMB. */ 3253a0bca955SPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3254d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3255d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3256a0bca955SPyun YongHyeon } else 3257d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3258d68875ebSPyun YongHyeon /* 3259d68875ebSPyun YongHyeon * Hardware can be configured to issue SMB interrupt based 3260d68875ebSPyun YongHyeon * on programmed interval. Since there is a callout that is 3261d68875ebSPyun YongHyeon * invoked for every hz in driver we use that instead of 3262d68875ebSPyun YongHyeon * relying on periodic SMB interrupt. 3263d68875ebSPyun YongHyeon */ 3264d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3265d68875ebSPyun YongHyeon /* Clear MAC statistics. */ 3266d68875ebSPyun YongHyeon alc_stats_clear(sc); 3267d68875ebSPyun YongHyeon 3268d68875ebSPyun YongHyeon /* 3269d68875ebSPyun YongHyeon * Always use maximum frame size that controller can support. 3270d68875ebSPyun YongHyeon * Otherwise received frames that has larger frame length 3271d68875ebSPyun YongHyeon * than alc(4) MTU would be silently dropped in hardware. This 3272d68875ebSPyun YongHyeon * would make path-MTU discovery hard as sender wouldn't get 3273d68875ebSPyun YongHyeon * any responses from receiver. alc(4) supports 3274d68875ebSPyun YongHyeon * multi-fragmented frames on Rx path so it has no issue on 3275d68875ebSPyun YongHyeon * assembling fragmented frames. Using maximum frame size also 3276d68875ebSPyun YongHyeon * removes the need to reinitialize hardware when interface 3277d68875ebSPyun YongHyeon * MTU configuration was changed. 3278d68875ebSPyun YongHyeon * 3279d68875ebSPyun YongHyeon * Be conservative in what you do, be liberal in what you 3280d68875ebSPyun YongHyeon * accept from others - RFC 793. 3281d68875ebSPyun YongHyeon */ 32822f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3283d68875ebSPyun YongHyeon 3284d68875ebSPyun YongHyeon /* Disable header split(?) */ 3285d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3286d68875ebSPyun YongHyeon 3287d68875ebSPyun YongHyeon /* Configure IPG/IFG parameters. */ 3288d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3289d68875ebSPyun YongHyeon ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3290d68875ebSPyun YongHyeon ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3291d68875ebSPyun YongHyeon ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3292d68875ebSPyun YongHyeon ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3293d68875ebSPyun YongHyeon /* Set parameters for half-duplex media. */ 3294d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_HDPX_CFG, 3295d68875ebSPyun YongHyeon ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3296d68875ebSPyun YongHyeon HDPX_CFG_LCOL_MASK) | 3297d68875ebSPyun YongHyeon ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3298d68875ebSPyun YongHyeon HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3299d68875ebSPyun YongHyeon ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3300d68875ebSPyun YongHyeon HDPX_CFG_ABEBT_MASK) | 3301d68875ebSPyun YongHyeon ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3302d68875ebSPyun YongHyeon HDPX_CFG_JAMIPG_MASK)); 3303d68875ebSPyun YongHyeon /* 3304d68875ebSPyun YongHyeon * Set TSO/checksum offload threshold. For frames that is 3305d68875ebSPyun YongHyeon * larger than this threshold, hardware wouldn't do 3306d68875ebSPyun YongHyeon * TSO/checksum offloading. 3307d68875ebSPyun YongHyeon */ 3308d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 33092f70cceaSPyun YongHyeon (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3310d68875ebSPyun YongHyeon TSO_OFFLOAD_THRESH_MASK); 3311d68875ebSPyun YongHyeon /* Configure TxQ. */ 3312d68875ebSPyun YongHyeon reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3313d68875ebSPyun YongHyeon TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 33142f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 33152f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 33162f70cceaSPyun YongHyeon reg >>= 1; 3317d68875ebSPyun YongHyeon reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3318d68875ebSPyun YongHyeon TXQ_CFG_TD_BURST_MASK; 3319d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3320d68875ebSPyun YongHyeon 3321d68875ebSPyun YongHyeon /* Configure Rx free descriptor pre-fetching. */ 3322d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3323d68875ebSPyun YongHyeon ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3324d68875ebSPyun YongHyeon RX_RD_FREE_THRESH_HI_MASK) | 3325d68875ebSPyun YongHyeon ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3326d68875ebSPyun YongHyeon RX_RD_FREE_THRESH_LO_MASK)); 3327d68875ebSPyun YongHyeon 3328d68875ebSPyun YongHyeon /* 3329d68875ebSPyun YongHyeon * Configure flow control parameters. 3330d68875ebSPyun YongHyeon * XON : 80% of Rx FIFO 3331d68875ebSPyun YongHyeon * XOFF : 30% of Rx FIFO 3332d68875ebSPyun YongHyeon */ 33332f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 33342f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3335d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3336d68875ebSPyun YongHyeon rxf_hi = (reg * 8) / 10; 3337d68875ebSPyun YongHyeon rxf_lo = (reg * 3) / 10; 3338d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3339d68875ebSPyun YongHyeon ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3340d68875ebSPyun YongHyeon RX_FIFO_PAUSE_THRESH_LO_MASK) | 3341d68875ebSPyun YongHyeon ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3342d68875ebSPyun YongHyeon RX_FIFO_PAUSE_THRESH_HI_MASK)); 33432f70cceaSPyun YongHyeon } 33442f70cceaSPyun YongHyeon 33452f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 33462f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 33472f70cceaSPyun YongHyeon CSR_WRITE_4(sc, ALC_SERDES_LOCK, 33482f70cceaSPyun YongHyeon CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 33492f70cceaSPyun YongHyeon SERDES_PHY_CLK_SLOWDOWN); 3350d68875ebSPyun YongHyeon 3351d68875ebSPyun YongHyeon /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3352d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3353d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3354d68875ebSPyun YongHyeon 3355d68875ebSPyun YongHyeon /* Configure RxQ. */ 3356d68875ebSPyun YongHyeon reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3357d68875ebSPyun YongHyeon RXQ_CFG_RD_BURST_MASK; 3358d68875ebSPyun YongHyeon reg |= RXQ_CFG_RSS_MODE_DIS; 3359d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 33602f70cceaSPyun YongHyeon reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3361d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3362d68875ebSPyun YongHyeon 3363d68875ebSPyun YongHyeon /* Configure DMA parameters. */ 3364d68875ebSPyun YongHyeon reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3365d68875ebSPyun YongHyeon reg |= sc->alc_rcb; 3366d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3367d68875ebSPyun YongHyeon reg |= DMA_CFG_CMB_ENB; 3368d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3369d68875ebSPyun YongHyeon reg |= DMA_CFG_SMB_ENB; 3370d68875ebSPyun YongHyeon else 3371d68875ebSPyun YongHyeon reg |= DMA_CFG_SMB_DIS; 3372d68875ebSPyun YongHyeon reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3373d68875ebSPyun YongHyeon DMA_CFG_RD_BURST_SHIFT; 3374d68875ebSPyun YongHyeon reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3375d68875ebSPyun YongHyeon DMA_CFG_WR_BURST_SHIFT; 3376d68875ebSPyun YongHyeon reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3377d68875ebSPyun YongHyeon DMA_CFG_RD_DELAY_CNT_MASK; 3378d68875ebSPyun YongHyeon reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3379d68875ebSPyun YongHyeon DMA_CFG_WR_DELAY_CNT_MASK; 3380d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3381d68875ebSPyun YongHyeon 3382d68875ebSPyun YongHyeon /* 3383d68875ebSPyun YongHyeon * Configure Tx/Rx MACs. 3384d68875ebSPyun YongHyeon * - Auto-padding for short frames. 3385d68875ebSPyun YongHyeon * - Enable CRC generation. 3386d68875ebSPyun YongHyeon * Actual reconfiguration of MAC for resolved speed/duplex 3387d68875ebSPyun YongHyeon * is followed after detection of link establishment. 33882f70cceaSPyun YongHyeon * AR813x/AR815x always does checksum computation regardless 3389d68875ebSPyun YongHyeon * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3390d68875ebSPyun YongHyeon * have bug in protocol field in Rx return structure so 3391d68875ebSPyun YongHyeon * these controllers can't handle fragmented frames. Disable 3392d68875ebSPyun YongHyeon * Rx checksum offloading until there is a newer controller 3393d68875ebSPyun YongHyeon * that has sane implementation. 3394d68875ebSPyun YongHyeon */ 3395d68875ebSPyun YongHyeon reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3396d68875ebSPyun YongHyeon ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3397d68875ebSPyun YongHyeon MAC_CFG_PREAMBLE_MASK); 33982f70cceaSPyun YongHyeon if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 33992f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 34002f70cceaSPyun YongHyeon sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 34012f70cceaSPyun YongHyeon reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3402d68875ebSPyun YongHyeon if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3403d68875ebSPyun YongHyeon reg |= MAC_CFG_SPEED_10_100; 3404d68875ebSPyun YongHyeon else 3405d68875ebSPyun YongHyeon reg |= MAC_CFG_SPEED_1000; 3406d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3407d68875ebSPyun YongHyeon 3408d68875ebSPyun YongHyeon /* Set up the receive filter. */ 3409d68875ebSPyun YongHyeon alc_rxfilter(sc); 3410d68875ebSPyun YongHyeon alc_rxvlan(sc); 3411d68875ebSPyun YongHyeon 3412d68875ebSPyun YongHyeon /* Acknowledge all pending interrupts and clear it. */ 3413d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3414d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3415d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3416d68875ebSPyun YongHyeon 3417d68875ebSPyun YongHyeon sc->alc_flags &= ~ALC_FLAG_LINK; 3418d68875ebSPyun YongHyeon /* Switch to the current media. */ 3419d68875ebSPyun YongHyeon mii_mediachg(mii); 3420d68875ebSPyun YongHyeon 3421d68875ebSPyun YongHyeon callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3422d68875ebSPyun YongHyeon 3423d68875ebSPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_RUNNING; 3424d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3425d68875ebSPyun YongHyeon } 3426d68875ebSPyun YongHyeon 3427d68875ebSPyun YongHyeon static void 3428d68875ebSPyun YongHyeon alc_stop(struct alc_softc *sc) 3429d68875ebSPyun YongHyeon { 3430d68875ebSPyun YongHyeon struct ifnet *ifp; 3431d68875ebSPyun YongHyeon struct alc_txdesc *txd; 3432d68875ebSPyun YongHyeon struct alc_rxdesc *rxd; 3433d68875ebSPyun YongHyeon uint32_t reg; 3434d68875ebSPyun YongHyeon int i; 3435d68875ebSPyun YongHyeon 3436d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3437d68875ebSPyun YongHyeon /* 3438d68875ebSPyun YongHyeon * Mark the interface down and cancel the watchdog timer. 3439d68875ebSPyun YongHyeon */ 3440d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 3441d68875ebSPyun YongHyeon ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3442d68875ebSPyun YongHyeon sc->alc_flags &= ~ALC_FLAG_LINK; 3443d68875ebSPyun YongHyeon callout_stop(&sc->alc_tick_ch); 3444d68875ebSPyun YongHyeon sc->alc_watchdog_timer = 0; 3445d68875ebSPyun YongHyeon alc_stats_update(sc); 3446d68875ebSPyun YongHyeon /* Disable interrupts. */ 3447d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3448d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3449d68875ebSPyun YongHyeon alc_stop_queue(sc); 3450d68875ebSPyun YongHyeon /* Disable DMA. */ 3451d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_DMA_CFG); 3452d68875ebSPyun YongHyeon reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3453d68875ebSPyun YongHyeon reg |= DMA_CFG_SMB_DIS; 3454d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3455d68875ebSPyun YongHyeon DELAY(1000); 3456d68875ebSPyun YongHyeon /* Stop Rx/Tx MACs. */ 3457d68875ebSPyun YongHyeon alc_stop_mac(sc); 3458d68875ebSPyun YongHyeon /* Disable interrupts which might be touched in taskq handler. */ 3459d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3460d68875ebSPyun YongHyeon 3461d68875ebSPyun YongHyeon /* Reclaim Rx buffers that have been processed. */ 3462d68875ebSPyun YongHyeon if (sc->alc_cdata.alc_rxhead != NULL) 3463d68875ebSPyun YongHyeon m_freem(sc->alc_cdata.alc_rxhead); 3464d68875ebSPyun YongHyeon ALC_RXCHAIN_RESET(sc); 3465d68875ebSPyun YongHyeon /* 3466d68875ebSPyun YongHyeon * Free Tx/Rx mbufs still in the queues. 3467d68875ebSPyun YongHyeon */ 3468d68875ebSPyun YongHyeon for (i = 0; i < ALC_RX_RING_CNT; i++) { 3469d68875ebSPyun YongHyeon rxd = &sc->alc_cdata.alc_rxdesc[i]; 3470d68875ebSPyun YongHyeon if (rxd->rx_m != NULL) { 3471d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3472d68875ebSPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3473d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3474d68875ebSPyun YongHyeon rxd->rx_dmamap); 3475d68875ebSPyun YongHyeon m_freem(rxd->rx_m); 3476d68875ebSPyun YongHyeon rxd->rx_m = NULL; 3477d68875ebSPyun YongHyeon } 3478d68875ebSPyun YongHyeon } 3479d68875ebSPyun YongHyeon for (i = 0; i < ALC_TX_RING_CNT; i++) { 3480d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[i]; 3481d68875ebSPyun YongHyeon if (txd->tx_m != NULL) { 3482d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3483d68875ebSPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3484d68875ebSPyun YongHyeon bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3485d68875ebSPyun YongHyeon txd->tx_dmamap); 3486d68875ebSPyun YongHyeon m_freem(txd->tx_m); 3487d68875ebSPyun YongHyeon txd->tx_m = NULL; 3488d68875ebSPyun YongHyeon } 3489d68875ebSPyun YongHyeon } 3490d68875ebSPyun YongHyeon } 3491d68875ebSPyun YongHyeon 3492d68875ebSPyun YongHyeon static void 3493d68875ebSPyun YongHyeon alc_stop_mac(struct alc_softc *sc) 3494d68875ebSPyun YongHyeon { 3495d68875ebSPyun YongHyeon uint32_t reg; 3496d68875ebSPyun YongHyeon int i; 3497d68875ebSPyun YongHyeon 3498d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3499d68875ebSPyun YongHyeon 3500d68875ebSPyun YongHyeon /* Disable Rx/Tx MAC. */ 3501d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MAC_CFG); 3502d68875ebSPyun YongHyeon if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 35035bec76e7SPyun YongHyeon reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3504d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3505d68875ebSPyun YongHyeon } 3506d68875ebSPyun YongHyeon for (i = ALC_TIMEOUT; i > 0; i--) { 3507d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3508d68875ebSPyun YongHyeon if (reg == 0) 3509d68875ebSPyun YongHyeon break; 3510d68875ebSPyun YongHyeon DELAY(10); 3511d68875ebSPyun YongHyeon } 3512d68875ebSPyun YongHyeon if (i == 0) 3513d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 3514d68875ebSPyun YongHyeon "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3515d68875ebSPyun YongHyeon } 3516d68875ebSPyun YongHyeon 3517d68875ebSPyun YongHyeon static void 3518d68875ebSPyun YongHyeon alc_start_queue(struct alc_softc *sc) 3519d68875ebSPyun YongHyeon { 3520d68875ebSPyun YongHyeon uint32_t qcfg[] = { 3521d68875ebSPyun YongHyeon 0, 3522d68875ebSPyun YongHyeon RXQ_CFG_QUEUE0_ENB, 3523d68875ebSPyun YongHyeon RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3524d68875ebSPyun YongHyeon RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3525d68875ebSPyun YongHyeon RXQ_CFG_ENB 3526d68875ebSPyun YongHyeon }; 3527d68875ebSPyun YongHyeon uint32_t cfg; 3528d68875ebSPyun YongHyeon 3529d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3530d68875ebSPyun YongHyeon 3531d68875ebSPyun YongHyeon /* Enable RxQ. */ 3532d68875ebSPyun YongHyeon cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3533d68875ebSPyun YongHyeon cfg &= ~RXQ_CFG_ENB; 3534d68875ebSPyun YongHyeon cfg |= qcfg[1]; 3535d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3536d68875ebSPyun YongHyeon /* Enable TxQ. */ 3537d68875ebSPyun YongHyeon cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3538d68875ebSPyun YongHyeon cfg |= TXQ_CFG_ENB; 3539d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3540d68875ebSPyun YongHyeon } 3541d68875ebSPyun YongHyeon 3542d68875ebSPyun YongHyeon static void 3543d68875ebSPyun YongHyeon alc_stop_queue(struct alc_softc *sc) 3544d68875ebSPyun YongHyeon { 3545d68875ebSPyun YongHyeon uint32_t reg; 3546d68875ebSPyun YongHyeon int i; 3547d68875ebSPyun YongHyeon 3548d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3549d68875ebSPyun YongHyeon 3550d68875ebSPyun YongHyeon /* Disable RxQ. */ 3551d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3552d68875ebSPyun YongHyeon if ((reg & RXQ_CFG_ENB) != 0) { 3553d68875ebSPyun YongHyeon reg &= ~RXQ_CFG_ENB; 3554d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3555d68875ebSPyun YongHyeon } 3556d68875ebSPyun YongHyeon /* Disable TxQ. */ 3557d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3558d68875ebSPyun YongHyeon if ((reg & TXQ_CFG_ENB) == 0) { 3559d68875ebSPyun YongHyeon reg &= ~TXQ_CFG_ENB; 3560d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3561d68875ebSPyun YongHyeon } 3562d68875ebSPyun YongHyeon for (i = ALC_TIMEOUT; i > 0; i--) { 3563d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3564d68875ebSPyun YongHyeon if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3565d68875ebSPyun YongHyeon break; 3566d68875ebSPyun YongHyeon DELAY(10); 3567d68875ebSPyun YongHyeon } 3568d68875ebSPyun YongHyeon if (i == 0) 3569d68875ebSPyun YongHyeon device_printf(sc->alc_dev, 3570d68875ebSPyun YongHyeon "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3571d68875ebSPyun YongHyeon } 3572d68875ebSPyun YongHyeon 3573d68875ebSPyun YongHyeon static void 3574d68875ebSPyun YongHyeon alc_init_tx_ring(struct alc_softc *sc) 3575d68875ebSPyun YongHyeon { 3576d68875ebSPyun YongHyeon struct alc_ring_data *rd; 3577d68875ebSPyun YongHyeon struct alc_txdesc *txd; 3578d68875ebSPyun YongHyeon int i; 3579d68875ebSPyun YongHyeon 3580d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3581d68875ebSPyun YongHyeon 3582d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_prod = 0; 3583d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cons = 0; 3584d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_cnt = 0; 3585d68875ebSPyun YongHyeon 3586d68875ebSPyun YongHyeon rd = &sc->alc_rdata; 3587d68875ebSPyun YongHyeon bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3588d68875ebSPyun YongHyeon for (i = 0; i < ALC_TX_RING_CNT; i++) { 3589d68875ebSPyun YongHyeon txd = &sc->alc_cdata.alc_txdesc[i]; 3590d68875ebSPyun YongHyeon txd->tx_m = NULL; 3591d68875ebSPyun YongHyeon } 3592d68875ebSPyun YongHyeon 3593d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3594d68875ebSPyun YongHyeon sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3595d68875ebSPyun YongHyeon } 3596d68875ebSPyun YongHyeon 3597d68875ebSPyun YongHyeon static int 3598d68875ebSPyun YongHyeon alc_init_rx_ring(struct alc_softc *sc) 3599d68875ebSPyun YongHyeon { 3600d68875ebSPyun YongHyeon struct alc_ring_data *rd; 3601d68875ebSPyun YongHyeon struct alc_rxdesc *rxd; 3602d68875ebSPyun YongHyeon int i; 3603d68875ebSPyun YongHyeon 3604d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3605d68875ebSPyun YongHyeon 3606d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3607d68875ebSPyun YongHyeon sc->alc_morework = 0; 3608d68875ebSPyun YongHyeon rd = &sc->alc_rdata; 3609d68875ebSPyun YongHyeon bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3610d68875ebSPyun YongHyeon for (i = 0; i < ALC_RX_RING_CNT; i++) { 3611d68875ebSPyun YongHyeon rxd = &sc->alc_cdata.alc_rxdesc[i]; 3612d68875ebSPyun YongHyeon rxd->rx_m = NULL; 3613d68875ebSPyun YongHyeon rxd->rx_desc = &rd->alc_rx_ring[i]; 3614d68875ebSPyun YongHyeon if (alc_newbuf(sc, rxd) != 0) 3615d68875ebSPyun YongHyeon return (ENOBUFS); 3616d68875ebSPyun YongHyeon } 3617d68875ebSPyun YongHyeon 3618d68875ebSPyun YongHyeon /* 3619d68875ebSPyun YongHyeon * Since controller does not update Rx descriptors, driver 3620d68875ebSPyun YongHyeon * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3621d68875ebSPyun YongHyeon * is enough to ensure coherence. 3622d68875ebSPyun YongHyeon */ 3623d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3624d68875ebSPyun YongHyeon sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3625d68875ebSPyun YongHyeon /* Let controller know availability of new Rx buffers. */ 3626d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3627d68875ebSPyun YongHyeon 3628d68875ebSPyun YongHyeon return (0); 3629d68875ebSPyun YongHyeon } 3630d68875ebSPyun YongHyeon 3631d68875ebSPyun YongHyeon static void 3632d68875ebSPyun YongHyeon alc_init_rr_ring(struct alc_softc *sc) 3633d68875ebSPyun YongHyeon { 3634d68875ebSPyun YongHyeon struct alc_ring_data *rd; 3635d68875ebSPyun YongHyeon 3636d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3637d68875ebSPyun YongHyeon 3638d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_cons = 0; 3639d68875ebSPyun YongHyeon ALC_RXCHAIN_RESET(sc); 3640d68875ebSPyun YongHyeon 3641d68875ebSPyun YongHyeon rd = &sc->alc_rdata; 3642d68875ebSPyun YongHyeon bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3643d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3644d68875ebSPyun YongHyeon sc->alc_cdata.alc_rr_ring_map, 3645d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3646d68875ebSPyun YongHyeon } 3647d68875ebSPyun YongHyeon 3648d68875ebSPyun YongHyeon static void 3649d68875ebSPyun YongHyeon alc_init_cmb(struct alc_softc *sc) 3650d68875ebSPyun YongHyeon { 3651d68875ebSPyun YongHyeon struct alc_ring_data *rd; 3652d68875ebSPyun YongHyeon 3653d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3654d68875ebSPyun YongHyeon 3655d68875ebSPyun YongHyeon rd = &sc->alc_rdata; 3656d68875ebSPyun YongHyeon bzero(rd->alc_cmb, ALC_CMB_SZ); 3657d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3658d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3659d68875ebSPyun YongHyeon } 3660d68875ebSPyun YongHyeon 3661d68875ebSPyun YongHyeon static void 3662d68875ebSPyun YongHyeon alc_init_smb(struct alc_softc *sc) 3663d68875ebSPyun YongHyeon { 3664d68875ebSPyun YongHyeon struct alc_ring_data *rd; 3665d68875ebSPyun YongHyeon 3666d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3667d68875ebSPyun YongHyeon 3668d68875ebSPyun YongHyeon rd = &sc->alc_rdata; 3669d68875ebSPyun YongHyeon bzero(rd->alc_smb, ALC_SMB_SZ); 3670d68875ebSPyun YongHyeon bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3671d68875ebSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3672d68875ebSPyun YongHyeon } 3673d68875ebSPyun YongHyeon 3674d68875ebSPyun YongHyeon static void 3675d68875ebSPyun YongHyeon alc_rxvlan(struct alc_softc *sc) 3676d68875ebSPyun YongHyeon { 3677d68875ebSPyun YongHyeon struct ifnet *ifp; 3678d68875ebSPyun YongHyeon uint32_t reg; 3679d68875ebSPyun YongHyeon 3680d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3681d68875ebSPyun YongHyeon 3682d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 3683d68875ebSPyun YongHyeon reg = CSR_READ_4(sc, ALC_MAC_CFG); 3684d68875ebSPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3685d68875ebSPyun YongHyeon reg |= MAC_CFG_VLAN_TAG_STRIP; 3686d68875ebSPyun YongHyeon else 3687d68875ebSPyun YongHyeon reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3688d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3689d68875ebSPyun YongHyeon } 3690d68875ebSPyun YongHyeon 3691d68875ebSPyun YongHyeon static void 3692d68875ebSPyun YongHyeon alc_rxfilter(struct alc_softc *sc) 3693d68875ebSPyun YongHyeon { 3694d68875ebSPyun YongHyeon struct ifnet *ifp; 3695d68875ebSPyun YongHyeon struct ifmultiaddr *ifma; 3696d68875ebSPyun YongHyeon uint32_t crc; 3697d68875ebSPyun YongHyeon uint32_t mchash[2]; 3698d68875ebSPyun YongHyeon uint32_t rxcfg; 3699d68875ebSPyun YongHyeon 3700d68875ebSPyun YongHyeon ALC_LOCK_ASSERT(sc); 3701d68875ebSPyun YongHyeon 3702d68875ebSPyun YongHyeon ifp = sc->alc_ifp; 3703d68875ebSPyun YongHyeon 3704d68875ebSPyun YongHyeon bzero(mchash, sizeof(mchash)); 3705d68875ebSPyun YongHyeon rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3706d68875ebSPyun YongHyeon rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3707d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_BROADCAST) != 0) 3708d68875ebSPyun YongHyeon rxcfg |= MAC_CFG_BCAST; 3709d68875ebSPyun YongHyeon if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3710d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_PROMISC) != 0) 3711d68875ebSPyun YongHyeon rxcfg |= MAC_CFG_PROMISC; 3712d68875ebSPyun YongHyeon if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3713d68875ebSPyun YongHyeon rxcfg |= MAC_CFG_ALLMULTI; 3714d68875ebSPyun YongHyeon mchash[0] = 0xFFFFFFFF; 3715d68875ebSPyun YongHyeon mchash[1] = 0xFFFFFFFF; 3716d68875ebSPyun YongHyeon goto chipit; 3717d68875ebSPyun YongHyeon } 3718d68875ebSPyun YongHyeon 3719eb956cd0SRobert Watson if_maddr_rlock(ifp); 3720d68875ebSPyun YongHyeon TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3721d68875ebSPyun YongHyeon if (ifma->ifma_addr->sa_family != AF_LINK) 3722d68875ebSPyun YongHyeon continue; 3723cb2cdeceSPyun YongHyeon crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3724d68875ebSPyun YongHyeon ifma->ifma_addr), ETHER_ADDR_LEN); 3725d68875ebSPyun YongHyeon mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3726d68875ebSPyun YongHyeon } 3727eb956cd0SRobert Watson if_maddr_runlock(ifp); 3728d68875ebSPyun YongHyeon 3729d68875ebSPyun YongHyeon chipit: 3730d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3731d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3732d68875ebSPyun YongHyeon CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3733d68875ebSPyun YongHyeon } 3734d68875ebSPyun YongHyeon 3735d68875ebSPyun YongHyeon static int 3736d68875ebSPyun YongHyeon sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3737d68875ebSPyun YongHyeon { 3738d68875ebSPyun YongHyeon int error, value; 3739d68875ebSPyun YongHyeon 3740d68875ebSPyun YongHyeon if (arg1 == NULL) 3741d68875ebSPyun YongHyeon return (EINVAL); 3742d68875ebSPyun YongHyeon value = *(int *)arg1; 3743d68875ebSPyun YongHyeon error = sysctl_handle_int(oidp, &value, 0, req); 3744d68875ebSPyun YongHyeon if (error || req->newptr == NULL) 3745d68875ebSPyun YongHyeon return (error); 3746d68875ebSPyun YongHyeon if (value < low || value > high) 3747d68875ebSPyun YongHyeon return (EINVAL); 3748d68875ebSPyun YongHyeon *(int *)arg1 = value; 3749d68875ebSPyun YongHyeon 3750d68875ebSPyun YongHyeon return (0); 3751d68875ebSPyun YongHyeon } 3752d68875ebSPyun YongHyeon 3753d68875ebSPyun YongHyeon static int 3754d68875ebSPyun YongHyeon sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3755d68875ebSPyun YongHyeon { 3756d68875ebSPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3757d68875ebSPyun YongHyeon ALC_PROC_MIN, ALC_PROC_MAX)); 3758d68875ebSPyun YongHyeon } 3759d68875ebSPyun YongHyeon 3760d68875ebSPyun YongHyeon static int 3761d68875ebSPyun YongHyeon sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3762d68875ebSPyun YongHyeon { 3763d68875ebSPyun YongHyeon 3764d68875ebSPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, 3765d68875ebSPyun YongHyeon ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3766d68875ebSPyun YongHyeon } 3767