1 /* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $ 7 */ 8 9 #include <sys/cdefs.h> 10 #include <dev/aic7xxx/aic7xxx_osm.h> 11 12 static ahc_reg_parse_entry_t SCSISEQ_parse_table[] = { 13 { "SCSIRSTO", 0x01, 0x01 }, 14 { "ENAUTOATNP", 0x02, 0x02 }, 15 { "ENAUTOATNI", 0x04, 0x04 }, 16 { "ENAUTOATNO", 0x08, 0x08 }, 17 { "ENRSELI", 0x10, 0x10 }, 18 { "ENSELI", 0x20, 0x20 }, 19 { "ENSELO", 0x40, 0x40 }, 20 { "TEMODE", 0x80, 0x80 } 21 }; 22 23 int 24 ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap) 25 { 26 return (ahc_print_register(SCSISEQ_parse_table, 8, "SCSISEQ", 27 0x00, regvalue, cur_col, wrap)); 28 } 29 30 static ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = { 31 { "CLRCHN", 0x02, 0x02 }, 32 { "SCAMEN", 0x04, 0x04 }, 33 { "SPIOEN", 0x08, 0x08 }, 34 { "CLRSTCNT", 0x10, 0x10 }, 35 { "FAST20", 0x20, 0x20 }, 36 { "DFPEXP", 0x40, 0x40 }, 37 { "DFON", 0x80, 0x80 } 38 }; 39 40 int 41 ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 42 { 43 return (ahc_print_register(SXFRCTL0_parse_table, 7, "SXFRCTL0", 44 0x01, regvalue, cur_col, wrap)); 45 } 46 47 static ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = { 48 { "STPWEN", 0x01, 0x01 }, 49 { "ACTNEGEN", 0x02, 0x02 }, 50 { "ENSTIMER", 0x04, 0x04 }, 51 { "ENSPCHK", 0x20, 0x20 }, 52 { "SWRAPEN", 0x40, 0x40 }, 53 { "BITBUCKET", 0x80, 0x80 }, 54 { "STIMESEL", 0x18, 0x18 } 55 }; 56 57 int 58 ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 59 { 60 return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1", 61 0x02, regvalue, cur_col, wrap)); 62 } 63 64 static ahc_reg_parse_entry_t SCSISIGI_parse_table[] = { 65 { "ACKI", 0x01, 0x01 }, 66 { "REQI", 0x02, 0x02 }, 67 { "BSYI", 0x04, 0x04 }, 68 { "SELI", 0x08, 0x08 }, 69 { "ATNI", 0x10, 0x10 }, 70 { "MSGI", 0x20, 0x20 }, 71 { "IOI", 0x40, 0x40 }, 72 { "CDI", 0x80, 0x80 }, 73 { "P_DATAOUT", 0x00, 0x00 }, 74 { "P_DATAOUT_DT", 0x20, 0x20 }, 75 { "P_DATAIN", 0x40, 0x40 }, 76 { "P_DATAIN_DT", 0x60, 0x60 }, 77 { "P_COMMAND", 0x80, 0x80 }, 78 { "P_MESGOUT", 0xa0, 0xa0 }, 79 { "P_STATUS", 0xc0, 0xc0 }, 80 { "PHASE_MASK", 0xe0, 0xe0 }, 81 { "P_MESGIN", 0xe0, 0xe0 } 82 }; 83 84 int 85 ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap) 86 { 87 return (ahc_print_register(SCSISIGI_parse_table, 17, "SCSISIGI", 88 0x03, regvalue, cur_col, wrap)); 89 } 90 91 static ahc_reg_parse_entry_t SCSISIGO_parse_table[] = { 92 { "ACKO", 0x01, 0x01 }, 93 { "REQO", 0x02, 0x02 }, 94 { "BSYO", 0x04, 0x04 }, 95 { "SELO", 0x08, 0x08 }, 96 { "ATNO", 0x10, 0x10 }, 97 { "MSGO", 0x20, 0x20 }, 98 { "IOO", 0x40, 0x40 }, 99 { "CDO", 0x80, 0x80 }, 100 { "P_DATAOUT", 0x00, 0x00 }, 101 { "P_DATAIN", 0x40, 0x40 }, 102 { "P_COMMAND", 0x80, 0x80 }, 103 { "P_MESGOUT", 0xa0, 0xa0 }, 104 { "P_STATUS", 0xc0, 0xc0 }, 105 { "PHASE_MASK", 0xe0, 0xe0 }, 106 { "P_MESGIN", 0xe0, 0xe0 } 107 }; 108 109 int 110 ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) 111 { 112 return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO", 113 0x03, regvalue, cur_col, wrap)); 114 } 115 116 static ahc_reg_parse_entry_t SCSIRATE_parse_table[] = { 117 { "SINGLE_EDGE", 0x10, 0x10 }, 118 { "ENABLE_CRC", 0x40, 0x40 }, 119 { "WIDEXFER", 0x80, 0x80 }, 120 { "SXFR_ULTRA2", 0x0f, 0x0f }, 121 { "SOFS", 0x0f, 0x0f }, 122 { "SXFR", 0x70, 0x70 } 123 }; 124 125 int 126 ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap) 127 { 128 return (ahc_print_register(SCSIRATE_parse_table, 6, "SCSIRATE", 129 0x04, regvalue, cur_col, wrap)); 130 } 131 132 static ahc_reg_parse_entry_t SCSIID_parse_table[] = { 133 { "TWIN_CHNLB", 0x80, 0x80 }, 134 { "OID", 0x0f, 0x0f }, 135 { "TWIN_TID", 0x70, 0x70 }, 136 { "SOFS_ULTRA2", 0x7f, 0x7f }, 137 { "TID", 0xf0, 0xf0 } 138 }; 139 140 int 141 ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 142 { 143 return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID", 144 0x05, regvalue, cur_col, wrap)); 145 } 146 147 int 148 ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap) 149 { 150 return (ahc_print_register(NULL, 0, "SCSIDATL", 151 0x06, regvalue, cur_col, wrap)); 152 } 153 154 int 155 ahc_scsidath_print(u_int regvalue, u_int *cur_col, u_int wrap) 156 { 157 return (ahc_print_register(NULL, 0, "SCSIDATH", 158 0x07, regvalue, cur_col, wrap)); 159 } 160 161 static ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = { 162 { "DIS_MSGIN_DUALEDGE", 0x01, 0x01 }, 163 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 164 { "SCSIDATL_IMGEN", 0x04, 0x04 }, 165 { "EXPPHASEDIS", 0x08, 0x08 }, 166 { "BUSFREEREV", 0x10, 0x10 }, 167 { "ATNMGMNTEN", 0x20, 0x20 }, 168 { "AUTOACKEN", 0x40, 0x40 }, 169 { "AUTORATEEN", 0x80, 0x80 }, 170 { "OPTIONMODE_DEFAULTS",0x03, 0x03 } 171 }; 172 173 int 174 ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap) 175 { 176 return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE", 177 0x08, regvalue, cur_col, wrap)); 178 } 179 180 int 181 ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 182 { 183 return (ahc_print_register(NULL, 0, "STCNT", 184 0x08, regvalue, cur_col, wrap)); 185 } 186 187 int 188 ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 189 { 190 return (ahc_print_register(NULL, 0, "TARGCRCCNT", 191 0x0a, regvalue, cur_col, wrap)); 192 } 193 194 static ahc_reg_parse_entry_t CLRSINT0_parse_table[] = { 195 { "CLRSPIORDY", 0x02, 0x02 }, 196 { "CLRSWRAP", 0x08, 0x08 }, 197 { "CLRIOERR", 0x08, 0x08 }, 198 { "CLRSELINGO", 0x10, 0x10 }, 199 { "CLRSELDI", 0x20, 0x20 }, 200 { "CLRSELDO", 0x40, 0x40 } 201 }; 202 203 int 204 ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 205 { 206 return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0", 207 0x0b, regvalue, cur_col, wrap)); 208 } 209 210 static ahc_reg_parse_entry_t SSTAT0_parse_table[] = { 211 { "DMADONE", 0x01, 0x01 }, 212 { "SPIORDY", 0x02, 0x02 }, 213 { "SDONE", 0x04, 0x04 }, 214 { "SWRAP", 0x08, 0x08 }, 215 { "IOERR", 0x08, 0x08 }, 216 { "SELINGO", 0x10, 0x10 }, 217 { "SELDI", 0x20, 0x20 }, 218 { "SELDO", 0x40, 0x40 }, 219 { "TARGET", 0x80, 0x80 } 220 }; 221 222 int 223 ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 224 { 225 return (ahc_print_register(SSTAT0_parse_table, 9, "SSTAT0", 226 0x0b, regvalue, cur_col, wrap)); 227 } 228 229 static ahc_reg_parse_entry_t CLRSINT1_parse_table[] = { 230 { "CLRREQINIT", 0x01, 0x01 }, 231 { "CLRPHASECHG", 0x02, 0x02 }, 232 { "CLRSCSIPERR", 0x04, 0x04 }, 233 { "CLRBUSFREE", 0x08, 0x08 }, 234 { "CLRSCSIRSTI", 0x20, 0x20 }, 235 { "CLRATNO", 0x40, 0x40 }, 236 { "CLRSELTIMEO", 0x80, 0x80 } 237 }; 238 239 int 240 ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 241 { 242 return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", 243 0x0c, regvalue, cur_col, wrap)); 244 } 245 246 static ahc_reg_parse_entry_t SSTAT1_parse_table[] = { 247 { "REQINIT", 0x01, 0x01 }, 248 { "PHASECHG", 0x02, 0x02 }, 249 { "SCSIPERR", 0x04, 0x04 }, 250 { "BUSFREE", 0x08, 0x08 }, 251 { "PHASEMIS", 0x10, 0x10 }, 252 { "SCSIRSTI", 0x20, 0x20 }, 253 { "ATNTARG", 0x40, 0x40 }, 254 { "SELTO", 0x80, 0x80 } 255 }; 256 257 int 258 ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 259 { 260 return (ahc_print_register(SSTAT1_parse_table, 8, "SSTAT1", 261 0x0c, regvalue, cur_col, wrap)); 262 } 263 264 static ahc_reg_parse_entry_t SSTAT2_parse_table[] = { 265 { "DUAL_EDGE_ERR", 0x01, 0x01 }, 266 { "CRCREQERR", 0x02, 0x02 }, 267 { "CRCENDERR", 0x04, 0x04 }, 268 { "CRCVALERR", 0x08, 0x08 }, 269 { "EXP_ACTIVE", 0x10, 0x10 }, 270 { "SHVALID", 0x40, 0x40 }, 271 { "OVERRUN", 0x80, 0x80 }, 272 { "SFCNT", 0x1f, 0x1f } 273 }; 274 275 int 276 ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 277 { 278 return (ahc_print_register(SSTAT2_parse_table, 8, "SSTAT2", 279 0x0d, regvalue, cur_col, wrap)); 280 } 281 282 static ahc_reg_parse_entry_t SSTAT3_parse_table[] = { 283 { "OFFCNT", 0x0f, 0x0f }, 284 { "U2OFFCNT", 0x7f, 0x7f }, 285 { "SCSICNT", 0xf0, 0xf0 } 286 }; 287 288 int 289 ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap) 290 { 291 return (ahc_print_register(SSTAT3_parse_table, 3, "SSTAT3", 292 0x0e, regvalue, cur_col, wrap)); 293 } 294 295 static ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = { 296 { "OID", 0x0f, 0x0f }, 297 { "TID", 0xf0, 0xf0 } 298 }; 299 300 int 301 ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap) 302 { 303 return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2", 304 0x0f, regvalue, cur_col, wrap)); 305 } 306 307 static ahc_reg_parse_entry_t SIMODE0_parse_table[] = { 308 { "ENDMADONE", 0x01, 0x01 }, 309 { "ENSPIORDY", 0x02, 0x02 }, 310 { "ENSDONE", 0x04, 0x04 }, 311 { "ENSWRAP", 0x08, 0x08 }, 312 { "ENIOERR", 0x08, 0x08 }, 313 { "ENSELINGO", 0x10, 0x10 }, 314 { "ENSELDI", 0x20, 0x20 }, 315 { "ENSELDO", 0x40, 0x40 } 316 }; 317 318 int 319 ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 320 { 321 return (ahc_print_register(SIMODE0_parse_table, 8, "SIMODE0", 322 0x10, regvalue, cur_col, wrap)); 323 } 324 325 static ahc_reg_parse_entry_t SIMODE1_parse_table[] = { 326 { "ENREQINIT", 0x01, 0x01 }, 327 { "ENPHASECHG", 0x02, 0x02 }, 328 { "ENSCSIPERR", 0x04, 0x04 }, 329 { "ENBUSFREE", 0x08, 0x08 }, 330 { "ENPHASEMIS", 0x10, 0x10 }, 331 { "ENSCSIRST", 0x20, 0x20 }, 332 { "ENATNTARG", 0x40, 0x40 }, 333 { "ENSELTIMO", 0x80, 0x80 } 334 }; 335 336 int 337 ahc_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 338 { 339 return (ahc_print_register(SIMODE1_parse_table, 8, "SIMODE1", 340 0x11, regvalue, cur_col, wrap)); 341 } 342 343 int 344 ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap) 345 { 346 return (ahc_print_register(NULL, 0, "SCSIBUSL", 347 0x12, regvalue, cur_col, wrap)); 348 } 349 350 static ahc_reg_parse_entry_t SXFRCTL2_parse_table[] = { 351 { "CMDDMAEN", 0x08, 0x08 }, 352 { "AUTORSTDIS", 0x10, 0x10 }, 353 { "ASYNC_SETUP", 0x07, 0x07 } 354 }; 355 356 int 357 ahc_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) 358 { 359 return (ahc_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2", 360 0x13, regvalue, cur_col, wrap)); 361 } 362 363 int 364 ahc_scsibush_print(u_int regvalue, u_int *cur_col, u_int wrap) 365 { 366 return (ahc_print_register(NULL, 0, "SCSIBUSH", 367 0x13, regvalue, cur_col, wrap)); 368 } 369 370 int 371 ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 372 { 373 return (ahc_print_register(NULL, 0, "SHADDR", 374 0x14, regvalue, cur_col, wrap)); 375 } 376 377 static ahc_reg_parse_entry_t SELTIMER_parse_table[] = { 378 { "STAGE1", 0x01, 0x01 }, 379 { "STAGE2", 0x02, 0x02 }, 380 { "STAGE3", 0x04, 0x04 }, 381 { "STAGE4", 0x08, 0x08 }, 382 { "STAGE5", 0x10, 0x10 }, 383 { "STAGE6", 0x20, 0x20 } 384 }; 385 386 int 387 ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap) 388 { 389 return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER", 390 0x18, regvalue, cur_col, wrap)); 391 } 392 393 static ahc_reg_parse_entry_t SELID_parse_table[] = { 394 { "ONEBIT", 0x08, 0x08 }, 395 { "SELID_MASK", 0xf0, 0xf0 } 396 }; 397 398 int 399 ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap) 400 { 401 return (ahc_print_register(SELID_parse_table, 2, "SELID", 402 0x19, regvalue, cur_col, wrap)); 403 } 404 405 static ahc_reg_parse_entry_t SCAMCTL_parse_table[] = { 406 { "DFLTTID", 0x10, 0x10 }, 407 { "ALTSTIM", 0x20, 0x20 }, 408 { "CLRSCAMSELID", 0x40, 0x40 }, 409 { "ENSCAMSELO", 0x80, 0x80 }, 410 { "SCAMLVL", 0x03, 0x03 } 411 }; 412 413 int 414 ahc_scamctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 415 { 416 return (ahc_print_register(SCAMCTL_parse_table, 5, "SCAMCTL", 417 0x1a, regvalue, cur_col, wrap)); 418 } 419 420 int 421 ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap) 422 { 423 return (ahc_print_register(NULL, 0, "TARGID", 424 0x1b, regvalue, cur_col, wrap)); 425 } 426 427 static ahc_reg_parse_entry_t SPIOCAP_parse_table[] = { 428 { "SSPIOCPS", 0x01, 0x01 }, 429 { "ROM", 0x02, 0x02 }, 430 { "EEPROM", 0x04, 0x04 }, 431 { "SEEPROM", 0x08, 0x08 }, 432 { "EXT_BRDCTL", 0x10, 0x10 }, 433 { "SOFTCMDEN", 0x20, 0x20 }, 434 { "SOFT0", 0x40, 0x40 }, 435 { "SOFT1", 0x80, 0x80 } 436 }; 437 438 int 439 ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap) 440 { 441 return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP", 442 0x1b, regvalue, cur_col, wrap)); 443 } 444 445 static ahc_reg_parse_entry_t BRDCTL_parse_table[] = { 446 { "BRDCTL0", 0x01, 0x01 }, 447 { "BRDSTB_ULTRA2", 0x01, 0x01 }, 448 { "BRDCTL1", 0x02, 0x02 }, 449 { "BRDRW_ULTRA2", 0x02, 0x02 }, 450 { "BRDRW", 0x04, 0x04 }, 451 { "BRDDAT2", 0x04, 0x04 }, 452 { "BRDCS", 0x08, 0x08 }, 453 { "BRDDAT3", 0x08, 0x08 }, 454 { "BRDSTB", 0x10, 0x10 }, 455 { "BRDDAT4", 0x10, 0x10 }, 456 { "BRDDAT5", 0x20, 0x20 }, 457 { "BRDDAT6", 0x40, 0x40 }, 458 { "BRDDAT7", 0x80, 0x80 } 459 }; 460 461 int 462 ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 463 { 464 return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL", 465 0x1d, regvalue, cur_col, wrap)); 466 } 467 468 static ahc_reg_parse_entry_t SEECTL_parse_table[] = { 469 { "SEEDI", 0x01, 0x01 }, 470 { "SEEDO", 0x02, 0x02 }, 471 { "SEECK", 0x04, 0x04 }, 472 { "SEECS", 0x08, 0x08 }, 473 { "SEERDY", 0x10, 0x10 }, 474 { "SEEMS", 0x20, 0x20 }, 475 { "EXTARBREQ", 0x40, 0x40 }, 476 { "EXTARBACK", 0x80, 0x80 } 477 }; 478 479 int 480 ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap) 481 { 482 return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL", 483 0x1e, regvalue, cur_col, wrap)); 484 } 485 486 static ahc_reg_parse_entry_t SBLKCTL_parse_table[] = { 487 { "XCVR", 0x01, 0x01 }, 488 { "SELWIDE", 0x02, 0x02 }, 489 { "ENAB20", 0x04, 0x04 }, 490 { "SELBUSB", 0x08, 0x08 }, 491 { "ENAB40", 0x08, 0x08 }, 492 { "AUTOFLUSHDIS", 0x20, 0x20 }, 493 { "DIAGLEDON", 0x40, 0x40 }, 494 { "DIAGLEDEN", 0x80, 0x80 } 495 }; 496 497 int 498 ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 499 { 500 return (ahc_print_register(SBLKCTL_parse_table, 8, "SBLKCTL", 501 0x1f, regvalue, cur_col, wrap)); 502 } 503 504 int 505 ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap) 506 { 507 return (ahc_print_register(NULL, 0, "BUSY_TARGETS", 508 0x20, regvalue, cur_col, wrap)); 509 } 510 511 int 512 ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap) 513 { 514 return (ahc_print_register(NULL, 0, "ULTRA_ENB", 515 0x30, regvalue, cur_col, wrap)); 516 } 517 518 int 519 ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap) 520 { 521 return (ahc_print_register(NULL, 0, "DISC_DSB", 522 0x32, regvalue, cur_col, wrap)); 523 } 524 525 int 526 ahc_cmdsize_table_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) 527 { 528 return (ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 529 0x34, regvalue, cur_col, wrap)); 530 } 531 532 int 533 ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap) 534 { 535 return (ahc_print_register(NULL, 0, "MWI_RESIDUAL", 536 0x38, regvalue, cur_col, wrap)); 537 } 538 539 int 540 ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) 541 { 542 return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 543 0x39, regvalue, cur_col, wrap)); 544 } 545 546 int 547 ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap) 548 { 549 return (ahc_print_register(NULL, 0, "MSG_OUT", 550 0x3a, regvalue, cur_col, wrap)); 551 } 552 553 static ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = { 554 { "FIFORESET", 0x01, 0x01 }, 555 { "FIFOFLUSH", 0x02, 0x02 }, 556 { "DIRECTION", 0x04, 0x04 }, 557 { "HDMAEN", 0x08, 0x08 }, 558 { "HDMAENACK", 0x08, 0x08 }, 559 { "SDMAEN", 0x10, 0x10 }, 560 { "SDMAENACK", 0x10, 0x10 }, 561 { "SCSIEN", 0x20, 0x20 }, 562 { "WIDEODD", 0x40, 0x40 }, 563 { "PRELOADEN", 0x80, 0x80 } 564 }; 565 566 int 567 ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap) 568 { 569 return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS", 570 0x3b, regvalue, cur_col, wrap)); 571 } 572 573 static ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 574 { "NO_DISCONNECT", 0x01, 0x01 }, 575 { "SPHASE_PENDING", 0x02, 0x02 }, 576 { "DPHASE_PENDING", 0x04, 0x04 }, 577 { "CMDPHASE_PENDING", 0x08, 0x08 }, 578 { "TARG_CMD_PENDING", 0x10, 0x10 }, 579 { "DPHASE", 0x20, 0x20 }, 580 { "NO_CDB_SENT", 0x40, 0x40 }, 581 { "TARGET_CMD_IS_TAGGED",0x40, 0x40 }, 582 { "NOT_IDENTIFIED", 0x80, 0x80 } 583 }; 584 585 int 586 ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 587 { 588 return (ahc_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS", 589 0x3c, regvalue, cur_col, wrap)); 590 } 591 592 int 593 ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 594 { 595 return (ahc_print_register(NULL, 0, "SAVED_SCSIID", 596 0x3d, regvalue, cur_col, wrap)); 597 } 598 599 int 600 ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 601 { 602 return (ahc_print_register(NULL, 0, "SAVED_LUN", 603 0x3e, regvalue, cur_col, wrap)); 604 } 605 606 static ahc_reg_parse_entry_t LASTPHASE_parse_table[] = { 607 { "MSGI", 0x20, 0x20 }, 608 { "IOI", 0x40, 0x40 }, 609 { "CDI", 0x80, 0x80 }, 610 { "P_DATAOUT", 0x00, 0x00 }, 611 { "P_BUSFREE", 0x01, 0x01 }, 612 { "P_DATAIN", 0x40, 0x40 }, 613 { "P_COMMAND", 0x80, 0x80 }, 614 { "P_MESGOUT", 0xa0, 0xa0 }, 615 { "P_STATUS", 0xc0, 0xc0 }, 616 { "PHASE_MASK", 0xe0, 0xe0 }, 617 { "P_MESGIN", 0xe0, 0xe0 } 618 }; 619 620 int 621 ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 622 { 623 return (ahc_print_register(LASTPHASE_parse_table, 11, "LASTPHASE", 624 0x3f, regvalue, cur_col, wrap)); 625 } 626 627 int 628 ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) 629 { 630 return (ahc_print_register(NULL, 0, "WAITING_SCBH", 631 0x40, regvalue, cur_col, wrap)); 632 } 633 634 int 635 ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) 636 { 637 return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 638 0x41, regvalue, cur_col, wrap)); 639 } 640 641 int 642 ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) 643 { 644 return (ahc_print_register(NULL, 0, "FREE_SCBH", 645 0x42, regvalue, cur_col, wrap)); 646 } 647 648 int 649 ahc_complete_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap) 650 { 651 return (ahc_print_register(NULL, 0, "COMPLETE_SCBH", 652 0x43, regvalue, cur_col, wrap)); 653 } 654 655 int 656 ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 657 { 658 return (ahc_print_register(NULL, 0, "HSCB_ADDR", 659 0x44, regvalue, cur_col, wrap)); 660 } 661 662 int 663 ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 664 { 665 return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 666 0x48, regvalue, cur_col, wrap)); 667 } 668 669 int 670 ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 671 { 672 return (ahc_print_register(NULL, 0, "KERNEL_QINPOS", 673 0x4c, regvalue, cur_col, wrap)); 674 } 675 676 int 677 ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 678 { 679 return (ahc_print_register(NULL, 0, "QINPOS", 680 0x4d, regvalue, cur_col, wrap)); 681 } 682 683 int 684 ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 685 { 686 return (ahc_print_register(NULL, 0, "QOUTPOS", 687 0x4e, regvalue, cur_col, wrap)); 688 } 689 690 int 691 ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 692 { 693 return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 694 0x4f, regvalue, cur_col, wrap)); 695 } 696 697 int 698 ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 699 { 700 return (ahc_print_register(NULL, 0, "TQINPOS", 701 0x50, regvalue, cur_col, wrap)); 702 } 703 704 static ahc_reg_parse_entry_t ARG_1_parse_table[] = { 705 { "SPARE", 0x01, 0x01 }, 706 { "CONT_TARG_SESSION", 0x02, 0x02 }, 707 { "CONT_MSG_LOOP", 0x04, 0x04 }, 708 { "EXIT_MSG_LOOP", 0x08, 0x08 }, 709 { "MSGOUT_PHASEMIS", 0x10, 0x10 }, 710 { "SEND_REJ", 0x20, 0x20 }, 711 { "SEND_SENSE", 0x40, 0x40 }, 712 { "SEND_MSG", 0x80, 0x80 } 713 }; 714 715 int 716 ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap) 717 { 718 return (ahc_print_register(ARG_1_parse_table, 8, "ARG_1", 719 0x51, regvalue, cur_col, wrap)); 720 } 721 722 int 723 ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap) 724 { 725 return (ahc_print_register(NULL, 0, "ARG_2", 726 0x52, regvalue, cur_col, wrap)); 727 } 728 729 int 730 ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap) 731 { 732 return (ahc_print_register(NULL, 0, "LAST_MSG", 733 0x53, regvalue, cur_col, wrap)); 734 } 735 736 static ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 737 { "ENAUTOATNP", 0x02, 0x02 }, 738 { "ENAUTOATNI", 0x04, 0x04 }, 739 { "ENAUTOATNO", 0x08, 0x08 }, 740 { "ENRSELI", 0x10, 0x10 }, 741 { "ENSELI", 0x20, 0x20 }, 742 { "ENSELO", 0x40, 0x40 } 743 }; 744 745 int 746 ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap) 747 { 748 return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE", 749 0x54, regvalue, cur_col, wrap)); 750 } 751 752 static ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = { 753 { "HA_274_EXTENDED_TRANS",0x01, 0x01 } 754 }; 755 756 int 757 ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap) 758 { 759 return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL", 760 0x56, regvalue, cur_col, wrap)); 761 } 762 763 static ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 764 { "SCB_DMA", 0x01, 0x01 }, 765 { "TARGET_MSG_PENDING", 0x02, 0x02 } 766 }; 767 768 int 769 ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap) 770 { 771 return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2", 772 0x57, regvalue, cur_col, wrap)); 773 } 774 775 static ahc_reg_parse_entry_t SCSICONF_parse_table[] = { 776 { "ENSPCHK", 0x20, 0x20 }, 777 { "RESET_SCSI", 0x40, 0x40 }, 778 { "TERM_ENB", 0x80, 0x80 }, 779 { "HSCSIID", 0x07, 0x07 }, 780 { "HWSCSIID", 0x0f, 0x0f } 781 }; 782 783 int 784 ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap) 785 { 786 return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF", 787 0x5a, regvalue, cur_col, wrap)); 788 } 789 790 static ahc_reg_parse_entry_t INTDEF_parse_table[] = { 791 { "EDGE_TRIG", 0x80, 0x80 }, 792 { "VECTOR", 0x0f, 0x0f } 793 }; 794 795 int 796 ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap) 797 { 798 return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF", 799 0x5c, regvalue, cur_col, wrap)); 800 } 801 802 int 803 ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap) 804 { 805 return (ahc_print_register(NULL, 0, "HOSTCONF", 806 0x5d, regvalue, cur_col, wrap)); 807 } 808 809 static ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = { 810 { "CHANNEL_B_PRIMARY", 0x08, 0x08 }, 811 { "BIOSMODE", 0x30, 0x30 }, 812 { "BIOSDISABLED", 0x30, 0x30 } 813 }; 814 815 int 816 ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 817 { 818 return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL", 819 0x5f, regvalue, cur_col, wrap)); 820 } 821 822 static ahc_reg_parse_entry_t SEQCTL_parse_table[] = { 823 { "LOADRAM", 0x01, 0x01 }, 824 { "SEQRESET", 0x02, 0x02 }, 825 { "STEP", 0x04, 0x04 }, 826 { "BRKADRINTEN", 0x08, 0x08 }, 827 { "FASTMODE", 0x10, 0x10 }, 828 { "FAILDIS", 0x20, 0x20 }, 829 { "PAUSEDIS", 0x40, 0x40 }, 830 { "PERRORDIS", 0x80, 0x80 } 831 }; 832 833 int 834 ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 835 { 836 return (ahc_print_register(SEQCTL_parse_table, 8, "SEQCTL", 837 0x60, regvalue, cur_col, wrap)); 838 } 839 840 int 841 ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap) 842 { 843 return (ahc_print_register(NULL, 0, "SEQRAM", 844 0x61, regvalue, cur_col, wrap)); 845 } 846 847 int 848 ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 849 { 850 return (ahc_print_register(NULL, 0, "SEQADDR0", 851 0x62, regvalue, cur_col, wrap)); 852 } 853 854 static ahc_reg_parse_entry_t SEQADDR1_parse_table[] = { 855 { "SEQADDR1_MASK", 0x01, 0x01 } 856 }; 857 858 int 859 ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 860 { 861 return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1", 862 0x63, regvalue, cur_col, wrap)); 863 } 864 865 int 866 ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap) 867 { 868 return (ahc_print_register(NULL, 0, "ACCUM", 869 0x64, regvalue, cur_col, wrap)); 870 } 871 872 int 873 ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 874 { 875 return (ahc_print_register(NULL, 0, "SINDEX", 876 0x65, regvalue, cur_col, wrap)); 877 } 878 879 int 880 ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 881 { 882 return (ahc_print_register(NULL, 0, "DINDEX", 883 0x66, regvalue, cur_col, wrap)); 884 } 885 886 int 887 ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) 888 { 889 return (ahc_print_register(NULL, 0, "ALLONES", 890 0x69, regvalue, cur_col, wrap)); 891 } 892 893 int 894 ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap) 895 { 896 return (ahc_print_register(NULL, 0, "NONE", 897 0x6a, regvalue, cur_col, wrap)); 898 } 899 900 int 901 ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap) 902 { 903 return (ahc_print_register(NULL, 0, "ALLZEROS", 904 0x6a, regvalue, cur_col, wrap)); 905 } 906 907 static ahc_reg_parse_entry_t FLAGS_parse_table[] = { 908 { "CARRY", 0x01, 0x01 }, 909 { "ZERO", 0x02, 0x02 } 910 }; 911 912 int 913 ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 914 { 915 return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS", 916 0x6b, regvalue, cur_col, wrap)); 917 } 918 919 int 920 ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 921 { 922 return (ahc_print_register(NULL, 0, "SINDIR", 923 0x6c, regvalue, cur_col, wrap)); 924 } 925 926 int 927 ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 928 { 929 return (ahc_print_register(NULL, 0, "DINDIR", 930 0x6d, regvalue, cur_col, wrap)); 931 } 932 933 int 934 ahc_function1_print(u_int regvalue, u_int *cur_col, u_int wrap) 935 { 936 return (ahc_print_register(NULL, 0, "FUNCTION1", 937 0x6e, regvalue, cur_col, wrap)); 938 } 939 940 int 941 ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 942 { 943 return (ahc_print_register(NULL, 0, "STACK", 944 0x6f, regvalue, cur_col, wrap)); 945 } 946 947 int 948 ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap) 949 { 950 return (ahc_print_register(NULL, 0, "TARG_OFFSET", 951 0x70, regvalue, cur_col, wrap)); 952 } 953 954 int 955 ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 956 { 957 return (ahc_print_register(NULL, 0, "SRAM_BASE", 958 0x70, regvalue, cur_col, wrap)); 959 } 960 961 static ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = { 962 { "CIOPARCKEN", 0x01, 0x01 }, 963 { "USCBSIZE32", 0x02, 0x02 }, 964 { "RAMPS", 0x04, 0x04 }, 965 { "INTSCBRAMSEL", 0x08, 0x08 }, 966 { "EXTREQLCK", 0x10, 0x10 }, 967 { "MPARCKEN", 0x20, 0x20 }, 968 { "DPARCKEN", 0x40, 0x40 }, 969 { "CACHETHEN", 0x80, 0x80 } 970 }; 971 972 int 973 ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap) 974 { 975 return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0", 976 0x84, regvalue, cur_col, wrap)); 977 } 978 979 static ahc_reg_parse_entry_t BCTL_parse_table[] = { 980 { "ENABLE", 0x01, 0x01 }, 981 { "ACE", 0x08, 0x08 } 982 }; 983 984 int 985 ahc_bctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 986 { 987 return (ahc_print_register(BCTL_parse_table, 2, "BCTL", 988 0x84, regvalue, cur_col, wrap)); 989 } 990 991 static ahc_reg_parse_entry_t BUSTIME_parse_table[] = { 992 { "BON", 0x0f, 0x0f }, 993 { "BOFF", 0xf0, 0xf0 } 994 }; 995 996 int 997 ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap) 998 { 999 return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME", 1000 0x85, regvalue, cur_col, wrap)); 1001 } 1002 1003 static ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = { 1004 { "HADDLDSEL0", 0x01, 0x01 }, 1005 { "HADDLDSEL1", 0x02, 0x02 }, 1006 { "DSLATT", 0xfc, 0xfc } 1007 }; 1008 1009 int 1010 ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1011 { 1012 return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1", 1013 0x85, regvalue, cur_col, wrap)); 1014 } 1015 1016 static ahc_reg_parse_entry_t BUSSPD_parse_table[] = { 1017 { "STBON", 0x07, 0x07 }, 1018 { "STBOFF", 0x38, 0x38 }, 1019 { "DFTHRSH_75", 0x80, 0x80 }, 1020 { "DFTHRSH", 0xc0, 0xc0 }, 1021 { "DFTHRSH_100", 0xc0, 0xc0 } 1022 }; 1023 1024 int 1025 ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap) 1026 { 1027 return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD", 1028 0x86, regvalue, cur_col, wrap)); 1029 } 1030 1031 static ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 1032 { "SEQ_MAILBOX", 0x0f, 0x0f }, 1033 { "HOST_TQINPOS", 0x80, 0x80 }, 1034 { "HOST_MAILBOX", 0xf0, 0xf0 } 1035 }; 1036 1037 int 1038 ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) 1039 { 1040 return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX", 1041 0x86, regvalue, cur_col, wrap)); 1042 } 1043 1044 static ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = { 1045 { "DFTHRSH_100", 0xc0, 0xc0 } 1046 }; 1047 1048 int 1049 ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap) 1050 { 1051 return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS", 1052 0x86, regvalue, cur_col, wrap)); 1053 } 1054 1055 static ahc_reg_parse_entry_t HCNTRL_parse_table[] = { 1056 { "CHIPRST", 0x01, 0x01 }, 1057 { "CHIPRSTACK", 0x01, 0x01 }, 1058 { "INTEN", 0x02, 0x02 }, 1059 { "PAUSE", 0x04, 0x04 }, 1060 { "IRQMS", 0x08, 0x08 }, 1061 { "SWINT", 0x10, 0x10 }, 1062 { "POWRDN", 0x40, 0x40 } 1063 }; 1064 1065 int 1066 ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1067 { 1068 return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL", 1069 0x87, regvalue, cur_col, wrap)); 1070 } 1071 1072 int 1073 ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1074 { 1075 return (ahc_print_register(NULL, 0, "HADDR", 1076 0x88, regvalue, cur_col, wrap)); 1077 } 1078 1079 int 1080 ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1081 { 1082 return (ahc_print_register(NULL, 0, "HCNT", 1083 0x8c, regvalue, cur_col, wrap)); 1084 } 1085 1086 int 1087 ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1088 { 1089 return (ahc_print_register(NULL, 0, "SCBPTR", 1090 0x90, regvalue, cur_col, wrap)); 1091 } 1092 1093 static ahc_reg_parse_entry_t INTSTAT_parse_table[] = { 1094 { "SEQINT", 0x01, 0x01 }, 1095 { "CMDCMPLT", 0x02, 0x02 }, 1096 { "SCSIINT", 0x04, 0x04 }, 1097 { "BRKADRINT", 0x08, 0x08 }, 1098 { "BAD_PHASE", 0x01, 0x01 }, 1099 { "INT_PEND", 0x0f, 0x0f }, 1100 { "SEND_REJECT", 0x11, 0x11 }, 1101 { "PROTO_VIOLATION", 0x21, 0x21 }, 1102 { "NO_MATCH", 0x31, 0x31 }, 1103 { "IGN_WIDE_RES", 0x41, 0x41 }, 1104 { "PDATA_REINIT", 0x51, 0x51 }, 1105 { "HOST_MSG_LOOP", 0x61, 0x61 }, 1106 { "BAD_STATUS", 0x71, 0x71 }, 1107 { "PERR_DETECTED", 0x81, 0x81 }, 1108 { "DATA_OVERRUN", 0x91, 0x91 }, 1109 { "MKMSG_FAILED", 0xa1, 0xa1 }, 1110 { "MISSED_BUSFREE", 0xb1, 0xb1 }, 1111 { "SCB_MISMATCH", 0xc1, 0xc1 }, 1112 { "NO_FREE_SCB", 0xd1, 0xd1 }, 1113 { "OUT_OF_RANGE", 0xe1, 0xe1 }, 1114 { "SEQINT_MASK", 0xf1, 0xf1 } 1115 }; 1116 1117 int 1118 ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1119 { 1120 return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT", 1121 0x91, regvalue, cur_col, wrap)); 1122 } 1123 1124 static ahc_reg_parse_entry_t ERROR_parse_table[] = { 1125 { "ILLHADDR", 0x01, 0x01 }, 1126 { "ILLSADDR", 0x02, 0x02 }, 1127 { "ILLOPCODE", 0x04, 0x04 }, 1128 { "SQPARERR", 0x08, 0x08 }, 1129 { "DPARERR", 0x10, 0x10 }, 1130 { "MPARERR", 0x20, 0x20 }, 1131 { "PCIERRSTAT", 0x40, 0x40 }, 1132 { "CIOPARERR", 0x80, 0x80 } 1133 }; 1134 1135 int 1136 ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap) 1137 { 1138 return (ahc_print_register(ERROR_parse_table, 8, "ERROR", 1139 0x92, regvalue, cur_col, wrap)); 1140 } 1141 1142 static ahc_reg_parse_entry_t CLRINT_parse_table[] = { 1143 { "CLRSEQINT", 0x01, 0x01 }, 1144 { "CLRCMDINT", 0x02, 0x02 }, 1145 { "CLRSCSIINT", 0x04, 0x04 }, 1146 { "CLRBRKADRINT", 0x08, 0x08 }, 1147 { "CLRPARERR", 0x10, 0x10 } 1148 }; 1149 1150 int 1151 ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) 1152 { 1153 return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT", 1154 0x92, regvalue, cur_col, wrap)); 1155 } 1156 1157 static ahc_reg_parse_entry_t DFCNTRL_parse_table[] = { 1158 { "FIFORESET", 0x01, 0x01 }, 1159 { "FIFOFLUSH", 0x02, 0x02 }, 1160 { "DIRECTION", 0x04, 0x04 }, 1161 { "HDMAEN", 0x08, 0x08 }, 1162 { "HDMAENACK", 0x08, 0x08 }, 1163 { "SDMAEN", 0x10, 0x10 }, 1164 { "SDMAENACK", 0x10, 0x10 }, 1165 { "SCSIEN", 0x20, 0x20 }, 1166 { "WIDEODD", 0x40, 0x40 }, 1167 { "PRELOADEN", 0x80, 0x80 } 1168 }; 1169 1170 int 1171 ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1172 { 1173 return (ahc_print_register(DFCNTRL_parse_table, 10, "DFCNTRL", 1174 0x93, regvalue, cur_col, wrap)); 1175 } 1176 1177 static ahc_reg_parse_entry_t DFSTATUS_parse_table[] = { 1178 { "FIFOEMP", 0x01, 0x01 }, 1179 { "FIFOFULL", 0x02, 0x02 }, 1180 { "DFTHRESH", 0x04, 0x04 }, 1181 { "HDONE", 0x08, 0x08 }, 1182 { "MREQPEND", 0x10, 0x10 }, 1183 { "FIFOQWDEMP", 0x20, 0x20 }, 1184 { "DFCACHETH", 0x40, 0x40 }, 1185 { "PRELOAD_AVAIL", 0x80, 0x80 } 1186 }; 1187 1188 int 1189 ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap) 1190 { 1191 return (ahc_print_register(DFSTATUS_parse_table, 8, "DFSTATUS", 1192 0x94, regvalue, cur_col, wrap)); 1193 } 1194 1195 int 1196 ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1197 { 1198 return (ahc_print_register(NULL, 0, "DFWADDR", 1199 0x95, regvalue, cur_col, wrap)); 1200 } 1201 1202 int 1203 ahc_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1204 { 1205 return (ahc_print_register(NULL, 0, "DFRADDR", 1206 0x97, regvalue, cur_col, wrap)); 1207 } 1208 1209 int 1210 ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1211 { 1212 return (ahc_print_register(NULL, 0, "DFDAT", 1213 0x99, regvalue, cur_col, wrap)); 1214 } 1215 1216 static ahc_reg_parse_entry_t SCBCNT_parse_table[] = { 1217 { "SCBAUTO", 0x80, 0x80 }, 1218 { "SCBCNT_MASK", 0x1f, 0x1f } 1219 }; 1220 1221 int 1222 ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1223 { 1224 return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT", 1225 0x9a, regvalue, cur_col, wrap)); 1226 } 1227 1228 int 1229 ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1230 { 1231 return (ahc_print_register(NULL, 0, "QINFIFO", 1232 0x9b, regvalue, cur_col, wrap)); 1233 } 1234 1235 int 1236 ahc_qincnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1237 { 1238 return (ahc_print_register(NULL, 0, "QINCNT", 1239 0x9c, regvalue, cur_col, wrap)); 1240 } 1241 1242 static ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = { 1243 { "TARGCRCCNTEN", 0x04, 0x04 }, 1244 { "TARGCRCENDEN", 0x08, 0x08 }, 1245 { "CRCREQCHKEN", 0x10, 0x10 }, 1246 { "CRCENDCHKEN", 0x20, 0x20 }, 1247 { "CRCVALCHKEN", 0x40, 0x40 }, 1248 { "CRCONSEEN", 0x80, 0x80 } 1249 }; 1250 1251 int 1252 ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1253 { 1254 return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1", 1255 0x9d, regvalue, cur_col, wrap)); 1256 } 1257 1258 int 1259 ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1260 { 1261 return (ahc_print_register(NULL, 0, "QOUTFIFO", 1262 0x9d, regvalue, cur_col, wrap)); 1263 } 1264 1265 int 1266 ahc_qoutcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1267 { 1268 return (ahc_print_register(NULL, 0, "QOUTCNT", 1269 0x9e, regvalue, cur_col, wrap)); 1270 } 1271 1272 static ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = { 1273 { "DATA_OUT_PHASE", 0x01, 0x01 }, 1274 { "DATA_IN_PHASE", 0x02, 0x02 }, 1275 { "MSG_OUT_PHASE", 0x04, 0x04 }, 1276 { "MSG_IN_PHASE", 0x08, 0x08 }, 1277 { "COMMAND_PHASE", 0x10, 0x10 }, 1278 { "STATUS_PHASE", 0x20, 0x20 }, 1279 { "DATA_PHASE_MASK", 0x03, 0x03 } 1280 }; 1281 1282 int 1283 ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 1284 { 1285 return (ahc_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE", 1286 0x9e, regvalue, cur_col, wrap)); 1287 } 1288 1289 static ahc_reg_parse_entry_t SFUNCT_parse_table[] = { 1290 { "ALT_MODE", 0x80, 0x80 } 1291 }; 1292 1293 int 1294 ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap) 1295 { 1296 return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT", 1297 0x9f, regvalue, cur_col, wrap)); 1298 } 1299 1300 int 1301 ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 1302 { 1303 return (ahc_print_register(NULL, 0, "SCB_BASE", 1304 0xa0, regvalue, cur_col, wrap)); 1305 } 1306 1307 int 1308 ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1309 { 1310 return (ahc_print_register(NULL, 0, "SCB_CDB_PTR", 1311 0xa0, regvalue, cur_col, wrap)); 1312 } 1313 1314 int 1315 ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1316 { 1317 return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 1318 0xa4, regvalue, cur_col, wrap)); 1319 } 1320 1321 int 1322 ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap) 1323 { 1324 return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 1325 0xa8, regvalue, cur_col, wrap)); 1326 } 1327 1328 int 1329 ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap) 1330 { 1331 return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 1332 0xa9, regvalue, cur_col, wrap)); 1333 } 1334 1335 int 1336 ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap) 1337 { 1338 return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 1339 0xaa, regvalue, cur_col, wrap)); 1340 } 1341 1342 int 1343 ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1344 { 1345 return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 1346 0xab, regvalue, cur_col, wrap)); 1347 } 1348 1349 int 1350 ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1351 { 1352 return (ahc_print_register(NULL, 0, "SCB_DATAPTR", 1353 0xac, regvalue, cur_col, wrap)); 1354 } 1355 1356 static ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 1357 { "SG_LAST_SEG", 0x80, 0x80 }, 1358 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f } 1359 }; 1360 1361 int 1362 ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1363 { 1364 return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT", 1365 0xb0, regvalue, cur_col, wrap)); 1366 } 1367 1368 static ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 1369 { "SG_LIST_NULL", 0x01, 0x01 }, 1370 { "SG_FULL_RESID", 0x02, 0x02 }, 1371 { "SG_RESID_VALID", 0x04, 0x04 } 1372 }; 1373 1374 int 1375 ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1376 { 1377 return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR", 1378 0xb4, regvalue, cur_col, wrap)); 1379 } 1380 1381 static ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 1382 { "DISCONNECTED", 0x04, 0x04 }, 1383 { "ULTRAENB", 0x08, 0x08 }, 1384 { "MK_MESSAGE", 0x10, 0x10 }, 1385 { "TAG_ENB", 0x20, 0x20 }, 1386 { "DISCENB", 0x40, 0x40 }, 1387 { "TARGET_SCB", 0x80, 0x80 }, 1388 { "STATUS_RCVD", 0x80, 0x80 }, 1389 { "SCB_TAG_TYPE", 0x03, 0x03 } 1390 }; 1391 1392 int 1393 ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap) 1394 { 1395 return (ahc_print_register(SCB_CONTROL_parse_table, 8, "SCB_CONTROL", 1396 0xb8, regvalue, cur_col, wrap)); 1397 } 1398 1399 static ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 1400 { "TWIN_CHNLB", 0x80, 0x80 }, 1401 { "OID", 0x0f, 0x0f }, 1402 { "TWIN_TID", 0x70, 0x70 }, 1403 { "TID", 0xf0, 0xf0 } 1404 }; 1405 1406 int 1407 ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1408 { 1409 return (ahc_print_register(SCB_SCSIID_parse_table, 4, "SCB_SCSIID", 1410 0xb9, regvalue, cur_col, wrap)); 1411 } 1412 1413 static ahc_reg_parse_entry_t SCB_LUN_parse_table[] = { 1414 { "SCB_XFERLEN_ODD", 0x80, 0x80 }, 1415 { "LID", 0x3f, 0x3f } 1416 }; 1417 1418 int 1419 ahc_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 1420 { 1421 return (ahc_print_register(SCB_LUN_parse_table, 2, "SCB_LUN", 1422 0xba, regvalue, cur_col, wrap)); 1423 } 1424 1425 int 1426 ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1427 { 1428 return (ahc_print_register(NULL, 0, "SCB_TAG", 1429 0xbb, regvalue, cur_col, wrap)); 1430 } 1431 1432 int 1433 ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap) 1434 { 1435 return (ahc_print_register(NULL, 0, "SCB_CDB_LEN", 1436 0xbc, regvalue, cur_col, wrap)); 1437 } 1438 1439 int 1440 ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap) 1441 { 1442 return (ahc_print_register(NULL, 0, "SCB_SCSIRATE", 1443 0xbd, regvalue, cur_col, wrap)); 1444 } 1445 1446 int 1447 ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap) 1448 { 1449 return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 1450 0xbe, regvalue, cur_col, wrap)); 1451 } 1452 1453 int 1454 ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap) 1455 { 1456 return (ahc_print_register(NULL, 0, "SCB_NEXT", 1457 0xbf, regvalue, cur_col, wrap)); 1458 } 1459 1460 int 1461 ahc_scb_64_spare_print(u_int regvalue, u_int *cur_col, u_int wrap) 1462 { 1463 return (ahc_print_register(NULL, 0, "SCB_64_SPARE", 1464 0xc0, regvalue, cur_col, wrap)); 1465 } 1466 1467 static ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = { 1468 { "DO_2840", 0x01, 0x01 }, 1469 { "CK_2840", 0x02, 0x02 }, 1470 { "CS_2840", 0x04, 0x04 } 1471 }; 1472 1473 int 1474 ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap) 1475 { 1476 return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840", 1477 0xc0, regvalue, cur_col, wrap)); 1478 } 1479 1480 static ahc_reg_parse_entry_t STATUS_2840_parse_table[] = { 1481 { "DI_2840", 0x01, 0x01 }, 1482 { "EEPROM_TF", 0x80, 0x80 }, 1483 { "ADSEL", 0x1e, 0x1e }, 1484 { "BIOS_SEL", 0x60, 0x60 } 1485 }; 1486 1487 int 1488 ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap) 1489 { 1490 return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840", 1491 0xc1, regvalue, cur_col, wrap)); 1492 } 1493 1494 int 1495 ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1496 { 1497 return (ahc_print_register(NULL, 0, "SCB_64_BTT", 1498 0xd0, regvalue, cur_col, wrap)); 1499 } 1500 1501 int 1502 ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1503 { 1504 return (ahc_print_register(NULL, 0, "CCHADDR", 1505 0xe0, regvalue, cur_col, wrap)); 1506 } 1507 1508 int 1509 ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1510 { 1511 return (ahc_print_register(NULL, 0, "CCHCNT", 1512 0xe8, regvalue, cur_col, wrap)); 1513 } 1514 1515 int 1516 ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap) 1517 { 1518 return (ahc_print_register(NULL, 0, "CCSGRAM", 1519 0xe9, regvalue, cur_col, wrap)); 1520 } 1521 1522 int 1523 ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1524 { 1525 return (ahc_print_register(NULL, 0, "CCSGADDR", 1526 0xea, regvalue, cur_col, wrap)); 1527 } 1528 1529 static ahc_reg_parse_entry_t CCSGCTL_parse_table[] = { 1530 { "CCSGRESET", 0x01, 0x01 }, 1531 { "SG_FETCH_NEEDED", 0x02, 0x02 }, 1532 { "CCSGEN", 0x08, 0x08 }, 1533 { "CCSGDONE", 0x80, 0x80 } 1534 }; 1535 1536 int 1537 ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1538 { 1539 return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL", 1540 0xeb, regvalue, cur_col, wrap)); 1541 } 1542 1543 int 1544 ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) 1545 { 1546 return (ahc_print_register(NULL, 0, "CCSCBRAM", 1547 0xec, regvalue, cur_col, wrap)); 1548 } 1549 1550 int 1551 ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1552 { 1553 return (ahc_print_register(NULL, 0, "CCSCBADDR", 1554 0xed, regvalue, cur_col, wrap)); 1555 } 1556 1557 static ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = { 1558 { "CCSCBRESET", 0x01, 0x01 }, 1559 { "CCSCBDIR", 0x04, 0x04 }, 1560 { "CCSCBEN", 0x08, 0x08 }, 1561 { "CCARREN", 0x10, 0x10 }, 1562 { "ARRDONE", 0x40, 0x40 }, 1563 { "CCSCBDONE", 0x80, 0x80 } 1564 }; 1565 1566 int 1567 ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1568 { 1569 return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL", 1570 0xee, regvalue, cur_col, wrap)); 1571 } 1572 1573 int 1574 ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1575 { 1576 return (ahc_print_register(NULL, 0, "CCSCBCNT", 1577 0xef, regvalue, cur_col, wrap)); 1578 } 1579 1580 int 1581 ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1582 { 1583 return (ahc_print_register(NULL, 0, "SCBBADDR", 1584 0xf0, regvalue, cur_col, wrap)); 1585 } 1586 1587 int 1588 ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1589 { 1590 return (ahc_print_register(NULL, 0, "CCSCBPTR", 1591 0xf1, regvalue, cur_col, wrap)); 1592 } 1593 1594 int 1595 ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 1596 { 1597 return (ahc_print_register(NULL, 0, "HNSCB_QOFF", 1598 0xf4, regvalue, cur_col, wrap)); 1599 } 1600 1601 int 1602 ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 1603 { 1604 return (ahc_print_register(NULL, 0, "SNSCB_QOFF", 1605 0xf6, regvalue, cur_col, wrap)); 1606 } 1607 1608 int 1609 ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 1610 { 1611 return (ahc_print_register(NULL, 0, "SDSCB_QOFF", 1612 0xf8, regvalue, cur_col, wrap)); 1613 } 1614 1615 static ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 1616 { "SDSCB_ROLLOVER", 0x10, 0x10 }, 1617 { "SNSCB_ROLLOVER", 0x20, 0x20 }, 1618 { "SCB_AVAIL", 0x40, 0x40 }, 1619 { "SCB_QSIZE_256", 0x06, 0x06 }, 1620 { "SCB_QSIZE", 0x07, 0x07 } 1621 }; 1622 1623 int 1624 ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap) 1625 { 1626 return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA", 1627 0xfa, regvalue, cur_col, wrap)); 1628 } 1629 1630 static ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = { 1631 { "RD_DFTHRSH_MIN", 0x00, 0x00 }, 1632 { "WR_DFTHRSH_MIN", 0x00, 0x00 }, 1633 { "RD_DFTHRSH_25", 0x01, 0x01 }, 1634 { "RD_DFTHRSH_50", 0x02, 0x02 }, 1635 { "RD_DFTHRSH_63", 0x03, 0x03 }, 1636 { "RD_DFTHRSH_75", 0x04, 0x04 }, 1637 { "RD_DFTHRSH_85", 0x05, 0x05 }, 1638 { "RD_DFTHRSH_90", 0x06, 0x06 }, 1639 { "RD_DFTHRSH", 0x07, 0x07 }, 1640 { "RD_DFTHRSH_MAX", 0x07, 0x07 }, 1641 { "WR_DFTHRSH_25", 0x10, 0x10 }, 1642 { "WR_DFTHRSH_50", 0x20, 0x20 }, 1643 { "WR_DFTHRSH_63", 0x30, 0x30 }, 1644 { "WR_DFTHRSH_75", 0x40, 0x40 }, 1645 { "WR_DFTHRSH_85", 0x50, 0x50 }, 1646 { "WR_DFTHRSH_90", 0x60, 0x60 }, 1647 { "WR_DFTHRSH", 0x70, 0x70 }, 1648 { "WR_DFTHRSH_MAX", 0x70, 0x70 } 1649 }; 1650 1651 int 1652 ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap) 1653 { 1654 return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH", 1655 0xfb, regvalue, cur_col, wrap)); 1656 } 1657 1658 static ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 1659 { "LAST_SEG_DONE", 0x01, 0x01 }, 1660 { "LAST_SEG", 0x02, 0x02 }, 1661 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1662 }; 1663 1664 int 1665 ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap) 1666 { 1667 return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW", 1668 0xfc, regvalue, cur_col, wrap)); 1669 } 1670 1671 static ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { 1672 { "LAST_SEG_DONE", 0x01, 0x01 }, 1673 { "LAST_SEG", 0x02, 0x02 }, 1674 { "SG_ADDR_MASK", 0xf8, 0xf8 } 1675 }; 1676 1677 int 1678 ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap) 1679 { 1680 return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE", 1681 0xfc, regvalue, cur_col, wrap)); 1682 } 1683