1 /* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: aic7xxx_reg.h,v 1.11 1996/05/21 18:32:23 gibbs Exp $ 32 */ 33 34 /* 35 * This header is shared by the sequencer code and the kernel level driver. 36 * 37 * All page numbers refer to the Adaptec AIC-7770 Data Book availible from 38 * Adaptec's Technical Documents Department 1-800-934-2766 39 */ 40 41 /* 42 * SCSI Sequence Control (p. 3-11). 43 * Each bit, when set starts a specific SCSI sequence on the bus 44 */ 45 #define SCSISEQ 0x000 46 #define TEMODEO 0x80 47 #define ENSELO 0x40 48 #define ENSELI 0x20 49 #define ENRSELI 0x10 50 #define ENAUTOATNO 0x08 51 #define ENAUTOATNI 0x04 52 #define ENAUTOATNP 0x02 53 #define SCSIRSTO 0x01 54 55 /* 56 * SCSI Transfer Control 0 Register (pp. 3-13). 57 * Controls the SCSI module data path. 58 */ 59 #define SXFRCTL0 0x001 60 #define DFON 0x80 61 #define DFPEXP 0x40 62 #define ULTRAEN 0x20 63 #define CLRSTCNT 0x10 64 #define SPIOEN 0x08 65 #define SCAMEN 0x04 66 #define CLRCHN 0x02 67 /* UNUSED 0x01 */ 68 69 /* 70 * SCSI Transfer Control 1 Register (pp. 3-14,15). 71 * Controls the SCSI module data path. 72 */ 73 #define SXFRCTL1 0x002 74 #define BITBUCKET 0x80 75 #define SWRAPEN 0x40 76 #define ENSPCHK 0x20 77 #define STIMESEL 0x18 78 #define ENSTIMER 0x04 79 #define ACTNEGEN 0x02 80 #define STPWEN 0x01 /* Powered Termination */ 81 82 /* 83 * SCSI Control Signal Read Register (p. 3-15). 84 * Reads the actual state of the SCSI bus pins 85 */ 86 #define SCSISIGI 0x003 87 #define CDI 0x80 88 #define IOI 0x40 89 #define MSGI 0x20 90 #define ATNI 0x10 91 #define SELI 0x08 92 #define BSYI 0x04 93 #define REQI 0x02 94 #define ACKI 0x01 95 96 /* 97 * Possible phases in SCSISIGI 98 */ 99 #define PHASE_MASK 0xe0 100 #define P_DATAOUT 0x00 101 #define P_DATAIN 0x40 102 #define P_COMMAND 0x80 103 #define P_MESGOUT 0xa0 104 #define P_STATUS 0xc0 105 #define P_MESGIN 0xe0 106 /* 107 * SCSI Contol Signal Write Register (p. 3-16). 108 * Writing to this register modifies the control signals on the bus. Only 109 * those signals that are allowed in the current mode (Initiator/Target) are 110 * asserted. 111 */ 112 #define SCSISIGO 0x003 113 #define CDO 0x80 114 #define IOO 0x40 115 #define MSGO 0x20 116 #define ATNO 0x10 117 #define SELO 0x08 118 #define BSYO 0x04 119 #define REQO 0x02 120 #define ACKO 0x01 121 122 /* 123 * SCSI Rate Control (p. 3-17). 124 * Contents of this register determine the Synchronous SCSI data transfer 125 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 126 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 127 * greater than 0 enables synchronous transfers. 128 */ 129 #define SCSIRATE 0x004 130 #define WIDEXFER 0x80 /* Wide transfer control */ 131 #define SXFR 0x70 /* Sync transfer rate */ 132 #define SOFS 0x0f /* Sync offset */ 133 134 /* 135 * SCSI ID (p. 3-18). 136 * Contains the ID of the board and the current target on the 137 * selected channel. 138 */ 139 #define SCSIID 0x005 140 #define TID 0xf0 /* Target ID mask */ 141 #define OID 0x0f /* Our ID mask */ 142 143 /* 144 * SCSI Latched Data (p. 3-19). 145 * Read/Write latchs used to transfer data on the SCSI bus during 146 * Automatic or Manual PIO mode. SCSIDATH can be used for the 147 * upper byte of a 16bit wide asyncronouse data phase transfer. 148 */ 149 #define SCSIDATL 0x006 150 #define SCSIDATH 0x007 151 152 /* 153 * SCSI Transfer Count (pp. 3-19,20) 154 * These registers count down the number of bytes transfered 155 * across the SCSI bus. The counter is decremented only once 156 * the data has been safely transfered. SDONE in SSTAT0 is 157 * set when STCNT goes to 0 158 */ 159 #define STCNT 0x008 160 #define STCNT0 0x008 161 #define STCNT1 0x009 162 #define STCNT2 0x00a 163 164 /* 165 * Clear SCSI Interrupt 0 (p. 3-20) 166 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 167 */ 168 #define CLRSINT0 0x00b 169 #define CLRSELDO 0x40 170 #define CLRSELDI 0x20 171 #define CLRSELINGO 0x10 172 #define CLRSWRAP 0x08 173 /* UNUSED 0x04 */ 174 #define CLRSPIORDY 0x02 175 /* UNUSED 0x01 */ 176 177 /* 178 * SCSI Status 0 (p. 3-21) 179 * Contains one set of SCSI Interrupt codes 180 * These are most likely of interest to the sequencer 181 */ 182 #define SSTAT0 0x00b 183 #define TARGET 0x80 /* Board acting as target */ 184 #define SELDO 0x40 /* Selection Done */ 185 #define SELDI 0x20 /* Board has been selected */ 186 #define SELINGO 0x10 /* Selection In Progress */ 187 #define SWRAP 0x08 /* 24bit counter wrap */ 188 #define SDONE 0x04 /* STCNT = 0x000000 */ 189 #define SPIORDY 0x02 /* SCSI PIO Ready */ 190 #define DMADONE 0x01 /* DMA transfer completed */ 191 192 /* 193 * Clear SCSI Interrupt 1 (p. 3-23) 194 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 195 */ 196 #define CLRSINT1 0x00c 197 #define CLRSELTIMEO 0x80 198 #define CLRATNO 0x40 199 #define CLRSCSIRSTI 0x20 200 /* UNUSED 0x10 */ 201 #define CLRBUSFREE 0x08 202 #define CLRSCSIPERR 0x04 203 #define CLRPHASECHG 0x02 204 #define CLRREQINIT 0x01 205 206 /* 207 * SCSI Status 1 (p. 3-24) 208 */ 209 #define SSTAT1 0x00c 210 #define SELTO 0x80 211 #define ATNTARG 0x40 212 #define SCSIRSTI 0x20 213 #define PHASEMIS 0x10 214 #define BUSFREE 0x08 215 #define SCSIPERR 0x04 216 #define PHASECHG 0x02 217 #define REQINIT 0x01 218 219 /* 220 * SCSI Interrupt Mode 1 (pp. 3-28,29) 221 * Setting any bit will enable the corresponding function 222 * in SIMODE1 to interrupt via the IRQ pin. 223 */ 224 #define SIMODE1 0x011 225 #define ENSELTIMO 0x80 226 #define ENATNTARG 0x40 227 #define ENSCSIRST 0x20 228 #define ENPHASEMIS 0x10 229 #define ENBUSFREE 0x08 230 #define ENSCSIPERR 0x04 231 #define ENPHASECHG 0x02 232 #define ENREQINIT 0x01 233 234 /* 235 * SCSI Data Bus (High) (p. 3-29) 236 * This register reads data on the SCSI Data bus directly. 237 */ 238 #define SCSIBUSL 0x012 239 #define SCSIBUSH 0x013 240 241 /* 242 * SCSI/Host Address (p. 3-30) 243 * These registers hold the host address for the byte about to be 244 * transfered on the SCSI bus. They are counted up in the same 245 * manner as STCNT is counted down. SHADDR should always be used 246 * to determine the address of the last byte transfered since HADDR 247 * can be squewed by write ahead. 248 */ 249 #define SHADDR 0x014 250 #define SHADDR0 0x014 251 #define SHADDR1 0x015 252 #define SHADDR2 0x016 253 #define SHADDR3 0x017 254 255 /* 256 * Selection/Reselection ID (p. 3-31) 257 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 258 * device did not set its own ID. 259 */ 260 #define SELID 0x019 261 #define SELID_MASK 0xf0 262 #define ONEBIT 0x08 263 /* UNUSED 0x07 */ 264 265 /* 266 * SCSI Block Control (p. 3-32) 267 * Controls Bus type and channel selection. In a twin channel configuration 268 * addresses 0x00-0x1e are gated to the appropriate channel based on this 269 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 270 * on a wide bus. 271 */ 272 #define SBLKCTL 0x01f 273 #define DIAGLEDEN 0x80 /* Aic78X0 only */ 274 #define DIAGLEDON 0x40 /* Aic78X0 only */ 275 #define AUTOFLUSHDIS 0x20 276 /* UNUSED 0x10 */ 277 #define SELBUS_MASK 0x0a 278 #define SELBUSB 0x08 279 /* UNUSED 0x04 */ 280 #define SELWIDE 0x02 281 /* UNUSED 0x01 */ 282 #define SELNARROW 0x00 283 284 /* 285 * Sequencer Control (p. 3-33) 286 * Error detection mode and speed configuration 287 */ 288 #define SEQCTL 0x060 289 #define PERRORDIS 0x80 290 #define PAUSEDIS 0x40 291 #define FAILDIS 0x20 292 #define FASTMODE 0x10 293 #define BRKADRINTEN 0x08 294 #define STEP 0x04 295 #define SEQRESET 0x02 296 #define LOADRAM 0x01 297 298 /* 299 * Sequencer RAM Data (p. 3-34) 300 * Single byte window into the Scratch Ram area starting at the address 301 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 302 * four bytes in sucessesion. The SEQADDRs will increment after the most 303 * significant byte is written 304 */ 305 #define SEQRAM 0x061 306 307 /* 308 * Sequencer Address Registers (p. 3-35) 309 * Only the first bit of SEQADDR1 holds addressing information 310 */ 311 #define SEQADDR0 0x062 312 #define SEQADDR1 0x063 313 #define SEQADDR1_MASK 0x01 314 315 /* 316 * Accumulator 317 * We cheat by passing arguments in the Accumulator up to the kernel driver 318 */ 319 #define ACCUM 0x064 320 321 #define SINDEX 0x065 322 #define DINDEX 0x066 323 #define ALLZEROS 0x06a 324 #define NONE 0x06a 325 #define SINDIR 0x06c 326 #define DINDIR 0x06d 327 #define FUNCTION1 0x06e 328 329 /* 330 * Host Address (p. 3-48) 331 * This register contains the address of the byte about 332 * to be transfered across the host bus. 333 */ 334 #define HADDR 0x088 335 #define HADDR0 0x088 336 #define HADDR1 0x089 337 #define HADDR2 0x08a 338 #define HADDR3 0x08b 339 340 #define HCNT 0x08c 341 #define HCNT0 0x08c 342 #define HCNT1 0x08d 343 #define HCNT2 0x08e 344 /* 345 * SCB Pointer (p. 3-49) 346 * Gate one of the four SCBs into the SCBARRAY window. 347 */ 348 #define SCBPTR 0x090 349 350 /* 351 * Board Control (p. 3-43) 352 */ 353 #define BCTL 0x084 354 /* RSVD 0xf0 */ 355 #define ACE 0x08 /* Support for external processors */ 356 /* RSVD 0x06 */ 357 #define ENABLE 0x01 358 359 /* 360 * On the aic78X0 chips, Board Control is replaced by the DSCommand 361 * register (p. 4-64) 362 */ 363 #define DSCOMMAND 0x084 364 #define CACHETHEN 0x80 /* Cache Threshold enable */ 365 #define DPARCKEN 0x40 /* Data Parity Check Enable */ 366 #define MPARCKEN 0x20 /* Memory Parity Check Enable */ 367 #define EXTREQLCK 0x10 /* External Request Lock */ 368 369 /* 370 * Bus On/Off Time (p. 3-44) 371 */ 372 #define BUSTIME 0x085 373 #define BOFF 0xf0 374 #define BON 0x0f 375 376 /* 377 * Bus Speed (p. 3-45) 378 */ 379 #define BUSSPD 0x086 380 #define DFTHRSH 0xc0 381 #define STBOFF 0x38 382 #define STBON 0x07 383 #define DFTHRSH_100 0xc0 384 385 /* 386 * Host Control (p. 3-47) R/W 387 * Overal host control of the device. 388 */ 389 #define HCNTRL 0x087 390 /* UNUSED 0x80 */ 391 #define POWRDN 0x40 392 /* UNUSED 0x20 */ 393 #define SWINT 0x10 394 #define IRQMS 0x08 395 #define PAUSE 0x04 396 #define INTEN 0x02 397 #define CHIPRST 0x01 398 #define CHIPRSTACK 0x01 399 400 /* 401 * Interrupt Status (p. 3-50) 402 * Status for system interrupts 403 */ 404 #define INTSTAT 0x091 405 #define SEQINT_MASK 0xf1 /* SEQINT Status Codes */ 406 #define BAD_PHASE 0x01 /* unknown scsi bus phase */ 407 #define SEND_REJECT 0x11 /* sending a message reject */ 408 #define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/ 409 #define NO_MATCH 0x31 /* no cmd match for reconnect */ 410 #define SDTR_MSG 0x41 /* SDTR message received */ 411 #define WDTR_MSG 0x51 /* WDTR message received */ 412 #define REJECT_MSG 0x61 /* Reject message received */ 413 #define BAD_STATUS 0x71 /* Bad status from target */ 414 #define RESIDUAL 0x81 /* Residual byte count != 0 */ 415 #define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */ 416 #define AWAITING_MSG 0xa1 /* 417 * Kernel requested to specify 418 * a message to this target 419 * (command was null), so tell 420 * it that it can fill the 421 * message buffer. 422 */ 423 #define IMMEDDONE 0xb1 /* 424 * An immediate command has 425 * completed 426 */ 427 #define MSG_BUFFER_BUSY 0xc1 /* 428 * Sequencer wants to use the 429 * message buffer, but it 430 * already contains a message 431 */ 432 #define MSGIN_PHASEMIS 0xd1 /* 433 * Target changed phase on us 434 * when we were expecting 435 * another msgin byte. 436 */ 437 #define DATA_OVERRUN 0xe1 /* 438 * Target attempted to write 439 * beyond the bounds of its 440 * command. 441 */ 442 #define BRKADRINT 0x08 443 #define SCSIINT 0x04 444 #define CMDCMPLT 0x02 445 #define SEQINT 0x01 446 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 447 448 /* 449 * Hard Error (p. 3-53) 450 * Reporting of catastrophic errors. You usually cannot recover from 451 * these without a full board reset. 452 */ 453 #define ERROR 0x092 454 /* UNUSED 0xf0 */ 455 #define PARERR 0x08 456 #define ILLOPCODE 0x04 457 #define ILLSADDR 0x02 458 #define ILLHADDR 0x01 459 460 /* 461 * Clear Interrupt Status (p. 3-52) 462 */ 463 #define CLRINT 0x092 464 #define CLRBRKADRINT 0x08 465 #define CLRSCSIINT 0x04 466 #define CLRCMDINT 0x02 467 #define CLRSEQINT 0x01 468 469 #define DFCNTRL 0x093 470 #define WIDEODD 0x40 471 #define SCSIEN 0x20 472 #define SDMAEN 0x10 473 #define SDMAENACK 0x10 474 #define HDMAEN 0x08 475 #define HDMAENACK 0x08 476 #define DIRECTION 0x04 477 #define FIFOFLUSH 0x02 478 #define FIFORESET 0x01 479 480 #define DFSTATUS 0x094 481 #define HDONE 0x08 482 #define FIFOEMP 0x01 483 484 #define DFDAT 0x099 485 486 /* 487 * SCB Auto Increment (p. 3-59) 488 * Byte offset into the SCB Array and an optional bit to allow auto 489 * incrementing of the address during download and upload operations 490 */ 491 #define SCBCNT 0x09a 492 #define SCBAUTO 0x80 493 #define SCBCNT_MASK 0x1f 494 495 /* 496 * Queue In FIFO (p. 3-60) 497 * Input queue for queued SCBs (commands that the seqencer has yet to start) 498 */ 499 #define QINFIFO 0x09b 500 501 /* 502 * Queue In Count (p. 3-60) 503 * Number of queued SCBs 504 */ 505 #define QINCNT 0x09c 506 507 /* 508 * Queue Out FIFO (p. 3-61) 509 * Queue of SCBs that have completed and await the host 510 */ 511 #define QOUTFIFO 0x09d 512 513 /* 514 * Queue Out Count (p. 3-61) 515 * Number of queued SCBs in the Out FIFO 516 */ 517 #define QOUTCNT 0x09e 518 519 /* 520 * SCB Definition (p. 5-4) 521 * The two reserved bytes at SCBARRAY+1[23] are expected to be set to 522 * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate 523 * whether or not to DMA an SCB from host ram. This flag prevents the 524 * "re-fetching" of transactions that are requed because the target is 525 * busy with another command. We also use bits 6 & 7 to indicate whether 526 * or not to initiate SDTR or WDTR repectively when starting this command. 527 */ 528 #define SCBARRAY 0x0a0 529 #define SCB_CONTROL 0x0a0 530 #define NEEDWDTR 0x80 531 #define DISCENB 0x40 532 #define TAG_ENB 0x20 533 #define NEEDSDTR 0x10 534 #define DISCONNECTED 0x04 535 #define SCB_TAG_TYPE 0x03 536 #define SCB_TCL 0x0a1 537 #define SCB_TARGET_STATUS 0x0a2 538 #define SCB_SGCOUNT 0x0a3 539 #define SCB_SGPTR 0x0a4 540 #define SCB_SGPTR0 0x0a4 541 #define SCB_SGPTR1 0x0a5 542 #define SCB_SGPTR2 0x0a6 543 #define SCB_SGPTR3 0x0a7 544 #define SCB_RESID_SGCNT 0x0a8 545 #define SCB_RESID_DCNT 0x0a9 546 #define SCB_RESID_DCNT0 0x0a9 547 #define SCB_RESID_DCNT1 0x0aa 548 #define SCB_RESID_DCNT2 0x0ab 549 #define SCB_DATAPTR 0x0ac 550 #define SCB_DATAPTR0 0x0ac 551 #define SCB_DATAPTR1 0x0ad 552 #define SCB_DATAPTR2 0x0ae 553 #define SCB_DATAPTR3 0x0af 554 #define SCB_DATACNT 0x0b0 555 #define SCB_DATACNT0 0x0b0 556 #define SCB_DATACNT1 0x0b1 557 #define SCB_DATACNT2 0x0b2 558 /* UNUSED - QUAD PADDING 0x0b3 */ 559 #define SCB_CMDPTR 0x0b4 560 #define SCB_CMDPTR0 0x0b4 561 #define SCB_CMDPTR1 0x0b5 562 #define SCB_CMDPTR2 0x0b6 563 #define SCB_CMDPTR3 0x0b7 564 #define SCB_CMDLEN 0x0b8 565 #define SCB_TAG 0x0b9 566 #define SCB_NEXT 0x0ba 567 #define SCB_PREV 0x0bb 568 569 #ifdef __linux__ 570 #define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */ 571 #else 572 #define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 573 #endif 574 575 /* --------------------- AHA-2840-only definitions -------------------- */ 576 577 #define SEECTL_2840 0x0c0 578 /* UNUSED 0xf8 */ 579 #define CS_2840 0x04 580 #define CK_2840 0x02 581 #define DO_2840 0x01 582 583 #define STATUS_2840 0x0c1 584 #define EEPROM_TF 0x80 585 #define BIOS_SEL 0x60 586 #define ADSEL 0x1e 587 #define DI_2840 0x01 588 589 /* --------------------- AIC-7870-only definitions -------------------- */ 590 591 #define DSPCISTATUS 0x086 592 593 /* 594 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 595 * Controls the reading and writing of an external serial 1-bit 596 * EEPROM Device. In order to access the serial EEPROM, you must 597 * first set the SEEMS bit that generates a request to the memory 598 * port for access to the serial EEPROM device. When the memory 599 * port is not busy servicing another request, it reconfigures 600 * to allow access to the serial EEPROM. When this happens, SEERDY 601 * gets set high to verify that the memory port access has been 602 * granted. 603 * 604 * After successful arbitration for the memory port, the SEECS bit of 605 * the SEECTL register is connected to the chip select. The SEECK, 606 * SEEDO, and SEEDI are connected to the clock, data out, and data in 607 * lines respectively. The SEERDY bit of SEECTL is useful in that it 608 * gives us an 800 nsec timer. After a write to the SEECTL register, 609 * the SEERDY goes high 800 nsec later. The one exception to this is 610 * when we first request access to the memory port. The SEERDY goes 611 * high to signify that access has been granted and, for this case, has 612 * no implied timing. 613 * 614 * See 93cx6.c for detailed information on the protocol necessary to 615 * read the serial EEPROM. 616 */ 617 #define SEECTL 0x01e 618 #define EXTARBACK 0x80 619 #define EXTARBREQ 0x40 620 #define SEEMS 0x20 621 #define SEERDY 0x10 622 #define SEECS 0x08 623 #define SEECK 0x04 624 #define SEEDO 0x02 625 #define SEEDI 0x01 626 627 /* ---------------------- Scratch RAM Offsets ------------------------- */ 628 /* These offsets are either to values that are initialized by the board's 629 * BIOS or are specified by the sequencer code. 630 * 631 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 632 * device information, 32-33 and 5a-5f as well. As it turns out, the 633 * BIOS trashes 20-2f, writing the synchronous negotiation results 634 * on top of the BIOS values, so we re-use those for our per-target 635 * scratchspace (actually a value that can be copied directly into 636 * SCSIRATE). The kernel driver will enable synchronous negotiation 637 * for all targets that have a value other than 0 in the lower four 638 * bits of the target scratch space. This should work regardless of 639 * whether the bios has been installed. 640 */ 641 642 /* 643 * 1 byte per target starting at this address for configuration values 644 */ 645 #define TARG_SCRATCH 0x020 646 647 /* 648 * The sequencer will stick the frist byte of any rejected message here so 649 * we can see what is getting thrown away. Extended messages put the 650 * extended message type in REJBYTE_EXT. 651 */ 652 #define REJBYTE 0x030 653 #define REJBYTE_EXT 0x031 654 655 /* 656 * Bit vector of targets that have disconnection disabled. 657 */ 658 #define DISC_DSB 0x032 659 #define DISC_DSB_A 0x032 660 #define DISC_DSB_B 0x033 661 662 /* 663 * Length of pending message 664 */ 665 #define MSG_LEN 0x034 666 667 /* We reserve 8bytes to store outgoing messages */ 668 #define MSG0 0x035 669 #define COMP_MSG0 0xcb /* 2's complement of MSG0 */ 670 #define MSG1 0x036 671 #define MSG2 0x037 672 #define MSG3 0x038 673 #define MSG4 0x039 674 #define MSG5 0x03a 675 #define MSG6 0x03b 676 #define MSG7 0x03c 677 678 /* 679 * These are offsets into the card's scratch ram. Some of the values are 680 * specified in the AHA2742 technical reference manual and are initialized 681 * by the BIOS at boot time. 682 */ 683 #define LASTPHASE 0x03d 684 #define ARG_1 0x03e 685 #define MAXOFFSET 0x01 686 #define RETURN_1 0x03f 687 #define SEND_WDTR 0x80 688 #define SEND_SDTR 0x60 689 #define SEND_SENSE 0x40 690 #define SEND_REJ 0x20 691 #define SCB_PAGEDIN 0x10 692 693 #define SIGSTATE 0x040 694 695 #define DMAPARAMS 0x041 /* Parameters for DMA Logic */ 696 697 #define SG_COUNT 0x042 698 #define SG_NEXT 0x043 /* working value of SG pointer */ 699 #define SG_NEXT0 0x043 700 #define SG_NEXT1 0x044 701 #define SG_NEXT2 0x045 702 #define SG_NEXT3 0x046 703 704 #define SCBCOUNT 0x047 /* 705 * Number of SCBs supported by 706 * this card. 707 */ 708 #define COMP_SCBCOUNT 0x048 /* 709 * Two's compliment of SCBCOUNT 710 */ 711 #define QCNTMASK 0x049 /* 712 * Mask of bits to test against 713 * when looking at the Queue Count 714 * registers. Works around a bug 715 * on aic7850 chips. 716 */ 717 #define FLAGS 0x04a 718 #define SINGLE_BUS 0x00 719 #define TWIN_BUS 0x01 720 #define WIDE_BUS 0x02 721 #define PAGESCBS 0x04 722 #define DPHASE 0x10 723 #define SELECTED 0x20 724 #define IDENTIFY_SEEN 0x40 725 #define RESELECTED 0x80 726 727 #define SAVED_TCL 0x04b /* 728 * Temporary storage for the 729 * target/channel/lun of a 730 * reconnecting target 731 */ 732 #define ACTIVE_A 0x04c 733 #define ACTIVE_B 0x04d 734 #define WAITING_SCBH 0x04e /* 735 * head of list of SCBs awaiting 736 * selection 737 */ 738 #define DISCONNECTED_SCBH 0x04f /* 739 * head of list of SCBs that are 740 * disconnected. Used for SCB 741 * paging. 742 */ 743 #define SCB_LIST_NULL 0xff 744 745 #define SAVED_LINKPTR 0x050 746 #define SAVED_SCBPTR 0x051 747 #define ULTRA_ENB 0x052 748 #define ULTRA_ENB_B 0x053 749 750 #define SCSICONF 0x05a 751 #define RESET_SCSI 0x40 752 753 #define HOSTCONF 0x05d 754 755 #define HA_274_BIOSCTRL 0x05f 756 #define BIOSMODE 0x30 757 #define BIOSDISABLED 0x30 758 #define CHANNEL_B_PRIMARY 0x08 759 760 /* Message codes */ 761 #define MSG_EXTENDED 0x01 762 #define MSG_SDTR 0x01 763 #define MSG_WDTR 0x03 764 #define MSG_SDPTRS 0x02 765 #define MSG_RDPTRS 0x03 766 #define MSG_DISCONNECT 0x04 767 #define MSG_INITIATOR_DET_ERROR 0x05 768 #define MSG_ABORT 0x06 769 #define MSG_REJECT 0x07 770 #define MSG_NOP 0x08 771 #define MSG_MSG_PARITY_ERROR 0x09 772 #define MSG_BUS_DEVICE_RESET 0x0c 773 #define MSG_ABORT_TAG 0x0d 774 #define MSG_SIMPLE_TAG 0x20 775 #define MSG_IDENTIFY 0x80 776 777 /* WDTR Message values */ 778 #define BUS_8_BIT 0x00 779 #define BUS_16_BIT 0x01 780 #define BUS_32_BIT 0x02 781 782 #define MAX_OFFSET_8BIT 0x0f 783 #define MAX_OFFSET_16BIT 0x08 784