1 /* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Absolutely no warranty of function or purpose is made by the author 17 * Justin T. Gibbs. 18 * 4. Modifications may be freely made to this file if the above conditions 19 * are met. 20 * 21 * $Id: aic7xxx_reg.h,v 1.6 1996/03/10 07:02:32 gibbs Exp $ 22 */ 23 24 /* 25 * This header is shared by the sequencer code and the kernel level driver. 26 * 27 * All page numbers refer to the Adaptec AIC-7770 Data Book availible from 28 * Adaptec's Technical Documents Department 1-800-934-2766 29 */ 30 31 /* 32 * SCSI Sequence Control (p. 3-11). 33 * Each bit, when set starts a specific SCSI sequence on the bus 34 */ 35 #define SCSISEQ 0x000 36 #define TEMODEO 0x80 37 #define ENSELO 0x40 38 #define ENSELI 0x20 39 #define ENRSELI 0x10 40 #define ENAUTOATNO 0x08 41 #define ENAUTOATNI 0x04 42 #define ENAUTOATNP 0x02 43 #define SCSIRSTO 0x01 44 45 /* 46 * SCSI Transfer Control 0 Register (pp. 3-13). 47 * Controls the SCSI module data path. 48 */ 49 #define SXFRCTL0 0x001 50 #define DFON 0x80 51 #define DFPEXP 0x40 52 #define ULTRAEN 0x20 53 #define CLRSTCNT 0x10 54 #define SPIOEN 0x08 55 #define SCAMEN 0x04 56 #define CLRCHN 0x02 57 /* UNUSED 0x01 */ 58 59 /* 60 * SCSI Transfer Control 1 Register (pp. 3-14,15). 61 * Controls the SCSI module data path. 62 */ 63 #define SXFRCTL1 0x002 64 #define BITBUCKET 0x80 65 #define SWRAPEN 0x40 66 #define ENSPCHK 0x20 67 #define STIMESEL 0x18 68 #define ENSTIMER 0x04 69 #define ACTNEGEN 0x02 70 #define STPWEN 0x01 /* Powered Termination */ 71 72 /* 73 * SCSI Control Signal Read Register (p. 3-15). 74 * Reads the actual state of the SCSI bus pins 75 */ 76 #define SCSISIGI 0x003 77 #define CDI 0x80 78 #define IOI 0x40 79 #define MSGI 0x20 80 #define ATNI 0x10 81 #define SELI 0x08 82 #define BSYI 0x04 83 #define REQI 0x02 84 #define ACKI 0x01 85 86 /* 87 * Possible phases in SCSISIGI 88 */ 89 #define PHASE_MASK 0xe0 90 #define P_DATAOUT 0x00 91 #define P_DATAIN 0x40 92 #define P_COMMAND 0x80 93 #define P_MESGOUT 0xa0 94 #define P_STATUS 0xc0 95 #define P_MESGIN 0xe0 96 /* 97 * SCSI Contol Signal Write Register (p. 3-16). 98 * Writing to this register modifies the control signals on the bus. Only 99 * those signals that are allowed in the current mode (Initiator/Target) are 100 * asserted. 101 */ 102 #define SCSISIGO 0x003 103 #define CDO 0x80 104 #define IOO 0x40 105 #define MSGO 0x20 106 #define ATNO 0x10 107 #define SELO 0x08 108 #define BSYO 0x04 109 #define REQO 0x02 110 #define ACKO 0x01 111 112 /* 113 * SCSI Rate Control (p. 3-17). 114 * Contents of this register determine the Synchronous SCSI data transfer 115 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 116 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 117 * greater than 0 enables synchronous transfers. 118 */ 119 #define SCSIRATE 0x004 120 #define WIDEXFER 0x80 /* Wide transfer control */ 121 #define SXFR 0x70 /* Sync transfer rate */ 122 #define SOFS 0x0f /* Sync offset */ 123 124 /* 125 * SCSI ID (p. 3-18). 126 * Contains the ID of the board and the current target on the 127 * selected channel. 128 */ 129 #define SCSIID 0x005 130 #define TID 0xf0 /* Target ID mask */ 131 #define OID 0x0f /* Our ID mask */ 132 133 /* 134 * SCSI Latched Data (p. 3-19). 135 * Read/Write latchs used to transfer data on the SCSI bus during 136 * Automatic or Manual PIO mode. SCSIDATH can be used for the 137 * upper byte of a 16bit wide asyncronouse data phase transfer. 138 */ 139 #define SCSIDATL 0x006 140 #define SCSIDATH 0x007 141 142 /* 143 * SCSI Transfer Count (pp. 3-19,20) 144 * These registers count down the number of bytes transfered 145 * across the SCSI bus. The counter is decremented only once 146 * the data has been safely transfered. SDONE in SSTAT0 is 147 * set when STCNT goes to 0 148 */ 149 #define STCNT 0x008 150 #define STCNT0 0x008 151 #define STCNT1 0x009 152 #define STCNT2 0x00a 153 154 /* 155 * Clear SCSI Interrupt 0 (p. 3-20) 156 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 157 */ 158 #define CLRSINT0 0x00b 159 #define CLRSELDO 0x40 160 #define CLRSELDI 0x20 161 #define CLRSELINGO 0x10 162 #define CLRSWRAP 0x08 163 /* UNUSED 0x04 */ 164 #define CLRSPIORDY 0x02 165 /* UNUSED 0x01 */ 166 167 /* 168 * SCSI Status 0 (p. 3-21) 169 * Contains one set of SCSI Interrupt codes 170 * These are most likely of interest to the sequencer 171 */ 172 #define SSTAT0 0x00b 173 #define TARGET 0x80 /* Board acting as target */ 174 #define SELDO 0x40 /* Selection Done */ 175 #define SELDI 0x20 /* Board has been selected */ 176 #define SELINGO 0x10 /* Selection In Progress */ 177 #define SWRAP 0x08 /* 24bit counter wrap */ 178 #define SDONE 0x04 /* STCNT = 0x000000 */ 179 #define SPIORDY 0x02 /* SCSI PIO Ready */ 180 #define DMADONE 0x01 /* DMA transfer completed */ 181 182 /* 183 * Clear SCSI Interrupt 1 (p. 3-23) 184 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 185 */ 186 #define CLRSINT1 0x00c 187 #define CLRSELTIMEO 0x80 188 #define CLRATNO 0x40 189 #define CLRSCSIRSTI 0x20 190 /* UNUSED 0x10 */ 191 #define CLRBUSFREE 0x08 192 #define CLRSCSIPERR 0x04 193 #define CLRPHASECHG 0x02 194 #define CLRREQINIT 0x01 195 196 /* 197 * SCSI Status 1 (p. 3-24) 198 */ 199 #define SSTAT1 0x00c 200 #define SELTO 0x80 201 #define ATNTARG 0x40 202 #define SCSIRSTI 0x20 203 #define PHASEMIS 0x10 204 #define BUSFREE 0x08 205 #define SCSIPERR 0x04 206 #define PHASECHG 0x02 207 #define REQINIT 0x01 208 209 /* 210 * SCSI Interrupt Mode 1 (pp. 3-28,29) 211 * Setting any bit will enable the corresponding function 212 * in SIMODE1 to interrupt via the IRQ pin. 213 */ 214 #define SIMODE1 0x011 215 #define ENSELTIMO 0x80 216 #define ENATNTARG 0x40 217 #define ENSCSIRST 0x20 218 #define ENPHASEMIS 0x10 219 #define ENBUSFREE 0x08 220 #define ENSCSIPERR 0x04 221 #define ENPHASECHG 0x02 222 #define ENREQINIT 0x01 223 224 /* 225 * SCSI Data Bus (High) (p. 3-29) 226 * This register reads data on the SCSI Data bus directly. 227 */ 228 #define SCSIBUSL 0x012 229 #define SCSIBUSH 0x013 230 231 /* 232 * SCSI/Host Address (p. 3-30) 233 * These registers hold the host address for the byte about to be 234 * transfered on the SCSI bus. They are counted up in the same 235 * manner as STCNT is counted down. SHADDR should always be used 236 * to determine the address of the last byte transfered since HADDR 237 * can be squewed by write ahead. 238 */ 239 #define SHADDR 0x014 240 #define SHADDR0 0x014 241 #define SHADDR1 0x015 242 #define SHADDR2 0x016 243 #define SHADDR3 0x017 244 245 /* 246 * Selection/Reselection ID (p. 3-31) 247 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 248 * device did not set its own ID. 249 */ 250 #define SELID 0x019 251 #define SELID_MASK 0xf0 252 #define ONEBIT 0x08 253 /* UNUSED 0x07 */ 254 255 /* 256 * SCSI Block Control (p. 3-32) 257 * Controls Bus type and channel selection. In a twin channel configuration 258 * addresses 0x00-0x1e are gated to the appropriate channel based on this 259 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 260 * on a wide bus. 261 */ 262 #define SBLKCTL 0x01f 263 #define DIAGLEDEN 0x80 /* Aic78X0 only */ 264 #define DIAGLEDON 0x40 /* Aic78X0 only */ 265 #define AUTOFLUSHDIS 0x20 266 /* UNUSED 0x10 */ 267 #define SELBUS_MASK 0x0a 268 #define SELBUSB 0x08 269 /* UNUSED 0x04 */ 270 #define SELWIDE 0x02 271 /* UNUSED 0x01 */ 272 #define SELNARROW 0x00 273 274 /* 275 * Sequencer Control (p. 3-33) 276 * Error detection mode and speed configuration 277 */ 278 #define SEQCTL 0x060 279 #define PERRORDIS 0x80 280 #define PAUSEDIS 0x40 281 #define FAILDIS 0x20 282 #define FASTMODE 0x10 283 #define BRKADRINTEN 0x08 284 #define STEP 0x04 285 #define SEQRESET 0x02 286 #define LOADRAM 0x01 287 288 /* 289 * Sequencer RAM Data (p. 3-34) 290 * Single byte window into the Scratch Ram area starting at the address 291 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 292 * four bytes in sucessesion. The SEQADDRs will increment after the most 293 * significant byte is written 294 */ 295 #define SEQRAM 0x061 296 297 /* 298 * Sequencer Address Registers (p. 3-35) 299 * Only the first bit of SEQADDR1 holds addressing information 300 */ 301 #define SEQADDR0 0x062 302 #define SEQADDR1 0x063 303 #define SEQADDR1_MASK 0x01 304 305 /* 306 * Accumulator 307 * We cheat by passing arguments in the Accumulator up to the kernel driver 308 */ 309 #define ACCUM 0x064 310 311 #define SINDEX 0x065 312 #define DINDEX 0x066 313 #define ALLZEROS 0x06a 314 #define NONE 0x06a 315 #define SINDIR 0x06c 316 #define DINDIR 0x06d 317 #define FUNCTION1 0x06e 318 319 /* 320 * Host Address (p. 3-48) 321 * This register contains the address of the byte about 322 * to be transfered across the host bus. 323 */ 324 #define HADDR 0x088 325 #define HADDR0 0x088 326 #define HADDR1 0x089 327 #define HADDR2 0x08a 328 #define HADDR3 0x08b 329 330 #define HCNT 0x08c 331 #define HCNT0 0x08c 332 #define HCNT1 0x08d 333 #define HCNT2 0x08e 334 /* 335 * SCB Pointer (p. 3-49) 336 * Gate one of the four SCBs into the SCBARRAY window. 337 */ 338 #define SCBPTR 0x090 339 340 /* 341 * Board Control (p. 3-43) 342 */ 343 #define BCTL 0x084 344 /* RSVD 0xf0 */ 345 #define ACE 0x08 /* Support for external processors */ 346 /* RSVD 0x06 */ 347 #define ENABLE 0x01 348 349 /* 350 * On the aic78X0 chips, Board Control is replaced by the DSCommand 351 * register (p. 4-64) 352 */ 353 #define DSCOMMAND 0x084 354 #define CACHETHEN 0x80 /* Cache Threshold enable */ 355 #define DPARCKEN 0x40 /* Data Parity Check Enable */ 356 #define MPARCKEN 0x20 /* Memory Parity Check Enable */ 357 #define EXTREQLCK 0x10 /* External Request Lock */ 358 359 /* 360 * Bus On/Off Time (p. 3-44) 361 */ 362 #define BUSTIME 0x085 363 #define BOFF 0xf0 364 #define BON 0x0f 365 #define BOFF_60BCLKS 0xf0 366 367 /* 368 * Bus Speed (p. 3-45) 369 */ 370 #define BUSSPD 0x086 371 #define DFTHRSH 0xc0 372 #define STBOFF 0x38 373 #define STBON 0x07 374 #define DFTHRSH_100 0xc0 375 376 /* 377 * Host Control (p. 3-47) R/W 378 * Overal host control of the device. 379 */ 380 #define HCNTRL 0x087 381 /* UNUSED 0x80 */ 382 #define POWRDN 0x40 383 /* UNUSED 0x20 */ 384 #define SWINT 0x10 385 #define IRQMS 0x08 386 #define PAUSE 0x04 387 #define INTEN 0x02 388 #define CHIPRST 0x01 389 390 /* 391 * Interrupt Status (p. 3-50) 392 * Status for system interrupts 393 */ 394 #define INTSTAT 0x091 395 #define SEQINT_MASK 0xf1 /* SEQINT Status Codes */ 396 #define BAD_PHASE 0x01 /* unknown scsi bus phase */ 397 #define SEND_REJECT 0x11 /* sending a message reject */ 398 #define NO_IDENT 0x21 /* no IDENTIFY after reconnect*/ 399 #define NO_MATCH 0x31 /* no cmd match for reconnect */ 400 #define SDTR_MSG 0x41 /* SDTR message received */ 401 #define WDTR_MSG 0x51 /* WDTR message received */ 402 #define REJECT_MSG 0x61 /* Reject message received */ 403 #define BAD_STATUS 0x71 /* Bad status from target */ 404 #define RESIDUAL 0x81 /* Residual byte count != 0 */ 405 #define ABORT_TAG 0x91 /* Sent an ABORT_TAG message */ 406 #define AWAITING_MSG 0xa1 /* 407 * Kernel requested to specify 408 * a message to this target 409 * (command was null), so tell 410 * it that it can fill the 411 * message buffer. 412 */ 413 #define IMMEDDONE 0xb1 /* 414 * An immediate command has 415 * completed 416 */ 417 #define MSG_BUFFER_BUSY 0xc1 /* 418 * Sequencer wants to use the 419 * message buffer, but it 420 * already contains a message 421 */ 422 #define MSGIN_PHASEMIS 0xd1 /* 423 * Target changed phase on us 424 * when we were expecting 425 * another msgin byte. 426 */ 427 #define BRKADRINT 0x08 428 #define SCSIINT 0x04 429 #define CMDCMPLT 0x02 430 #define SEQINT 0x01 431 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 432 433 /* 434 * Hard Error (p. 3-53) 435 * Reporting of catastrophic errors. You usually cannot recover from 436 * these without a full board reset. 437 */ 438 #define ERROR 0x092 439 /* UNUSED 0xf0 */ 440 #define PARERR 0x08 441 #define ILLOPCODE 0x04 442 #define ILLSADDR 0x02 443 #define ILLHADDR 0x01 444 445 /* 446 * Clear Interrupt Status (p. 3-52) 447 */ 448 #define CLRINT 0x092 449 #define CLRBRKADRINT 0x08 450 #define CLRSCSIINT 0x04 451 #define CLRCMDINT 0x02 452 #define CLRSEQINT 0x01 453 454 #define DFCNTRL 0x093 455 #define WIDEODD 0x40 456 #define SCSIEN 0x20 457 #define SDMAEN 0x10 458 #define SDMAENACK 0x10 459 #define HDMAEN 0x08 460 #define HDMAENACK 0x08 461 #define DIRECTION 0x04 462 #define FIFOFLUSH 0x02 463 #define FIFORESET 0x01 464 465 #define DFSTATUS 0x094 466 #define HDONE 0x08 467 #define FIFOEMP 0x01 468 469 #define DFDAT 0x099 470 471 /* 472 * SCB Auto Increment (p. 3-59) 473 * Byte offset into the SCB Array and an optional bit to allow auto 474 * incrementing of the address during download and upload operations 475 */ 476 #define SCBCNT 0x09a 477 #define SCBAUTO 0x80 478 #define SCBCNT_MASK 0x1f 479 480 /* 481 * Queue In FIFO (p. 3-60) 482 * Input queue for queued SCBs (commands that the seqencer has yet to start) 483 */ 484 #define QINFIFO 0x09b 485 486 /* 487 * Queue In Count (p. 3-60) 488 * Number of queued SCBs 489 */ 490 #define QINCNT 0x09c 491 492 /* 493 * Queue Out FIFO (p. 3-61) 494 * Queue of SCBs that have completed and await the host 495 */ 496 #define QOUTFIFO 0x09d 497 498 /* 499 * Queue Out Count (p. 3-61) 500 * Number of queued SCBs in the Out FIFO 501 */ 502 #define QOUTCNT 0x09e 503 504 /* 505 * SCB Definition (p. 5-4) 506 * The two reserved bytes at SCBARRAY+1[23] are expected to be set to 507 * zero. Bit 3 in SCBARRAY+0 is used as an internal flag to indicate 508 * whether or not to DMA an SCB from host ram. This flag prevents the 509 * "re-fetching" of transactions that are requed because the target is 510 * busy with another command. We also use bits 6 & 7 to indicate whether 511 * or not to initiate SDTR or WDTR repectively when starting this command. 512 */ 513 #define SCBARRAY 0x0a0 514 #define SCB_CONTROL 0x0a0 515 #define NEEDWDTR 0x80 516 #define DISCENB 0x40 517 #define TAG_ENB 0x20 518 #define NEEDSDTR 0x10 519 #define DISCONNECTED 0x04 520 #define SCB_TAG_TYPE 0x03 521 #define SCB_TCL 0x0a1 522 #define SCB_TARGET_STATUS 0x0a2 523 #define SCB_SGCOUNT 0x0a3 524 #define SCB_SGPTR 0x0a4 525 #define SCB_SGPTR0 0x0a4 526 #define SCB_SGPTR1 0x0a5 527 #define SCB_SGPTR2 0x0a6 528 #define SCB_SGPTR3 0x0a7 529 #define SCB_RESID_SGCNT 0x0a8 530 #define SCB_RESID_DCNT 0x0a9 531 #define SCB_RESID_DCNT0 0x0a9 532 #define SCB_RESID_DCNT1 0x0aa 533 #define SCB_RESID_DCNT2 0x0ab 534 #define SCB_DATAPTR 0x0ac 535 #define SCB_DATAPTR0 0x0ac 536 #define SCB_DATAPTR1 0x0ad 537 #define SCB_DATAPTR2 0x0ae 538 #define SCB_DATAPTR3 0x0af 539 #define SCB_DATACNT 0x0b0 540 #define SCB_DATACNT0 0x0b0 541 #define SCB_DATACNT1 0x0b1 542 #define SCB_DATACNT2 0x0b2 543 /* UNUSED - QUAD PADDING 0x0b3 */ 544 #define SCB_CMDPTR 0x0b4 545 #define SCB_CMDPTR0 0x0b4 546 #define SCB_CMDPTR1 0x0b5 547 #define SCB_CMDPTR2 0x0b6 548 #define SCB_CMDPTR3 0x0b7 549 #define SCB_CMDLEN 0x0b8 550 #define SCB_NEXT_WAITING 0x0b9 551 552 #ifdef linux 553 #define SG_SIZEOF 0x0c /* sizeof(struct scatterlist) */ 554 #else 555 #define SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 556 #endif 557 558 /* --------------------- AHA-2840-only definitions -------------------- */ 559 560 #define SEECTL_2840 0x0c0 561 /* UNUSED 0xf8 */ 562 #define CS_2840 0x04 563 #define CK_2840 0x02 564 #define DO_2840 0x01 565 566 #define STATUS_2840 0x0c1 567 #define EEPROM_TF 0x80 568 #define BIOS_SEL 0x60 569 #define ADSEL 0x1e 570 #define DI_2840 0x01 571 572 /* --------------------- AIC-7870-only definitions -------------------- */ 573 574 #define DSPCISTATUS 0x086 575 576 /* 577 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 578 * Controls the reading and writing of an external serial 1-bit 579 * EEPROM Device. In order to access the serial EEPROM, you must 580 * first set the SEEMS bit that generates a request to the memory 581 * port for access to the serial EEPROM device. When the memory 582 * port is not busy servicing another request, it reconfigures 583 * to allow access to the serial EEPROM. When this happens, SEERDY 584 * gets set high to verify that the memory port access has been 585 * granted. 586 * 587 * After successful arbitration for the memory port, the SEECS bit of 588 * the SEECTL register is connected to the chip select. The SEECK, 589 * SEEDO, and SEEDI are connected to the clock, data out, and data in 590 * lines respectively. The SEERDY bit of SEECTL is useful in that it 591 * gives us an 800 nsec timer. After a write to the SEECTL register, 592 * the SEERDY goes high 800 nsec later. The one exception to this is 593 * when we first request access to the memory port. The SEERDY goes 594 * high to signify that access has been granted and, for this case, has 595 * no implied timing. 596 * 597 * See 93cx6.c for detailed information on the protocol necessary to 598 * read the serial EEPROM. 599 */ 600 #define SEECTL 0x01e 601 #define EXTARBACK 0x80 602 #define EXTARBREQ 0x40 603 #define SEEMS 0x20 604 #define SEERDY 0x10 605 #define SEECS 0x08 606 #define SEECK 0x04 607 #define SEEDO 0x02 608 #define SEEDI 0x01 609 610 /* ---------------------- Scratch RAM Offsets ------------------------- */ 611 /* These offsets are either to values that are initialized by the board's 612 * BIOS or are specified by the sequencer code. 613 * 614 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 615 * device information, 32-33 and 5a-5f as well. As it turns out, the 616 * BIOS trashes 20-2f, writing the synchronous negotiation results 617 * on top of the BIOS values, so we re-use those for our per-target 618 * scratchspace (actually a value that can be copied directly into 619 * SCSIRATE). The kernel driver will enable synchronous negotiation 620 * for all targets that have a value other than 0 in the lower four 621 * bits of the target scratch space. This should work regardless of 622 * whether the bios has been installed. 623 */ 624 625 /* 626 * 1 byte per target starting at this address for configuration values 627 */ 628 #define TARG_SCRATCH 0x020 629 630 /* 631 * The sequencer will stick the frist byte of any rejected message here so 632 * we can see what is getting thrown away. 633 */ 634 #define REJBYTE 0x031 635 636 /* 637 * Bit vector of targets that have disconnection disabled. 638 */ 639 #define DISC_DSB 0x032 640 #define DISC_DSB_A 0x032 641 #define DISC_DSB_B 0x033 642 643 /* 644 * Length of pending message 645 */ 646 #define MSG_LEN 0x034 647 648 #define MSG0 0x035 649 #define COMP_MSG0 0xcb /* 2's complement of MSG0 */ 650 #define MSG1 0x036 651 #define MSG2 0x037 652 #define MSG3 0x038 653 #define MSG4 0x039 654 #define MSG5 0x03a 655 656 /* 657 * These are offsets into the card's scratch ram. Some of the values are 658 * specified in the AHA2742 technical reference manual and are initialized 659 * by the BIOS at boot time. 660 */ 661 #define LASTPHASE 0x049 662 #define ARG_1 0x04a 663 #define RETURN_1 0x04a 664 #define SEND_SENSE 0x80 665 #define SEND_WDTR 0x80 666 #define SEND_SDTR 0x80 667 #define SEND_REJ 0x40 668 669 #define SIGSTATE 0x04b 670 671 #define DMAPARAMS 0x04c /* Parameters for DMA Logic */ 672 673 #define SG_COUNT 0x04d 674 #define SG_NEXT 0x04e /* working value of SG pointer */ 675 #define SG_NEXT0 0x04e 676 #define SG_NEXT1 0x04f 677 #define SG_NEXT2 0x050 678 #define SG_NEXT3 0x051 679 680 #define SCBCOUNT 0x052 /* 681 * Number of SCBs supported by 682 * this card. 683 */ 684 #define FLAGS 0x053 685 #define SINGLE_BUS 0x00 686 #define TWIN_BUS 0x01 687 #define WIDE_BUS 0x02 688 #define DPHASE 0x04 689 #define MAXOFFSET 0x08 690 #define IDENTIFY_SEEN 0x40 691 #define RESELECTED 0x80 692 693 #define ACTIVE_A 0x054 694 #define ACTIVE_B 0x055 695 #define SAVED_TCL 0x056 /* 696 * Temporary storage for the 697 * target/channel/lun of a 698 * reconnecting target 699 */ 700 #define WAITING_SCBH 0x057 /* 701 * head of list of SCBs awaiting 702 * selection 703 */ 704 #define QCNTMASK 0x058 /* 705 * Mask of bits to test against 706 * when looking at the Queue Count 707 * registers. Works around a bug 708 * on aic7850 chips. 709 */ 710 #define COMP_SCBCOUNT 0x059 711 #define SCB_LIST_NULL 0xff 712 713 #define SCSICONF 0x05a 714 #define HOSTCONF 0x05d 715 716 #define HA_274_BIOSCTRL 0x05f 717 #define BIOSMODE 0x30 718 #define BIOSDISABLED 0x30 719 720 /* Message codes */ 721 #define MSG_EXTENDED 0x01 722 #define MSG_SDTR 0x01 723 #define MSG_WDTR 0x03 724 #define MSG_SDPTRS 0x02 725 #define MSG_RDPTRS 0x03 726 #define MSG_DISCONNECT 0x04 727 #define MSG_INITIATOR_DET_ERROR 0x05 728 #define MSG_ABORT 0x06 729 #define MSG_REJECT 0x07 730 #define MSG_NOP 0x08 731 #define MSG_MSG_PARITY_ERROR 0x09 732 #define MSG_BUS_DEVICE_RESET 0x0c 733 #define MSG_SIMPLE_TAG 0x20 734 #define MSG_IDENTIFY 0x80 735 736 /* WDTR Message values */ 737 #define BUS_8_BIT 0x00 738 #define BUS_16_BIT 0x01 739 #define BUS_32_BIT 0x02 740 741 #define MAX_OFFSET_8BIT 0x0f 742 #define MAX_OFFSET_16BIT 0x08 743