1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#50 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 59 60 static __inline uint64_t 61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 77 #define ID_9005_SISL_ID 0x0005900500000000ull 78 #define ID_AIC7850 0x5078900400000000ull 79 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 80 #define ID_AIC7855 0x5578900400000000ull 81 #define ID_AIC7859 0x3860900400000000ull 82 #define ID_AHA_2930CU 0x3860900438699004ull 83 #define ID_AIC7860 0x6078900400000000ull 84 #define ID_AIC7860C 0x6078900478609004ull 85 #define ID_AHA_1480A 0x6075900400000000ull 86 #define ID_AHA_2940AU_0 0x6178900400000000ull 87 #define ID_AHA_2940AU_1 0x6178900478619004ull 88 #define ID_AHA_2940AU_CN 0x2178900478219004ull 89 #define ID_AHA_2930C_VAR 0x6038900438689004ull 90 91 #define ID_AIC7870 0x7078900400000000ull 92 #define ID_AHA_2940 0x7178900400000000ull 93 #define ID_AHA_3940 0x7278900400000000ull 94 #define ID_AHA_398X 0x7378900400000000ull 95 #define ID_AHA_2944 0x7478900400000000ull 96 #define ID_AHA_3944 0x7578900400000000ull 97 #define ID_AHA_4944 0x7678900400000000ull 98 99 #define ID_AIC7880 0x8078900400000000ull 100 #define ID_AIC7880_B 0x8078900478809004ull 101 #define ID_AHA_2940U 0x8178900400000000ull 102 #define ID_AHA_3940U 0x8278900400000000ull 103 #define ID_AHA_2944U 0x8478900400000000ull 104 #define ID_AHA_3944U 0x8578900400000000ull 105 #define ID_AHA_398XU 0x8378900400000000ull 106 #define ID_AHA_4944U 0x8678900400000000ull 107 #define ID_AHA_2940UB 0x8178900478819004ull 108 #define ID_AHA_2930U 0x8878900478889004ull 109 #define ID_AHA_2940U_PRO 0x8778900478879004ull 110 #define ID_AHA_2940U_CN 0x0078900478009004ull 111 112 #define ID_AIC7895 0x7895900478959004ull 113 #define ID_AIC7895_ARO 0x7890900478939004ull 114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 116 #define ID_AHA_3940AU 0x7895900478929004ull 117 #define ID_AHA_3944AU 0x7895900478949004ull 118 119 #define ID_AIC7890 0x001F9005000F9005ull 120 #define ID_AIC7890_ARO 0x00139005000F9005ull 121 #define ID_AAA_131U2 0x0013900500039005ull 122 #define ID_AHA_2930U2 0x0011900501819005ull 123 #define ID_AHA_2940U2B 0x00109005A1009005ull 124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 125 #define ID_AHA_2940U2 0x00109005A1809005ull 126 #define ID_AHA_2950U2B 0x00109005E1009005ull 127 128 #define ID_AIC7892 0x008F9005FFFF9005ull 129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 130 #define ID_AHA_29160 0x00809005E2A09005ull 131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132 #define ID_AHA_29160N 0x0080900562A09005ull 133 #define ID_AHA_29160C 0x0080900562209005ull 134 #define ID_AHA_29160B 0x00809005E2209005ull 135 #define ID_AHA_19160B 0x0081900562A19005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 /* aic7895 based controllers */ 474 { 475 ID_AHA_2940U_DUAL, 476 ID_ALL_MASK, 477 "Adaptec 2940/DUAL Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AHA_3940AU, 482 ID_ALL_MASK, 483 "Adaptec 3940A Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3944AU, 488 ID_ALL_MASK, 489 "Adaptec 3944A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_ARO, 494 ID_AIC7895_ARO_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 496 ahc_aic7895_setup 497 }, 498 /* aic7896/97 based controllers */ 499 { 500 ID_AHA_3950U2B_0, 501 ID_ALL_MASK, 502 "Adaptec 3950B Ultra2 SCSI adapter", 503 ahc_aic7896_setup 504 }, 505 { 506 ID_AHA_3950U2B_1, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2D_0, 513 ID_ALL_MASK, 514 "Adaptec 3950D Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_1, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AIC7896_ARO, 525 ID_ALL_MASK, 526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 527 ahc_aic7896_setup 528 }, 529 /* aic7899 based controllers */ 530 { 531 ID_AHA_3960D, 532 ID_ALL_MASK, 533 "Adaptec 3960D Ultra160 SCSI adapter", 534 ahc_aic7899_setup 535 }, 536 { 537 ID_AHA_3960D_CPQ, 538 ID_ALL_MASK, 539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AIC7899_ARO, 544 ID_ALL_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 546 ahc_aic7899_setup 547 }, 548 /* Generic chip probes for devices we don't know 'exactly' */ 549 { 550 ID_AIC7850 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7850 SCSI adapter", 553 ahc_aic785X_setup 554 }, 555 { 556 ID_AIC7855 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7855 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7859 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7859 SCSI adapter", 565 ahc_aic7860_setup 566 }, 567 { 568 ID_AIC7860 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7860 Ultra SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7870 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7870 SCSI adapter", 577 ahc_aic7870_setup 578 }, 579 { 580 ID_AIC7880 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7880 Ultra SCSI adapter", 583 ahc_aic7880_setup 584 }, 585 { 586 ID_AIC7890 & ID_9005_GENERIC_MASK, 587 ID_9005_GENERIC_MASK, 588 "Adaptec aic7890/91 Ultra2 SCSI adapter", 589 ahc_aic7890_setup 590 }, 591 { 592 ID_AIC7892 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7892 Ultra160 SCSI adapter", 595 ahc_aic7892_setup 596 }, 597 { 598 ID_AIC7895 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7895 Ultra SCSI adapter", 601 ahc_aic7895_setup 602 }, 603 { 604 ID_AIC7896 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7896/97 Ultra2 SCSI adapter", 607 ahc_aic7896_setup 608 }, 609 { 610 ID_AIC7899 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7899 Ultra160 SCSI adapter", 613 ahc_aic7899_setup 614 }, 615 { 616 ID_AIC7810 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7810 RAID memory controller", 619 ahc_raid_setup 620 }, 621 { 622 ID_AIC7815 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7815 RAID memory controller", 625 ahc_raid_setup 626 } 627 }; 628 629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 630 631 #define AHC_394X_SLOT_CHANNEL_A 4 632 #define AHC_394X_SLOT_CHANNEL_B 5 633 634 #define AHC_398X_SLOT_CHANNEL_A 4 635 #define AHC_398X_SLOT_CHANNEL_B 8 636 #define AHC_398X_SLOT_CHANNEL_C 12 637 638 #define AHC_494X_SLOT_CHANNEL_A 4 639 #define AHC_494X_SLOT_CHANNEL_B 5 640 #define AHC_494X_SLOT_CHANNEL_C 6 641 #define AHC_494X_SLOT_CHANNEL_D 7 642 643 #define DEVCONFIG 0x40 644 #define SCBSIZE32 0x00010000ul /* aic789X only */ 645 #define REXTVALID 0x00001000ul /* ultra cards only */ 646 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 647 #define RAMPSM 0x00000200ul /* aic7870+ only */ 648 #define VOLSENSE 0x00000100ul 649 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 650 #define SCBRAMSEL 0x00000080ul 651 #define MRDCEN 0x00000040ul 652 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 653 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 654 #define BERREN 0x00000008ul 655 #define DACEN 0x00000004ul 656 #define STPWLEVEL 0x00000002ul 657 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 658 659 #define CSIZE_LATTIME 0x0c 660 #define CACHESIZE 0x0000003ful /* only 5 bits */ 661 #define LATTIME 0x0000ff00ul 662 663 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 664 uint16_t subvendor, uint16_t subdevice); 665 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 666 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 667 int pcheck, int fast, int large); 668 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 669 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 670 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 671 struct seeprom_config *sc); 672 static void configure_termination(struct ahc_softc *ahc, 673 struct seeprom_descriptor *sd, 674 u_int adapter_control, 675 u_int *sxfrctl1); 676 677 static void ahc_new_term_detect(struct ahc_softc *ahc, 678 int *enableSEC_low, 679 int *enableSEC_high, 680 int *enablePRI_low, 681 int *enablePRI_high, 682 int *eeprom_present); 683 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 684 int *internal68_present, 685 int *externalcable_present, 686 int *eeprom_present); 687 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 688 int *externalcable_present, 689 int *eeprom_present); 690 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 691 static uint8_t read_brdctl(struct ahc_softc *ahc); 692 693 static int 694 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 695 uint16_t subdevice, uint16_t subvendor) 696 { 697 int result; 698 699 /* Default to invalid. */ 700 result = 0; 701 if (vendor == 0x9005 702 && subvendor == 0x9005 703 && subdevice != device 704 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 705 706 switch (SUBID_9005_TYPE(subdevice)) { 707 case SUBID_9005_TYPE_MB: 708 break; 709 case SUBID_9005_TYPE_CARD: 710 case SUBID_9005_TYPE_LCCARD: 711 /* 712 * Currently only trust Adaptec cards to 713 * get the sub device info correct. 714 */ 715 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 716 result = 1; 717 break; 718 case SUBID_9005_TYPE_RAID: 719 break; 720 default: 721 break; 722 } 723 } 724 return (result); 725 } 726 727 struct ahc_pci_identity * 728 ahc_find_pci_device(ahc_dev_softc_t pci) 729 { 730 uint64_t full_id; 731 uint16_t device; 732 uint16_t vendor; 733 uint16_t subdevice; 734 uint16_t subvendor; 735 struct ahc_pci_identity *entry; 736 u_int i; 737 738 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 739 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 740 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 741 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 742 full_id = ahc_compose_id(device, 743 vendor, 744 subdevice, 745 subvendor); 746 747 /* 748 * If the second function is not hooked up, ignore it. 749 * Unfortunately, not all MB vendors implement the 750 * subdevice ID as per the Adaptec spec, so do our best 751 * to sanity check it prior to accepting the subdevice 752 * ID as valid. 753 */ 754 if (ahc_get_pci_function(pci) > 0 755 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 756 && SUBID_9005_MFUNCENB(subdevice) == 0) 757 return (NULL); 758 759 for (i = 0; i < ahc_num_pci_devs; i++) { 760 entry = &ahc_pci_ident_table[i]; 761 if (entry->full_id == (full_id & entry->id_mask)) { 762 /* Honor exclusion entries. */ 763 if (entry->name == NULL) 764 return (NULL); 765 return (entry); 766 } 767 } 768 return (NULL); 769 } 770 771 int 772 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 773 { 774 u_long l; 775 u_int command; 776 u_int our_id; 777 u_int sxfrctl1; 778 u_int scsiseq; 779 u_int dscommand0; 780 int error; 781 uint8_t sblkctl; 782 783 our_id = 0; 784 error = entry->setup(ahc); 785 if (error != 0) 786 return (error); 787 ahc->chip |= AHC_PCI; 788 ahc->description = entry->name; 789 790 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 791 792 error = ahc_pci_map_registers(ahc); 793 if (error != 0) 794 return (error); 795 796 /* 797 * Before we continue probing the card, ensure that 798 * its interrupts are *disabled*. We don't want 799 * a misstep to hang the machine in an interrupt 800 * storm. 801 */ 802 ahc_intr_enable(ahc, FALSE); 803 804 /* 805 * If we need to support high memory, enable dual 806 * address cycles. This bit must be set to enable 807 * high address bit generation even if we are on a 808 * 64bit bus (PCI64BIT set in devconfig). 809 */ 810 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 811 uint32_t devconfig; 812 813 if (bootverbose) 814 printf("%s: Enabling 39Bit Addressing\n", 815 ahc_name(ahc)); 816 devconfig = ahc_pci_read_config(ahc->dev_softc, 817 DEVCONFIG, /*bytes*/4); 818 devconfig |= DACEN; 819 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 820 devconfig, /*bytes*/4); 821 } 822 823 /* Ensure busmastering is enabled */ 824 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 825 command |= PCIM_CMD_BUSMASTEREN; 826 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 827 828 /* On all PCI adapters, we allow SCB paging */ 829 ahc->flags |= AHC_PAGESCBS; 830 831 error = ahc_softc_init(ahc); 832 if (error != 0) 833 return (error); 834 835 ahc->bus_intr = ahc_pci_intr; 836 837 /* Remeber how the card was setup in case there is no SEEPROM */ 838 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 839 ahc_pause(ahc); 840 if ((ahc->features & AHC_ULTRA2) != 0) 841 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 842 else 843 our_id = ahc_inb(ahc, SCSIID) & OID; 844 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 845 scsiseq = ahc_inb(ahc, SCSISEQ); 846 } else { 847 sxfrctl1 = STPWEN; 848 our_id = 7; 849 scsiseq = 0; 850 } 851 852 error = ahc_reset(ahc); 853 if (error != 0) 854 return (ENXIO); 855 856 if ((ahc->features & AHC_DT) != 0) { 857 u_int sfunct; 858 859 /* Perform ALT-Mode Setup */ 860 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 861 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 862 ahc_outb(ahc, OPTIONMODE, 863 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 864 ahc_outb(ahc, SFUNCT, sfunct); 865 866 /* Normal mode setup */ 867 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 868 |TARGCRCENDEN); 869 } 870 871 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 872 dscommand0 |= MPARCKEN|CACHETHEN; 873 if ((ahc->features & AHC_ULTRA2) != 0) { 874 875 /* 876 * DPARCKEN doesn't work correctly on 877 * some MBs so don't use it. 878 */ 879 dscommand0 &= ~DPARCKEN; 880 } 881 882 /* 883 * Handle chips that must have cache line 884 * streaming (dis/en)abled. 885 */ 886 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 887 dscommand0 |= CACHETHEN; 888 889 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 890 dscommand0 &= ~CACHETHEN; 891 892 ahc_outb(ahc, DSCOMMAND0, dscommand0); 893 894 ahc->pci_cachesize = 895 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 896 /*bytes*/1) & CACHESIZE; 897 ahc->pci_cachesize *= 4; 898 899 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 900 && ahc->pci_cachesize == 4) { 901 902 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 903 0, /*bytes*/1); 904 ahc->pci_cachesize = 0; 905 } 906 907 /* 908 * We cannot perform ULTRA speeds without the presense 909 * of the external precision resistor. 910 */ 911 if ((ahc->features & AHC_ULTRA) != 0) { 912 uint32_t devconfig; 913 914 devconfig = ahc_pci_read_config(ahc->dev_softc, 915 DEVCONFIG, /*bytes*/4); 916 if ((devconfig & REXTVALID) == 0) 917 ahc->features &= ~AHC_ULTRA; 918 } 919 920 /* See if we have a SEEPROM and perform auto-term */ 921 check_extport(ahc, &sxfrctl1); 922 923 /* 924 * Take the LED out of diagnostic mode 925 */ 926 sblkctl = ahc_inb(ahc, SBLKCTL); 927 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 928 929 if ((ahc->features & AHC_ULTRA2) != 0) { 930 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 931 } else { 932 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 933 } 934 935 if (ahc->flags & AHC_USEDEFAULTS) { 936 /* 937 * PCI Adapter default setup 938 * Should only be used if the adapter does not have 939 * a SEEPROM. 940 */ 941 /* See if someone else set us up already */ 942 if (scsiseq != 0) { 943 printf("%s: Using left over BIOS settings\n", 944 ahc_name(ahc)); 945 ahc->flags &= ~AHC_USEDEFAULTS; 946 ahc->flags |= AHC_BIOS_ENABLED; 947 } else { 948 /* 949 * Assume only one connector and always turn 950 * on termination. 951 */ 952 our_id = 0x07; 953 sxfrctl1 = STPWEN; 954 } 955 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 956 957 ahc->our_id = our_id; 958 } 959 960 /* 961 * Take a look to see if we have external SRAM. 962 * We currently do not attempt to use SRAM that is 963 * shared among multiple controllers. 964 */ 965 ahc_probe_ext_scbram(ahc); 966 967 /* 968 * Record our termination setting for the 969 * generic initialization routine. 970 */ 971 if ((sxfrctl1 & STPWEN) != 0) 972 ahc->flags |= AHC_TERM_ENB_A; 973 974 /* Core initialization */ 975 error = ahc_init(ahc); 976 if (error != 0) 977 return (error); 978 979 /* 980 * Allow interrupts now that we are completely setup. 981 */ 982 error = ahc_pci_map_int(ahc); 983 if (error != 0) 984 return (error); 985 986 ahc_list_lock(&l); 987 /* 988 * Link this softc in with all other ahc instances. 989 */ 990 ahc_softc_insert(ahc); 991 ahc_list_unlock(&l); 992 return (0); 993 } 994 995 /* 996 * Test for the presense of external sram in an 997 * "unshared" configuration. 998 */ 999 static int 1000 ahc_ext_scbram_present(struct ahc_softc *ahc) 1001 { 1002 u_int chip; 1003 int ramps; 1004 int single_user; 1005 uint32_t devconfig; 1006 1007 chip = ahc->chip & AHC_CHIPID_MASK; 1008 devconfig = ahc_pci_read_config(ahc->dev_softc, 1009 DEVCONFIG, /*bytes*/4); 1010 single_user = (devconfig & MPORTMODE) != 0; 1011 1012 if ((ahc->features & AHC_ULTRA2) != 0) 1013 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1014 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1015 /* 1016 * External SCBRAM arbitration is flakey 1017 * on these chips. Unfortunately this means 1018 * we don't use the extra SCB ram space on the 1019 * 3940AUW. 1020 */ 1021 ramps = 0; 1022 else if (chip >= AHC_AIC7870) 1023 ramps = (devconfig & RAMPSM) != 0; 1024 else 1025 ramps = 0; 1026 1027 if (ramps && single_user) 1028 return (1); 1029 return (0); 1030 } 1031 1032 /* 1033 * Enable external scbram. 1034 */ 1035 static void 1036 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1037 int fast, int large) 1038 { 1039 uint32_t devconfig; 1040 1041 if (ahc->features & AHC_MULTI_FUNC) { 1042 /* 1043 * Set the SCB Base addr (highest address bit) 1044 * depending on which channel we are. 1045 */ 1046 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1047 } 1048 1049 ahc->flags &= ~AHC_LSCBS_ENABLED; 1050 if (large) 1051 ahc->flags |= AHC_LSCBS_ENABLED; 1052 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1053 if ((ahc->features & AHC_ULTRA2) != 0) { 1054 u_int dscommand0; 1055 1056 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1057 if (enable) 1058 dscommand0 &= ~INTSCBRAMSEL; 1059 else 1060 dscommand0 |= INTSCBRAMSEL; 1061 if (large) 1062 dscommand0 &= ~USCBSIZE32; 1063 else 1064 dscommand0 |= USCBSIZE32; 1065 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1066 } else { 1067 if (fast) 1068 devconfig &= ~EXTSCBTIME; 1069 else 1070 devconfig |= EXTSCBTIME; 1071 if (enable) 1072 devconfig &= ~SCBRAMSEL; 1073 else 1074 devconfig |= SCBRAMSEL; 1075 if (large) 1076 devconfig &= ~SCBSIZE32; 1077 else 1078 devconfig |= SCBSIZE32; 1079 } 1080 if (pcheck) 1081 devconfig |= EXTSCBPEN; 1082 else 1083 devconfig &= ~EXTSCBPEN; 1084 1085 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1086 } 1087 1088 /* 1089 * Take a look to see if we have external SRAM. 1090 * We currently do not attempt to use SRAM that is 1091 * shared among multiple controllers. 1092 */ 1093 static void 1094 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1095 { 1096 int num_scbs; 1097 int test_num_scbs; 1098 int enable; 1099 int pcheck; 1100 int fast; 1101 int large; 1102 1103 enable = FALSE; 1104 pcheck = FALSE; 1105 fast = FALSE; 1106 large = FALSE; 1107 num_scbs = 0; 1108 1109 if (ahc_ext_scbram_present(ahc) == 0) 1110 goto done; 1111 1112 /* 1113 * Probe for the best parameters to use. 1114 */ 1115 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1116 num_scbs = ahc_probe_scbs(ahc); 1117 if (num_scbs == 0) { 1118 /* The SRAM wasn't really present. */ 1119 goto done; 1120 } 1121 enable = TRUE; 1122 1123 /* 1124 * Clear any outstanding parity error 1125 * and ensure that parity error reporting 1126 * is enabled. 1127 */ 1128 ahc_outb(ahc, SEQCTL, 0); 1129 ahc_outb(ahc, CLRINT, CLRPARERR); 1130 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1131 1132 /* Now see if we can do parity */ 1133 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1134 num_scbs = ahc_probe_scbs(ahc); 1135 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1136 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1137 pcheck = TRUE; 1138 1139 /* Clear any resulting parity error */ 1140 ahc_outb(ahc, CLRINT, CLRPARERR); 1141 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1142 1143 /* Now see if we can do fast timing */ 1144 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1145 test_num_scbs = ahc_probe_scbs(ahc); 1146 if (test_num_scbs == num_scbs 1147 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1148 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1149 fast = TRUE; 1150 1151 /* 1152 * See if we can use large SCBs and still maintain 1153 * the same overall count of SCBs. 1154 */ 1155 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1156 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1157 test_num_scbs = ahc_probe_scbs(ahc); 1158 if (test_num_scbs >= num_scbs) { 1159 large = TRUE; 1160 num_scbs = test_num_scbs; 1161 if (num_scbs >= 64) { 1162 /* 1163 * We have enough space to move the 1164 * "busy targets table" into SCB space 1165 * and make it qualify all the way to the 1166 * lun level. 1167 */ 1168 ahc->flags |= AHC_SCB_BTT; 1169 } 1170 } 1171 } 1172 done: 1173 /* 1174 * Disable parity error reporting until we 1175 * can load instruction ram. 1176 */ 1177 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1178 /* Clear any latched parity error */ 1179 ahc_outb(ahc, CLRINT, CLRPARERR); 1180 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1181 if (bootverbose && enable) { 1182 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1183 ahc_name(ahc), fast ? "fast" : "slow", 1184 pcheck ? ", parity checking enabled" : "", 1185 large ? 64 : 32); 1186 } 1187 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1188 } 1189 1190 /* 1191 * Check the external port logic for a serial eeprom 1192 * and termination/cable detection contrls. 1193 */ 1194 static void 1195 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1196 { 1197 struct seeprom_descriptor sd; 1198 struct seeprom_config *sc; 1199 int have_seeprom; 1200 int have_autoterm; 1201 1202 sd.sd_ahc = ahc; 1203 sd.sd_control_offset = SEECTL; 1204 sd.sd_status_offset = SEECTL; 1205 sd.sd_dataout_offset = SEECTL; 1206 sc = ahc->seep_config; 1207 1208 /* 1209 * For some multi-channel devices, the c46 is simply too 1210 * small to work. For the other controller types, we can 1211 * get our information from either SEEPROM type. Set the 1212 * type to start our probe with accordingly. 1213 */ 1214 if (ahc->flags & AHC_LARGE_SEEPROM) 1215 sd.sd_chip = C56_66; 1216 else 1217 sd.sd_chip = C46; 1218 1219 sd.sd_MS = SEEMS; 1220 sd.sd_RDY = SEERDY; 1221 sd.sd_CS = SEECS; 1222 sd.sd_CK = SEECK; 1223 sd.sd_DO = SEEDO; 1224 sd.sd_DI = SEEDI; 1225 1226 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1227 if (have_seeprom) { 1228 1229 if (bootverbose) 1230 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1231 1232 for (;;) { 1233 u_int start_addr; 1234 1235 start_addr = 32 * (ahc->channel - 'A'); 1236 1237 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1238 start_addr, 1239 sizeof(*sc)/2); 1240 1241 if (have_seeprom) 1242 have_seeprom = ahc_verify_cksum(sc); 1243 1244 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1245 if (bootverbose) { 1246 if (have_seeprom == 0) 1247 printf ("checksum error\n"); 1248 else 1249 printf ("done.\n"); 1250 } 1251 break; 1252 } 1253 sd.sd_chip = C56_66; 1254 } 1255 ahc_release_seeprom(&sd); 1256 } 1257 1258 if (!have_seeprom) { 1259 /* 1260 * Pull scratch ram settings and treat them as 1261 * if they are the contents of an seeprom if 1262 * the 'ADPT' signature is found in SCB2. 1263 * We manually compose the data as 16bit values 1264 * to avoid endian issues. 1265 */ 1266 ahc_outb(ahc, SCBPTR, 2); 1267 if (ahc_inb(ahc, SCB_BASE) == 'A' 1268 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1269 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1270 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1271 uint16_t *sc_data; 1272 int i; 1273 1274 sc_data = (uint16_t *)sc; 1275 for (i = 0; i < 32; i++, sc_data++) { 1276 int j; 1277 1278 j = i * 2; 1279 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1280 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1281 } 1282 have_seeprom = ahc_verify_cksum(sc); 1283 if (have_seeprom) 1284 ahc->flags |= AHC_SCB_CONFIG_USED; 1285 } 1286 /* 1287 * Clear any SCB parity errors in case this data and 1288 * its associated parity was not initialized by the BIOS 1289 */ 1290 ahc_outb(ahc, CLRINT, CLRPARERR); 1291 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1292 } 1293 1294 if (!have_seeprom) { 1295 if (bootverbose) 1296 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1297 ahc->flags |= AHC_USEDEFAULTS; 1298 free(ahc->seep_config, M_DEVBUF); 1299 ahc->seep_config = NULL; 1300 sc = NULL; 1301 } else { 1302 ahc_parse_pci_eeprom(ahc, sc); 1303 } 1304 1305 /* 1306 * Cards that have the external logic necessary to talk to 1307 * a SEEPROM, are almost certain to have the remaining logic 1308 * necessary for auto-termination control. This assumption 1309 * hasn't failed yet... 1310 */ 1311 have_autoterm = have_seeprom; 1312 1313 /* 1314 * Some low-cost chips have SEEPROM and auto-term control built 1315 * in, instead of using a GAL. They can tell us directly 1316 * if the termination logic is enabled. 1317 */ 1318 if ((ahc->features & AHC_SPIOCAP) != 0) { 1319 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1320 have_autoterm = FALSE; 1321 } 1322 1323 if (have_autoterm) { 1324 ahc_acquire_seeprom(ahc, &sd); 1325 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1326 ahc_release_seeprom(&sd); 1327 } else if (have_seeprom) { 1328 *sxfrctl1 &= ~STPWEN; 1329 if ((sc->adapter_control & CFSTERM) != 0) 1330 *sxfrctl1 |= STPWEN; 1331 if (bootverbose) 1332 printf("%s: Low byte termination %sabled\n", 1333 ahc_name(ahc), 1334 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1335 } 1336 } 1337 1338 static void 1339 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1340 { 1341 /* 1342 * Put the data we've collected down into SRAM 1343 * where ahc_init will find it. 1344 */ 1345 int i; 1346 int max_targ = sc->max_targets & CFMAXTARG; 1347 u_int scsi_conf; 1348 uint16_t discenable; 1349 uint16_t ultraenb; 1350 1351 discenable = 0; 1352 ultraenb = 0; 1353 if ((sc->adapter_control & CFULTRAEN) != 0) { 1354 /* 1355 * Determine if this adapter has a "newstyle" 1356 * SEEPROM format. 1357 */ 1358 for (i = 0; i < max_targ; i++) { 1359 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1360 ahc->flags |= AHC_NEWEEPROM_FMT; 1361 break; 1362 } 1363 } 1364 } 1365 1366 for (i = 0; i < max_targ; i++) { 1367 u_int scsirate; 1368 uint16_t target_mask; 1369 1370 target_mask = 0x01 << i; 1371 if (sc->device_flags[i] & CFDISC) 1372 discenable |= target_mask; 1373 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1374 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1375 ultraenb |= target_mask; 1376 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1377 ultraenb |= target_mask; 1378 } 1379 if ((sc->device_flags[i] & CFXFER) == 0x04 1380 && (ultraenb & target_mask) != 0) { 1381 /* Treat 10MHz as a non-ultra speed */ 1382 sc->device_flags[i] &= ~CFXFER; 1383 ultraenb &= ~target_mask; 1384 } 1385 if ((ahc->features & AHC_ULTRA2) != 0) { 1386 u_int offset; 1387 1388 if (sc->device_flags[i] & CFSYNCH) 1389 offset = MAX_OFFSET_ULTRA2; 1390 else 1391 offset = 0; 1392 ahc_outb(ahc, TARG_OFFSET + i, offset); 1393 1394 /* 1395 * The ultra enable bits contain the 1396 * high bit of the ultra2 sync rate 1397 * field. 1398 */ 1399 scsirate = (sc->device_flags[i] & CFXFER) 1400 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1401 if (sc->device_flags[i] & CFWIDEB) 1402 scsirate |= WIDEXFER; 1403 } else { 1404 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1405 if (sc->device_flags[i] & CFSYNCH) 1406 scsirate |= SOFS; 1407 if (sc->device_flags[i] & CFWIDEB) 1408 scsirate |= WIDEXFER; 1409 } 1410 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1411 } 1412 ahc->our_id = sc->brtime_id & CFSCSIID; 1413 1414 scsi_conf = (ahc->our_id & 0x7); 1415 if (sc->adapter_control & CFSPARITY) 1416 scsi_conf |= ENSPCHK; 1417 if (sc->adapter_control & CFRESETB) 1418 scsi_conf |= RESET_SCSI; 1419 1420 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1421 1422 if (sc->bios_control & CFEXTEND) 1423 ahc->flags |= AHC_EXTENDED_TRANS_A; 1424 1425 if (sc->bios_control & CFBIOSEN) 1426 ahc->flags |= AHC_BIOS_ENABLED; 1427 if (ahc->features & AHC_ULTRA 1428 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1429 /* Should we enable Ultra mode? */ 1430 if (!(sc->adapter_control & CFULTRAEN)) 1431 /* Treat us as a non-ultra card */ 1432 ultraenb = 0; 1433 } 1434 1435 if (sc->signature == CFSIGNATURE 1436 || sc->signature == CFSIGNATURE2) { 1437 uint32_t devconfig; 1438 1439 /* Honor the STPWLEVEL settings */ 1440 devconfig = ahc_pci_read_config(ahc->dev_softc, 1441 DEVCONFIG, /*bytes*/4); 1442 devconfig &= ~STPWLEVEL; 1443 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1444 devconfig |= STPWLEVEL; 1445 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1446 devconfig, /*bytes*/4); 1447 } 1448 /* Set SCSICONF info */ 1449 ahc_outb(ahc, SCSICONF, scsi_conf); 1450 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1451 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1452 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1453 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1454 } 1455 1456 static void 1457 configure_termination(struct ahc_softc *ahc, 1458 struct seeprom_descriptor *sd, 1459 u_int adapter_control, 1460 u_int *sxfrctl1) 1461 { 1462 uint8_t brddat; 1463 1464 brddat = 0; 1465 1466 /* 1467 * Update the settings in sxfrctl1 to match the 1468 * termination settings 1469 */ 1470 *sxfrctl1 = 0; 1471 1472 /* 1473 * SEECS must be on for the GALS to latch 1474 * the data properly. Be sure to leave MS 1475 * on or we will release the seeprom. 1476 */ 1477 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1478 if ((adapter_control & CFAUTOTERM) != 0 1479 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1480 int internal50_present; 1481 int internal68_present; 1482 int externalcable_present; 1483 int eeprom_present; 1484 int enableSEC_low; 1485 int enableSEC_high; 1486 int enablePRI_low; 1487 int enablePRI_high; 1488 int sum; 1489 1490 enableSEC_low = 0; 1491 enableSEC_high = 0; 1492 enablePRI_low = 0; 1493 enablePRI_high = 0; 1494 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1495 ahc_new_term_detect(ahc, &enableSEC_low, 1496 &enableSEC_high, 1497 &enablePRI_low, 1498 &enablePRI_high, 1499 &eeprom_present); 1500 if ((adapter_control & CFSEAUTOTERM) == 0) { 1501 if (bootverbose) 1502 printf("%s: Manual SE Termination\n", 1503 ahc_name(ahc)); 1504 enableSEC_low = (adapter_control & CFSELOWTERM); 1505 enableSEC_high = 1506 (adapter_control & CFSEHIGHTERM); 1507 } 1508 if ((adapter_control & CFAUTOTERM) == 0) { 1509 if (bootverbose) 1510 printf("%s: Manual LVD Termination\n", 1511 ahc_name(ahc)); 1512 enablePRI_low = (adapter_control & CFSTERM); 1513 enablePRI_high = (adapter_control & CFWSTERM); 1514 } 1515 /* Make the table calculations below happy */ 1516 internal50_present = 0; 1517 internal68_present = 1; 1518 externalcable_present = 1; 1519 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1520 aic785X_cable_detect(ahc, &internal50_present, 1521 &externalcable_present, 1522 &eeprom_present); 1523 /* Can never support a wide connector. */ 1524 internal68_present = 0; 1525 } else { 1526 aic787X_cable_detect(ahc, &internal50_present, 1527 &internal68_present, 1528 &externalcable_present, 1529 &eeprom_present); 1530 } 1531 1532 if ((ahc->features & AHC_WIDE) == 0) 1533 internal68_present = 0; 1534 1535 if (bootverbose 1536 && (ahc->features & AHC_ULTRA2) == 0) { 1537 printf("%s: internal 50 cable %s present", 1538 ahc_name(ahc), 1539 internal50_present ? "is":"not"); 1540 1541 if ((ahc->features & AHC_WIDE) != 0) 1542 printf(", internal 68 cable %s present", 1543 internal68_present ? "is":"not"); 1544 printf("\n%s: external cable %s present\n", 1545 ahc_name(ahc), 1546 externalcable_present ? "is":"not"); 1547 } 1548 if (bootverbose) 1549 printf("%s: BIOS eeprom %s present\n", 1550 ahc_name(ahc), eeprom_present ? "is" : "not"); 1551 1552 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1553 /* 1554 * The 50 pin connector is a separate bus, 1555 * so force it to always be terminated. 1556 * In the future, perform current sensing 1557 * to determine if we are in the middle of 1558 * a properly terminated bus. 1559 */ 1560 internal50_present = 0; 1561 } 1562 1563 /* 1564 * Now set the termination based on what 1565 * we found. 1566 * Flash Enable = BRDDAT7 1567 * Secondary High Term Enable = BRDDAT6 1568 * Secondary Low Term Enable = BRDDAT5 (7890) 1569 * Primary High Term Enable = BRDDAT4 (7890) 1570 */ 1571 if ((ahc->features & AHC_ULTRA2) == 0 1572 && (internal50_present != 0) 1573 && (internal68_present != 0) 1574 && (externalcable_present != 0)) { 1575 printf("%s: Illegal cable configuration!!. " 1576 "Only two connectors on the " 1577 "adapter may be used at a " 1578 "time!\n", ahc_name(ahc)); 1579 1580 /* 1581 * Pretend there are no cables in the hope 1582 * that having all of the termination on 1583 * gives us a more stable bus. 1584 */ 1585 internal50_present = 0; 1586 internal68_present = 0; 1587 externalcable_present = 0; 1588 } 1589 1590 if ((ahc->features & AHC_WIDE) != 0 1591 && ((externalcable_present == 0) 1592 || (internal68_present == 0) 1593 || (enableSEC_high != 0))) { 1594 brddat |= BRDDAT6; 1595 if (bootverbose) { 1596 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1597 printf("%s: 68 pin termination " 1598 "Enabled\n", ahc_name(ahc)); 1599 else 1600 printf("%s: %sHigh byte termination " 1601 "Enabled\n", ahc_name(ahc), 1602 enableSEC_high ? "Secondary " 1603 : ""); 1604 } 1605 } 1606 1607 sum = internal50_present + internal68_present 1608 + externalcable_present; 1609 if (sum < 2 || (enableSEC_low != 0)) { 1610 if ((ahc->features & AHC_ULTRA2) != 0) 1611 brddat |= BRDDAT5; 1612 else 1613 *sxfrctl1 |= STPWEN; 1614 if (bootverbose) { 1615 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1616 printf("%s: 50 pin termination " 1617 "Enabled\n", ahc_name(ahc)); 1618 else 1619 printf("%s: %sLow byte termination " 1620 "Enabled\n", ahc_name(ahc), 1621 enableSEC_low ? "Secondary " 1622 : ""); 1623 } 1624 } 1625 1626 if (enablePRI_low != 0) { 1627 *sxfrctl1 |= STPWEN; 1628 if (bootverbose) 1629 printf("%s: Primary Low Byte termination " 1630 "Enabled\n", ahc_name(ahc)); 1631 } 1632 1633 /* 1634 * Setup STPWEN before setting up the rest of 1635 * the termination per the tech note on the U160 cards. 1636 */ 1637 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1638 1639 if (enablePRI_high != 0) { 1640 brddat |= BRDDAT4; 1641 if (bootverbose) 1642 printf("%s: Primary High Byte " 1643 "termination Enabled\n", 1644 ahc_name(ahc)); 1645 } 1646 1647 write_brdctl(ahc, brddat); 1648 1649 } else { 1650 if ((adapter_control & CFSTERM) != 0) { 1651 *sxfrctl1 |= STPWEN; 1652 1653 if (bootverbose) 1654 printf("%s: %sLow byte termination Enabled\n", 1655 ahc_name(ahc), 1656 (ahc->features & AHC_ULTRA2) ? "Primary " 1657 : ""); 1658 } 1659 1660 if ((adapter_control & CFWSTERM) != 0 1661 && (ahc->features & AHC_WIDE) != 0) { 1662 brddat |= BRDDAT6; 1663 if (bootverbose) 1664 printf("%s: %sHigh byte termination Enabled\n", 1665 ahc_name(ahc), 1666 (ahc->features & AHC_ULTRA2) 1667 ? "Secondary " : ""); 1668 } 1669 1670 /* 1671 * Setup STPWEN before setting up the rest of 1672 * the termination per the tech note on the U160 cards. 1673 */ 1674 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1675 1676 if ((ahc->features & AHC_WIDE) != 0) 1677 write_brdctl(ahc, brddat); 1678 } 1679 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1680 } 1681 1682 static void 1683 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1684 int *enableSEC_high, int *enablePRI_low, 1685 int *enablePRI_high, int *eeprom_present) 1686 { 1687 uint8_t brdctl; 1688 1689 /* 1690 * BRDDAT7 = Eeprom 1691 * BRDDAT6 = Enable Secondary High Byte termination 1692 * BRDDAT5 = Enable Secondary Low Byte termination 1693 * BRDDAT4 = Enable Primary high byte termination 1694 * BRDDAT3 = Enable Primary low byte termination 1695 */ 1696 brdctl = read_brdctl(ahc); 1697 *eeprom_present = brdctl & BRDDAT7; 1698 *enableSEC_high = (brdctl & BRDDAT6); 1699 *enableSEC_low = (brdctl & BRDDAT5); 1700 *enablePRI_high = (brdctl & BRDDAT4); 1701 *enablePRI_low = (brdctl & BRDDAT3); 1702 } 1703 1704 static void 1705 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1706 int *internal68_present, int *externalcable_present, 1707 int *eeprom_present) 1708 { 1709 uint8_t brdctl; 1710 1711 /* 1712 * First read the status of our cables. 1713 * Set the rom bank to 0 since the 1714 * bank setting serves as a multiplexor 1715 * for the cable detection logic. 1716 * BRDDAT5 controls the bank switch. 1717 */ 1718 write_brdctl(ahc, 0); 1719 1720 /* 1721 * Now read the state of the internal 1722 * connectors. BRDDAT6 is INT50 and 1723 * BRDDAT7 is INT68. 1724 */ 1725 brdctl = read_brdctl(ahc); 1726 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1727 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1728 1729 /* 1730 * Set the rom bank to 1 and determine 1731 * the other signals. 1732 */ 1733 write_brdctl(ahc, BRDDAT5); 1734 1735 /* 1736 * Now read the state of the external 1737 * connectors. BRDDAT6 is EXT68 and 1738 * BRDDAT7 is EPROMPS. 1739 */ 1740 brdctl = read_brdctl(ahc); 1741 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1742 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1743 } 1744 1745 static void 1746 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1747 int *externalcable_present, int *eeprom_present) 1748 { 1749 uint8_t brdctl; 1750 uint8_t spiocap; 1751 1752 spiocap = ahc_inb(ahc, SPIOCAP); 1753 spiocap &= ~SOFTCMDEN; 1754 spiocap |= EXT_BRDCTL; 1755 ahc_outb(ahc, SPIOCAP, spiocap); 1756 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1757 ahc_outb(ahc, BRDCTL, 0); 1758 brdctl = ahc_inb(ahc, BRDCTL); 1759 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1760 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1761 1762 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1763 } 1764 1765 int 1766 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1767 { 1768 int wait; 1769 1770 if ((ahc->features & AHC_SPIOCAP) != 0 1771 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1772 return (0); 1773 1774 /* 1775 * Request access of the memory port. When access is 1776 * granted, SEERDY will go high. We use a 1 second 1777 * timeout which should be near 1 second more than 1778 * is needed. Reason: after the chip reset, there 1779 * should be no contention. 1780 */ 1781 SEEPROM_OUTB(sd, sd->sd_MS); 1782 wait = 1000; /* 1 second timeout in msec */ 1783 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1784 ahc_delay(1000); /* delay 1 msec */ 1785 } 1786 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1787 SEEPROM_OUTB(sd, 0); 1788 return (0); 1789 } 1790 return(1); 1791 } 1792 1793 void 1794 ahc_release_seeprom(struct seeprom_descriptor *sd) 1795 { 1796 /* Release access to the memory port and the serial EEPROM. */ 1797 SEEPROM_OUTB(sd, 0); 1798 } 1799 1800 static void 1801 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1802 { 1803 uint8_t brdctl; 1804 1805 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1806 brdctl = BRDSTB; 1807 if (ahc->channel == 'B') 1808 brdctl |= BRDCS; 1809 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1810 brdctl = 0; 1811 } else { 1812 brdctl = BRDSTB|BRDCS; 1813 } 1814 ahc_outb(ahc, BRDCTL, brdctl); 1815 ahc_flush_device_writes(ahc); 1816 brdctl |= value; 1817 ahc_outb(ahc, BRDCTL, brdctl); 1818 ahc_flush_device_writes(ahc); 1819 if ((ahc->features & AHC_ULTRA2) != 0) 1820 brdctl |= BRDSTB_ULTRA2; 1821 else 1822 brdctl &= ~BRDSTB; 1823 ahc_outb(ahc, BRDCTL, brdctl); 1824 ahc_flush_device_writes(ahc); 1825 if ((ahc->features & AHC_ULTRA2) != 0) 1826 brdctl = 0; 1827 else 1828 brdctl &= ~BRDCS; 1829 ahc_outb(ahc, BRDCTL, brdctl); 1830 } 1831 1832 static uint8_t 1833 read_brdctl(ahc) 1834 struct ahc_softc *ahc; 1835 { 1836 uint8_t brdctl; 1837 uint8_t value; 1838 1839 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1840 brdctl = BRDRW; 1841 if (ahc->channel == 'B') 1842 brdctl |= BRDCS; 1843 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1844 brdctl = BRDRW_ULTRA2; 1845 } else { 1846 brdctl = BRDRW|BRDCS; 1847 } 1848 ahc_outb(ahc, BRDCTL, brdctl); 1849 ahc_flush_device_writes(ahc); 1850 value = ahc_inb(ahc, BRDCTL); 1851 ahc_outb(ahc, BRDCTL, 0); 1852 return (value); 1853 } 1854 1855 #define DPE 0x80 1856 #define SSE 0x40 1857 #define RMA 0x20 1858 #define RTA 0x10 1859 #define STA 0x08 1860 #define DPR 0x01 1861 1862 void 1863 ahc_pci_intr(struct ahc_softc *ahc) 1864 { 1865 u_int error; 1866 u_int status1; 1867 1868 error = ahc_inb(ahc, ERROR); 1869 if ((error & PCIERRSTAT) == 0) 1870 return; 1871 1872 status1 = ahc_pci_read_config(ahc->dev_softc, 1873 PCIR_STATUS + 1, /*bytes*/1); 1874 1875 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1876 ahc_name(ahc), 1877 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1878 1879 if (status1 & DPE) { 1880 printf("%s: Data Parity Error Detected during address " 1881 "or write data phase\n", ahc_name(ahc)); 1882 } 1883 if (status1 & SSE) { 1884 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1885 } 1886 if (status1 & RMA) { 1887 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1888 } 1889 if (status1 & RTA) { 1890 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1891 } 1892 if (status1 & STA) { 1893 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1894 } 1895 if (status1 & DPR) { 1896 printf("%s: Data Parity Error has been reported via PERR#\n", 1897 ahc_name(ahc)); 1898 } 1899 1900 /* Clear latched errors. */ 1901 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1902 status1, /*bytes*/1); 1903 1904 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1905 printf("%s: Latched PCIERR interrupt with " 1906 "no status bits set\n", ahc_name(ahc)); 1907 } else { 1908 ahc_outb(ahc, CLRINT, CLRPARERR); 1909 } 1910 1911 ahc_unpause(ahc); 1912 } 1913 1914 static int 1915 ahc_aic785X_setup(struct ahc_softc *ahc) 1916 { 1917 ahc_dev_softc_t pci; 1918 uint8_t rev; 1919 1920 pci = ahc->dev_softc; 1921 ahc->channel = 'A'; 1922 ahc->chip = AHC_AIC7850; 1923 ahc->features = AHC_AIC7850_FE; 1924 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1925 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1926 if (rev >= 1) 1927 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1928 return (0); 1929 } 1930 1931 static int 1932 ahc_aic7860_setup(struct ahc_softc *ahc) 1933 { 1934 ahc_dev_softc_t pci; 1935 uint8_t rev; 1936 1937 pci = ahc->dev_softc; 1938 ahc->channel = 'A'; 1939 ahc->chip = AHC_AIC7860; 1940 ahc->features = AHC_AIC7860_FE; 1941 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1942 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1943 if (rev >= 1) 1944 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1945 return (0); 1946 } 1947 1948 static int 1949 ahc_apa1480_setup(struct ahc_softc *ahc) 1950 { 1951 int error; 1952 1953 error = ahc_aic7860_setup(ahc); 1954 if (error != 0) 1955 return (error); 1956 ahc->features |= AHC_REMOVABLE; 1957 return (0); 1958 } 1959 1960 static int 1961 ahc_aic7870_setup(struct ahc_softc *ahc) 1962 { 1963 1964 ahc->channel = 'A'; 1965 ahc->chip = AHC_AIC7870; 1966 ahc->features = AHC_AIC7870_FE; 1967 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1968 return (0); 1969 } 1970 1971 static int 1972 ahc_aha394X_setup(struct ahc_softc *ahc) 1973 { 1974 int error; 1975 1976 error = ahc_aic7870_setup(ahc); 1977 if (error == 0) 1978 error = ahc_aha394XX_setup(ahc); 1979 return (error); 1980 } 1981 1982 static int 1983 ahc_aha398X_setup(struct ahc_softc *ahc) 1984 { 1985 int error; 1986 1987 error = ahc_aic7870_setup(ahc); 1988 if (error == 0) 1989 error = ahc_aha398XX_setup(ahc); 1990 return (error); 1991 } 1992 1993 static int 1994 ahc_aha494X_setup(struct ahc_softc *ahc) 1995 { 1996 int error; 1997 1998 error = ahc_aic7870_setup(ahc); 1999 if (error == 0) 2000 error = ahc_aha494XX_setup(ahc); 2001 return (error); 2002 } 2003 2004 static int 2005 ahc_aic7880_setup(struct ahc_softc *ahc) 2006 { 2007 ahc_dev_softc_t pci; 2008 uint8_t rev; 2009 2010 pci = ahc->dev_softc; 2011 ahc->channel = 'A'; 2012 ahc->chip = AHC_AIC7880; 2013 ahc->features = AHC_AIC7880_FE; 2014 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2015 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2016 if (rev >= 1) { 2017 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2018 } else { 2019 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2020 } 2021 return (0); 2022 } 2023 2024 static int 2025 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2026 { 2027 2028 ahc->flags |= AHC_INT50_SPEEDFLEX; 2029 return (ahc_aic7880_setup(ahc)); 2030 } 2031 2032 static int 2033 ahc_aha394XU_setup(struct ahc_softc *ahc) 2034 { 2035 int error; 2036 2037 error = ahc_aic7880_setup(ahc); 2038 if (error == 0) 2039 error = ahc_aha394XX_setup(ahc); 2040 return (error); 2041 } 2042 2043 static int 2044 ahc_aha398XU_setup(struct ahc_softc *ahc) 2045 { 2046 int error; 2047 2048 error = ahc_aic7880_setup(ahc); 2049 if (error == 0) 2050 error = ahc_aha398XX_setup(ahc); 2051 return (error); 2052 } 2053 2054 static int 2055 ahc_aic7890_setup(struct ahc_softc *ahc) 2056 { 2057 ahc_dev_softc_t pci; 2058 uint8_t rev; 2059 2060 pci = ahc->dev_softc; 2061 ahc->channel = 'A'; 2062 ahc->chip = AHC_AIC7890; 2063 ahc->features = AHC_AIC7890_FE; 2064 ahc->flags |= AHC_NEWEEPROM_FMT; 2065 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2066 if (rev == 0) 2067 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2068 return (0); 2069 } 2070 2071 static int 2072 ahc_aic7892_setup(struct ahc_softc *ahc) 2073 { 2074 2075 ahc->channel = 'A'; 2076 ahc->chip = AHC_AIC7892; 2077 ahc->features = AHC_AIC7892_FE; 2078 ahc->flags |= AHC_NEWEEPROM_FMT; 2079 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2080 return (0); 2081 } 2082 2083 static int 2084 ahc_aic7895_setup(struct ahc_softc *ahc) 2085 { 2086 ahc_dev_softc_t pci; 2087 uint8_t rev; 2088 2089 pci = ahc->dev_softc; 2090 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2091 /* 2092 * The 'C' revision of the aic7895 has a few additional features. 2093 */ 2094 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2095 if (rev >= 4) { 2096 ahc->chip = AHC_AIC7895C; 2097 ahc->features = AHC_AIC7895C_FE; 2098 } else { 2099 u_int command; 2100 2101 ahc->chip = AHC_AIC7895; 2102 ahc->features = AHC_AIC7895_FE; 2103 2104 /* 2105 * The BIOS disables the use of MWI transactions 2106 * since it does not have the MWI bug work around 2107 * we have. Disabling MWI reduces performance, so 2108 * turn it on again. 2109 */ 2110 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2111 command |= PCIM_CMD_MWRICEN; 2112 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2113 ahc->bugs |= AHC_PCI_MWI_BUG; 2114 } 2115 /* 2116 * XXX Does CACHETHEN really not work??? What about PCI retry? 2117 * on C level chips. Need to test, but for now, play it safe. 2118 */ 2119 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2120 | AHC_CACHETHEN_BUG; 2121 2122 #if 0 2123 uint32_t devconfig; 2124 2125 /* 2126 * Cachesize must also be zero due to stray DAC 2127 * problem when sitting behind some bridges. 2128 */ 2129 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2130 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2131 devconfig |= MRDCEN; 2132 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2133 #endif 2134 ahc->flags |= AHC_NEWEEPROM_FMT; 2135 return (0); 2136 } 2137 2138 static int 2139 ahc_aic7896_setup(struct ahc_softc *ahc) 2140 { 2141 ahc_dev_softc_t pci; 2142 2143 pci = ahc->dev_softc; 2144 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2145 ahc->chip = AHC_AIC7896; 2146 ahc->features = AHC_AIC7896_FE; 2147 ahc->flags |= AHC_NEWEEPROM_FMT; 2148 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2149 return (0); 2150 } 2151 2152 static int 2153 ahc_aic7899_setup(struct ahc_softc *ahc) 2154 { 2155 ahc_dev_softc_t pci; 2156 2157 pci = ahc->dev_softc; 2158 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2159 ahc->chip = AHC_AIC7899; 2160 ahc->features = AHC_AIC7899_FE; 2161 ahc->flags |= AHC_NEWEEPROM_FMT; 2162 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2163 return (0); 2164 } 2165 2166 static int 2167 ahc_aha29160C_setup(struct ahc_softc *ahc) 2168 { 2169 int error; 2170 2171 error = ahc_aic7899_setup(ahc); 2172 if (error != 0) 2173 return (error); 2174 ahc->features |= AHC_REMOVABLE; 2175 return (0); 2176 } 2177 2178 static int 2179 ahc_raid_setup(struct ahc_softc *ahc) 2180 { 2181 printf("RAID functionality unsupported\n"); 2182 return (ENXIO); 2183 } 2184 2185 static int 2186 ahc_aha394XX_setup(struct ahc_softc *ahc) 2187 { 2188 ahc_dev_softc_t pci; 2189 2190 pci = ahc->dev_softc; 2191 switch (ahc_get_pci_slot(pci)) { 2192 case AHC_394X_SLOT_CHANNEL_A: 2193 ahc->channel = 'A'; 2194 break; 2195 case AHC_394X_SLOT_CHANNEL_B: 2196 ahc->channel = 'B'; 2197 break; 2198 default: 2199 printf("adapter at unexpected slot %d\n" 2200 "unable to map to a channel\n", 2201 ahc_get_pci_slot(pci)); 2202 ahc->channel = 'A'; 2203 } 2204 return (0); 2205 } 2206 2207 static int 2208 ahc_aha398XX_setup(struct ahc_softc *ahc) 2209 { 2210 ahc_dev_softc_t pci; 2211 2212 pci = ahc->dev_softc; 2213 switch (ahc_get_pci_slot(pci)) { 2214 case AHC_398X_SLOT_CHANNEL_A: 2215 ahc->channel = 'A'; 2216 break; 2217 case AHC_398X_SLOT_CHANNEL_B: 2218 ahc->channel = 'B'; 2219 break; 2220 case AHC_398X_SLOT_CHANNEL_C: 2221 ahc->channel = 'C'; 2222 break; 2223 default: 2224 printf("adapter at unexpected slot %d\n" 2225 "unable to map to a channel\n", 2226 ahc_get_pci_slot(pci)); 2227 ahc->channel = 'A'; 2228 break; 2229 } 2230 ahc->flags |= AHC_LARGE_SEEPROM; 2231 return (0); 2232 } 2233 2234 static int 2235 ahc_aha494XX_setup(struct ahc_softc *ahc) 2236 { 2237 ahc_dev_softc_t pci; 2238 2239 pci = ahc->dev_softc; 2240 switch (ahc_get_pci_slot(pci)) { 2241 case AHC_494X_SLOT_CHANNEL_A: 2242 ahc->channel = 'A'; 2243 break; 2244 case AHC_494X_SLOT_CHANNEL_B: 2245 ahc->channel = 'B'; 2246 break; 2247 case AHC_494X_SLOT_CHANNEL_C: 2248 ahc->channel = 'C'; 2249 break; 2250 case AHC_494X_SLOT_CHANNEL_D: 2251 ahc->channel = 'D'; 2252 break; 2253 default: 2254 printf("adapter at unexpected slot %d\n" 2255 "unable to map to a channel\n", 2256 ahc_get_pci_slot(pci)); 2257 ahc->channel = 'A'; 2258 } 2259 ahc->flags |= AHC_LARGE_SEEPROM; 2260 return (0); 2261 } 2262