1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id$ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 59 60 static __inline uint64_t 61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 77 #define ID_9005_SISL_ID 0x0005900500000000ull 78 #define ID_AIC7850 0x5078900400000000ull 79 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 80 #define ID_AIC7855 0x5578900400000000ull 81 #define ID_AIC7859 0x3860900400000000ull 82 #define ID_AHA_2930CU 0x3860900438699004ull 83 #define ID_AIC7860 0x6078900400000000ull 84 #define ID_AIC7860C 0x6078900478609004ull 85 #define ID_AHA_1480A 0x6075900400000000ull 86 #define ID_AHA_2940AU_0 0x6178900400000000ull 87 #define ID_AHA_2940AU_1 0x6178900478619004ull 88 #define ID_AHA_2940AU_CN 0x2178900478219004ull 89 #define ID_AHA_2930C_VAR 0x6038900438689004ull 90 91 #define ID_AIC7870 0x7078900400000000ull 92 #define ID_AHA_2940 0x7178900400000000ull 93 #define ID_AHA_3940 0x7278900400000000ull 94 #define ID_AHA_398X 0x7378900400000000ull 95 #define ID_AHA_2944 0x7478900400000000ull 96 #define ID_AHA_3944 0x7578900400000000ull 97 #define ID_AHA_4944 0x7678900400000000ull 98 99 #define ID_AIC7880 0x8078900400000000ull 100 #define ID_AIC7880_B 0x8078900478809004ull 101 #define ID_AHA_2940U 0x8178900400000000ull 102 #define ID_AHA_3940U 0x8278900400000000ull 103 #define ID_AHA_2944U 0x8478900400000000ull 104 #define ID_AHA_3944U 0x8578900400000000ull 105 #define ID_AHA_398XU 0x8378900400000000ull 106 #define ID_AHA_4944U 0x8678900400000000ull 107 #define ID_AHA_2940UB 0x8178900478819004ull 108 #define ID_AHA_2930U 0x8878900478889004ull 109 #define ID_AHA_2940U_PRO 0x8778900478879004ull 110 #define ID_AHA_2940U_CN 0x0078900478009004ull 111 112 #define ID_AIC7895 0x7895900478959004ull 113 #define ID_AIC7895_ARO 0x7890900478939004ull 114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 116 #define ID_AHA_3940AU 0x7895900478929004ull 117 #define ID_AHA_3944AU 0x7895900478949004ull 118 119 #define ID_AIC7890 0x001F9005000F9005ull 120 #define ID_AIC7890_ARO 0x00139005000F9005ull 121 #define ID_AAA_131U2 0x0013900500039005ull 122 #define ID_AHA_2930U2 0x0011900501819005ull 123 #define ID_AHA_2940U2B 0x00109005A1009005ull 124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 125 #define ID_AHA_2940U2 0x00109005A1809005ull 126 #define ID_AHA_2950U2B 0x00109005E1009005ull 127 128 #define ID_AIC7892 0x008F9005FFFF9005ull 129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 130 #define ID_AHA_29160 0x00809005E2A09005ull 131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132 #define ID_AHA_29160N 0x0080900562A09005ull 133 #define ID_AHA_29160C 0x0080900562209005ull 134 #define ID_AHA_29160B 0x00809005E2209005ull 135 #define ID_AHA_19160B 0x0081900562A19005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 /* aic7895 based controllers */ 474 { 475 ID_AHA_2940U_DUAL, 476 ID_ALL_MASK, 477 "Adaptec 2940/DUAL Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AHA_3940AU, 482 ID_ALL_MASK, 483 "Adaptec 3940A Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3944AU, 488 ID_ALL_MASK, 489 "Adaptec 3944A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_ARO, 494 ID_AIC7895_ARO_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 496 ahc_aic7895_setup 497 }, 498 /* aic7896/97 based controllers */ 499 { 500 ID_AHA_3950U2B_0, 501 ID_ALL_MASK, 502 "Adaptec 3950B Ultra2 SCSI adapter", 503 ahc_aic7896_setup 504 }, 505 { 506 ID_AHA_3950U2B_1, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2D_0, 513 ID_ALL_MASK, 514 "Adaptec 3950D Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_1, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AIC7896_ARO, 525 ID_ALL_MASK, 526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 527 ahc_aic7896_setup 528 }, 529 /* aic7899 based controllers */ 530 { 531 ID_AHA_3960D, 532 ID_ALL_MASK, 533 "Adaptec 3960D Ultra160 SCSI adapter", 534 ahc_aic7899_setup 535 }, 536 { 537 ID_AHA_3960D_CPQ, 538 ID_ALL_MASK, 539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AIC7899_ARO, 544 ID_ALL_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 546 ahc_aic7899_setup 547 }, 548 /* Generic chip probes for devices we don't know 'exactly' */ 549 { 550 ID_AIC7850 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7850 SCSI adapter", 553 ahc_aic785X_setup 554 }, 555 { 556 ID_AIC7855 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7855 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7859 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7859 SCSI adapter", 565 ahc_aic7860_setup 566 }, 567 { 568 ID_AIC7860 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7860 Ultra SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7870 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7870 SCSI adapter", 577 ahc_aic7870_setup 578 }, 579 { 580 ID_AIC7880 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7880 Ultra SCSI adapter", 583 ahc_aic7880_setup 584 }, 585 { 586 ID_AIC7890 & ID_9005_GENERIC_MASK, 587 ID_9005_GENERIC_MASK, 588 "Adaptec aic7890/91 Ultra2 SCSI adapter", 589 ahc_aic7890_setup 590 }, 591 { 592 ID_AIC7892 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7892 Ultra160 SCSI adapter", 595 ahc_aic7892_setup 596 }, 597 { 598 ID_AIC7895 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7895 Ultra SCSI adapter", 601 ahc_aic7895_setup 602 }, 603 { 604 ID_AIC7896 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7896/97 Ultra2 SCSI adapter", 607 ahc_aic7896_setup 608 }, 609 { 610 ID_AIC7899 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7899 Ultra160 SCSI adapter", 613 ahc_aic7899_setup 614 }, 615 { 616 ID_AIC7810 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7810 RAID memory controller", 619 ahc_raid_setup 620 }, 621 { 622 ID_AIC7815 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7815 RAID memory controller", 625 ahc_raid_setup 626 } 627 }; 628 629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 630 631 #define AHC_394X_SLOT_CHANNEL_A 4 632 #define AHC_394X_SLOT_CHANNEL_B 5 633 634 #define AHC_398X_SLOT_CHANNEL_A 4 635 #define AHC_398X_SLOT_CHANNEL_B 8 636 #define AHC_398X_SLOT_CHANNEL_C 12 637 638 #define AHC_494X_SLOT_CHANNEL_A 4 639 #define AHC_494X_SLOT_CHANNEL_B 5 640 #define AHC_494X_SLOT_CHANNEL_C 6 641 #define AHC_494X_SLOT_CHANNEL_D 7 642 643 #define DEVCONFIG 0x40 644 #define PCIERRGENDIS 0x80000000ul 645 #define SCBSIZE32 0x00010000ul /* aic789X only */ 646 #define REXTVALID 0x00001000ul /* ultra cards only */ 647 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 648 #define RAMPSM 0x00000200ul /* aic7870+ only */ 649 #define VOLSENSE 0x00000100ul 650 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 651 #define SCBRAMSEL 0x00000080ul 652 #define MRDCEN 0x00000040ul 653 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 654 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 655 #define BERREN 0x00000008ul 656 #define DACEN 0x00000004ul 657 #define STPWLEVEL 0x00000002ul 658 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 659 660 #define CSIZE_LATTIME 0x0c 661 #define CACHESIZE 0x0000003ful /* only 5 bits */ 662 #define LATTIME 0x0000ff00ul 663 664 /* PCI STATUS definitions */ 665 #define DPE 0x80 666 #define SSE 0x40 667 #define RMA 0x20 668 #define RTA 0x10 669 #define STA 0x08 670 #define DPR 0x01 671 672 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 673 uint16_t subvendor, uint16_t subdevice); 674 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 675 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 676 int pcheck, int fast, int large); 677 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 678 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 679 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 680 struct seeprom_config *sc); 681 static void configure_termination(struct ahc_softc *ahc, 682 struct seeprom_descriptor *sd, 683 u_int adapter_control, 684 u_int *sxfrctl1); 685 686 static void ahc_new_term_detect(struct ahc_softc *ahc, 687 int *enableSEC_low, 688 int *enableSEC_high, 689 int *enablePRI_low, 690 int *enablePRI_high, 691 int *eeprom_present); 692 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 693 int *internal68_present, 694 int *externalcable_present, 695 int *eeprom_present); 696 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 697 int *externalcable_present, 698 int *eeprom_present); 699 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 700 static uint8_t read_brdctl(struct ahc_softc *ahc); 701 static void ahc_pci_intr(struct ahc_softc *ahc); 702 static int ahc_pci_chip_init(struct ahc_softc *ahc); 703 static int ahc_pci_suspend(struct ahc_softc *ahc); 704 static int ahc_pci_resume(struct ahc_softc *ahc); 705 706 static int 707 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 708 uint16_t subdevice, uint16_t subvendor) 709 { 710 int result; 711 712 /* Default to invalid. */ 713 result = 0; 714 if (vendor == 0x9005 715 && subvendor == 0x9005 716 && subdevice != device 717 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 718 719 switch (SUBID_9005_TYPE(subdevice)) { 720 case SUBID_9005_TYPE_MB: 721 break; 722 case SUBID_9005_TYPE_CARD: 723 case SUBID_9005_TYPE_LCCARD: 724 /* 725 * Currently only trust Adaptec cards to 726 * get the sub device info correct. 727 */ 728 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 729 result = 1; 730 break; 731 case SUBID_9005_TYPE_RAID: 732 break; 733 default: 734 break; 735 } 736 } 737 return (result); 738 } 739 740 struct ahc_pci_identity * 741 ahc_find_pci_device(ahc_dev_softc_t pci) 742 { 743 uint64_t full_id; 744 uint16_t device; 745 uint16_t vendor; 746 uint16_t subdevice; 747 uint16_t subvendor; 748 struct ahc_pci_identity *entry; 749 u_int i; 750 751 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 752 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 753 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 754 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 755 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 756 757 /* 758 * If the second function is not hooked up, ignore it. 759 * Unfortunately, not all MB vendors implement the 760 * subdevice ID as per the Adaptec spec, so do our best 761 * to sanity check it prior to accepting the subdevice 762 * ID as valid. 763 */ 764 if (ahc_get_pci_function(pci) > 0 765 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 766 && SUBID_9005_MFUNCENB(subdevice) == 0) 767 return (NULL); 768 769 for (i = 0; i < ahc_num_pci_devs; i++) { 770 entry = &ahc_pci_ident_table[i]; 771 if (entry->full_id == (full_id & entry->id_mask)) { 772 /* Honor exclusion entries. */ 773 if (entry->name == NULL) 774 return (NULL); 775 return (entry); 776 } 777 } 778 return (NULL); 779 } 780 781 int 782 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 783 { 784 u_long l; 785 u_int command; 786 u_int our_id; 787 u_int sxfrctl1; 788 u_int scsiseq; 789 u_int dscommand0; 790 uint32_t devconfig; 791 int error; 792 uint8_t sblkctl; 793 794 our_id = 0; 795 error = entry->setup(ahc); 796 if (error != 0) 797 return (error); 798 ahc->chip |= AHC_PCI; 799 ahc->description = entry->name; 800 801 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 802 803 error = ahc_pci_map_registers(ahc); 804 if (error != 0) 805 return (error); 806 807 /* 808 * Before we continue probing the card, ensure that 809 * its interrupts are *disabled*. We don't want 810 * a misstep to hang the machine in an interrupt 811 * storm. 812 */ 813 ahc_intr_enable(ahc, FALSE); 814 815 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 816 817 /* 818 * If we need to support high memory, enable dual 819 * address cycles. This bit must be set to enable 820 * high address bit generation even if we are on a 821 * 64bit bus (PCI64BIT set in devconfig). 822 */ 823 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 824 825 if (bootverbose) 826 printf("%s: Enabling 39Bit Addressing\n", 827 ahc_name(ahc)); 828 devconfig |= DACEN; 829 } 830 831 /* Ensure that pci error generation, a test feature, is disabled. */ 832 devconfig |= PCIERRGENDIS; 833 834 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 835 836 /* Ensure busmastering is enabled */ 837 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 838 command |= PCIM_CMD_BUSMASTEREN; 839 840 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 841 842 /* On all PCI adapters, we allow SCB paging */ 843 ahc->flags |= AHC_PAGESCBS; 844 845 error = ahc_softc_init(ahc); 846 if (error != 0) 847 return (error); 848 849 /* 850 * Disable PCI parity error checking. Users typically 851 * do this to work around broken PCI chipsets that get 852 * the parity timing wrong and thus generate lots of spurious 853 * errors. The chip only allows us to disable *all* parity 854 * error reporting when doing this, so CIO bus, scb ram, and 855 * scratch ram parity errors will be ignored too. 856 */ 857 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) { 858 ahc->pause |= FAILDIS; 859 ahc->unpause |= FAILDIS; 860 } 861 862 ahc->bus_intr = ahc_pci_intr; 863 ahc->bus_chip_init = ahc_pci_chip_init; 864 ahc->bus_suspend = ahc_pci_suspend; 865 ahc->bus_resume = ahc_pci_resume; 866 867 /* Remeber how the card was setup in case there is no SEEPROM */ 868 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 869 ahc_pause(ahc); 870 if ((ahc->features & AHC_ULTRA2) != 0) 871 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 872 else 873 our_id = ahc_inb(ahc, SCSIID) & OID; 874 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 875 scsiseq = ahc_inb(ahc, SCSISEQ); 876 } else { 877 sxfrctl1 = STPWEN; 878 our_id = 7; 879 scsiseq = 0; 880 } 881 882 error = ahc_reset(ahc); 883 if (error != 0) 884 return (ENXIO); 885 886 if ((ahc->features & AHC_DT) != 0) { 887 u_int sfunct; 888 889 /* Perform ALT-Mode Setup */ 890 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 891 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 892 ahc_outb(ahc, OPTIONMODE, 893 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 894 ahc_outb(ahc, SFUNCT, sfunct); 895 896 /* Normal mode setup */ 897 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 898 |TARGCRCENDEN); 899 } 900 901 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 902 dscommand0 |= MPARCKEN|CACHETHEN; 903 if ((ahc->features & AHC_ULTRA2) != 0) { 904 905 /* 906 * DPARCKEN doesn't work correctly on 907 * some MBs so don't use it. 908 */ 909 dscommand0 &= ~DPARCKEN; 910 } 911 912 /* 913 * Handle chips that must have cache line 914 * streaming (dis/en)abled. 915 */ 916 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 917 dscommand0 |= CACHETHEN; 918 919 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 920 dscommand0 &= ~CACHETHEN; 921 922 ahc_outb(ahc, DSCOMMAND0, dscommand0); 923 924 ahc->pci_cachesize = 925 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 926 /*bytes*/1) & CACHESIZE; 927 ahc->pci_cachesize *= 4; 928 929 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 930 && ahc->pci_cachesize == 4) { 931 932 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 933 0, /*bytes*/1); 934 ahc->pci_cachesize = 0; 935 } 936 937 /* 938 * We cannot perform ULTRA speeds without the presense 939 * of the external precision resistor. 940 */ 941 if ((ahc->features & AHC_ULTRA) != 0) { 942 uint32_t devconfig; 943 944 devconfig = ahc_pci_read_config(ahc->dev_softc, 945 DEVCONFIG, /*bytes*/4); 946 if ((devconfig & REXTVALID) == 0) 947 ahc->features &= ~AHC_ULTRA; 948 } 949 950 /* See if we have a SEEPROM and perform auto-term */ 951 check_extport(ahc, &sxfrctl1); 952 953 /* 954 * Take the LED out of diagnostic mode 955 */ 956 sblkctl = ahc_inb(ahc, SBLKCTL); 957 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 958 959 if ((ahc->features & AHC_ULTRA2) != 0) { 960 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 961 } else { 962 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 963 } 964 965 if (ahc->flags & AHC_USEDEFAULTS) { 966 /* 967 * PCI Adapter default setup 968 * Should only be used if the adapter does not have 969 * a SEEPROM. 970 */ 971 /* See if someone else set us up already */ 972 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 973 && scsiseq != 0) { 974 printf("%s: Using left over BIOS settings\n", 975 ahc_name(ahc)); 976 ahc->flags &= ~AHC_USEDEFAULTS; 977 ahc->flags |= AHC_BIOS_ENABLED; 978 } else { 979 /* 980 * Assume only one connector and always turn 981 * on termination. 982 */ 983 our_id = 0x07; 984 sxfrctl1 = STPWEN; 985 } 986 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 987 988 ahc->our_id = our_id; 989 } 990 991 /* 992 * Take a look to see if we have external SRAM. 993 * We currently do not attempt to use SRAM that is 994 * shared among multiple controllers. 995 */ 996 ahc_probe_ext_scbram(ahc); 997 998 /* 999 * Record our termination setting for the 1000 * generic initialization routine. 1001 */ 1002 if ((sxfrctl1 & STPWEN) != 0) 1003 ahc->flags |= AHC_TERM_ENB_A; 1004 1005 /* 1006 * Save chip register configuration data for chip resets 1007 * that occur during runtime and resume events. 1008 */ 1009 ahc->bus_softc.pci_softc.devconfig = 1010 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1011 ahc->bus_softc.pci_softc.command = 1012 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 1013 ahc->bus_softc.pci_softc.csize_lattime = 1014 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 1015 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1016 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1017 if ((ahc->features & AHC_DT) != 0) { 1018 u_int sfunct; 1019 1020 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1021 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1022 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1023 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1024 ahc_outb(ahc, SFUNCT, sfunct); 1025 ahc->bus_softc.pci_softc.crccontrol1 = 1026 ahc_inb(ahc, CRCCONTROL1); 1027 } 1028 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1029 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1030 1031 if ((ahc->features & AHC_ULTRA2) != 0) 1032 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1033 1034 /* Core initialization */ 1035 error = ahc_init(ahc); 1036 if (error != 0) 1037 return (error); 1038 1039 /* 1040 * Allow interrupts now that we are completely setup. 1041 */ 1042 error = ahc_pci_map_int(ahc); 1043 if (error != 0) 1044 return (error); 1045 1046 ahc_list_lock(&l); 1047 /* 1048 * Link this softc in with all other ahc instances. 1049 */ 1050 ahc_softc_insert(ahc); 1051 ahc_list_unlock(&l); 1052 return (0); 1053 } 1054 1055 /* 1056 * Test for the presense of external sram in an 1057 * "unshared" configuration. 1058 */ 1059 static int 1060 ahc_ext_scbram_present(struct ahc_softc *ahc) 1061 { 1062 u_int chip; 1063 int ramps; 1064 int single_user; 1065 uint32_t devconfig; 1066 1067 chip = ahc->chip & AHC_CHIPID_MASK; 1068 devconfig = ahc_pci_read_config(ahc->dev_softc, 1069 DEVCONFIG, /*bytes*/4); 1070 single_user = (devconfig & MPORTMODE) != 0; 1071 1072 if ((ahc->features & AHC_ULTRA2) != 0) 1073 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1074 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1075 /* 1076 * External SCBRAM arbitration is flakey 1077 * on these chips. Unfortunately this means 1078 * we don't use the extra SCB ram space on the 1079 * 3940AUW. 1080 */ 1081 ramps = 0; 1082 else if (chip >= AHC_AIC7870) 1083 ramps = (devconfig & RAMPSM) != 0; 1084 else 1085 ramps = 0; 1086 1087 if (ramps && single_user) 1088 return (1); 1089 return (0); 1090 } 1091 1092 /* 1093 * Enable external scbram. 1094 */ 1095 static void 1096 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1097 int fast, int large) 1098 { 1099 uint32_t devconfig; 1100 1101 if (ahc->features & AHC_MULTI_FUNC) { 1102 /* 1103 * Set the SCB Base addr (highest address bit) 1104 * depending on which channel we are. 1105 */ 1106 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1107 } 1108 1109 ahc->flags &= ~AHC_LSCBS_ENABLED; 1110 if (large) 1111 ahc->flags |= AHC_LSCBS_ENABLED; 1112 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1113 if ((ahc->features & AHC_ULTRA2) != 0) { 1114 u_int dscommand0; 1115 1116 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1117 if (enable) 1118 dscommand0 &= ~INTSCBRAMSEL; 1119 else 1120 dscommand0 |= INTSCBRAMSEL; 1121 if (large) 1122 dscommand0 &= ~USCBSIZE32; 1123 else 1124 dscommand0 |= USCBSIZE32; 1125 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1126 } else { 1127 if (fast) 1128 devconfig &= ~EXTSCBTIME; 1129 else 1130 devconfig |= EXTSCBTIME; 1131 if (enable) 1132 devconfig &= ~SCBRAMSEL; 1133 else 1134 devconfig |= SCBRAMSEL; 1135 if (large) 1136 devconfig &= ~SCBSIZE32; 1137 else 1138 devconfig |= SCBSIZE32; 1139 } 1140 if (pcheck) 1141 devconfig |= EXTSCBPEN; 1142 else 1143 devconfig &= ~EXTSCBPEN; 1144 1145 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1146 } 1147 1148 /* 1149 * Take a look to see if we have external SRAM. 1150 * We currently do not attempt to use SRAM that is 1151 * shared among multiple controllers. 1152 */ 1153 static void 1154 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1155 { 1156 int num_scbs; 1157 int test_num_scbs; 1158 int enable; 1159 int pcheck; 1160 int fast; 1161 int large; 1162 1163 enable = FALSE; 1164 pcheck = FALSE; 1165 fast = FALSE; 1166 large = FALSE; 1167 num_scbs = 0; 1168 1169 if (ahc_ext_scbram_present(ahc) == 0) 1170 goto done; 1171 1172 /* 1173 * Probe for the best parameters to use. 1174 */ 1175 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1176 num_scbs = ahc_probe_scbs(ahc); 1177 if (num_scbs == 0) { 1178 /* The SRAM wasn't really present. */ 1179 goto done; 1180 } 1181 enable = TRUE; 1182 1183 /* 1184 * Clear any outstanding parity error 1185 * and ensure that parity error reporting 1186 * is enabled. 1187 */ 1188 ahc_outb(ahc, SEQCTL, 0); 1189 ahc_outb(ahc, CLRINT, CLRPARERR); 1190 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1191 1192 /* Now see if we can do parity */ 1193 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1194 num_scbs = ahc_probe_scbs(ahc); 1195 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1196 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1197 pcheck = TRUE; 1198 1199 /* Clear any resulting parity error */ 1200 ahc_outb(ahc, CLRINT, CLRPARERR); 1201 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1202 1203 /* Now see if we can do fast timing */ 1204 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1205 test_num_scbs = ahc_probe_scbs(ahc); 1206 if (test_num_scbs == num_scbs 1207 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1208 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1209 fast = TRUE; 1210 1211 /* 1212 * See if we can use large SCBs and still maintain 1213 * the same overall count of SCBs. 1214 */ 1215 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1216 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1217 test_num_scbs = ahc_probe_scbs(ahc); 1218 if (test_num_scbs >= num_scbs) { 1219 large = TRUE; 1220 num_scbs = test_num_scbs; 1221 if (num_scbs >= 64) { 1222 /* 1223 * We have enough space to move the 1224 * "busy targets table" into SCB space 1225 * and make it qualify all the way to the 1226 * lun level. 1227 */ 1228 ahc->flags |= AHC_SCB_BTT; 1229 } 1230 } 1231 } 1232 done: 1233 /* 1234 * Disable parity error reporting until we 1235 * can load instruction ram. 1236 */ 1237 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1238 /* Clear any latched parity error */ 1239 ahc_outb(ahc, CLRINT, CLRPARERR); 1240 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1241 if (bootverbose && enable) { 1242 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1243 ahc_name(ahc), fast ? "fast" : "slow", 1244 pcheck ? ", parity checking enabled" : "", 1245 large ? 64 : 32); 1246 } 1247 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1248 } 1249 1250 /* 1251 * Perform some simple tests that should catch situations where 1252 * our registers are invalidly mapped. 1253 */ 1254 int 1255 ahc_pci_test_register_access(struct ahc_softc *ahc) 1256 { 1257 int error; 1258 u_int status1; 1259 uint32_t cmd; 1260 uint8_t hcntrl; 1261 1262 error = EIO; 1263 1264 /* 1265 * Enable PCI error interrupt status, but suppress NMIs 1266 * generated by SERR raised due to target aborts. 1267 */ 1268 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1269 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1270 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1271 1272 /* 1273 * First a simple test to see if any 1274 * registers can be read. Reading 1275 * HCNTRL has no side effects and has 1276 * at least one bit that is guaranteed to 1277 * be zero so it is a good register to 1278 * use for this test. 1279 */ 1280 hcntrl = ahc_inb(ahc, HCNTRL); 1281 if (hcntrl == 0xFF) 1282 goto fail; 1283 1284 /* 1285 * Next create a situation where write combining 1286 * or read prefetching could be initiated by the 1287 * CPU or host bridge. Our device does not support 1288 * either, so look for data corruption and/or flagged 1289 * PCI errors. 1290 */ 1291 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1292 while (ahc_is_paused(ahc) == 0) 1293 ; 1294 ahc_outb(ahc, SEQCTL, PERRORDIS); 1295 ahc_outb(ahc, SCBPTR, 0); 1296 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1297 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1298 goto fail; 1299 1300 status1 = ahc_pci_read_config(ahc->dev_softc, 1301 PCIR_STATUS + 1, /*bytes*/1); 1302 if ((status1 & STA) != 0) 1303 goto fail; 1304 1305 error = 0; 1306 1307 fail: 1308 /* Silently clear any latched errors. */ 1309 status1 = ahc_pci_read_config(ahc->dev_softc, 1310 PCIR_STATUS + 1, /*bytes*/1); 1311 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1312 status1, /*bytes*/1); 1313 ahc_outb(ahc, CLRINT, CLRPARERR); 1314 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1315 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1316 return (error); 1317 } 1318 1319 /* 1320 * Check the external port logic for a serial eeprom 1321 * and termination/cable detection contrls. 1322 */ 1323 static void 1324 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1325 { 1326 struct seeprom_descriptor sd; 1327 struct seeprom_config *sc; 1328 int have_seeprom; 1329 int have_autoterm; 1330 1331 sd.sd_ahc = ahc; 1332 sd.sd_control_offset = SEECTL; 1333 sd.sd_status_offset = SEECTL; 1334 sd.sd_dataout_offset = SEECTL; 1335 sc = ahc->seep_config; 1336 1337 /* 1338 * For some multi-channel devices, the c46 is simply too 1339 * small to work. For the other controller types, we can 1340 * get our information from either SEEPROM type. Set the 1341 * type to start our probe with accordingly. 1342 */ 1343 if (ahc->flags & AHC_LARGE_SEEPROM) 1344 sd.sd_chip = C56_66; 1345 else 1346 sd.sd_chip = C46; 1347 1348 sd.sd_MS = SEEMS; 1349 sd.sd_RDY = SEERDY; 1350 sd.sd_CS = SEECS; 1351 sd.sd_CK = SEECK; 1352 sd.sd_DO = SEEDO; 1353 sd.sd_DI = SEEDI; 1354 1355 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1356 if (have_seeprom) { 1357 1358 if (bootverbose) 1359 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1360 1361 for (;;) { 1362 u_int start_addr; 1363 1364 start_addr = 32 * (ahc->channel - 'A'); 1365 1366 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1367 start_addr, 1368 sizeof(*sc)/2); 1369 1370 if (have_seeprom) 1371 have_seeprom = ahc_verify_cksum(sc); 1372 1373 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1374 if (bootverbose) { 1375 if (have_seeprom == 0) 1376 printf ("checksum error\n"); 1377 else 1378 printf ("done.\n"); 1379 } 1380 break; 1381 } 1382 sd.sd_chip = C56_66; 1383 } 1384 ahc_release_seeprom(&sd); 1385 } 1386 1387 if (!have_seeprom) { 1388 /* 1389 * Pull scratch ram settings and treat them as 1390 * if they are the contents of an seeprom if 1391 * the 'ADPT' signature is found in SCB2. 1392 * We manually compose the data as 16bit values 1393 * to avoid endian issues. 1394 */ 1395 ahc_outb(ahc, SCBPTR, 2); 1396 if (ahc_inb(ahc, SCB_BASE) == 'A' 1397 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1398 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1399 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1400 uint16_t *sc_data; 1401 int i; 1402 1403 sc_data = (uint16_t *)sc; 1404 for (i = 0; i < 32; i++, sc_data++) { 1405 int j; 1406 1407 j = i * 2; 1408 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1409 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1410 } 1411 have_seeprom = ahc_verify_cksum(sc); 1412 if (have_seeprom) 1413 ahc->flags |= AHC_SCB_CONFIG_USED; 1414 } 1415 /* 1416 * Clear any SCB parity errors in case this data and 1417 * its associated parity was not initialized by the BIOS 1418 */ 1419 ahc_outb(ahc, CLRINT, CLRPARERR); 1420 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1421 } 1422 1423 if (!have_seeprom) { 1424 if (bootverbose) 1425 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1426 ahc->flags |= AHC_USEDEFAULTS; 1427 free(ahc->seep_config, M_DEVBUF); 1428 ahc->seep_config = NULL; 1429 sc = NULL; 1430 } else { 1431 ahc_parse_pci_eeprom(ahc, sc); 1432 } 1433 1434 /* 1435 * Cards that have the external logic necessary to talk to 1436 * a SEEPROM, are almost certain to have the remaining logic 1437 * necessary for auto-termination control. This assumption 1438 * hasn't failed yet... 1439 */ 1440 have_autoterm = have_seeprom; 1441 1442 /* 1443 * Some low-cost chips have SEEPROM and auto-term control built 1444 * in, instead of using a GAL. They can tell us directly 1445 * if the termination logic is enabled. 1446 */ 1447 if ((ahc->features & AHC_SPIOCAP) != 0) { 1448 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1449 have_autoterm = FALSE; 1450 } 1451 1452 if (have_autoterm) { 1453 ahc->flags |= AHC_HAS_TERM_LOGIC; 1454 ahc_acquire_seeprom(ahc, &sd); 1455 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1456 ahc_release_seeprom(&sd); 1457 } else if (have_seeprom) { 1458 *sxfrctl1 &= ~STPWEN; 1459 if ((sc->adapter_control & CFSTERM) != 0) 1460 *sxfrctl1 |= STPWEN; 1461 if (bootverbose) 1462 printf("%s: Low byte termination %sabled\n", 1463 ahc_name(ahc), 1464 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1465 } 1466 } 1467 1468 static void 1469 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1470 { 1471 /* 1472 * Put the data we've collected down into SRAM 1473 * where ahc_init will find it. 1474 */ 1475 int i; 1476 int max_targ = sc->max_targets & CFMAXTARG; 1477 u_int scsi_conf; 1478 uint16_t discenable; 1479 uint16_t ultraenb; 1480 1481 discenable = 0; 1482 ultraenb = 0; 1483 if ((sc->adapter_control & CFULTRAEN) != 0) { 1484 /* 1485 * Determine if this adapter has a "newstyle" 1486 * SEEPROM format. 1487 */ 1488 for (i = 0; i < max_targ; i++) { 1489 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1490 ahc->flags |= AHC_NEWEEPROM_FMT; 1491 break; 1492 } 1493 } 1494 } 1495 1496 for (i = 0; i < max_targ; i++) { 1497 u_int scsirate; 1498 uint16_t target_mask; 1499 1500 target_mask = 0x01 << i; 1501 if (sc->device_flags[i] & CFDISC) 1502 discenable |= target_mask; 1503 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1504 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1505 ultraenb |= target_mask; 1506 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1507 ultraenb |= target_mask; 1508 } 1509 if ((sc->device_flags[i] & CFXFER) == 0x04 1510 && (ultraenb & target_mask) != 0) { 1511 /* Treat 10MHz as a non-ultra speed */ 1512 sc->device_flags[i] &= ~CFXFER; 1513 ultraenb &= ~target_mask; 1514 } 1515 if ((ahc->features & AHC_ULTRA2) != 0) { 1516 u_int offset; 1517 1518 if (sc->device_flags[i] & CFSYNCH) 1519 offset = MAX_OFFSET_ULTRA2; 1520 else 1521 offset = 0; 1522 ahc_outb(ahc, TARG_OFFSET + i, offset); 1523 1524 /* 1525 * The ultra enable bits contain the 1526 * high bit of the ultra2 sync rate 1527 * field. 1528 */ 1529 scsirate = (sc->device_flags[i] & CFXFER) 1530 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1531 if (sc->device_flags[i] & CFWIDEB) 1532 scsirate |= WIDEXFER; 1533 } else { 1534 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1535 if (sc->device_flags[i] & CFSYNCH) 1536 scsirate |= SOFS; 1537 if (sc->device_flags[i] & CFWIDEB) 1538 scsirate |= WIDEXFER; 1539 } 1540 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1541 } 1542 ahc->our_id = sc->brtime_id & CFSCSIID; 1543 1544 scsi_conf = (ahc->our_id & 0x7); 1545 if (sc->adapter_control & CFSPARITY) 1546 scsi_conf |= ENSPCHK; 1547 if (sc->adapter_control & CFRESETB) 1548 scsi_conf |= RESET_SCSI; 1549 1550 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1551 1552 if (sc->bios_control & CFEXTEND) 1553 ahc->flags |= AHC_EXTENDED_TRANS_A; 1554 1555 if (sc->bios_control & CFBIOSEN) 1556 ahc->flags |= AHC_BIOS_ENABLED; 1557 if (ahc->features & AHC_ULTRA 1558 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1559 /* Should we enable Ultra mode? */ 1560 if (!(sc->adapter_control & CFULTRAEN)) 1561 /* Treat us as a non-ultra card */ 1562 ultraenb = 0; 1563 } 1564 1565 if (sc->signature == CFSIGNATURE 1566 || sc->signature == CFSIGNATURE2) { 1567 uint32_t devconfig; 1568 1569 /* Honor the STPWLEVEL settings */ 1570 devconfig = ahc_pci_read_config(ahc->dev_softc, 1571 DEVCONFIG, /*bytes*/4); 1572 devconfig &= ~STPWLEVEL; 1573 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1574 devconfig |= STPWLEVEL; 1575 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1576 devconfig, /*bytes*/4); 1577 } 1578 /* Set SCSICONF info */ 1579 ahc_outb(ahc, SCSICONF, scsi_conf); 1580 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1581 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1582 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1583 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1584 } 1585 1586 static void 1587 configure_termination(struct ahc_softc *ahc, 1588 struct seeprom_descriptor *sd, 1589 u_int adapter_control, 1590 u_int *sxfrctl1) 1591 { 1592 uint8_t brddat; 1593 1594 brddat = 0; 1595 1596 /* 1597 * Update the settings in sxfrctl1 to match the 1598 * termination settings 1599 */ 1600 *sxfrctl1 = 0; 1601 1602 /* 1603 * SEECS must be on for the GALS to latch 1604 * the data properly. Be sure to leave MS 1605 * on or we will release the seeprom. 1606 */ 1607 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1608 if ((adapter_control & CFAUTOTERM) != 0 1609 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1610 int internal50_present; 1611 int internal68_present; 1612 int externalcable_present; 1613 int eeprom_present; 1614 int enableSEC_low; 1615 int enableSEC_high; 1616 int enablePRI_low; 1617 int enablePRI_high; 1618 int sum; 1619 1620 enableSEC_low = 0; 1621 enableSEC_high = 0; 1622 enablePRI_low = 0; 1623 enablePRI_high = 0; 1624 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1625 ahc_new_term_detect(ahc, &enableSEC_low, 1626 &enableSEC_high, 1627 &enablePRI_low, 1628 &enablePRI_high, 1629 &eeprom_present); 1630 if ((adapter_control & CFSEAUTOTERM) == 0) { 1631 if (bootverbose) 1632 printf("%s: Manual SE Termination\n", 1633 ahc_name(ahc)); 1634 enableSEC_low = (adapter_control & CFSELOWTERM); 1635 enableSEC_high = 1636 (adapter_control & CFSEHIGHTERM); 1637 } 1638 if ((adapter_control & CFAUTOTERM) == 0) { 1639 if (bootverbose) 1640 printf("%s: Manual LVD Termination\n", 1641 ahc_name(ahc)); 1642 enablePRI_low = (adapter_control & CFSTERM); 1643 enablePRI_high = (adapter_control & CFWSTERM); 1644 } 1645 /* Make the table calculations below happy */ 1646 internal50_present = 0; 1647 internal68_present = 1; 1648 externalcable_present = 1; 1649 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1650 aic785X_cable_detect(ahc, &internal50_present, 1651 &externalcable_present, 1652 &eeprom_present); 1653 /* Can never support a wide connector. */ 1654 internal68_present = 0; 1655 } else { 1656 aic787X_cable_detect(ahc, &internal50_present, 1657 &internal68_present, 1658 &externalcable_present, 1659 &eeprom_present); 1660 } 1661 1662 if ((ahc->features & AHC_WIDE) == 0) 1663 internal68_present = 0; 1664 1665 if (bootverbose 1666 && (ahc->features & AHC_ULTRA2) == 0) { 1667 printf("%s: internal 50 cable %s present", 1668 ahc_name(ahc), 1669 internal50_present ? "is":"not"); 1670 1671 if ((ahc->features & AHC_WIDE) != 0) 1672 printf(", internal 68 cable %s present", 1673 internal68_present ? "is":"not"); 1674 printf("\n%s: external cable %s present\n", 1675 ahc_name(ahc), 1676 externalcable_present ? "is":"not"); 1677 } 1678 if (bootverbose) 1679 printf("%s: BIOS eeprom %s present\n", 1680 ahc_name(ahc), eeprom_present ? "is" : "not"); 1681 1682 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1683 /* 1684 * The 50 pin connector is a separate bus, 1685 * so force it to always be terminated. 1686 * In the future, perform current sensing 1687 * to determine if we are in the middle of 1688 * a properly terminated bus. 1689 */ 1690 internal50_present = 0; 1691 } 1692 1693 /* 1694 * Now set the termination based on what 1695 * we found. 1696 * Flash Enable = BRDDAT7 1697 * Secondary High Term Enable = BRDDAT6 1698 * Secondary Low Term Enable = BRDDAT5 (7890) 1699 * Primary High Term Enable = BRDDAT4 (7890) 1700 */ 1701 if ((ahc->features & AHC_ULTRA2) == 0 1702 && (internal50_present != 0) 1703 && (internal68_present != 0) 1704 && (externalcable_present != 0)) { 1705 printf("%s: Illegal cable configuration!!. " 1706 "Only two connectors on the " 1707 "adapter may be used at a " 1708 "time!\n", ahc_name(ahc)); 1709 1710 /* 1711 * Pretend there are no cables in the hope 1712 * that having all of the termination on 1713 * gives us a more stable bus. 1714 */ 1715 internal50_present = 0; 1716 internal68_present = 0; 1717 externalcable_present = 0; 1718 } 1719 1720 if ((ahc->features & AHC_WIDE) != 0 1721 && ((externalcable_present == 0) 1722 || (internal68_present == 0) 1723 || (enableSEC_high != 0))) { 1724 brddat |= BRDDAT6; 1725 if (bootverbose) { 1726 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1727 printf("%s: 68 pin termination " 1728 "Enabled\n", ahc_name(ahc)); 1729 else 1730 printf("%s: %sHigh byte termination " 1731 "Enabled\n", ahc_name(ahc), 1732 enableSEC_high ? "Secondary " 1733 : ""); 1734 } 1735 } 1736 1737 sum = internal50_present + internal68_present 1738 + externalcable_present; 1739 if (sum < 2 || (enableSEC_low != 0)) { 1740 if ((ahc->features & AHC_ULTRA2) != 0) 1741 brddat |= BRDDAT5; 1742 else 1743 *sxfrctl1 |= STPWEN; 1744 if (bootverbose) { 1745 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1746 printf("%s: 50 pin termination " 1747 "Enabled\n", ahc_name(ahc)); 1748 else 1749 printf("%s: %sLow byte termination " 1750 "Enabled\n", ahc_name(ahc), 1751 enableSEC_low ? "Secondary " 1752 : ""); 1753 } 1754 } 1755 1756 if (enablePRI_low != 0) { 1757 *sxfrctl1 |= STPWEN; 1758 if (bootverbose) 1759 printf("%s: Primary Low Byte termination " 1760 "Enabled\n", ahc_name(ahc)); 1761 } 1762 1763 /* 1764 * Setup STPWEN before setting up the rest of 1765 * the termination per the tech note on the U160 cards. 1766 */ 1767 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1768 1769 if (enablePRI_high != 0) { 1770 brddat |= BRDDAT4; 1771 if (bootverbose) 1772 printf("%s: Primary High Byte " 1773 "termination Enabled\n", 1774 ahc_name(ahc)); 1775 } 1776 1777 write_brdctl(ahc, brddat); 1778 1779 } else { 1780 if ((adapter_control & CFSTERM) != 0) { 1781 *sxfrctl1 |= STPWEN; 1782 1783 if (bootverbose) 1784 printf("%s: %sLow byte termination Enabled\n", 1785 ahc_name(ahc), 1786 (ahc->features & AHC_ULTRA2) ? "Primary " 1787 : ""); 1788 } 1789 1790 if ((adapter_control & CFWSTERM) != 0 1791 && (ahc->features & AHC_WIDE) != 0) { 1792 brddat |= BRDDAT6; 1793 if (bootverbose) 1794 printf("%s: %sHigh byte termination Enabled\n", 1795 ahc_name(ahc), 1796 (ahc->features & AHC_ULTRA2) 1797 ? "Secondary " : ""); 1798 } 1799 1800 /* 1801 * Setup STPWEN before setting up the rest of 1802 * the termination per the tech note on the U160 cards. 1803 */ 1804 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1805 1806 if ((ahc->features & AHC_WIDE) != 0) 1807 write_brdctl(ahc, brddat); 1808 } 1809 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1810 } 1811 1812 static void 1813 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1814 int *enableSEC_high, int *enablePRI_low, 1815 int *enablePRI_high, int *eeprom_present) 1816 { 1817 uint8_t brdctl; 1818 1819 /* 1820 * BRDDAT7 = Eeprom 1821 * BRDDAT6 = Enable Secondary High Byte termination 1822 * BRDDAT5 = Enable Secondary Low Byte termination 1823 * BRDDAT4 = Enable Primary high byte termination 1824 * BRDDAT3 = Enable Primary low byte termination 1825 */ 1826 brdctl = read_brdctl(ahc); 1827 *eeprom_present = brdctl & BRDDAT7; 1828 *enableSEC_high = (brdctl & BRDDAT6); 1829 *enableSEC_low = (brdctl & BRDDAT5); 1830 *enablePRI_high = (brdctl & BRDDAT4); 1831 *enablePRI_low = (brdctl & BRDDAT3); 1832 } 1833 1834 static void 1835 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1836 int *internal68_present, int *externalcable_present, 1837 int *eeprom_present) 1838 { 1839 uint8_t brdctl; 1840 1841 /* 1842 * First read the status of our cables. 1843 * Set the rom bank to 0 since the 1844 * bank setting serves as a multiplexor 1845 * for the cable detection logic. 1846 * BRDDAT5 controls the bank switch. 1847 */ 1848 write_brdctl(ahc, 0); 1849 1850 /* 1851 * Now read the state of the internal 1852 * connectors. BRDDAT6 is INT50 and 1853 * BRDDAT7 is INT68. 1854 */ 1855 brdctl = read_brdctl(ahc); 1856 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1857 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1858 1859 /* 1860 * Set the rom bank to 1 and determine 1861 * the other signals. 1862 */ 1863 write_brdctl(ahc, BRDDAT5); 1864 1865 /* 1866 * Now read the state of the external 1867 * connectors. BRDDAT6 is EXT68 and 1868 * BRDDAT7 is EPROMPS. 1869 */ 1870 brdctl = read_brdctl(ahc); 1871 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1872 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1873 } 1874 1875 static void 1876 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1877 int *externalcable_present, int *eeprom_present) 1878 { 1879 uint8_t brdctl; 1880 uint8_t spiocap; 1881 1882 spiocap = ahc_inb(ahc, SPIOCAP); 1883 spiocap &= ~SOFTCMDEN; 1884 spiocap |= EXT_BRDCTL; 1885 ahc_outb(ahc, SPIOCAP, spiocap); 1886 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1887 ahc_flush_device_writes(ahc); 1888 ahc_delay(500); 1889 ahc_outb(ahc, BRDCTL, 0); 1890 ahc_flush_device_writes(ahc); 1891 ahc_delay(500); 1892 brdctl = ahc_inb(ahc, BRDCTL); 1893 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1894 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1895 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1896 } 1897 1898 int 1899 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1900 { 1901 int wait; 1902 1903 if ((ahc->features & AHC_SPIOCAP) != 0 1904 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1905 return (0); 1906 1907 /* 1908 * Request access of the memory port. When access is 1909 * granted, SEERDY will go high. We use a 1 second 1910 * timeout which should be near 1 second more than 1911 * is needed. Reason: after the chip reset, there 1912 * should be no contention. 1913 */ 1914 SEEPROM_OUTB(sd, sd->sd_MS); 1915 wait = 1000; /* 1 second timeout in msec */ 1916 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1917 ahc_delay(1000); /* delay 1 msec */ 1918 } 1919 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1920 SEEPROM_OUTB(sd, 0); 1921 return (0); 1922 } 1923 return(1); 1924 } 1925 1926 void 1927 ahc_release_seeprom(struct seeprom_descriptor *sd) 1928 { 1929 /* Release access to the memory port and the serial EEPROM. */ 1930 SEEPROM_OUTB(sd, 0); 1931 } 1932 1933 static void 1934 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1935 { 1936 uint8_t brdctl; 1937 1938 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1939 brdctl = BRDSTB; 1940 if (ahc->channel == 'B') 1941 brdctl |= BRDCS; 1942 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1943 brdctl = 0; 1944 } else { 1945 brdctl = BRDSTB|BRDCS; 1946 } 1947 ahc_outb(ahc, BRDCTL, brdctl); 1948 ahc_flush_device_writes(ahc); 1949 brdctl |= value; 1950 ahc_outb(ahc, BRDCTL, brdctl); 1951 ahc_flush_device_writes(ahc); 1952 if ((ahc->features & AHC_ULTRA2) != 0) 1953 brdctl |= BRDSTB_ULTRA2; 1954 else 1955 brdctl &= ~BRDSTB; 1956 ahc_outb(ahc, BRDCTL, brdctl); 1957 ahc_flush_device_writes(ahc); 1958 if ((ahc->features & AHC_ULTRA2) != 0) 1959 brdctl = 0; 1960 else 1961 brdctl &= ~BRDCS; 1962 ahc_outb(ahc, BRDCTL, brdctl); 1963 } 1964 1965 static uint8_t 1966 read_brdctl(ahc) 1967 struct ahc_softc *ahc; 1968 { 1969 uint8_t brdctl; 1970 uint8_t value; 1971 1972 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1973 brdctl = BRDRW; 1974 if (ahc->channel == 'B') 1975 brdctl |= BRDCS; 1976 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1977 brdctl = BRDRW_ULTRA2; 1978 } else { 1979 brdctl = BRDRW|BRDCS; 1980 } 1981 ahc_outb(ahc, BRDCTL, brdctl); 1982 ahc_flush_device_writes(ahc); 1983 value = ahc_inb(ahc, BRDCTL); 1984 ahc_outb(ahc, BRDCTL, 0); 1985 return (value); 1986 } 1987 1988 static void 1989 ahc_pci_intr(struct ahc_softc *ahc) 1990 { 1991 u_int error; 1992 u_int status1; 1993 1994 error = ahc_inb(ahc, ERROR); 1995 if ((error & PCIERRSTAT) == 0) 1996 return; 1997 1998 status1 = ahc_pci_read_config(ahc->dev_softc, 1999 PCIR_STATUS + 1, /*bytes*/1); 2000 2001 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 2002 ahc_name(ahc), 2003 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 2004 2005 if (status1 & DPE) { 2006 ahc->pci_target_perr_count++; 2007 printf("%s: Data Parity Error Detected during address " 2008 "or write data phase\n", ahc_name(ahc)); 2009 } 2010 if (status1 & SSE) { 2011 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 2012 } 2013 if (status1 & RMA) { 2014 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 2015 } 2016 if (status1 & RTA) { 2017 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 2018 } 2019 if (status1 & STA) { 2020 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 2021 } 2022 if (status1 & DPR) { 2023 printf("%s: Data Parity Error has been reported via PERR#\n", 2024 ahc_name(ahc)); 2025 } 2026 2027 /* Clear latched errors. */ 2028 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 2029 status1, /*bytes*/1); 2030 2031 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 2032 printf("%s: Latched PCIERR interrupt with " 2033 "no status bits set\n", ahc_name(ahc)); 2034 } else { 2035 ahc_outb(ahc, CLRINT, CLRPARERR); 2036 } 2037 2038 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 2039 printf( 2040 "%s: WARNING WARNING WARNING WARNING\n" 2041 "%s: Too many PCI parity errors observed as a target.\n" 2042 "%s: Some device on this bus is generating bad parity.\n" 2043 "%s: This is an error *observed by*, not *generated by*, this controller.\n" 2044 "%s: PCI parity error checking has been disabled.\n" 2045 "%s: WARNING WARNING WARNING WARNING\n", 2046 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 2047 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 2048 ahc->pause |= FAILDIS; 2049 ahc->unpause |= FAILDIS; 2050 } 2051 ahc_unpause(ahc); 2052 } 2053 2054 static int 2055 ahc_pci_chip_init(struct ahc_softc *ahc) 2056 { 2057 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 2058 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 2059 if ((ahc->features & AHC_DT) != 0) { 2060 u_int sfunct; 2061 2062 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 2063 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2064 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2065 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2066 ahc_outb(ahc, SFUNCT, sfunct); 2067 ahc_outb(ahc, CRCCONTROL1, 2068 ahc->bus_softc.pci_softc.crccontrol1); 2069 } 2070 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2071 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2072 2073 if ((ahc->features & AHC_ULTRA2) != 0) 2074 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2075 2076 return (ahc_chip_init(ahc)); 2077 } 2078 2079 static int 2080 ahc_pci_suspend(struct ahc_softc *ahc) 2081 { 2082 return (ahc_suspend(ahc)); 2083 } 2084 2085 static int 2086 ahc_pci_resume(struct ahc_softc *ahc) 2087 { 2088 2089 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 2090 2091 /* 2092 * We assume that the OS has restored our register 2093 * mappings, etc. Just update the config space registers 2094 * that the OS doesn't know about and rely on our chip 2095 * reset handler to handle the rest. 2096 */ 2097 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4, 2098 ahc->bus_softc.pci_softc.devconfig); 2099 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1, 2100 ahc->bus_softc.pci_softc.command); 2101 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1, 2102 ahc->bus_softc.pci_softc.csize_lattime); 2103 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2104 struct seeprom_descriptor sd; 2105 u_int sxfrctl1; 2106 2107 sd.sd_ahc = ahc; 2108 sd.sd_control_offset = SEECTL; 2109 sd.sd_status_offset = SEECTL; 2110 sd.sd_dataout_offset = SEECTL; 2111 2112 ahc_acquire_seeprom(ahc, &sd); 2113 configure_termination(ahc, &sd, 2114 ahc->seep_config->adapter_control, 2115 &sxfrctl1); 2116 ahc_release_seeprom(&sd); 2117 } 2118 return (ahc_resume(ahc)); 2119 } 2120 2121 static int 2122 ahc_aic785X_setup(struct ahc_softc *ahc) 2123 { 2124 ahc_dev_softc_t pci; 2125 uint8_t rev; 2126 2127 pci = ahc->dev_softc; 2128 ahc->channel = 'A'; 2129 ahc->chip = AHC_AIC7850; 2130 ahc->features = AHC_AIC7850_FE; 2131 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2132 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2133 if (rev >= 1) 2134 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2135 ahc->instruction_ram_size = 512; 2136 return (0); 2137 } 2138 2139 static int 2140 ahc_aic7860_setup(struct ahc_softc *ahc) 2141 { 2142 ahc_dev_softc_t pci; 2143 uint8_t rev; 2144 2145 pci = ahc->dev_softc; 2146 ahc->channel = 'A'; 2147 ahc->chip = AHC_AIC7860; 2148 ahc->features = AHC_AIC7860_FE; 2149 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2150 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2151 if (rev >= 1) 2152 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2153 ahc->instruction_ram_size = 512; 2154 return (0); 2155 } 2156 2157 static int 2158 ahc_apa1480_setup(struct ahc_softc *ahc) 2159 { 2160 int error; 2161 2162 error = ahc_aic7860_setup(ahc); 2163 if (error != 0) 2164 return (error); 2165 ahc->features |= AHC_REMOVABLE; 2166 return (0); 2167 } 2168 2169 static int 2170 ahc_aic7870_setup(struct ahc_softc *ahc) 2171 { 2172 2173 ahc->channel = 'A'; 2174 ahc->chip = AHC_AIC7870; 2175 ahc->features = AHC_AIC7870_FE; 2176 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2177 ahc->instruction_ram_size = 512; 2178 return (0); 2179 } 2180 2181 static int 2182 ahc_aha394X_setup(struct ahc_softc *ahc) 2183 { 2184 int error; 2185 2186 error = ahc_aic7870_setup(ahc); 2187 if (error == 0) 2188 error = ahc_aha394XX_setup(ahc); 2189 return (error); 2190 } 2191 2192 static int 2193 ahc_aha398X_setup(struct ahc_softc *ahc) 2194 { 2195 int error; 2196 2197 error = ahc_aic7870_setup(ahc); 2198 if (error == 0) 2199 error = ahc_aha398XX_setup(ahc); 2200 return (error); 2201 } 2202 2203 static int 2204 ahc_aha494X_setup(struct ahc_softc *ahc) 2205 { 2206 int error; 2207 2208 error = ahc_aic7870_setup(ahc); 2209 if (error == 0) 2210 error = ahc_aha494XX_setup(ahc); 2211 return (error); 2212 } 2213 2214 static int 2215 ahc_aic7880_setup(struct ahc_softc *ahc) 2216 { 2217 ahc_dev_softc_t pci; 2218 uint8_t rev; 2219 2220 pci = ahc->dev_softc; 2221 ahc->channel = 'A'; 2222 ahc->chip = AHC_AIC7880; 2223 ahc->features = AHC_AIC7880_FE; 2224 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2225 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2226 if (rev >= 1) { 2227 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2228 } else { 2229 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2230 } 2231 ahc->instruction_ram_size = 512; 2232 return (0); 2233 } 2234 2235 static int 2236 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2237 { 2238 2239 ahc->flags |= AHC_INT50_SPEEDFLEX; 2240 return (ahc_aic7880_setup(ahc)); 2241 } 2242 2243 static int 2244 ahc_aha394XU_setup(struct ahc_softc *ahc) 2245 { 2246 int error; 2247 2248 error = ahc_aic7880_setup(ahc); 2249 if (error == 0) 2250 error = ahc_aha394XX_setup(ahc); 2251 return (error); 2252 } 2253 2254 static int 2255 ahc_aha398XU_setup(struct ahc_softc *ahc) 2256 { 2257 int error; 2258 2259 error = ahc_aic7880_setup(ahc); 2260 if (error == 0) 2261 error = ahc_aha398XX_setup(ahc); 2262 return (error); 2263 } 2264 2265 static int 2266 ahc_aic7890_setup(struct ahc_softc *ahc) 2267 { 2268 ahc_dev_softc_t pci; 2269 uint8_t rev; 2270 2271 pci = ahc->dev_softc; 2272 ahc->channel = 'A'; 2273 ahc->chip = AHC_AIC7890; 2274 ahc->features = AHC_AIC7890_FE; 2275 ahc->flags |= AHC_NEWEEPROM_FMT; 2276 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2277 if (rev == 0) 2278 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2279 ahc->instruction_ram_size = 768; 2280 return (0); 2281 } 2282 2283 static int 2284 ahc_aic7892_setup(struct ahc_softc *ahc) 2285 { 2286 2287 ahc->channel = 'A'; 2288 ahc->chip = AHC_AIC7892; 2289 ahc->features = AHC_AIC7892_FE; 2290 ahc->flags |= AHC_NEWEEPROM_FMT; 2291 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2292 ahc->instruction_ram_size = 1024; 2293 return (0); 2294 } 2295 2296 static int 2297 ahc_aic7895_setup(struct ahc_softc *ahc) 2298 { 2299 ahc_dev_softc_t pci; 2300 uint8_t rev; 2301 2302 pci = ahc->dev_softc; 2303 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2304 /* 2305 * The 'C' revision of the aic7895 has a few additional features. 2306 */ 2307 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2308 if (rev >= 4) { 2309 ahc->chip = AHC_AIC7895C; 2310 ahc->features = AHC_AIC7895C_FE; 2311 } else { 2312 u_int command; 2313 2314 ahc->chip = AHC_AIC7895; 2315 ahc->features = AHC_AIC7895_FE; 2316 2317 /* 2318 * The BIOS disables the use of MWI transactions 2319 * since it does not have the MWI bug work around 2320 * we have. Disabling MWI reduces performance, so 2321 * turn it on again. 2322 */ 2323 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2324 command |= PCIM_CMD_MWRICEN; 2325 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2326 ahc->bugs |= AHC_PCI_MWI_BUG; 2327 } 2328 /* 2329 * XXX Does CACHETHEN really not work??? What about PCI retry? 2330 * on C level chips. Need to test, but for now, play it safe. 2331 */ 2332 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2333 | AHC_CACHETHEN_BUG; 2334 2335 #if 0 2336 uint32_t devconfig; 2337 2338 /* 2339 * Cachesize must also be zero due to stray DAC 2340 * problem when sitting behind some bridges. 2341 */ 2342 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2343 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2344 devconfig |= MRDCEN; 2345 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2346 #endif 2347 ahc->flags |= AHC_NEWEEPROM_FMT; 2348 ahc->instruction_ram_size = 512; 2349 return (0); 2350 } 2351 2352 static int 2353 ahc_aic7896_setup(struct ahc_softc *ahc) 2354 { 2355 ahc_dev_softc_t pci; 2356 2357 pci = ahc->dev_softc; 2358 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2359 ahc->chip = AHC_AIC7896; 2360 ahc->features = AHC_AIC7896_FE; 2361 ahc->flags |= AHC_NEWEEPROM_FMT; 2362 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2363 ahc->instruction_ram_size = 768; 2364 return (0); 2365 } 2366 2367 static int 2368 ahc_aic7899_setup(struct ahc_softc *ahc) 2369 { 2370 ahc_dev_softc_t pci; 2371 2372 pci = ahc->dev_softc; 2373 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2374 ahc->chip = AHC_AIC7899; 2375 ahc->features = AHC_AIC7899_FE; 2376 ahc->flags |= AHC_NEWEEPROM_FMT; 2377 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2378 ahc->instruction_ram_size = 1024; 2379 return (0); 2380 } 2381 2382 static int 2383 ahc_aha29160C_setup(struct ahc_softc *ahc) 2384 { 2385 int error; 2386 2387 error = ahc_aic7899_setup(ahc); 2388 if (error != 0) 2389 return (error); 2390 ahc->features |= AHC_REMOVABLE; 2391 return (0); 2392 } 2393 2394 static int 2395 ahc_raid_setup(struct ahc_softc *ahc) 2396 { 2397 printf("RAID functionality unsupported\n"); 2398 return (ENXIO); 2399 } 2400 2401 static int 2402 ahc_aha394XX_setup(struct ahc_softc *ahc) 2403 { 2404 ahc_dev_softc_t pci; 2405 2406 pci = ahc->dev_softc; 2407 switch (ahc_get_pci_slot(pci)) { 2408 case AHC_394X_SLOT_CHANNEL_A: 2409 ahc->channel = 'A'; 2410 break; 2411 case AHC_394X_SLOT_CHANNEL_B: 2412 ahc->channel = 'B'; 2413 break; 2414 default: 2415 printf("adapter at unexpected slot %d\n" 2416 "unable to map to a channel\n", 2417 ahc_get_pci_slot(pci)); 2418 ahc->channel = 'A'; 2419 } 2420 return (0); 2421 } 2422 2423 static int 2424 ahc_aha398XX_setup(struct ahc_softc *ahc) 2425 { 2426 ahc_dev_softc_t pci; 2427 2428 pci = ahc->dev_softc; 2429 switch (ahc_get_pci_slot(pci)) { 2430 case AHC_398X_SLOT_CHANNEL_A: 2431 ahc->channel = 'A'; 2432 break; 2433 case AHC_398X_SLOT_CHANNEL_B: 2434 ahc->channel = 'B'; 2435 break; 2436 case AHC_398X_SLOT_CHANNEL_C: 2437 ahc->channel = 'C'; 2438 break; 2439 default: 2440 printf("adapter at unexpected slot %d\n" 2441 "unable to map to a channel\n", 2442 ahc_get_pci_slot(pci)); 2443 ahc->channel = 'A'; 2444 break; 2445 } 2446 ahc->flags |= AHC_LARGE_SEEPROM; 2447 return (0); 2448 } 2449 2450 static int 2451 ahc_aha494XX_setup(struct ahc_softc *ahc) 2452 { 2453 ahc_dev_softc_t pci; 2454 2455 pci = ahc->dev_softc; 2456 switch (ahc_get_pci_slot(pci)) { 2457 case AHC_494X_SLOT_CHANNEL_A: 2458 ahc->channel = 'A'; 2459 break; 2460 case AHC_494X_SLOT_CHANNEL_B: 2461 ahc->channel = 'B'; 2462 break; 2463 case AHC_494X_SLOT_CHANNEL_C: 2464 ahc->channel = 'C'; 2465 break; 2466 case AHC_494X_SLOT_CHANNEL_D: 2467 ahc->channel = 'D'; 2468 break; 2469 default: 2470 printf("adapter at unexpected slot %d\n" 2471 "unable to map to a channel\n", 2472 ahc_get_pci_slot(pci)); 2473 ahc->channel = 'A'; 2474 } 2475 ahc->flags |= AHC_LARGE_SEEPROM; 2476 return (0); 2477 } 2478