1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#8 $ 34 * 35 * $FreeBSD$ 36 */ 37 38 #ifdef __linux__ 39 #include "aic7xxx_linux.h" 40 #include "aic7xxx_inline.h" 41 #include "aic7xxx_93cx6.h" 42 #endif 43 44 #ifdef __FreeBSD__ 45 #include <dev/aic7xxx/aic7xxx_freebsd.h> 46 #include <dev/aic7xxx/aic7xxx_inline.h> 47 #include <dev/aic7xxx/aic7xxx_93cx6.h> 48 #endif 49 50 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 51 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 52 53 static __inline uint64_t 54 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 55 { 56 uint64_t id; 57 58 id = subvendor 59 | (subdevice << 16) 60 | ((uint64_t)vendor << 32) 61 | ((uint64_t)device << 48); 62 63 return (id); 64 } 65 66 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 67 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 68 #define ID_AIC7850 0x5078900400000000ull 69 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 70 #define ID_AIC7855 0x5578900400000000ull 71 #define ID_AIC7859 0x3860900400000000ull 72 #define ID_AHA_2930CU 0x3860900438699004ull 73 #define ID_AIC7860 0x6078900400000000ull 74 #define ID_AIC7860C 0x6078900478609004ull 75 #define ID_AHA_1480A 0x6075900400000000ull 76 #define ID_AHA_2940AU_0 0x6178900400000000ull 77 #define ID_AHA_2940AU_1 0x6178900478619004ull 78 #define ID_AHA_2940AU_CN 0x2178900478219004ull 79 #define ID_AHA_2930C_VAR 0x6038900438689004ull 80 81 #define ID_AIC7870 0x7078900400000000ull 82 #define ID_AHA_2940 0x7178900400000000ull 83 #define ID_AHA_3940 0x7278900400000000ull 84 #define ID_AHA_398X 0x7378900400000000ull 85 #define ID_AHA_2944 0x7478900400000000ull 86 #define ID_AHA_3944 0x7578900400000000ull 87 #define ID_AHA_4944 0x7678900400000000ull 88 89 #define ID_AIC7880 0x8078900400000000ull 90 #define ID_AIC7880_B 0x8078900478809004ull 91 #define ID_AHA_2940U 0x8178900400000000ull 92 #define ID_AHA_3940U 0x8278900400000000ull 93 #define ID_AHA_2944U 0x8478900400000000ull 94 #define ID_AHA_3944U 0x8578900400000000ull 95 #define ID_AHA_398XU 0x8378900400000000ull 96 #define ID_AHA_4944U 0x8678900400000000ull 97 #define ID_AHA_2940UB 0x8178900478819004ull 98 #define ID_AHA_2930U 0x8878900478889004ull 99 #define ID_AHA_2940U_PRO 0x8778900478879004ull 100 #define ID_AHA_2940U_CN 0x0078900478009004ull 101 102 #define ID_AIC7895 0x7895900478959004ull 103 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 104 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 105 #define ID_AHA_3940AU 0x7895900478929004ull 106 #define ID_AHA_3944AU 0x7895900478949004ull 107 108 #define ID_AIC7890 0x001F9005000F9005ull 109 #define ID_AAA_131U2 0x0013900500039005ull 110 #define ID_AHA_2930U2 0x0011900501819005ull 111 #define ID_AHA_2940U2B 0x00109005A1009005ull 112 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 113 #define ID_AHA_2940U2 0x00109005A1809005ull 114 #define ID_AHA_2950U2B 0x00109005E1009005ull 115 116 #define ID_AIC7892 0x008F9005FFFF9005ull 117 #define ID_AHA_29160 0x00809005E2A09005ull 118 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 119 #define ID_AHA_29160N 0x0080900562A09005ull 120 #define ID_AHA_29160B 0x00809005E2209005ull 121 #define ID_AHA_19160B 0x0081900562A19005ull 122 123 #define ID_AIC7896 0x005F9005FFFF9005ull 124 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 125 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 126 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 127 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 128 129 #define ID_AIC7899 0x00CF9005FFFF9005ull 130 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 131 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 132 133 #define ID_AIC7810 0x1078900400000000ull 134 #define ID_AIC7815 0x7815900400000000ull 135 136 static ahc_device_setup_t ahc_aic7850_setup; 137 static ahc_device_setup_t ahc_aic7855_setup; 138 static ahc_device_setup_t ahc_aic7860_setup; 139 static ahc_device_setup_t ahc_aic7870_setup; 140 static ahc_device_setup_t ahc_aha394X_setup; 141 static ahc_device_setup_t ahc_aha494X_setup; 142 static ahc_device_setup_t ahc_aha398X_setup; 143 static ahc_device_setup_t ahc_aic7880_setup; 144 static ahc_device_setup_t ahc_2940Pro_setup; 145 static ahc_device_setup_t ahc_aha394XU_setup; 146 static ahc_device_setup_t ahc_aha398XU_setup; 147 static ahc_device_setup_t ahc_aic7890_setup; 148 static ahc_device_setup_t ahc_aic7892_setup; 149 static ahc_device_setup_t ahc_aic7895_setup; 150 static ahc_device_setup_t ahc_aic7896_setup; 151 static ahc_device_setup_t ahc_aic7899_setup; 152 static ahc_device_setup_t ahc_raid_setup; 153 static ahc_device_setup_t ahc_aha394XX_setup; 154 static ahc_device_setup_t ahc_aha494XX_setup; 155 static ahc_device_setup_t ahc_aha398XX_setup; 156 157 struct ahc_pci_identity ahc_pci_ident_table [] = 158 { 159 /* aic7850 based controllers */ 160 { 161 ID_AHA_2910_15_20_30C, 162 ID_ALL_MASK, 163 "Adaptec 2910/15/20/30C SCSI adapter", 164 ahc_aic7850_setup 165 }, 166 /* aic7860 based controllers */ 167 { 168 ID_AHA_2930CU, 169 ID_ALL_MASK, 170 "Adaptec 2930CU SCSI adapter", 171 ahc_aic7860_setup 172 }, 173 { 174 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 175 ID_DEV_VENDOR_MASK, 176 "Adaptec 1480A Ultra SCSI adapter", 177 ahc_aic7860_setup 178 }, 179 { 180 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 181 ID_DEV_VENDOR_MASK, 182 "Adaptec 2940A Ultra SCSI adapter", 183 ahc_aic7860_setup 184 }, 185 { 186 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 187 ID_DEV_VENDOR_MASK, 188 "Adaptec 2940A/CN Ultra SCSI adapter", 189 ahc_aic7860_setup 190 }, 191 { 192 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 193 ID_DEV_VENDOR_MASK, 194 "Adaptec 2930C SCSI adapter (VAR)", 195 ahc_aic7860_setup 196 }, 197 /* aic7870 based controllers */ 198 { 199 ID_AHA_2940, 200 ID_ALL_MASK, 201 "Adaptec 2940 SCSI adapter", 202 ahc_aic7870_setup 203 }, 204 { 205 ID_AHA_3940, 206 ID_ALL_MASK, 207 "Adaptec 3940 SCSI adapter", 208 ahc_aha394X_setup 209 }, 210 { 211 ID_AHA_398X, 212 ID_ALL_MASK, 213 "Adaptec 398X SCSI RAID adapter", 214 ahc_aha398X_setup 215 }, 216 { 217 ID_AHA_2944, 218 ID_ALL_MASK, 219 "Adaptec 2944 SCSI adapter", 220 ahc_aic7870_setup 221 }, 222 { 223 ID_AHA_3944, 224 ID_ALL_MASK, 225 "Adaptec 3944 SCSI adapter", 226 ahc_aha394X_setup 227 }, 228 { 229 ID_AHA_4944, 230 ID_ALL_MASK, 231 "Adaptec 4944 SCSI adapter", 232 ahc_aha494X_setup 233 }, 234 /* aic7880 based controllers */ 235 { 236 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 237 ID_DEV_VENDOR_MASK, 238 "Adaptec 2940 Ultra SCSI adapter", 239 ahc_aic7880_setup 240 }, 241 { 242 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 243 ID_DEV_VENDOR_MASK, 244 "Adaptec 3940 Ultra SCSI adapter", 245 ahc_aha394XU_setup 246 }, 247 { 248 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 249 ID_DEV_VENDOR_MASK, 250 "Adaptec 2944 Ultra SCSI adapter", 251 ahc_aic7880_setup 252 }, 253 { 254 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 255 ID_DEV_VENDOR_MASK, 256 "Adaptec 3944 Ultra SCSI adapter", 257 ahc_aha394XU_setup 258 }, 259 { 260 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 261 ID_DEV_VENDOR_MASK, 262 "Adaptec 398X Ultra SCSI RAID adapter", 263 ahc_aha398XU_setup 264 }, 265 { 266 /* 267 * XXX Don't know the slot numbers 268 * so we can't identify channels 269 */ 270 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 271 ID_DEV_VENDOR_MASK, 272 "Adaptec 4944 Ultra SCSI adapter", 273 ahc_aic7880_setup 274 }, 275 { 276 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 277 ID_DEV_VENDOR_MASK, 278 "Adaptec 2930 Ultra SCSI adapter", 279 ahc_aic7880_setup 280 }, 281 { 282 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 283 ID_DEV_VENDOR_MASK, 284 "Adaptec 2940 Pro Ultra SCSI adapter", 285 ahc_2940Pro_setup 286 }, 287 { 288 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 289 ID_DEV_VENDOR_MASK, 290 "Adaptec 2940/CN Ultra SCSI adapter", 291 ahc_aic7880_setup 292 }, 293 /* aic7890 based controllers */ 294 { 295 ID_AHA_2930U2, 296 ID_ALL_MASK, 297 "Adaptec 2930 Ultra2 SCSI adapter", 298 ahc_aic7890_setup 299 }, 300 { 301 ID_AHA_2940U2B, 302 ID_ALL_MASK, 303 "Adaptec 2940B Ultra2 SCSI adapter", 304 ahc_aic7890_setup 305 }, 306 { 307 ID_AHA_2940U2_OEM, 308 ID_ALL_MASK, 309 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 310 ahc_aic7890_setup 311 }, 312 { 313 ID_AHA_2940U2, 314 ID_ALL_MASK, 315 "Adaptec 2940 Ultra2 SCSI adapter", 316 ahc_aic7890_setup 317 }, 318 { 319 ID_AHA_2950U2B, 320 ID_ALL_MASK, 321 "Adaptec 2950 Ultra2 SCSI adapter", 322 ahc_aic7890_setup 323 }, 324 { 325 ID_AAA_131U2, 326 ID_ALL_MASK, 327 "Adaptec AAA-131 Ultra2 RAID adapter", 328 ahc_aic7890_setup 329 }, 330 /* aic7892 based controllers */ 331 { 332 ID_AHA_29160, 333 ID_ALL_MASK, 334 "Adaptec 29160 Ultra160 SCSI adapter", 335 ahc_aic7892_setup 336 }, 337 { 338 ID_AHA_29160_CPQ, 339 ID_ALL_MASK, 340 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 341 ahc_aic7892_setup 342 }, 343 { 344 ID_AHA_29160N, 345 ID_ALL_MASK, 346 "Adaptec 29160N Ultra160 SCSI adapter", 347 ahc_aic7892_setup 348 }, 349 { 350 ID_AHA_29160B, 351 ID_ALL_MASK, 352 "Adaptec 29160B Ultra160 SCSI adapter", 353 ahc_aic7892_setup 354 }, 355 { 356 ID_AHA_19160B, 357 ID_ALL_MASK, 358 "Adaptec 19160B Ultra160 SCSI adapter", 359 ahc_aic7892_setup 360 }, 361 /* aic7895 based controllers */ 362 { 363 ID_AHA_2940U_DUAL, 364 ID_ALL_MASK, 365 "Adaptec 2940/DUAL Ultra SCSI adapter", 366 ahc_aic7895_setup 367 }, 368 { 369 ID_AHA_3940AU, 370 ID_ALL_MASK, 371 "Adaptec 3940A Ultra SCSI adapter", 372 ahc_aic7895_setup 373 }, 374 { 375 ID_AHA_3944AU, 376 ID_ALL_MASK, 377 "Adaptec 3944A Ultra SCSI adapter", 378 ahc_aic7895_setup 379 }, 380 /* aic7896/97 based controllers */ 381 { 382 ID_AHA_3950U2B_0, 383 ID_ALL_MASK, 384 "Adaptec 3950B Ultra2 SCSI adapter", 385 ahc_aic7896_setup 386 }, 387 { 388 ID_AHA_3950U2B_1, 389 ID_ALL_MASK, 390 "Adaptec 3950B Ultra2 SCSI adapter", 391 ahc_aic7896_setup 392 }, 393 { 394 ID_AHA_3950U2D_0, 395 ID_ALL_MASK, 396 "Adaptec 3950D Ultra2 SCSI adapter", 397 ahc_aic7896_setup 398 }, 399 { 400 ID_AHA_3950U2D_1, 401 ID_ALL_MASK, 402 "Adaptec 3950D Ultra2 SCSI adapter", 403 ahc_aic7896_setup 404 }, 405 /* aic7899 based controllers */ 406 { 407 ID_AHA_3960D, 408 ID_ALL_MASK, 409 "Adaptec 3960D Ultra160 SCSI adapter", 410 ahc_aic7899_setup 411 }, 412 { 413 ID_AHA_3960D_CPQ, 414 ID_ALL_MASK, 415 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 416 ahc_aic7899_setup 417 }, 418 /* Generic chip probes for devices we don't know 'exactly' */ 419 { 420 ID_AIC7850 & ID_DEV_VENDOR_MASK, 421 ID_DEV_VENDOR_MASK, 422 "Adaptec aic7850 SCSI adapter", 423 ahc_aic7850_setup 424 }, 425 { 426 ID_AIC7855 & ID_DEV_VENDOR_MASK, 427 ID_DEV_VENDOR_MASK, 428 "Adaptec aic7855 SCSI adapter", 429 ahc_aic7855_setup 430 }, 431 { 432 ID_AIC7859 & ID_DEV_VENDOR_MASK, 433 ID_DEV_VENDOR_MASK, 434 "Adaptec aic7859 Ultra SCSI adapter", 435 ahc_aic7860_setup 436 }, 437 { 438 ID_AIC7860 & ID_DEV_VENDOR_MASK, 439 ID_DEV_VENDOR_MASK, 440 "Adaptec aic7860 SCSI adapter", 441 ahc_aic7860_setup 442 }, 443 { 444 ID_AIC7870 & ID_DEV_VENDOR_MASK, 445 ID_DEV_VENDOR_MASK, 446 "Adaptec aic7870 SCSI adapter", 447 ahc_aic7870_setup 448 }, 449 { 450 ID_AIC7880 & ID_DEV_VENDOR_MASK, 451 ID_DEV_VENDOR_MASK, 452 "Adaptec aic7880 Ultra SCSI adapter", 453 ahc_aic7880_setup 454 }, 455 { 456 ID_AIC7890 & ID_DEV_VENDOR_MASK, 457 ID_DEV_VENDOR_MASK, 458 "Adaptec aic7890/91 Ultra2 SCSI adapter", 459 ahc_aic7890_setup 460 }, 461 { 462 ID_AIC7892 & ID_DEV_VENDOR_MASK, 463 ID_DEV_VENDOR_MASK, 464 "Adaptec aic7892 Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7895 & ID_DEV_VENDOR_MASK, 469 ID_DEV_VENDOR_MASK, 470 "Adaptec aic7895 Ultra SCSI adapter", 471 ahc_aic7895_setup 472 }, 473 { 474 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 475 ID_DEV_VENDOR_MASK, 476 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 477 ahc_aic7895_setup 478 }, 479 { 480 ID_AIC7896 & ID_DEV_VENDOR_MASK, 481 ID_DEV_VENDOR_MASK, 482 "Adaptec aic7896/97 Ultra2 SCSI adapter", 483 ahc_aic7896_setup 484 }, 485 { 486 ID_AIC7899 & ID_DEV_VENDOR_MASK, 487 ID_DEV_VENDOR_MASK, 488 "Adaptec aic7899 Ultra160 SCSI adapter", 489 ahc_aic7899_setup 490 }, 491 { 492 ID_AIC7810 & ID_DEV_VENDOR_MASK, 493 ID_DEV_VENDOR_MASK, 494 "Adaptec aic7810 RAID memory controller", 495 ahc_raid_setup 496 }, 497 { 498 ID_AIC7815 & ID_DEV_VENDOR_MASK, 499 ID_DEV_VENDOR_MASK, 500 "Adaptec aic7815 RAID memory controller", 501 ahc_raid_setup 502 } 503 }; 504 505 const int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 506 507 #define AHC_394X_SLOT_CHANNEL_A 4 508 #define AHC_394X_SLOT_CHANNEL_B 5 509 510 #define AHC_398X_SLOT_CHANNEL_A 4 511 #define AHC_398X_SLOT_CHANNEL_B 8 512 #define AHC_398X_SLOT_CHANNEL_C 12 513 514 #define AHC_494X_SLOT_CHANNEL_A 4 515 #define AHC_494X_SLOT_CHANNEL_B 5 516 #define AHC_494X_SLOT_CHANNEL_C 6 517 #define AHC_494X_SLOT_CHANNEL_D 7 518 519 #define DEVCONFIG 0x40 520 #define SCBSIZE32 0x00010000ul /* aic789X only */ 521 #define MPORTMODE 0x00000400ul /* aic7870 only */ 522 #define RAMPSM 0x00000200ul /* aic7870 only */ 523 #define VOLSENSE 0x00000100ul 524 #define SCBRAMSEL 0x00000080ul 525 #define MRDCEN 0x00000040ul 526 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 527 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 528 #define BERREN 0x00000008ul 529 #define DACEN 0x00000004ul 530 #define STPWLEVEL 0x00000002ul 531 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 532 533 #define CSIZE_LATTIME 0x0c 534 #define CACHESIZE 0x0000003ful /* only 5 bits */ 535 #define LATTIME 0x0000ff00ul 536 537 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 538 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 539 int pcheck, int fast, int large); 540 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 541 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 542 static void configure_termination(struct ahc_softc *ahc, 543 struct seeprom_descriptor *sd, 544 u_int adapter_control, 545 u_int *sxfrctl1); 546 547 static void ahc_new_term_detect(struct ahc_softc *ahc, 548 int *enableSEC_low, 549 int *enableSEC_high, 550 int *enablePRI_low, 551 int *enablePRI_high, 552 int *eeprom_present); 553 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 554 int *internal68_present, 555 int *externalcable_present, 556 int *eeprom_present); 557 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 558 int *externalcable_present, 559 int *eeprom_present); 560 static int acquire_seeprom(struct ahc_softc *ahc, 561 struct seeprom_descriptor *sd); 562 static void release_seeprom(struct seeprom_descriptor *sd); 563 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 564 static uint8_t read_brdctl(struct ahc_softc *ahc); 565 566 struct ahc_pci_identity * 567 ahc_find_pci_device(ahc_dev_softc_t pci) 568 { 569 uint64_t full_id; 570 uint16_t device; 571 uint16_t vendor; 572 uint16_t subdevice; 573 uint16_t subvendor; 574 struct ahc_pci_identity *entry; 575 u_int i; 576 577 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 578 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 579 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 580 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 581 full_id = ahc_compose_id(device, 582 vendor, 583 subdevice, 584 subvendor); 585 586 for (i = 0; i < ahc_num_pci_devs; i++) { 587 entry = &ahc_pci_ident_table[i]; 588 if (entry->full_id == (full_id & entry->id_mask)) 589 return (entry); 590 } 591 return (NULL); 592 } 593 594 int 595 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 596 { 597 struct ahc_probe_config probe_config; 598 struct scb_data *shared_scb_data; 599 u_int command; 600 u_int our_id = 0; 601 u_int sxfrctl1; 602 u_int scsiseq; 603 u_int dscommand0; 604 int error; 605 uint8_t sblkctl; 606 607 shared_scb_data = NULL; 608 ahc_init_probe_config(&probe_config); 609 error = entry->setup(ahc->dev_softc, &probe_config); 610 if (error != 0) 611 return (error); 612 probe_config.chip |= AHC_PCI; 613 probe_config.description = entry->name; 614 615 error = ahc_pci_map_registers(ahc); 616 if (error != 0) 617 return (error); 618 619 /* Ensure busmastering is enabled */ 620 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 621 command |= PCIM_CMD_BUSMASTEREN; 622 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 623 624 /* On all PCI adapters, we allow SCB paging */ 625 probe_config.flags |= AHC_PAGESCBS; 626 627 error = ahc_softc_init(ahc, &probe_config); 628 if (error != 0) 629 return (error); 630 631 /* Remeber how the card was setup in case there is no SEEPROM */ 632 pause_sequencer(ahc); 633 if ((ahc->features & AHC_ULTRA2) != 0) 634 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 635 else 636 our_id = ahc_inb(ahc, SCSIID) & OID; 637 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 638 scsiseq = ahc_inb(ahc, SCSISEQ); 639 640 error = ahc_reset(ahc); 641 if (error != 0) 642 return (ENXIO); 643 644 if ((ahc->features & AHC_DT) != 0) { 645 u_int sfunct; 646 647 /* Perform ALT-Mode Setup */ 648 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 649 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 650 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 651 /* Send CRC info in target mode every 4K */ 652 ahc_outb(ahc, TARGCRCCNT, 0); 653 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 654 ahc_outb(ahc, SFUNCT, sfunct); 655 656 /* Normal mode setup */ 657 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 658 |TARGCRCENDEN|TARGCRCCNTEN); 659 } 660 661 error = ahc_pci_map_int(ahc); 662 if (error != 0) 663 return (error); 664 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 665 dscommand0 |= MPARCKEN|CACHETHEN; 666 if ((ahc->features & AHC_ULTRA2) != 0) { 667 668 /* 669 * DPARCKEN doesn't work correctly on 670 * some MBs so don't use it. 671 */ 672 dscommand0 &= ~DPARCKEN; 673 } 674 675 /* 676 * Handle chips that must have cache line 677 * streaming (dis/en)abled. 678 */ 679 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 680 dscommand0 |= CACHETHEN; 681 682 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 683 dscommand0 &= ~CACHETHEN; 684 685 ahc_outb(ahc, DSCOMMAND0, dscommand0); 686 687 ahc->pci_cachesize = 688 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 689 /*bytes*/1) & CACHESIZE; 690 ahc->pci_cachesize *= 4; 691 692 /* See if we have a SEEPROM and perform auto-term */ 693 check_extport(ahc, &sxfrctl1); 694 695 /* 696 * Take the LED out of diagnostic mode 697 */ 698 sblkctl = ahc_inb(ahc, SBLKCTL); 699 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 700 701 if ((ahc->features & AHC_ULTRA2) != 0) { 702 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 703 } else { 704 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 705 } 706 707 if (ahc->flags & AHC_USEDEFAULTS) { 708 /* 709 * PCI Adapter default setup 710 * Should only be used if the adapter does not have 711 * a SEEPROM. 712 */ 713 /* See if someone else set us up already */ 714 if (scsiseq != 0) { 715 printf("%s: Using left over BIOS settings\n", 716 ahc_name(ahc)); 717 ahc->flags &= ~AHC_USEDEFAULTS; 718 } else { 719 /* 720 * Assume only one connector and always turn 721 * on termination. 722 */ 723 our_id = 0x07; 724 sxfrctl1 = STPWEN; 725 } 726 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 727 728 ahc->our_id = our_id; 729 } 730 731 /* 732 * Take a look to see if we have external SRAM. 733 * We currently do not attempt to use SRAM that is 734 * shared among multiple controllers. 735 */ 736 ahc_probe_ext_scbram(ahc); 737 738 /* 739 * Record our termination setting for the 740 * generic initialization routine. 741 */ 742 if ((sxfrctl1 & STPWEN) != 0) 743 ahc->flags |= AHC_TERM_ENB_A; 744 745 /* Core initialization */ 746 error = ahc_init(ahc); 747 if (error != 0) 748 return (error); 749 750 /* 751 * Link this softc in with all other ahc instances. 752 */ 753 ahc_softc_insert(ahc); 754 755 return (0); 756 } 757 758 /* 759 * Test for the presense of external sram in an 760 * "unshared" configuration. 761 */ 762 static int 763 ahc_ext_scbram_present(struct ahc_softc *ahc) 764 { 765 u_int chip; 766 int ramps; 767 int single_user; 768 uint32_t devconfig; 769 770 chip = ahc->chip & AHC_CHIPID_MASK; 771 devconfig = ahc_pci_read_config(ahc->dev_softc, 772 DEVCONFIG, /*bytes*/4); 773 single_user = (devconfig & MPORTMODE) != 0; 774 775 if ((ahc->features & AHC_ULTRA2) != 0) 776 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 777 else if (chip >= AHC_AIC7870) 778 ramps = (devconfig & RAMPSM) != 0; 779 else 780 ramps = 0; 781 782 if (ramps && single_user) 783 return (1); 784 return (0); 785 } 786 787 /* 788 * Enable external scbram. 789 */ 790 static void 791 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 792 int fast, int large) 793 { 794 uint32_t devconfig; 795 796 if (ahc->features & AHC_MULTI_FUNC) { 797 /* 798 * Set the SCB Base addr (highest address bit) 799 * depending on which channel we are. 800 */ 801 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 802 } 803 804 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 805 if ((ahc->features & AHC_ULTRA2) != 0) { 806 u_int dscommand0; 807 808 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 809 if (enable) 810 dscommand0 &= ~INTSCBRAMSEL; 811 else 812 dscommand0 |= INTSCBRAMSEL; 813 if (large) 814 dscommand0 &= ~USCBSIZE32; 815 else 816 dscommand0 |= USCBSIZE32; 817 ahc_outb(ahc, DSCOMMAND0, dscommand0); 818 } else { 819 if (fast) 820 devconfig &= ~EXTSCBTIME; 821 else 822 devconfig |= EXTSCBTIME; 823 if (enable) 824 devconfig &= ~SCBRAMSEL; 825 else 826 devconfig |= SCBRAMSEL; 827 if (large) 828 devconfig &= ~SCBSIZE32; 829 else 830 devconfig |= SCBSIZE32; 831 } 832 if (pcheck) 833 devconfig |= EXTSCBPEN; 834 else 835 devconfig &= ~EXTSCBPEN; 836 837 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 838 } 839 840 /* 841 * Take a look to see if we have external SRAM. 842 * We currently do not attempt to use SRAM that is 843 * shared among multiple controllers. 844 */ 845 static void 846 ahc_probe_ext_scbram(struct ahc_softc *ahc) 847 { 848 int num_scbs; 849 int test_num_scbs; 850 int enable; 851 int pcheck; 852 int fast; 853 int large; 854 855 enable = FALSE; 856 pcheck = FALSE; 857 fast = FALSE; 858 large = FALSE; 859 num_scbs = 0; 860 861 if (ahc_ext_scbram_present(ahc) == 0) 862 goto done; 863 864 /* 865 * Probe for the best parameters to use. 866 */ 867 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 868 num_scbs = ahc_probe_scbs(ahc); 869 if (num_scbs == 0) { 870 /* The SRAM wasn't really present. */ 871 goto done; 872 } 873 enable = TRUE; 874 875 /* 876 * Clear any outstanding parity error 877 * and ensure that parity error reporting 878 * is enabled. 879 */ 880 ahc_outb(ahc, SEQCTL, 0); 881 ahc_outb(ahc, CLRINT, CLRPARERR); 882 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 883 884 /* Now see if we can do parity */ 885 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 886 num_scbs = ahc_probe_scbs(ahc); 887 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 888 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 889 pcheck = TRUE; 890 891 /* Clear any resulting parity error */ 892 ahc_outb(ahc, CLRINT, CLRPARERR); 893 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 894 895 /* Now see if we can do fast timing */ 896 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 897 test_num_scbs = ahc_probe_scbs(ahc); 898 if (test_num_scbs == num_scbs 899 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 900 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 901 fast = TRUE; 902 903 /* 904 * See if we can use large SCBs and still maintain 905 * the same overall count of SCBs. 906 */ 907 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 908 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 909 test_num_scbs = ahc_probe_scbs(ahc); 910 if (test_num_scbs >= num_scbs) { 911 large = TRUE; 912 num_scbs = test_num_scbs; 913 if (num_scbs >= 64) { 914 /* 915 * We have enough space to move the 916 * "busy targets table" into SCB space 917 * and make it qualify all the way to the 918 * lun level. 919 */ 920 ahc->flags |= AHC_SCB_BTT; 921 } 922 } 923 } 924 done: 925 /* 926 * Disable parity error reporting until we 927 * can load instruction ram. 928 */ 929 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 930 /* Clear any latched parity error */ 931 ahc_outb(ahc, CLRINT, CLRPARERR); 932 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 933 if (bootverbose && enable) { 934 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 935 ahc_name(ahc), fast ? "fast" : "slow", 936 pcheck ? ", parity checking enabled" : "", 937 large ? 64 : 32); 938 } 939 ahc_scbram_config(ahc, enable, pcheck, fast, large); 940 } 941 942 /* 943 * Check the external port logic for a serial eeprom 944 * and termination/cable detection contrls. 945 */ 946 static void 947 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 948 { 949 struct seeprom_descriptor sd; 950 struct seeprom_config sc; 951 u_int scsi_conf; 952 u_int adapter_control; 953 int have_seeprom; 954 int have_autoterm; 955 956 sd.sd_ahc = ahc; 957 sd.sd_control_offset = SEECTL; 958 sd.sd_status_offset = SEECTL; 959 sd.sd_dataout_offset = SEECTL; 960 961 /* 962 * For some multi-channel devices, the c46 is simply too 963 * small to work. For the other controller types, we can 964 * get our information from either SEEPROM type. Set the 965 * type to start our probe with accordingly. 966 */ 967 if (ahc->flags & AHC_LARGE_SEEPROM) 968 sd.sd_chip = C56_66; 969 else 970 sd.sd_chip = C46; 971 972 sd.sd_MS = SEEMS; 973 sd.sd_RDY = SEERDY; 974 sd.sd_CS = SEECS; 975 sd.sd_CK = SEECK; 976 sd.sd_DO = SEEDO; 977 sd.sd_DI = SEEDI; 978 979 have_seeprom = acquire_seeprom(ahc, &sd); 980 if (have_seeprom) { 981 982 if (bootverbose) 983 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 984 985 for (;;) { 986 u_int start_addr; 987 988 start_addr = 32 * (ahc->channel - 'A'); 989 990 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 991 start_addr, sizeof(sc)/2); 992 993 if (have_seeprom) 994 have_seeprom = verify_cksum(&sc); 995 996 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 997 if (bootverbose) { 998 if (have_seeprom == 0) 999 printf ("checksum error\n"); 1000 else 1001 printf ("done.\n"); 1002 } 1003 break; 1004 } 1005 sd.sd_chip = C56_66; 1006 } 1007 } 1008 1009 #if 0 1010 if (!have_seeprom) { 1011 /* 1012 * Pull scratch ram settings and treat them as 1013 * if they are the contents of an seeprom if 1014 * the 'ADPT' signature is found in SCB2. 1015 */ 1016 ahc_outb(ahc, SCBPTR, 2); 1017 if (ahc_inb(ahc, SCB_BASE) == 'A' 1018 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1019 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1020 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1021 uint8_t *sc_bytes; 1022 int i; 1023 1024 sc_bytes = (uint8_t *)≻ 1025 for (i = 0; i < 64; i++) 1026 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); 1027 /* Byte 0x1c is stored in byte 4 of SCB2 */ 1028 sc_bytes[0x1c] = ahc_inb(ahc, SCB_BASE + 4); 1029 have_seeprom = verify_cksum(&sc); 1030 } 1031 } 1032 #endif 1033 1034 if (!have_seeprom) { 1035 if (bootverbose) 1036 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1037 ahc->flags |= AHC_USEDEFAULTS; 1038 } else { 1039 /* 1040 * Put the data we've collected down into SRAM 1041 * where ahc_init will find it. 1042 */ 1043 int i; 1044 int max_targ = sc.max_targets & CFMAXTARG; 1045 uint16_t discenable; 1046 uint16_t ultraenb; 1047 1048 discenable = 0; 1049 ultraenb = 0; 1050 if ((sc.adapter_control & CFULTRAEN) != 0) { 1051 /* 1052 * Determine if this adapter has a "newstyle" 1053 * SEEPROM format. 1054 */ 1055 for (i = 0; i < max_targ; i++) { 1056 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1057 ahc->flags |= AHC_NEWEEPROM_FMT; 1058 break; 1059 } 1060 } 1061 } 1062 1063 for (i = 0; i < max_targ; i++) { 1064 u_int scsirate; 1065 uint16_t target_mask; 1066 1067 target_mask = 0x01 << i; 1068 if (sc.device_flags[i] & CFDISC) 1069 discenable |= target_mask; 1070 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1071 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1072 ultraenb |= target_mask; 1073 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1074 ultraenb |= target_mask; 1075 } 1076 if ((sc.device_flags[i] & CFXFER) == 0x04 1077 && (ultraenb & target_mask) != 0) { 1078 /* Treat 10MHz as a non-ultra speed */ 1079 sc.device_flags[i] &= ~CFXFER; 1080 ultraenb &= ~target_mask; 1081 } 1082 if ((ahc->features & AHC_ULTRA2) != 0) { 1083 u_int offset; 1084 1085 if (sc.device_flags[i] & CFSYNCH) 1086 offset = MAX_OFFSET_ULTRA2; 1087 else 1088 offset = 0; 1089 ahc_outb(ahc, TARG_OFFSET + i, offset); 1090 1091 /* 1092 * The ultra enable bits contain the 1093 * high bit of the ultra2 sync rate 1094 * field. 1095 */ 1096 scsirate = (sc.device_flags[i] & CFXFER) 1097 | ((ultraenb & target_mask) 1098 ? 0x8 : 0x0); 1099 if (sc.device_flags[i] & CFWIDEB) 1100 scsirate |= WIDEXFER; 1101 } else { 1102 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1103 if (sc.device_flags[i] & CFSYNCH) 1104 scsirate |= SOFS; 1105 if (sc.device_flags[i] & CFWIDEB) 1106 scsirate |= WIDEXFER; 1107 } 1108 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1109 } 1110 ahc->our_id = sc.brtime_id & CFSCSIID; 1111 1112 scsi_conf = (ahc->our_id & 0x7); 1113 if (sc.adapter_control & CFSPARITY) 1114 scsi_conf |= ENSPCHK; 1115 if (sc.adapter_control & CFRESETB) 1116 scsi_conf |= RESET_SCSI; 1117 1118 if (sc.bios_control & CFEXTEND) 1119 ahc->flags |= AHC_EXTENDED_TRANS_A; 1120 if (ahc->features & AHC_ULTRA 1121 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1122 /* Should we enable Ultra mode? */ 1123 if (!(sc.adapter_control & CFULTRAEN)) 1124 /* Treat us as a non-ultra card */ 1125 ultraenb = 0; 1126 } 1127 1128 if (sc.signature == CFSIGNATURE) { 1129 uint32_t devconfig; 1130 1131 /* Honor the STPWLEVEL settings */ 1132 devconfig = ahc_pci_read_config(ahc->dev_softc, 1133 DEVCONFIG, /*bytes*/4); 1134 devconfig &= ~STPWLEVEL; 1135 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1136 devconfig |= STPWLEVEL; 1137 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1138 devconfig, /*bytes*/4); 1139 } 1140 /* Set SCSICONF info */ 1141 ahc_outb(ahc, SCSICONF, scsi_conf); 1142 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1143 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1144 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1145 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1146 } 1147 1148 /* 1149 * Cards that have the external logic necessary to talk to 1150 * a SEEPROM, are almost certain to have the remaining logic 1151 * necessary for auto-termination control. This assumption 1152 * hasn't failed yet... 1153 */ 1154 have_autoterm = have_seeprom; 1155 if (have_seeprom) 1156 adapter_control = sc.adapter_control; 1157 else 1158 adapter_control = CFAUTOTERM; 1159 1160 /* 1161 * Some low-cost chips have SEEPROM and auto-term control built 1162 * in, instead of using a GAL. They can tell us directly 1163 * if the termination logic is enabled. 1164 */ 1165 if ((ahc->features & AHC_SPIOCAP) != 0) { 1166 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1167 have_autoterm = TRUE; 1168 else 1169 have_autoterm = FALSE; 1170 } 1171 1172 if (have_autoterm) 1173 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1174 1175 release_seeprom(&sd); 1176 } 1177 1178 static void 1179 configure_termination(struct ahc_softc *ahc, 1180 struct seeprom_descriptor *sd, 1181 u_int adapter_control, 1182 u_int *sxfrctl1) 1183 { 1184 uint8_t brddat; 1185 1186 brddat = 0; 1187 1188 /* 1189 * Update the settings in sxfrctl1 to match the 1190 * termination settings 1191 */ 1192 *sxfrctl1 = 0; 1193 1194 /* 1195 * SEECS must be on for the GALS to latch 1196 * the data properly. Be sure to leave MS 1197 * on or we will release the seeprom. 1198 */ 1199 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1200 if ((adapter_control & CFAUTOTERM) != 0 1201 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1202 int internal50_present; 1203 int internal68_present; 1204 int externalcable_present; 1205 int eeprom_present; 1206 int enableSEC_low; 1207 int enableSEC_high; 1208 int enablePRI_low; 1209 int enablePRI_high; 1210 1211 enableSEC_low = 0; 1212 enableSEC_high = 0; 1213 enablePRI_low = 0; 1214 enablePRI_high = 0; 1215 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1216 ahc_new_term_detect(ahc, &enableSEC_low, 1217 &enableSEC_high, 1218 &enablePRI_low, 1219 &enablePRI_high, 1220 &eeprom_present); 1221 if ((adapter_control & CFSEAUTOTERM) == 0) { 1222 if (bootverbose) 1223 printf("%s: Manual SE Termination\n", 1224 ahc_name(ahc)); 1225 enableSEC_low = (adapter_control & CFSELOWTERM); 1226 enableSEC_high = 1227 (adapter_control & CFSEHIGHTERM); 1228 } 1229 if ((adapter_control & CFAUTOTERM) == 0) { 1230 if (bootverbose) 1231 printf("%s: Manual LVD Termination\n", 1232 ahc_name(ahc)); 1233 enablePRI_low = (adapter_control & CFSTERM); 1234 enablePRI_high = (adapter_control & CFWSTERM); 1235 } 1236 /* Make the table calculations below happy */ 1237 internal50_present = 0; 1238 internal68_present = 1; 1239 externalcable_present = 1; 1240 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1241 aic785X_cable_detect(ahc, &internal50_present, 1242 &externalcable_present, 1243 &eeprom_present); 1244 } else { 1245 aic787X_cable_detect(ahc, &internal50_present, 1246 &internal68_present, 1247 &externalcable_present, 1248 &eeprom_present); 1249 } 1250 1251 if ((ahc->features & AHC_WIDE) == 0) 1252 internal68_present = 0; 1253 1254 if (bootverbose) { 1255 if ((ahc->features & AHC_ULTRA2) == 0) { 1256 printf("%s: internal 50 cable %s present, " 1257 "internal 68 cable %s present\n", 1258 ahc_name(ahc), 1259 internal50_present ? "is":"not", 1260 internal68_present ? "is":"not"); 1261 1262 printf("%s: external cable %s present\n", 1263 ahc_name(ahc), 1264 externalcable_present ? "is":"not"); 1265 } 1266 printf("%s: BIOS eeprom %s present\n", 1267 ahc_name(ahc), eeprom_present ? "is" : "not"); 1268 } 1269 1270 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1271 /* 1272 * The 50 pin connector is a separate bus, 1273 * so force it to always be terminated. 1274 * In the future, perform current sensing 1275 * to determine if we are in the middle of 1276 * a properly terminated bus. 1277 */ 1278 internal50_present = 0; 1279 } 1280 1281 /* 1282 * Now set the termination based on what 1283 * we found. 1284 * Flash Enable = BRDDAT7 1285 * Secondary High Term Enable = BRDDAT6 1286 * Secondary Low Term Enable = BRDDAT5 (7890) 1287 * Primary High Term Enable = BRDDAT4 (7890) 1288 */ 1289 if ((ahc->features & AHC_ULTRA2) == 0 1290 && (internal50_present != 0) 1291 && (internal68_present != 0) 1292 && (externalcable_present != 0)) { 1293 printf("%s: Illegal cable configuration!!. " 1294 "Only two connectors on the " 1295 "adapter may be used at a " 1296 "time!\n", ahc_name(ahc)); 1297 } 1298 1299 if ((ahc->features & AHC_WIDE) != 0 1300 && ((externalcable_present == 0) 1301 || (internal68_present == 0) 1302 || (enableSEC_high != 0))) { 1303 brddat |= BRDDAT6; 1304 if (bootverbose) { 1305 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1306 printf("%s: 68 pin termination " 1307 "Enabled\n", ahc_name(ahc)); 1308 else 1309 printf("%s: %sHigh byte termination " 1310 "Enabled\n", ahc_name(ahc), 1311 enableSEC_high ? "Secondary " 1312 : ""); 1313 } 1314 } 1315 1316 if (((internal50_present ? 1 : 0) 1317 + (internal68_present ? 1 : 0) 1318 + (externalcable_present ? 1 : 0)) <= 1 1319 || (enableSEC_low != 0)) { 1320 if ((ahc->features & AHC_ULTRA2) != 0) 1321 brddat |= BRDDAT5; 1322 else 1323 *sxfrctl1 |= STPWEN; 1324 if (bootverbose) { 1325 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1326 printf("%s: 50 pin termination " 1327 "Enabled\n", ahc_name(ahc)); 1328 else 1329 printf("%s: %sLow byte termination " 1330 "Enabled\n", ahc_name(ahc), 1331 enableSEC_low ? "Secondary " 1332 : ""); 1333 } 1334 } 1335 1336 if (enablePRI_low != 0) { 1337 *sxfrctl1 |= STPWEN; 1338 if (bootverbose) 1339 printf("%s: Primary Low Byte termination " 1340 "Enabled\n", ahc_name(ahc)); 1341 } 1342 1343 /* 1344 * Setup STPWEN before setting up the rest of 1345 * the termination per the tech note on the U160 cards. 1346 */ 1347 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1348 1349 if (enablePRI_high != 0) { 1350 brddat |= BRDDAT4; 1351 if (bootverbose) 1352 printf("%s: Primary High Byte " 1353 "termination Enabled\n", 1354 ahc_name(ahc)); 1355 } 1356 1357 write_brdctl(ahc, brddat); 1358 1359 } else { 1360 if ((adapter_control & CFSTERM) != 0) { 1361 *sxfrctl1 |= STPWEN; 1362 1363 if (bootverbose) 1364 printf("%s: %sLow byte termination Enabled\n", 1365 ahc_name(ahc), 1366 (ahc->features & AHC_ULTRA2) ? "Primary " 1367 : ""); 1368 } 1369 1370 if ((adapter_control & CFWSTERM) != 0) { 1371 brddat |= BRDDAT6; 1372 if (bootverbose) 1373 printf("%s: %sHigh byte termination Enabled\n", 1374 ahc_name(ahc), 1375 (ahc->features & AHC_ULTRA2) 1376 ? "Secondary " : ""); 1377 } 1378 1379 /* 1380 * Setup STPWEN before setting up the rest of 1381 * the termination per the tech note on the U160 cards. 1382 */ 1383 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1384 1385 write_brdctl(ahc, brddat); 1386 } 1387 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1388 } 1389 1390 static void 1391 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1392 int *enableSEC_high, int *enablePRI_low, 1393 int *enablePRI_high, int *eeprom_present) 1394 { 1395 uint8_t brdctl; 1396 1397 /* 1398 * BRDDAT7 = Eeprom 1399 * BRDDAT6 = Enable Secondary High Byte termination 1400 * BRDDAT5 = Enable Secondary Low Byte termination 1401 * BRDDAT4 = Enable Primary high byte termination 1402 * BRDDAT3 = Enable Primary low byte termination 1403 */ 1404 brdctl = read_brdctl(ahc); 1405 *eeprom_present = brdctl & BRDDAT7; 1406 *enableSEC_high = (brdctl & BRDDAT6); 1407 *enableSEC_low = (brdctl & BRDDAT5); 1408 *enablePRI_high = (brdctl & BRDDAT4); 1409 *enablePRI_low = (brdctl & BRDDAT3); 1410 } 1411 1412 static void 1413 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1414 int *internal68_present, int *externalcable_present, 1415 int *eeprom_present) 1416 { 1417 uint8_t brdctl; 1418 1419 /* 1420 * First read the status of our cables. 1421 * Set the rom bank to 0 since the 1422 * bank setting serves as a multiplexor 1423 * for the cable detection logic. 1424 * BRDDAT5 controls the bank switch. 1425 */ 1426 write_brdctl(ahc, 0); 1427 1428 /* 1429 * Now read the state of the internal 1430 * connectors. BRDDAT6 is INT50 and 1431 * BRDDAT7 is INT68. 1432 */ 1433 brdctl = read_brdctl(ahc); 1434 *internal50_present = !(brdctl & BRDDAT6); 1435 *internal68_present = !(brdctl & BRDDAT7); 1436 1437 /* 1438 * Set the rom bank to 1 and determine 1439 * the other signals. 1440 */ 1441 write_brdctl(ahc, BRDDAT5); 1442 1443 /* 1444 * Now read the state of the external 1445 * connectors. BRDDAT6 is EXT68 and 1446 * BRDDAT7 is EPROMPS. 1447 */ 1448 brdctl = read_brdctl(ahc); 1449 *externalcable_present = !(brdctl & BRDDAT6); 1450 *eeprom_present = brdctl & BRDDAT7; 1451 } 1452 1453 static void 1454 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1455 int *externalcable_present, int *eeprom_present) 1456 { 1457 uint8_t brdctl; 1458 1459 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1460 ahc_outb(ahc, BRDCTL, 0); 1461 brdctl = ahc_inb(ahc, BRDCTL); 1462 *internal50_present = !(brdctl & BRDDAT5); 1463 *externalcable_present = !(brdctl & BRDDAT6); 1464 1465 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1466 } 1467 1468 static int 1469 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1470 { 1471 int wait; 1472 1473 if ((ahc->features & AHC_SPIOCAP) != 0 1474 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1475 return (0); 1476 1477 /* 1478 * Request access of the memory port. When access is 1479 * granted, SEERDY will go high. We use a 1 second 1480 * timeout which should be near 1 second more than 1481 * is needed. Reason: after the chip reset, there 1482 * should be no contention. 1483 */ 1484 SEEPROM_OUTB(sd, sd->sd_MS); 1485 wait = 1000; /* 1 second timeout in msec */ 1486 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1487 ahc_delay(1000); /* delay 1 msec */ 1488 } 1489 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1490 SEEPROM_OUTB(sd, 0); 1491 return (0); 1492 } 1493 return(1); 1494 } 1495 1496 static void 1497 release_seeprom(struct seeprom_descriptor *sd) 1498 { 1499 /* Release access to the memory port and the serial EEPROM. */ 1500 SEEPROM_OUTB(sd, 0); 1501 } 1502 1503 static void 1504 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1505 { 1506 uint8_t brdctl; 1507 1508 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1509 brdctl = BRDSTB; 1510 if (ahc->channel == 'B') 1511 brdctl |= BRDCS; 1512 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1513 brdctl = 0; 1514 } else { 1515 brdctl = BRDSTB|BRDCS; 1516 } 1517 ahc_outb(ahc, BRDCTL, brdctl); 1518 ahc_delay(20); 1519 brdctl |= value; 1520 ahc_outb(ahc, BRDCTL, brdctl); 1521 ahc_delay(20); 1522 if ((ahc->features & AHC_ULTRA2) != 0) 1523 brdctl |= BRDSTB_ULTRA2; 1524 else 1525 brdctl &= ~BRDSTB; 1526 ahc_outb(ahc, BRDCTL, brdctl); 1527 ahc_delay(20); 1528 if ((ahc->features & AHC_ULTRA2) != 0) 1529 brdctl = 0; 1530 else 1531 brdctl &= ~BRDCS; 1532 ahc_outb(ahc, BRDCTL, brdctl); 1533 } 1534 1535 static uint8_t 1536 read_brdctl(ahc) 1537 struct ahc_softc *ahc; 1538 { 1539 uint8_t brdctl; 1540 uint8_t value; 1541 1542 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1543 brdctl = BRDRW; 1544 if (ahc->channel == 'B') 1545 brdctl |= BRDCS; 1546 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1547 brdctl = BRDRW_ULTRA2; 1548 } else { 1549 brdctl = BRDRW|BRDCS; 1550 } 1551 ahc_outb(ahc, BRDCTL, brdctl); 1552 ahc_delay(20); 1553 value = ahc_inb(ahc, BRDCTL); 1554 ahc_outb(ahc, BRDCTL, 0); 1555 return (value); 1556 } 1557 1558 #define DPE 0x80 1559 #define SSE 0x40 1560 #define RMA 0x20 1561 #define RTA 0x10 1562 #define STA 0x08 1563 #define DPR 0x01 1564 1565 void 1566 ahc_pci_intr(struct ahc_softc *ahc) 1567 { 1568 u_int error; 1569 u_int status1; 1570 1571 error = ahc_inb(ahc, ERROR); 1572 if ((error & PCIERRSTAT) == 0) 1573 return; 1574 1575 status1 = ahc_pci_read_config(ahc->dev_softc, 1576 PCIR_STATUS + 1, /*bytes*/1); 1577 1578 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1579 ahc_name(ahc), 1580 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1581 1582 if (status1 & DPE) { 1583 printf("%s: Data Parity Error Detected during address " 1584 "or write data phase\n", ahc_name(ahc)); 1585 } 1586 if (status1 & SSE) { 1587 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1588 } 1589 if (status1 & RMA) { 1590 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1591 } 1592 if (status1 & RTA) { 1593 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1594 } 1595 if (status1 & STA) { 1596 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1597 } 1598 if (status1 & DPR) { 1599 printf("%s: Data Parity Error has been reported via PERR#\n", 1600 ahc_name(ahc)); 1601 } 1602 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1603 printf("%s: Latched PCIERR interrupt with " 1604 "no status bits set\n", ahc_name(ahc)); 1605 } 1606 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1607 status1, /*bytes*/1); 1608 1609 if (status1 & (DPR|RMA|RTA)) { 1610 ahc_outb(ahc, CLRINT, CLRPARERR); 1611 } 1612 1613 unpause_sequencer(ahc); 1614 } 1615 1616 static int 1617 ahc_aic7850_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1618 { 1619 probe_config->channel = 'A'; 1620 probe_config->chip = AHC_AIC7850; 1621 probe_config->features = AHC_AIC7850_FE; 1622 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1623 | AHC_PCI_MWI_BUG; 1624 return (0); 1625 } 1626 1627 static int 1628 ahc_aic7855_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1629 { 1630 probe_config->channel = 'A'; 1631 probe_config->chip = AHC_AIC7855; 1632 probe_config->features = AHC_AIC7855_FE; 1633 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1634 | AHC_PCI_MWI_BUG; 1635 return (0); 1636 } 1637 1638 static int 1639 ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1640 { 1641 uint8_t rev; 1642 1643 probe_config->channel = 'A'; 1644 probe_config->chip = AHC_AIC7860; 1645 probe_config->features = AHC_AIC7860_FE; 1646 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1647 | AHC_PCI_MWI_BUG; 1648 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1649 if (rev >= 1) 1650 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1651 return (0); 1652 } 1653 1654 static int 1655 ahc_aic7870_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1656 { 1657 probe_config->channel = 'A'; 1658 probe_config->chip = AHC_AIC7870; 1659 probe_config->features = AHC_AIC7870_FE; 1660 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1661 | AHC_PCI_MWI_BUG; 1662 return (0); 1663 } 1664 1665 static int 1666 ahc_aha394X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1667 { 1668 int error; 1669 1670 error = ahc_aic7870_setup(pci, probe_config); 1671 if (error == 0) 1672 error = ahc_aha394XX_setup(pci, probe_config); 1673 return (error); 1674 } 1675 1676 static int 1677 ahc_aha398X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1678 { 1679 int error; 1680 1681 error = ahc_aic7870_setup(pci, probe_config); 1682 if (error == 0) 1683 error = ahc_aha398XX_setup(pci, probe_config); 1684 return (error); 1685 } 1686 1687 static int 1688 ahc_aha494X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1689 { 1690 int error; 1691 1692 error = ahc_aic7870_setup(pci, probe_config); 1693 if (error == 0) 1694 error = ahc_aha494XX_setup(pci, probe_config); 1695 return (error); 1696 } 1697 1698 static int 1699 ahc_aic7880_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1700 { 1701 uint8_t rev; 1702 1703 probe_config->channel = 'A'; 1704 probe_config->chip = AHC_AIC7880; 1705 probe_config->features = AHC_AIC7880_FE; 1706 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1707 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1708 if (rev >= 1) { 1709 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1710 } else { 1711 probe_config->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1712 } 1713 return (0); 1714 } 1715 1716 static int 1717 ahc_2940Pro_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1718 { 1719 int error; 1720 1721 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1722 error = ahc_aic7880_setup(pci, probe_config); 1723 return (0); 1724 } 1725 1726 static int 1727 ahc_aha394XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1728 { 1729 int error; 1730 1731 error = ahc_aic7880_setup(pci, probe_config); 1732 if (error == 0) 1733 error = ahc_aha394XX_setup(pci, probe_config); 1734 return (error); 1735 } 1736 1737 static int 1738 ahc_aha398XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1739 { 1740 int error; 1741 1742 error = ahc_aic7880_setup(pci, probe_config); 1743 if (error == 0) 1744 error = ahc_aha398XX_setup(pci, probe_config); 1745 return (error); 1746 } 1747 1748 static int 1749 ahc_aic7890_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1750 { 1751 uint8_t rev; 1752 1753 probe_config->channel = 'A'; 1754 probe_config->chip = AHC_AIC7890; 1755 probe_config->features = AHC_AIC7890_FE; 1756 probe_config->flags |= AHC_NEWEEPROM_FMT; 1757 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1758 if (rev == 0) 1759 probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1760 return (0); 1761 } 1762 1763 static int 1764 ahc_aic7892_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1765 { 1766 probe_config->channel = 'A'; 1767 probe_config->chip = AHC_AIC7892; 1768 probe_config->features = AHC_AIC7892_FE; 1769 probe_config->flags |= AHC_NEWEEPROM_FMT; 1770 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1771 return (0); 1772 } 1773 1774 static int 1775 ahc_aic7895_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1776 { 1777 uint8_t rev; 1778 1779 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1780 /* 1781 * The 'C' revision of the aic7895 has a few additional features. 1782 */ 1783 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1784 if (rev >= 4) { 1785 probe_config->chip = AHC_AIC7895C; 1786 probe_config->features = AHC_AIC7895C_FE; 1787 } else { 1788 u_int command; 1789 1790 probe_config->chip = AHC_AIC7895; 1791 probe_config->features = AHC_AIC7895_FE; 1792 1793 /* 1794 * The BIOS disables the use of MWI transactions 1795 * since it does not have the MWI bug work around 1796 * we have. Disabling MWI reduces performance, so 1797 * turn it on again. 1798 */ 1799 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 1800 command |= PCIM_CMD_MWRICEN; 1801 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 1802 probe_config->bugs |= AHC_PCI_MWI_BUG; 1803 } 1804 /* 1805 * XXX Does CACHETHEN really not work??? What about PCI retry? 1806 * on C level chips. Need to test, but for now, play it safe. 1807 */ 1808 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1809 | AHC_CACHETHEN_BUG; 1810 1811 #if 0 1812 uint32_t devconfig; 1813 1814 /* 1815 * Cachesize must also be zero due to stray DAC 1816 * problem when sitting behind some bridges. 1817 */ 1818 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 1819 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 1820 devconfig |= MRDCEN; 1821 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 1822 #endif 1823 probe_config->flags |= AHC_NEWEEPROM_FMT; 1824 return (0); 1825 } 1826 1827 static int 1828 ahc_aic7896_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1829 { 1830 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1831 probe_config->chip = AHC_AIC7896; 1832 probe_config->features = AHC_AIC7896_FE; 1833 probe_config->flags |= AHC_NEWEEPROM_FMT; 1834 probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; 1835 return (0); 1836 } 1837 1838 static int 1839 ahc_aic7899_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1840 { 1841 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1842 probe_config->chip = AHC_AIC7899; 1843 probe_config->features = AHC_AIC7899_FE; 1844 probe_config->flags |= AHC_NEWEEPROM_FMT; 1845 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1846 return (0); 1847 } 1848 1849 static int 1850 ahc_raid_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1851 { 1852 printf("RAID functionality unsupported\n"); 1853 return (ENXIO); 1854 } 1855 1856 static int 1857 ahc_aha394XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1858 { 1859 switch (ahc_get_pci_slot(pci)) { 1860 case AHC_394X_SLOT_CHANNEL_A: 1861 probe_config->channel = 'A'; 1862 break; 1863 case AHC_394X_SLOT_CHANNEL_B: 1864 probe_config->channel = 'B'; 1865 break; 1866 default: 1867 printf("adapter at unexpected slot %d\n" 1868 "unable to map to a channel\n", 1869 ahc_get_pci_slot(pci)); 1870 probe_config->channel = 'A'; 1871 } 1872 return (0); 1873 } 1874 1875 static int 1876 ahc_aha398XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1877 { 1878 switch (ahc_get_pci_slot(pci)) { 1879 case AHC_398X_SLOT_CHANNEL_A: 1880 probe_config->channel = 'A'; 1881 break; 1882 case AHC_398X_SLOT_CHANNEL_B: 1883 probe_config->channel = 'B'; 1884 break; 1885 case AHC_398X_SLOT_CHANNEL_C: 1886 probe_config->channel = 'C'; 1887 break; 1888 default: 1889 printf("adapter at unexpected slot %d\n" 1890 "unable to map to a channel\n", 1891 ahc_get_pci_slot(pci)); 1892 probe_config->channel = 'A'; 1893 break; 1894 } 1895 probe_config->flags |= AHC_LARGE_SEEPROM; 1896 return (0); 1897 } 1898 1899 static int 1900 ahc_aha494XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1901 { 1902 switch (ahc_get_pci_slot(pci)) { 1903 case AHC_494X_SLOT_CHANNEL_A: 1904 probe_config->channel = 'A'; 1905 break; 1906 case AHC_494X_SLOT_CHANNEL_B: 1907 probe_config->channel = 'B'; 1908 break; 1909 case AHC_494X_SLOT_CHANNEL_C: 1910 probe_config->channel = 'C'; 1911 break; 1912 case AHC_494X_SLOT_CHANNEL_D: 1913 probe_config->channel = 'D'; 1914 break; 1915 default: 1916 printf("adapter at unexpected slot %d\n" 1917 "unable to map to a channel\n", 1918 ahc_get_pci_slot(pci)); 1919 probe_config->channel = 'A'; 1920 } 1921 probe_config->flags |= AHC_LARGE_SEEPROM; 1922 return (0); 1923 } 1924