1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995-2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#24 $ 34 * 35 * $FreeBSD$ 36 */ 37 38 #include <dev/aic7xxx/aic7xxx_freebsd.h> 39 #include <dev/aic7xxx/aic7xxx_inline.h> 40 #include <dev/aic7xxx/aic7xxx_93cx6.h> 41 42 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 43 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 44 45 static __inline uint64_t 46 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 47 { 48 uint64_t id; 49 50 id = subvendor 51 | (subdevice << 16) 52 | ((uint64_t)vendor << 32) 53 | ((uint64_t)device << 48); 54 55 return (id); 56 } 57 58 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 59 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 60 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 61 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 62 #define ID_9005_SISL_ID 0x0005900500000000ull 63 #define ID_AIC7850 0x5078900400000000ull 64 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 65 #define ID_AIC7855 0x5578900400000000ull 66 #define ID_AIC7859 0x3860900400000000ull 67 #define ID_AHA_2930CU 0x3860900438699004ull 68 #define ID_AIC7860 0x6078900400000000ull 69 #define ID_AIC7860C 0x6078900478609004ull 70 #define ID_AHA_1480A 0x6075900400000000ull 71 #define ID_AHA_2940AU_0 0x6178900400000000ull 72 #define ID_AHA_2940AU_1 0x6178900478619004ull 73 #define ID_AHA_2940AU_CN 0x2178900478219004ull 74 #define ID_AHA_2930C_VAR 0x6038900438689004ull 75 76 #define ID_AIC7870 0x7078900400000000ull 77 #define ID_AHA_2940 0x7178900400000000ull 78 #define ID_AHA_3940 0x7278900400000000ull 79 #define ID_AHA_398X 0x7378900400000000ull 80 #define ID_AHA_2944 0x7478900400000000ull 81 #define ID_AHA_3944 0x7578900400000000ull 82 #define ID_AHA_4944 0x7678900400000000ull 83 84 #define ID_AIC7880 0x8078900400000000ull 85 #define ID_AIC7880_B 0x8078900478809004ull 86 #define ID_AHA_2940U 0x8178900400000000ull 87 #define ID_AHA_3940U 0x8278900400000000ull 88 #define ID_AHA_2944U 0x8478900400000000ull 89 #define ID_AHA_3944U 0x8578900400000000ull 90 #define ID_AHA_398XU 0x8378900400000000ull 91 #define ID_AHA_4944U 0x8678900400000000ull 92 #define ID_AHA_2940UB 0x8178900478819004ull 93 #define ID_AHA_2930U 0x8878900478889004ull 94 #define ID_AHA_2940U_PRO 0x8778900478879004ull 95 #define ID_AHA_2940U_CN 0x0078900478009004ull 96 97 #define ID_AIC7895 0x7895900478959004ull 98 #define ID_AIC7895_ARO 0x7890900478939004ull 99 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 100 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 101 #define ID_AHA_3940AU 0x7895900478929004ull 102 #define ID_AHA_3944AU 0x7895900478949004ull 103 104 #define ID_AIC7890 0x001F9005000F9005ull 105 #define ID_AIC7890_ARO 0x00139005000F9005ull 106 #define ID_AAA_131U2 0x0013900500039005ull 107 #define ID_AHA_2930U2 0x0011900501819005ull 108 #define ID_AHA_2940U2B 0x00109005A1009005ull 109 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 110 #define ID_AHA_2940U2 0x00109005A1809005ull 111 #define ID_AHA_2950U2B 0x00109005E1009005ull 112 113 #define ID_AIC7892 0x008F9005FFFF9005ull 114 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 115 #define ID_AHA_29160 0x00809005E2A09005ull 116 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 117 #define ID_AHA_29160N 0x0080900562A09005ull 118 #define ID_AHA_29160C 0x0080900562209005ull 119 #define ID_AHA_29160B 0x00809005E2209005ull 120 #define ID_AHA_19160B 0x0081900562A19005ull 121 122 #define ID_AIC7896 0x005F9005FFFF9005ull 123 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 124 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 125 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 126 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 127 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 128 129 #define ID_AIC7899 0x00CF9005FFFF9005ull 130 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 131 #define ID_AHA_3960D 0x00C09005F6209005ull 132 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 133 134 #define ID_AIC7810 0x1078900400000000ull 135 #define ID_AIC7815 0x7815900400000000ull 136 137 #define DEVID_9005_TYPE(id) ((id) & 0xF) 138 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 139 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 140 #define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */ 141 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 142 143 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 144 #define DEVID_9005_MAXRATE_U160 0x0 145 #define DEVID_9005_MAXRATE_ULTRA2 0x1 146 #define DEVID_9005_MAXRATE_ULTRA 0x2 147 #define DEVID_9005_MAXRATE_FAST 0x3 148 149 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 150 151 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 152 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 153 154 #define SUBID_9005_TYPE(id) ((id) & 0xF) 155 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 156 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 157 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 158 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 159 160 #define SUBID_9005_TYPE_KNOWN(id) \ 161 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 162 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 163 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 164 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 165 166 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 167 #define SUBID_9005_MAXRATE_ULTRA2 0x0 168 #define SUBID_9005_MAXRATE_ULTRA 0x1 169 #define SUBID_9005_MAXRATE_U160 0x2 170 #define SUBID_9005_MAXRATE_RESERVED 0x3 171 172 #define SUBID_9005_SEEPTYPE(id) \ 173 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 174 ? ((id) & 0xC0) >> 6 \ 175 : ((id) & 0x300) >> 8) 176 #define SUBID_9005_SEEPTYPE_NONE 0x0 177 #define SUBID_9005_SEEPTYPE_1K 0x1 178 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 179 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 180 #define SUBID_9005_AUTOTERM(id) \ 181 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 182 ? (((id) & 0x400) >> 10) == 0 \ 183 : (((id) & 0x40) >> 6) == 0) 184 185 #define SUBID_9005_NUMCHAN(id) \ 186 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 187 ? ((id) & 0x300) >> 8 \ 188 : ((id) & 0xC00) >> 10) 189 190 #define SUBID_9005_LEGACYCONN(id) \ 191 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 192 ? 0 \ 193 : ((id) & 0x80) >> 7) 194 195 #define SUBID_9005_MFUNCENB(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? ((id) & 0x800) >> 11 \ 198 : ((id) & 0x1000) >> 12) 199 /* 200 * Informational only. Should use chip register to be 201 * ceratian, but may be use in identification strings. 202 */ 203 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 204 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 205 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 206 207 static ahc_device_setup_t ahc_aic785X_setup; 208 static ahc_device_setup_t ahc_aic7860_setup; 209 static ahc_device_setup_t ahc_apa1480_setup; 210 static ahc_device_setup_t ahc_aic7870_setup; 211 static ahc_device_setup_t ahc_aha394X_setup; 212 static ahc_device_setup_t ahc_aha494X_setup; 213 static ahc_device_setup_t ahc_aha398X_setup; 214 static ahc_device_setup_t ahc_aic7880_setup; 215 static ahc_device_setup_t ahc_aha2940Pro_setup; 216 static ahc_device_setup_t ahc_aha394XU_setup; 217 static ahc_device_setup_t ahc_aha398XU_setup; 218 static ahc_device_setup_t ahc_aic7890_setup; 219 static ahc_device_setup_t ahc_aic7892_setup; 220 static ahc_device_setup_t ahc_aic7895_setup; 221 static ahc_device_setup_t ahc_aic7896_setup; 222 static ahc_device_setup_t ahc_aic7899_setup; 223 static ahc_device_setup_t ahc_aha29160C_setup; 224 static ahc_device_setup_t ahc_raid_setup; 225 static ahc_device_setup_t ahc_aha394XX_setup; 226 static ahc_device_setup_t ahc_aha494XX_setup; 227 static ahc_device_setup_t ahc_aha398XX_setup; 228 229 struct ahc_pci_identity ahc_pci_ident_table [] = 230 { 231 /* aic7850 based controllers */ 232 { 233 ID_AHA_2902_04_10_15_20_30C, 234 ID_ALL_MASK, 235 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 236 ahc_aic785X_setup 237 }, 238 /* aic7860 based controllers */ 239 { 240 ID_AHA_2930CU, 241 ID_ALL_MASK, 242 "Adaptec 2930CU SCSI adapter", 243 ahc_aic7860_setup 244 }, 245 { 246 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 247 ID_DEV_VENDOR_MASK, 248 "Adaptec 1480A Ultra SCSI adapter", 249 ahc_apa1480_setup 250 }, 251 { 252 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 253 ID_DEV_VENDOR_MASK, 254 "Adaptec 2940A Ultra SCSI adapter", 255 ahc_aic7860_setup 256 }, 257 { 258 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 259 ID_DEV_VENDOR_MASK, 260 "Adaptec 2940A/CN Ultra SCSI adapter", 261 ahc_aic7860_setup 262 }, 263 { 264 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 265 ID_DEV_VENDOR_MASK, 266 "Adaptec 2930C Ultra SCSI adapter (VAR)", 267 ahc_aic7860_setup 268 }, 269 /* aic7870 based controllers */ 270 { 271 ID_AHA_2940, 272 ID_ALL_MASK, 273 "Adaptec 2940 SCSI adapter", 274 ahc_aic7870_setup 275 }, 276 { 277 ID_AHA_3940, 278 ID_ALL_MASK, 279 "Adaptec 3940 SCSI adapter", 280 ahc_aha394X_setup 281 }, 282 { 283 ID_AHA_398X, 284 ID_ALL_MASK, 285 "Adaptec 398X SCSI RAID adapter", 286 ahc_aha398X_setup 287 }, 288 { 289 ID_AHA_2944, 290 ID_ALL_MASK, 291 "Adaptec 2944 SCSI adapter", 292 ahc_aic7870_setup 293 }, 294 { 295 ID_AHA_3944, 296 ID_ALL_MASK, 297 "Adaptec 3944 SCSI adapter", 298 ahc_aha394X_setup 299 }, 300 { 301 ID_AHA_4944, 302 ID_ALL_MASK, 303 "Adaptec 4944 SCSI adapter", 304 ahc_aha494X_setup 305 }, 306 /* aic7880 based controllers */ 307 { 308 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 309 ID_DEV_VENDOR_MASK, 310 "Adaptec 2940 Ultra SCSI adapter", 311 ahc_aic7880_setup 312 }, 313 { 314 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 315 ID_DEV_VENDOR_MASK, 316 "Adaptec 3940 Ultra SCSI adapter", 317 ahc_aha394XU_setup 318 }, 319 { 320 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 321 ID_DEV_VENDOR_MASK, 322 "Adaptec 2944 Ultra SCSI adapter", 323 ahc_aic7880_setup 324 }, 325 { 326 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 327 ID_DEV_VENDOR_MASK, 328 "Adaptec 3944 Ultra SCSI adapter", 329 ahc_aha394XU_setup 330 }, 331 { 332 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 333 ID_DEV_VENDOR_MASK, 334 "Adaptec 398X Ultra SCSI RAID adapter", 335 ahc_aha398XU_setup 336 }, 337 { 338 /* 339 * XXX Don't know the slot numbers 340 * so we can't identify channels 341 */ 342 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 343 ID_DEV_VENDOR_MASK, 344 "Adaptec 4944 Ultra SCSI adapter", 345 ahc_aic7880_setup 346 }, 347 { 348 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2930 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 2940 Pro Ultra SCSI adapter", 357 ahc_aha2940Pro_setup 358 }, 359 { 360 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2940/CN Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 /* Ignore all SISL (AAC on MB) based controllers. */ 366 { 367 ID_9005_SISL_ID, 368 ID_9005_SISL_MASK, 369 NULL, 370 NULL 371 }, 372 /* aic7890 based controllers */ 373 { 374 ID_AHA_2930U2, 375 ID_ALL_MASK, 376 "Adaptec 2930 Ultra2 SCSI adapter", 377 ahc_aic7890_setup 378 }, 379 { 380 ID_AHA_2940U2B, 381 ID_ALL_MASK, 382 "Adaptec 2940B Ultra2 SCSI adapter", 383 ahc_aic7890_setup 384 }, 385 { 386 ID_AHA_2940U2_OEM, 387 ID_ALL_MASK, 388 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 389 ahc_aic7890_setup 390 }, 391 { 392 ID_AHA_2940U2, 393 ID_ALL_MASK, 394 "Adaptec 2940 Ultra2 SCSI adapter", 395 ahc_aic7890_setup 396 }, 397 { 398 ID_AHA_2950U2B, 399 ID_ALL_MASK, 400 "Adaptec 2950 Ultra2 SCSI adapter", 401 ahc_aic7890_setup 402 }, 403 { 404 ID_AIC7890_ARO, 405 ID_ALL_MASK, 406 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 407 ahc_aic7890_setup 408 }, 409 { 410 ID_AAA_131U2, 411 ID_ALL_MASK, 412 "Adaptec AAA-131 Ultra2 RAID adapter", 413 ahc_aic7890_setup 414 }, 415 /* aic7892 based controllers */ 416 { 417 ID_AHA_29160, 418 ID_ALL_MASK, 419 "Adaptec 29160 Ultra160 SCSI adapter", 420 ahc_aic7892_setup 421 }, 422 { 423 ID_AHA_29160_CPQ, 424 ID_ALL_MASK, 425 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 426 ahc_aic7892_setup 427 }, 428 { 429 ID_AHA_29160N, 430 ID_ALL_MASK, 431 "Adaptec 29160N Ultra160 SCSI adapter", 432 ahc_aic7892_setup 433 }, 434 { 435 ID_AHA_29160C, 436 ID_ALL_MASK, 437 "Adaptec 29160C Ultra160 SCSI adapter", 438 ahc_aha29160C_setup 439 }, 440 { 441 ID_AHA_29160B, 442 ID_ALL_MASK, 443 "Adaptec 29160B Ultra160 SCSI adapter", 444 ahc_aic7892_setup 445 }, 446 { 447 ID_AHA_19160B, 448 ID_ALL_MASK, 449 "Adaptec 19160B Ultra160 SCSI adapter", 450 ahc_aic7892_setup 451 }, 452 { 453 ID_AIC7892_ARO, 454 ID_ALL_MASK, 455 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 456 ahc_aic7892_setup 457 }, 458 /* aic7895 based controllers */ 459 { 460 ID_AHA_2940U_DUAL, 461 ID_ALL_MASK, 462 "Adaptec 2940/DUAL Ultra SCSI adapter", 463 ahc_aic7895_setup 464 }, 465 { 466 ID_AHA_3940AU, 467 ID_ALL_MASK, 468 "Adaptec 3940A Ultra SCSI adapter", 469 ahc_aic7895_setup 470 }, 471 { 472 ID_AHA_3944AU, 473 ID_ALL_MASK, 474 "Adaptec 3944A Ultra SCSI adapter", 475 ahc_aic7895_setup 476 }, 477 { 478 ID_AIC7895_ARO, 479 ID_AIC7895_ARO_MASK, 480 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 481 ahc_aic7895_setup 482 }, 483 /* aic7896/97 based controllers */ 484 { 485 ID_AHA_3950U2B_0, 486 ID_ALL_MASK, 487 "Adaptec 3950B Ultra2 SCSI adapter", 488 ahc_aic7896_setup 489 }, 490 { 491 ID_AHA_3950U2B_1, 492 ID_ALL_MASK, 493 "Adaptec 3950B Ultra2 SCSI adapter", 494 ahc_aic7896_setup 495 }, 496 { 497 ID_AHA_3950U2D_0, 498 ID_ALL_MASK, 499 "Adaptec 3950D Ultra2 SCSI adapter", 500 ahc_aic7896_setup 501 }, 502 { 503 ID_AHA_3950U2D_1, 504 ID_ALL_MASK, 505 "Adaptec 3950D Ultra2 SCSI adapter", 506 ahc_aic7896_setup 507 }, 508 { 509 ID_AIC7896_ARO, 510 ID_ALL_MASK, 511 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 512 ahc_aic7896_setup 513 }, 514 /* aic7899 based controllers */ 515 { 516 ID_AHA_3960D, 517 ID_ALL_MASK, 518 "Adaptec 3960D Ultra160 SCSI adapter", 519 ahc_aic7899_setup 520 }, 521 { 522 ID_AHA_3960D_CPQ, 523 ID_ALL_MASK, 524 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 525 ahc_aic7899_setup 526 }, 527 { 528 ID_AIC7899_ARO, 529 ID_ALL_MASK, 530 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 531 ahc_aic7899_setup 532 }, 533 /* Generic chip probes for devices we don't know 'exactly' */ 534 { 535 ID_AIC7850 & ID_DEV_VENDOR_MASK, 536 ID_DEV_VENDOR_MASK, 537 "Adaptec aic7850 SCSI adapter", 538 ahc_aic785X_setup 539 }, 540 { 541 ID_AIC7855 & ID_DEV_VENDOR_MASK, 542 ID_DEV_VENDOR_MASK, 543 "Adaptec aic7855 SCSI adapter", 544 ahc_aic785X_setup 545 }, 546 { 547 ID_AIC7859 & ID_DEV_VENDOR_MASK, 548 ID_DEV_VENDOR_MASK, 549 "Adaptec aic7859 SCSI adapter", 550 ahc_aic7860_setup 551 }, 552 { 553 ID_AIC7860 & ID_DEV_VENDOR_MASK, 554 ID_DEV_VENDOR_MASK, 555 "Adaptec aic7860 Ultra SCSI adapter", 556 ahc_aic7860_setup 557 }, 558 { 559 ID_AIC7870 & ID_DEV_VENDOR_MASK, 560 ID_DEV_VENDOR_MASK, 561 "Adaptec aic7870 SCSI adapter", 562 ahc_aic7870_setup 563 }, 564 { 565 ID_AIC7880 & ID_DEV_VENDOR_MASK, 566 ID_DEV_VENDOR_MASK, 567 "Adaptec aic7880 Ultra SCSI adapter", 568 ahc_aic7880_setup 569 }, 570 { 571 ID_AIC7890 & ID_9005_GENERIC_MASK, 572 ID_9005_GENERIC_MASK, 573 "Adaptec aic7890/91 Ultra2 SCSI adapter", 574 ahc_aic7890_setup 575 }, 576 { 577 ID_AIC7892 & ID_9005_GENERIC_MASK, 578 ID_9005_GENERIC_MASK, 579 "Adaptec aic7892 Ultra160 SCSI adapter", 580 ahc_aic7892_setup 581 }, 582 { 583 ID_AIC7895 & ID_DEV_VENDOR_MASK, 584 ID_DEV_VENDOR_MASK, 585 "Adaptec aic7895 Ultra SCSI adapter", 586 ahc_aic7895_setup 587 }, 588 { 589 ID_AIC7896 & ID_9005_GENERIC_MASK, 590 ID_9005_GENERIC_MASK, 591 "Adaptec aic7896/97 Ultra2 SCSI adapter", 592 ahc_aic7896_setup 593 }, 594 { 595 ID_AIC7899 & ID_9005_GENERIC_MASK, 596 ID_9005_GENERIC_MASK, 597 "Adaptec aic7899 Ultra160 SCSI adapter", 598 ahc_aic7899_setup 599 }, 600 { 601 ID_AIC7810 & ID_DEV_VENDOR_MASK, 602 ID_DEV_VENDOR_MASK, 603 "Adaptec aic7810 RAID memory controller", 604 ahc_raid_setup 605 }, 606 { 607 ID_AIC7815 & ID_DEV_VENDOR_MASK, 608 ID_DEV_VENDOR_MASK, 609 "Adaptec aic7815 RAID memory controller", 610 ahc_raid_setup 611 } 612 }; 613 614 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 615 616 #define AHC_394X_SLOT_CHANNEL_A 4 617 #define AHC_394X_SLOT_CHANNEL_B 5 618 619 #define AHC_398X_SLOT_CHANNEL_A 4 620 #define AHC_398X_SLOT_CHANNEL_B 8 621 #define AHC_398X_SLOT_CHANNEL_C 12 622 623 #define AHC_494X_SLOT_CHANNEL_A 4 624 #define AHC_494X_SLOT_CHANNEL_B 5 625 #define AHC_494X_SLOT_CHANNEL_C 6 626 #define AHC_494X_SLOT_CHANNEL_D 7 627 628 #define DEVCONFIG 0x40 629 #define SCBSIZE32 0x00010000ul /* aic789X only */ 630 #define REXTVALID 0x00001000ul /* ultra cards only */ 631 #define MPORTMODE 0x00000400ul /* aic7870 only */ 632 #define RAMPSM 0x00000200ul /* aic7870 only */ 633 #define VOLSENSE 0x00000100ul 634 #define SCBRAMSEL 0x00000080ul 635 #define MRDCEN 0x00000040ul 636 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 637 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 638 #define BERREN 0x00000008ul 639 #define DACEN 0x00000004ul 640 #define STPWLEVEL 0x00000002ul 641 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 642 643 #define CSIZE_LATTIME 0x0c 644 #define CACHESIZE 0x0000003ful /* only 5 bits */ 645 #define LATTIME 0x0000ff00ul 646 647 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 648 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 649 int pcheck, int fast, int large); 650 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 651 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 652 static void configure_termination(struct ahc_softc *ahc, 653 struct seeprom_descriptor *sd, 654 u_int adapter_control, 655 u_int *sxfrctl1); 656 657 static void ahc_new_term_detect(struct ahc_softc *ahc, 658 int *enableSEC_low, 659 int *enableSEC_high, 660 int *enablePRI_low, 661 int *enablePRI_high, 662 int *eeprom_present); 663 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 664 int *internal68_present, 665 int *externalcable_present, 666 int *eeprom_present); 667 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 668 int *externalcable_present, 669 int *eeprom_present); 670 static int acquire_seeprom(struct ahc_softc *ahc, 671 struct seeprom_descriptor *sd); 672 static void release_seeprom(struct seeprom_descriptor *sd); 673 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 674 static uint8_t read_brdctl(struct ahc_softc *ahc); 675 676 struct ahc_pci_identity * 677 ahc_find_pci_device(ahc_dev_softc_t pci) 678 { 679 uint64_t full_id; 680 uint16_t device; 681 uint16_t vendor; 682 uint16_t subdevice; 683 uint16_t subvendor; 684 struct ahc_pci_identity *entry; 685 u_int i; 686 687 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 688 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 689 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 690 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 691 full_id = ahc_compose_id(device, 692 vendor, 693 subdevice, 694 subvendor); 695 696 /* If the second function is not hooked up, ignore it. */ 697 if (ahc_get_pci_function(pci) > 0 698 && subvendor == 0x9005 699 && SUBID_9005_TYPE_KNOWN(subdevice) != 0 700 && SUBID_9005_MFUNCENB(subdevice) == 0) 701 return (NULL); 702 703 for (i = 0; i < ahc_num_pci_devs; i++) { 704 entry = &ahc_pci_ident_table[i]; 705 if (entry->full_id == (full_id & entry->id_mask)) { 706 /* Honor exclusion entries. */ 707 if (entry->name == NULL) 708 return (NULL); 709 return (entry); 710 } 711 } 712 return (NULL); 713 } 714 715 int 716 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 717 { 718 struct ahc_probe_config probe_config; 719 struct scb_data *shared_scb_data; 720 u_int command; 721 u_int our_id = 0; 722 u_int sxfrctl1; 723 u_int scsiseq; 724 u_int dscommand0; 725 int error; 726 uint8_t sblkctl; 727 728 shared_scb_data = NULL; 729 ahc_init_probe_config(&probe_config); 730 error = entry->setup(ahc->dev_softc, &probe_config); 731 if (error != 0) 732 return (error); 733 probe_config.chip |= AHC_PCI; 734 probe_config.description = entry->name; 735 736 error = ahc_pci_map_registers(ahc); 737 if (error != 0) 738 return (error); 739 740 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 741 742 /* Ensure busmastering is enabled */ 743 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 744 command |= PCIM_CMD_BUSMASTEREN; 745 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 746 747 /* On all PCI adapters, we allow SCB paging */ 748 probe_config.flags |= AHC_PAGESCBS; 749 750 error = ahc_softc_init(ahc, &probe_config); 751 if (error != 0) 752 return (error); 753 754 ahc->bus_intr = ahc_pci_intr; 755 756 /* Remeber how the card was setup in case there is no SEEPROM */ 757 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 758 ahc_pause(ahc); 759 if ((ahc->features & AHC_ULTRA2) != 0) 760 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 761 else 762 our_id = ahc_inb(ahc, SCSIID) & OID; 763 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 764 scsiseq = ahc_inb(ahc, SCSISEQ); 765 } else { 766 sxfrctl1 = STPWEN; 767 our_id = 7; 768 scsiseq = 0; 769 } 770 771 error = ahc_reset(ahc); 772 if (error != 0) 773 return (ENXIO); 774 775 if ((ahc->features & AHC_DT) != 0) { 776 u_int sfunct; 777 778 /* Perform ALT-Mode Setup */ 779 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 780 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 781 ahc_outb(ahc, OPTIONMODE, 782 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 783 ahc_outb(ahc, SFUNCT, sfunct); 784 785 /* Normal mode setup */ 786 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 787 |TARGCRCENDEN); 788 } 789 790 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 791 dscommand0 |= MPARCKEN|CACHETHEN; 792 if ((ahc->features & AHC_ULTRA2) != 0) { 793 794 /* 795 * DPARCKEN doesn't work correctly on 796 * some MBs so don't use it. 797 */ 798 dscommand0 &= ~DPARCKEN; 799 } 800 801 /* 802 * Handle chips that must have cache line 803 * streaming (dis/en)abled. 804 */ 805 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 806 dscommand0 |= CACHETHEN; 807 808 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 809 dscommand0 &= ~CACHETHEN; 810 811 ahc_outb(ahc, DSCOMMAND0, dscommand0); 812 813 ahc->pci_cachesize = 814 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 815 /*bytes*/1) & CACHESIZE; 816 ahc->pci_cachesize *= 4; 817 818 /* 819 * We cannot perform ULTRA speeds without the presense 820 * of the external precision resistor. 821 */ 822 if ((ahc->features & AHC_ULTRA) != 0) { 823 uint32_t devconfig; 824 825 devconfig = ahc_pci_read_config(ahc->dev_softc, 826 DEVCONFIG, /*bytes*/4); 827 if ((devconfig & REXTVALID) == 0) 828 ahc->features &= ~AHC_ULTRA; 829 } 830 831 /* See if we have a SEEPROM and perform auto-term */ 832 check_extport(ahc, &sxfrctl1); 833 834 /* 835 * Take the LED out of diagnostic mode 836 */ 837 sblkctl = ahc_inb(ahc, SBLKCTL); 838 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 839 840 if ((ahc->features & AHC_ULTRA2) != 0) { 841 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 842 } else { 843 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 844 } 845 846 if (ahc->flags & AHC_USEDEFAULTS) { 847 /* 848 * PCI Adapter default setup 849 * Should only be used if the adapter does not have 850 * a SEEPROM. 851 */ 852 /* See if someone else set us up already */ 853 if (scsiseq != 0) { 854 printf("%s: Using left over BIOS settings\n", 855 ahc_name(ahc)); 856 ahc->flags &= ~AHC_USEDEFAULTS; 857 ahc->flags |= AHC_BIOS_ENABLED; 858 } else { 859 /* 860 * Assume only one connector and always turn 861 * on termination. 862 */ 863 our_id = 0x07; 864 sxfrctl1 = STPWEN; 865 } 866 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 867 868 ahc->our_id = our_id; 869 } 870 871 /* 872 * Take a look to see if we have external SRAM. 873 * We currently do not attempt to use SRAM that is 874 * shared among multiple controllers. 875 */ 876 ahc_probe_ext_scbram(ahc); 877 878 /* 879 * Record our termination setting for the 880 * generic initialization routine. 881 */ 882 if ((sxfrctl1 & STPWEN) != 0) 883 ahc->flags |= AHC_TERM_ENB_A; 884 885 /* Core initialization */ 886 error = ahc_init(ahc); 887 if (error != 0) 888 return (error); 889 890 /* 891 * Link this softc in with all other ahc instances. 892 */ 893 ahc_softc_insert(ahc); 894 895 /* 896 * Allow interrupts now that we are completely setup. 897 */ 898 error = ahc_pci_map_int(ahc); 899 if (error != 0) 900 return (error); 901 902 ahc_intr_enable(ahc, TRUE); 903 904 return (0); 905 } 906 907 /* 908 * Test for the presense of external sram in an 909 * "unshared" configuration. 910 */ 911 static int 912 ahc_ext_scbram_present(struct ahc_softc *ahc) 913 { 914 u_int chip; 915 int ramps; 916 int single_user; 917 uint32_t devconfig; 918 919 chip = ahc->chip & AHC_CHIPID_MASK; 920 devconfig = ahc_pci_read_config(ahc->dev_softc, 921 DEVCONFIG, /*bytes*/4); 922 single_user = (devconfig & MPORTMODE) != 0; 923 924 if ((ahc->features & AHC_ULTRA2) != 0) 925 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 926 else if (chip >= AHC_AIC7870) 927 ramps = (devconfig & RAMPSM) != 0; 928 else 929 ramps = 0; 930 931 if (ramps && single_user) 932 return (1); 933 return (0); 934 } 935 936 /* 937 * Enable external scbram. 938 */ 939 static void 940 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 941 int fast, int large) 942 { 943 uint32_t devconfig; 944 945 if (ahc->features & AHC_MULTI_FUNC) { 946 /* 947 * Set the SCB Base addr (highest address bit) 948 * depending on which channel we are. 949 */ 950 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 951 } 952 953 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 954 if ((ahc->features & AHC_ULTRA2) != 0) { 955 u_int dscommand0; 956 957 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 958 if (enable) 959 dscommand0 &= ~INTSCBRAMSEL; 960 else 961 dscommand0 |= INTSCBRAMSEL; 962 if (large) 963 dscommand0 &= ~USCBSIZE32; 964 else 965 dscommand0 |= USCBSIZE32; 966 ahc_outb(ahc, DSCOMMAND0, dscommand0); 967 } else { 968 if (fast) 969 devconfig &= ~EXTSCBTIME; 970 else 971 devconfig |= EXTSCBTIME; 972 if (enable) 973 devconfig &= ~SCBRAMSEL; 974 else 975 devconfig |= SCBRAMSEL; 976 if (large) 977 devconfig &= ~SCBSIZE32; 978 else 979 devconfig |= SCBSIZE32; 980 } 981 if (pcheck) 982 devconfig |= EXTSCBPEN; 983 else 984 devconfig &= ~EXTSCBPEN; 985 986 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 987 } 988 989 /* 990 * Take a look to see if we have external SRAM. 991 * We currently do not attempt to use SRAM that is 992 * shared among multiple controllers. 993 */ 994 static void 995 ahc_probe_ext_scbram(struct ahc_softc *ahc) 996 { 997 int num_scbs; 998 int test_num_scbs; 999 int enable; 1000 int pcheck; 1001 int fast; 1002 int large; 1003 1004 enable = FALSE; 1005 pcheck = FALSE; 1006 fast = FALSE; 1007 large = FALSE; 1008 num_scbs = 0; 1009 1010 if (ahc_ext_scbram_present(ahc) == 0) 1011 goto done; 1012 1013 /* 1014 * Probe for the best parameters to use. 1015 */ 1016 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1017 num_scbs = ahc_probe_scbs(ahc); 1018 if (num_scbs == 0) { 1019 /* The SRAM wasn't really present. */ 1020 goto done; 1021 } 1022 enable = TRUE; 1023 1024 /* 1025 * Clear any outstanding parity error 1026 * and ensure that parity error reporting 1027 * is enabled. 1028 */ 1029 ahc_outb(ahc, SEQCTL, 0); 1030 ahc_outb(ahc, CLRINT, CLRPARERR); 1031 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1032 1033 /* Now see if we can do parity */ 1034 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1035 num_scbs = ahc_probe_scbs(ahc); 1036 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1037 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1038 pcheck = TRUE; 1039 1040 /* Clear any resulting parity error */ 1041 ahc_outb(ahc, CLRINT, CLRPARERR); 1042 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1043 1044 /* Now see if we can do fast timing */ 1045 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1046 test_num_scbs = ahc_probe_scbs(ahc); 1047 if (test_num_scbs == num_scbs 1048 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1049 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1050 fast = TRUE; 1051 1052 /* 1053 * See if we can use large SCBs and still maintain 1054 * the same overall count of SCBs. 1055 */ 1056 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1057 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1058 test_num_scbs = ahc_probe_scbs(ahc); 1059 if (test_num_scbs >= num_scbs) { 1060 large = TRUE; 1061 num_scbs = test_num_scbs; 1062 if (num_scbs >= 64) { 1063 /* 1064 * We have enough space to move the 1065 * "busy targets table" into SCB space 1066 * and make it qualify all the way to the 1067 * lun level. 1068 */ 1069 ahc->flags |= AHC_SCB_BTT; 1070 } 1071 } 1072 } 1073 done: 1074 /* 1075 * Disable parity error reporting until we 1076 * can load instruction ram. 1077 */ 1078 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1079 /* Clear any latched parity error */ 1080 ahc_outb(ahc, CLRINT, CLRPARERR); 1081 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1082 if (bootverbose && enable) { 1083 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1084 ahc_name(ahc), fast ? "fast" : "slow", 1085 pcheck ? ", parity checking enabled" : "", 1086 large ? 64 : 32); 1087 } 1088 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1089 } 1090 1091 /* 1092 * Check the external port logic for a serial eeprom 1093 * and termination/cable detection contrls. 1094 */ 1095 static void 1096 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1097 { 1098 struct seeprom_descriptor sd; 1099 struct seeprom_config sc; 1100 u_int scsi_conf; 1101 u_int adapter_control; 1102 int have_seeprom; 1103 int have_autoterm; 1104 1105 sd.sd_ahc = ahc; 1106 sd.sd_control_offset = SEECTL; 1107 sd.sd_status_offset = SEECTL; 1108 sd.sd_dataout_offset = SEECTL; 1109 1110 /* 1111 * For some multi-channel devices, the c46 is simply too 1112 * small to work. For the other controller types, we can 1113 * get our information from either SEEPROM type. Set the 1114 * type to start our probe with accordingly. 1115 */ 1116 if (ahc->flags & AHC_LARGE_SEEPROM) 1117 sd.sd_chip = C56_66; 1118 else 1119 sd.sd_chip = C46; 1120 1121 sd.sd_MS = SEEMS; 1122 sd.sd_RDY = SEERDY; 1123 sd.sd_CS = SEECS; 1124 sd.sd_CK = SEECK; 1125 sd.sd_DO = SEEDO; 1126 sd.sd_DI = SEEDI; 1127 1128 have_seeprom = acquire_seeprom(ahc, &sd); 1129 if (have_seeprom) { 1130 1131 if (bootverbose) 1132 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1133 1134 for (;;) { 1135 u_int start_addr; 1136 1137 start_addr = 32 * (ahc->channel - 'A'); 1138 1139 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1140 start_addr, sizeof(sc)/2); 1141 1142 if (have_seeprom) 1143 have_seeprom = verify_cksum(&sc); 1144 1145 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1146 if (bootverbose) { 1147 if (have_seeprom == 0) 1148 printf ("checksum error\n"); 1149 else 1150 printf ("done.\n"); 1151 } 1152 break; 1153 } 1154 sd.sd_chip = C56_66; 1155 } 1156 release_seeprom(&sd); 1157 } 1158 1159 if (!have_seeprom) { 1160 /* 1161 * Pull scratch ram settings and treat them as 1162 * if they are the contents of an seeprom if 1163 * the 'ADPT' signature is found in SCB2. 1164 * We manually compose the data as 16bit values 1165 * to avoid endian issues. 1166 */ 1167 ahc_outb(ahc, SCBPTR, 2); 1168 if (ahc_inb(ahc, SCB_BASE) == 'A' 1169 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1170 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1171 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1172 uint16_t *sc_data; 1173 int i; 1174 1175 sc_data = (uint16_t *)≻ 1176 for (i = 0; i < 32; i++) { 1177 uint16_t val; 1178 int j; 1179 1180 j = i * 2; 1181 val = ahc_inb(ahc, SRAM_BASE + j) 1182 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1183 } 1184 have_seeprom = verify_cksum(&sc); 1185 } 1186 } 1187 1188 if (!have_seeprom) { 1189 if (bootverbose) 1190 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1191 ahc->flags |= AHC_USEDEFAULTS; 1192 } else { 1193 /* 1194 * Put the data we've collected down into SRAM 1195 * where ahc_init will find it. 1196 */ 1197 int i; 1198 int max_targ = sc.max_targets & CFMAXTARG; 1199 uint16_t discenable; 1200 uint16_t ultraenb; 1201 1202 discenable = 0; 1203 ultraenb = 0; 1204 if ((sc.adapter_control & CFULTRAEN) != 0) { 1205 /* 1206 * Determine if this adapter has a "newstyle" 1207 * SEEPROM format. 1208 */ 1209 for (i = 0; i < max_targ; i++) { 1210 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1211 ahc->flags |= AHC_NEWEEPROM_FMT; 1212 break; 1213 } 1214 } 1215 } 1216 1217 for (i = 0; i < max_targ; i++) { 1218 u_int scsirate; 1219 uint16_t target_mask; 1220 1221 target_mask = 0x01 << i; 1222 if (sc.device_flags[i] & CFDISC) 1223 discenable |= target_mask; 1224 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1225 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1226 ultraenb |= target_mask; 1227 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1228 ultraenb |= target_mask; 1229 } 1230 if ((sc.device_flags[i] & CFXFER) == 0x04 1231 && (ultraenb & target_mask) != 0) { 1232 /* Treat 10MHz as a non-ultra speed */ 1233 sc.device_flags[i] &= ~CFXFER; 1234 ultraenb &= ~target_mask; 1235 } 1236 if ((ahc->features & AHC_ULTRA2) != 0) { 1237 u_int offset; 1238 1239 if (sc.device_flags[i] & CFSYNCH) 1240 offset = MAX_OFFSET_ULTRA2; 1241 else 1242 offset = 0; 1243 ahc_outb(ahc, TARG_OFFSET + i, offset); 1244 1245 /* 1246 * The ultra enable bits contain the 1247 * high bit of the ultra2 sync rate 1248 * field. 1249 */ 1250 scsirate = (sc.device_flags[i] & CFXFER) 1251 | ((ultraenb & target_mask) 1252 ? 0x8 : 0x0); 1253 if (sc.device_flags[i] & CFWIDEB) 1254 scsirate |= WIDEXFER; 1255 } else { 1256 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1257 if (sc.device_flags[i] & CFSYNCH) 1258 scsirate |= SOFS; 1259 if (sc.device_flags[i] & CFWIDEB) 1260 scsirate |= WIDEXFER; 1261 } 1262 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1263 } 1264 ahc->our_id = sc.brtime_id & CFSCSIID; 1265 1266 scsi_conf = (ahc->our_id & 0x7); 1267 if (sc.adapter_control & CFSPARITY) 1268 scsi_conf |= ENSPCHK; 1269 if (sc.adapter_control & CFRESETB) 1270 scsi_conf |= RESET_SCSI; 1271 1272 ahc->flags |= 1273 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1274 1275 if (sc.bios_control & CFEXTEND) 1276 ahc->flags |= AHC_EXTENDED_TRANS_A; 1277 1278 if (sc.bios_control & CFBIOSEN) 1279 ahc->flags |= AHC_BIOS_ENABLED; 1280 if (ahc->features & AHC_ULTRA 1281 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1282 /* Should we enable Ultra mode? */ 1283 if (!(sc.adapter_control & CFULTRAEN)) 1284 /* Treat us as a non-ultra card */ 1285 ultraenb = 0; 1286 } 1287 1288 if (sc.signature == CFSIGNATURE 1289 || sc.signature == CFSIGNATURE2) { 1290 uint32_t devconfig; 1291 1292 /* Honor the STPWLEVEL settings */ 1293 devconfig = ahc_pci_read_config(ahc->dev_softc, 1294 DEVCONFIG, /*bytes*/4); 1295 devconfig &= ~STPWLEVEL; 1296 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1297 devconfig |= STPWLEVEL; 1298 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1299 devconfig, /*bytes*/4); 1300 } 1301 /* Set SCSICONF info */ 1302 ahc_outb(ahc, SCSICONF, scsi_conf); 1303 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1304 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1305 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1306 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1307 } 1308 1309 /* 1310 * Cards that have the external logic necessary to talk to 1311 * a SEEPROM, are almost certain to have the remaining logic 1312 * necessary for auto-termination control. This assumption 1313 * hasn't failed yet... 1314 */ 1315 have_autoterm = have_seeprom; 1316 if (have_seeprom) 1317 adapter_control = sc.adapter_control; 1318 else 1319 adapter_control = CFAUTOTERM; 1320 1321 /* 1322 * Some low-cost chips have SEEPROM and auto-term control built 1323 * in, instead of using a GAL. They can tell us directly 1324 * if the termination logic is enabled. 1325 */ 1326 if ((ahc->features & AHC_SPIOCAP) != 0) { 1327 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1328 have_autoterm = TRUE; 1329 else 1330 have_autoterm = FALSE; 1331 } 1332 1333 if (have_autoterm) { 1334 acquire_seeprom(ahc, &sd); 1335 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1336 release_seeprom(&sd); 1337 } 1338 } 1339 1340 static void 1341 configure_termination(struct ahc_softc *ahc, 1342 struct seeprom_descriptor *sd, 1343 u_int adapter_control, 1344 u_int *sxfrctl1) 1345 { 1346 uint8_t brddat; 1347 1348 brddat = 0; 1349 1350 /* 1351 * Update the settings in sxfrctl1 to match the 1352 * termination settings 1353 */ 1354 *sxfrctl1 = 0; 1355 1356 /* 1357 * SEECS must be on for the GALS to latch 1358 * the data properly. Be sure to leave MS 1359 * on or we will release the seeprom. 1360 */ 1361 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1362 if ((adapter_control & CFAUTOTERM) != 0 1363 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1364 int internal50_present; 1365 int internal68_present; 1366 int externalcable_present; 1367 int eeprom_present; 1368 int enableSEC_low; 1369 int enableSEC_high; 1370 int enablePRI_low; 1371 int enablePRI_high; 1372 int sum; 1373 1374 enableSEC_low = 0; 1375 enableSEC_high = 0; 1376 enablePRI_low = 0; 1377 enablePRI_high = 0; 1378 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1379 ahc_new_term_detect(ahc, &enableSEC_low, 1380 &enableSEC_high, 1381 &enablePRI_low, 1382 &enablePRI_high, 1383 &eeprom_present); 1384 if ((adapter_control & CFSEAUTOTERM) == 0) { 1385 if (bootverbose) 1386 printf("%s: Manual SE Termination\n", 1387 ahc_name(ahc)); 1388 enableSEC_low = (adapter_control & CFSELOWTERM); 1389 enableSEC_high = 1390 (adapter_control & CFSEHIGHTERM); 1391 } 1392 if ((adapter_control & CFAUTOTERM) == 0) { 1393 if (bootverbose) 1394 printf("%s: Manual LVD Termination\n", 1395 ahc_name(ahc)); 1396 enablePRI_low = (adapter_control & CFSTERM); 1397 enablePRI_high = (adapter_control & CFWSTERM); 1398 } 1399 /* Make the table calculations below happy */ 1400 internal50_present = 0; 1401 internal68_present = 1; 1402 externalcable_present = 1; 1403 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1404 aic785X_cable_detect(ahc, &internal50_present, 1405 &externalcable_present, 1406 &eeprom_present); 1407 } else { 1408 aic787X_cable_detect(ahc, &internal50_present, 1409 &internal68_present, 1410 &externalcable_present, 1411 &eeprom_present); 1412 } 1413 1414 if ((ahc->features & AHC_WIDE) == 0) 1415 internal68_present = 0; 1416 1417 if (bootverbose 1418 && (ahc->features & AHC_ULTRA2) == 0) { 1419 printf("%s: internal 50 cable %s present", 1420 ahc_name(ahc), 1421 internal50_present ? "is":"not"); 1422 1423 if ((ahc->features & AHC_WIDE) != 0) 1424 printf(", internal 68 cable %s present", 1425 internal68_present ? "is":"not"); 1426 printf("\n%s: external cable %s present\n", 1427 ahc_name(ahc), 1428 externalcable_present ? "is":"not"); 1429 } 1430 if (bootverbose) 1431 printf("%s: BIOS eeprom %s present\n", 1432 ahc_name(ahc), eeprom_present ? "is" : "not"); 1433 1434 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1435 /* 1436 * The 50 pin connector is a separate bus, 1437 * so force it to always be terminated. 1438 * In the future, perform current sensing 1439 * to determine if we are in the middle of 1440 * a properly terminated bus. 1441 */ 1442 internal50_present = 0; 1443 } 1444 1445 /* 1446 * Now set the termination based on what 1447 * we found. 1448 * Flash Enable = BRDDAT7 1449 * Secondary High Term Enable = BRDDAT6 1450 * Secondary Low Term Enable = BRDDAT5 (7890) 1451 * Primary High Term Enable = BRDDAT4 (7890) 1452 */ 1453 if ((ahc->features & AHC_ULTRA2) == 0 1454 && (internal50_present != 0) 1455 && (internal68_present != 0) 1456 && (externalcable_present != 0)) { 1457 printf("%s: Illegal cable configuration!!. " 1458 "Only two connectors on the " 1459 "adapter may be used at a " 1460 "time!\n", ahc_name(ahc)); 1461 } 1462 1463 if ((ahc->features & AHC_WIDE) != 0 1464 && ((externalcable_present == 0) 1465 || (internal68_present == 0) 1466 || (enableSEC_high != 0))) { 1467 brddat |= BRDDAT6; 1468 if (bootverbose) { 1469 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1470 printf("%s: 68 pin termination " 1471 "Enabled\n", ahc_name(ahc)); 1472 else 1473 printf("%s: %sHigh byte termination " 1474 "Enabled\n", ahc_name(ahc), 1475 enableSEC_high ? "Secondary " 1476 : ""); 1477 } 1478 } 1479 1480 sum = internal50_present + internal68_present 1481 + externalcable_present; 1482 if (sum < 2 || (enableSEC_low != 0)) { 1483 if ((ahc->features & AHC_ULTRA2) != 0) 1484 brddat |= BRDDAT5; 1485 else 1486 *sxfrctl1 |= STPWEN; 1487 if (bootverbose) { 1488 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1489 printf("%s: 50 pin termination " 1490 "Enabled\n", ahc_name(ahc)); 1491 else 1492 printf("%s: %sLow byte termination " 1493 "Enabled\n", ahc_name(ahc), 1494 enableSEC_low ? "Secondary " 1495 : ""); 1496 } 1497 } 1498 1499 if (enablePRI_low != 0) { 1500 *sxfrctl1 |= STPWEN; 1501 if (bootverbose) 1502 printf("%s: Primary Low Byte termination " 1503 "Enabled\n", ahc_name(ahc)); 1504 } 1505 1506 /* 1507 * Setup STPWEN before setting up the rest of 1508 * the termination per the tech note on the U160 cards. 1509 */ 1510 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1511 1512 if (enablePRI_high != 0) { 1513 brddat |= BRDDAT4; 1514 if (bootverbose) 1515 printf("%s: Primary High Byte " 1516 "termination Enabled\n", 1517 ahc_name(ahc)); 1518 } 1519 1520 write_brdctl(ahc, brddat); 1521 1522 } else { 1523 if ((adapter_control & CFSTERM) != 0) { 1524 *sxfrctl1 |= STPWEN; 1525 1526 if (bootverbose) 1527 printf("%s: %sLow byte termination Enabled\n", 1528 ahc_name(ahc), 1529 (ahc->features & AHC_ULTRA2) ? "Primary " 1530 : ""); 1531 } 1532 1533 if ((adapter_control & CFWSTERM) != 0 1534 && (ahc->features & AHC_WIDE) != 0) { 1535 brddat |= BRDDAT6; 1536 if (bootverbose) 1537 printf("%s: %sHigh byte termination Enabled\n", 1538 ahc_name(ahc), 1539 (ahc->features & AHC_ULTRA2) 1540 ? "Secondary " : ""); 1541 } 1542 1543 /* 1544 * Setup STPWEN before setting up the rest of 1545 * the termination per the tech note on the U160 cards. 1546 */ 1547 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1548 1549 if ((ahc->features & AHC_WIDE) != 0) 1550 write_brdctl(ahc, brddat); 1551 } 1552 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1553 } 1554 1555 static void 1556 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1557 int *enableSEC_high, int *enablePRI_low, 1558 int *enablePRI_high, int *eeprom_present) 1559 { 1560 uint8_t brdctl; 1561 1562 /* 1563 * BRDDAT7 = Eeprom 1564 * BRDDAT6 = Enable Secondary High Byte termination 1565 * BRDDAT5 = Enable Secondary Low Byte termination 1566 * BRDDAT4 = Enable Primary high byte termination 1567 * BRDDAT3 = Enable Primary low byte termination 1568 */ 1569 brdctl = read_brdctl(ahc); 1570 *eeprom_present = brdctl & BRDDAT7; 1571 *enableSEC_high = (brdctl & BRDDAT6); 1572 *enableSEC_low = (brdctl & BRDDAT5); 1573 *enablePRI_high = (brdctl & BRDDAT4); 1574 *enablePRI_low = (brdctl & BRDDAT3); 1575 } 1576 1577 static void 1578 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1579 int *internal68_present, int *externalcable_present, 1580 int *eeprom_present) 1581 { 1582 uint8_t brdctl; 1583 1584 /* 1585 * First read the status of our cables. 1586 * Set the rom bank to 0 since the 1587 * bank setting serves as a multiplexor 1588 * for the cable detection logic. 1589 * BRDDAT5 controls the bank switch. 1590 */ 1591 write_brdctl(ahc, 0); 1592 1593 /* 1594 * Now read the state of the internal 1595 * connectors. BRDDAT6 is INT50 and 1596 * BRDDAT7 is INT68. 1597 */ 1598 brdctl = read_brdctl(ahc); 1599 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1600 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1601 1602 /* 1603 * Set the rom bank to 1 and determine 1604 * the other signals. 1605 */ 1606 write_brdctl(ahc, BRDDAT5); 1607 1608 /* 1609 * Now read the state of the external 1610 * connectors. BRDDAT6 is EXT68 and 1611 * BRDDAT7 is EPROMPS. 1612 */ 1613 brdctl = read_brdctl(ahc); 1614 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1615 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1616 } 1617 1618 static void 1619 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1620 int *externalcable_present, int *eeprom_present) 1621 { 1622 uint8_t brdctl; 1623 1624 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1625 ahc_outb(ahc, BRDCTL, 0); 1626 brdctl = ahc_inb(ahc, BRDCTL); 1627 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1628 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1629 1630 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1631 } 1632 1633 static int 1634 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1635 { 1636 int wait; 1637 1638 if ((ahc->features & AHC_SPIOCAP) != 0 1639 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1640 return (0); 1641 1642 /* 1643 * Request access of the memory port. When access is 1644 * granted, SEERDY will go high. We use a 1 second 1645 * timeout which should be near 1 second more than 1646 * is needed. Reason: after the chip reset, there 1647 * should be no contention. 1648 */ 1649 SEEPROM_OUTB(sd, sd->sd_MS); 1650 wait = 1000; /* 1 second timeout in msec */ 1651 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1652 ahc_delay(1000); /* delay 1 msec */ 1653 } 1654 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1655 SEEPROM_OUTB(sd, 0); 1656 return (0); 1657 } 1658 return(1); 1659 } 1660 1661 static void 1662 release_seeprom(struct seeprom_descriptor *sd) 1663 { 1664 /* Release access to the memory port and the serial EEPROM. */ 1665 SEEPROM_OUTB(sd, 0); 1666 } 1667 1668 static void 1669 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1670 { 1671 uint8_t brdctl; 1672 1673 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1674 brdctl = BRDSTB; 1675 if (ahc->channel == 'B') 1676 brdctl |= BRDCS; 1677 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1678 brdctl = 0; 1679 } else { 1680 brdctl = BRDSTB|BRDCS; 1681 } 1682 ahc_outb(ahc, BRDCTL, brdctl); 1683 ahc_flush_device_writes(ahc); 1684 brdctl |= value; 1685 ahc_outb(ahc, BRDCTL, brdctl); 1686 ahc_flush_device_writes(ahc); 1687 if ((ahc->features & AHC_ULTRA2) != 0) 1688 brdctl |= BRDSTB_ULTRA2; 1689 else 1690 brdctl &= ~BRDSTB; 1691 ahc_outb(ahc, BRDCTL, brdctl); 1692 ahc_flush_device_writes(ahc); 1693 if ((ahc->features & AHC_ULTRA2) != 0) 1694 brdctl = 0; 1695 else 1696 brdctl &= ~BRDCS; 1697 ahc_outb(ahc, BRDCTL, brdctl); 1698 } 1699 1700 static uint8_t 1701 read_brdctl(ahc) 1702 struct ahc_softc *ahc; 1703 { 1704 uint8_t brdctl; 1705 uint8_t value; 1706 1707 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1708 brdctl = BRDRW; 1709 if (ahc->channel == 'B') 1710 brdctl |= BRDCS; 1711 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1712 brdctl = BRDRW_ULTRA2; 1713 } else { 1714 brdctl = BRDRW|BRDCS; 1715 } 1716 ahc_outb(ahc, BRDCTL, brdctl); 1717 ahc_flush_device_writes(ahc); 1718 value = ahc_inb(ahc, BRDCTL); 1719 ahc_outb(ahc, BRDCTL, 0); 1720 return (value); 1721 } 1722 1723 #define DPE 0x80 1724 #define SSE 0x40 1725 #define RMA 0x20 1726 #define RTA 0x10 1727 #define STA 0x08 1728 #define DPR 0x01 1729 1730 void 1731 ahc_pci_intr(struct ahc_softc *ahc) 1732 { 1733 u_int error; 1734 u_int status1; 1735 1736 error = ahc_inb(ahc, ERROR); 1737 if ((error & PCIERRSTAT) == 0) 1738 return; 1739 1740 status1 = ahc_pci_read_config(ahc->dev_softc, 1741 PCIR_STATUS + 1, /*bytes*/1); 1742 1743 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1744 ahc_name(ahc), 1745 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1746 1747 if (status1 & DPE) { 1748 printf("%s: Data Parity Error Detected during address " 1749 "or write data phase\n", ahc_name(ahc)); 1750 } 1751 if (status1 & SSE) { 1752 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1753 } 1754 if (status1 & RMA) { 1755 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1756 } 1757 if (status1 & RTA) { 1758 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1759 } 1760 if (status1 & STA) { 1761 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1762 } 1763 if (status1 & DPR) { 1764 printf("%s: Data Parity Error has been reported via PERR#\n", 1765 ahc_name(ahc)); 1766 } 1767 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1768 printf("%s: Latched PCIERR interrupt with " 1769 "no status bits set\n", ahc_name(ahc)); 1770 } 1771 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1772 status1, /*bytes*/1); 1773 1774 if (status1 & (DPR|RMA|RTA)) { 1775 ahc_outb(ahc, CLRINT, CLRPARERR); 1776 } 1777 1778 ahc_unpause(ahc); 1779 } 1780 1781 static int 1782 ahc_aic785X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1783 { 1784 uint8_t rev; 1785 1786 probe_config->channel = 'A'; 1787 probe_config->chip = AHC_AIC7850; 1788 probe_config->features = AHC_AIC7850_FE; 1789 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1790 | AHC_PCI_MWI_BUG; 1791 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1792 if (rev >= 1) 1793 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1794 return (0); 1795 } 1796 1797 static int 1798 ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1799 { 1800 uint8_t rev; 1801 1802 probe_config->channel = 'A'; 1803 probe_config->chip = AHC_AIC7860; 1804 probe_config->features = AHC_AIC7860_FE; 1805 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1806 | AHC_PCI_MWI_BUG; 1807 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1808 if (rev >= 1) 1809 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1810 return (0); 1811 } 1812 1813 static int 1814 ahc_apa1480_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1815 { 1816 int error; 1817 1818 error = ahc_aic7860_setup(pci, probe_config); 1819 if (error != 0) 1820 return (error); 1821 probe_config->features |= AHC_REMOVABLE; 1822 return (0); 1823 } 1824 1825 static int 1826 ahc_aic7870_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1827 { 1828 probe_config->channel = 'A'; 1829 probe_config->chip = AHC_AIC7870; 1830 probe_config->features = AHC_AIC7870_FE; 1831 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1832 | AHC_PCI_MWI_BUG; 1833 return (0); 1834 } 1835 1836 static int 1837 ahc_aha394X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1838 { 1839 int error; 1840 1841 error = ahc_aic7870_setup(pci, probe_config); 1842 if (error == 0) 1843 error = ahc_aha394XX_setup(pci, probe_config); 1844 return (error); 1845 } 1846 1847 static int 1848 ahc_aha398X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1849 { 1850 int error; 1851 1852 error = ahc_aic7870_setup(pci, probe_config); 1853 if (error == 0) 1854 error = ahc_aha398XX_setup(pci, probe_config); 1855 return (error); 1856 } 1857 1858 static int 1859 ahc_aha494X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1860 { 1861 int error; 1862 1863 error = ahc_aic7870_setup(pci, probe_config); 1864 if (error == 0) 1865 error = ahc_aha494XX_setup(pci, probe_config); 1866 return (error); 1867 } 1868 1869 static int 1870 ahc_aic7880_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1871 { 1872 uint8_t rev; 1873 1874 probe_config->channel = 'A'; 1875 probe_config->chip = AHC_AIC7880; 1876 probe_config->features = AHC_AIC7880_FE; 1877 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1878 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1879 if (rev >= 1) { 1880 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1881 } else { 1882 probe_config->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1883 } 1884 return (0); 1885 } 1886 1887 static int 1888 ahc_aha2940Pro_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1889 { 1890 int error; 1891 1892 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1893 error = ahc_aic7880_setup(pci, probe_config); 1894 return (0); 1895 } 1896 1897 static int 1898 ahc_aha394XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1899 { 1900 int error; 1901 1902 error = ahc_aic7880_setup(pci, probe_config); 1903 if (error == 0) 1904 error = ahc_aha394XX_setup(pci, probe_config); 1905 return (error); 1906 } 1907 1908 static int 1909 ahc_aha398XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1910 { 1911 int error; 1912 1913 error = ahc_aic7880_setup(pci, probe_config); 1914 if (error == 0) 1915 error = ahc_aha398XX_setup(pci, probe_config); 1916 return (error); 1917 } 1918 1919 static int 1920 ahc_aic7890_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1921 { 1922 uint8_t rev; 1923 1924 probe_config->channel = 'A'; 1925 probe_config->chip = AHC_AIC7890; 1926 probe_config->features = AHC_AIC7890_FE; 1927 probe_config->flags |= AHC_NEWEEPROM_FMT; 1928 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1929 if (rev == 0) 1930 probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1931 return (0); 1932 } 1933 1934 static int 1935 ahc_aic7892_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1936 { 1937 probe_config->channel = 'A'; 1938 probe_config->chip = AHC_AIC7892; 1939 probe_config->features = AHC_AIC7892_FE; 1940 probe_config->flags |= AHC_NEWEEPROM_FMT; 1941 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1942 return (0); 1943 } 1944 1945 static int 1946 ahc_aic7895_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1947 { 1948 uint8_t rev; 1949 1950 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1951 /* 1952 * The 'C' revision of the aic7895 has a few additional features. 1953 */ 1954 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1955 if (rev >= 4) { 1956 probe_config->chip = AHC_AIC7895C; 1957 probe_config->features = AHC_AIC7895C_FE; 1958 } else { 1959 u_int command; 1960 1961 probe_config->chip = AHC_AIC7895; 1962 probe_config->features = AHC_AIC7895_FE; 1963 1964 /* 1965 * The BIOS disables the use of MWI transactions 1966 * since it does not have the MWI bug work around 1967 * we have. Disabling MWI reduces performance, so 1968 * turn it on again. 1969 */ 1970 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 1971 command |= PCIM_CMD_MWRICEN; 1972 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 1973 probe_config->bugs |= AHC_PCI_MWI_BUG; 1974 } 1975 /* 1976 * XXX Does CACHETHEN really not work??? What about PCI retry? 1977 * on C level chips. Need to test, but for now, play it safe. 1978 */ 1979 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1980 | AHC_CACHETHEN_BUG; 1981 1982 #if 0 1983 uint32_t devconfig; 1984 1985 /* 1986 * Cachesize must also be zero due to stray DAC 1987 * problem when sitting behind some bridges. 1988 */ 1989 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 1990 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 1991 devconfig |= MRDCEN; 1992 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 1993 #endif 1994 probe_config->flags |= AHC_NEWEEPROM_FMT; 1995 return (0); 1996 } 1997 1998 static int 1999 ahc_aic7896_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2000 { 2001 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2002 probe_config->chip = AHC_AIC7896; 2003 probe_config->features = AHC_AIC7896_FE; 2004 probe_config->flags |= AHC_NEWEEPROM_FMT; 2005 probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; 2006 return (0); 2007 } 2008 2009 static int 2010 ahc_aic7899_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2011 { 2012 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2013 probe_config->chip = AHC_AIC7899; 2014 probe_config->features = AHC_AIC7899_FE; 2015 probe_config->flags |= AHC_NEWEEPROM_FMT; 2016 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2017 return (0); 2018 } 2019 2020 static int 2021 ahc_aha29160C_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2022 { 2023 int error; 2024 2025 error = ahc_aic7899_setup(pci, probe_config); 2026 if (error != 0) 2027 return (error); 2028 probe_config->features |= AHC_REMOVABLE; 2029 return (0); 2030 } 2031 2032 static int 2033 ahc_raid_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2034 { 2035 printf("RAID functionality unsupported\n"); 2036 return (ENXIO); 2037 } 2038 2039 static int 2040 ahc_aha394XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2041 { 2042 switch (ahc_get_pci_slot(pci)) { 2043 case AHC_394X_SLOT_CHANNEL_A: 2044 probe_config->channel = 'A'; 2045 break; 2046 case AHC_394X_SLOT_CHANNEL_B: 2047 probe_config->channel = 'B'; 2048 break; 2049 default: 2050 printf("adapter at unexpected slot %d\n" 2051 "unable to map to a channel\n", 2052 ahc_get_pci_slot(pci)); 2053 probe_config->channel = 'A'; 2054 } 2055 return (0); 2056 } 2057 2058 static int 2059 ahc_aha398XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2060 { 2061 switch (ahc_get_pci_slot(pci)) { 2062 case AHC_398X_SLOT_CHANNEL_A: 2063 probe_config->channel = 'A'; 2064 break; 2065 case AHC_398X_SLOT_CHANNEL_B: 2066 probe_config->channel = 'B'; 2067 break; 2068 case AHC_398X_SLOT_CHANNEL_C: 2069 probe_config->channel = 'C'; 2070 break; 2071 default: 2072 printf("adapter at unexpected slot %d\n" 2073 "unable to map to a channel\n", 2074 ahc_get_pci_slot(pci)); 2075 probe_config->channel = 'A'; 2076 break; 2077 } 2078 probe_config->flags |= AHC_LARGE_SEEPROM; 2079 return (0); 2080 } 2081 2082 static int 2083 ahc_aha494XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2084 { 2085 switch (ahc_get_pci_slot(pci)) { 2086 case AHC_494X_SLOT_CHANNEL_A: 2087 probe_config->channel = 'A'; 2088 break; 2089 case AHC_494X_SLOT_CHANNEL_B: 2090 probe_config->channel = 'B'; 2091 break; 2092 case AHC_494X_SLOT_CHANNEL_C: 2093 probe_config->channel = 'C'; 2094 break; 2095 case AHC_494X_SLOT_CHANNEL_D: 2096 probe_config->channel = 'D'; 2097 break; 2098 default: 2099 printf("adapter at unexpected slot %d\n" 2100 "unable to map to a channel\n", 2101 ahc_get_pci_slot(pci)); 2102 probe_config->channel = 'A'; 2103 } 2104 probe_config->flags |= AHC_LARGE_SEEPROM; 2105 return (0); 2106 } 2107