1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 59 60 static __inline uint64_t 61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 77 #define ID_9005_SISL_ID 0x0005900500000000ull 78 #define ID_AIC7850 0x5078900400000000ull 79 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 80 #define ID_AIC7855 0x5578900400000000ull 81 #define ID_AIC7859 0x3860900400000000ull 82 #define ID_AHA_2930CU 0x3860900438699004ull 83 #define ID_AIC7860 0x6078900400000000ull 84 #define ID_AIC7860C 0x6078900478609004ull 85 #define ID_AHA_1480A 0x6075900400000000ull 86 #define ID_AHA_2940AU_0 0x6178900400000000ull 87 #define ID_AHA_2940AU_1 0x6178900478619004ull 88 #define ID_AHA_2940AU_CN 0x2178900478219004ull 89 #define ID_AHA_2930C_VAR 0x6038900438689004ull 90 91 #define ID_AIC7870 0x7078900400000000ull 92 #define ID_AHA_2940 0x7178900400000000ull 93 #define ID_AHA_3940 0x7278900400000000ull 94 #define ID_AHA_398X 0x7378900400000000ull 95 #define ID_AHA_2944 0x7478900400000000ull 96 #define ID_AHA_3944 0x7578900400000000ull 97 #define ID_AHA_4944 0x7678900400000000ull 98 99 #define ID_AIC7880 0x8078900400000000ull 100 #define ID_AIC7880_B 0x8078900478809004ull 101 #define ID_AHA_2940U 0x8178900400000000ull 102 #define ID_AHA_3940U 0x8278900400000000ull 103 #define ID_AHA_2944U 0x8478900400000000ull 104 #define ID_AHA_3944U 0x8578900400000000ull 105 #define ID_AHA_398XU 0x8378900400000000ull 106 #define ID_AHA_4944U 0x8678900400000000ull 107 #define ID_AHA_2940UB 0x8178900478819004ull 108 #define ID_AHA_2930U 0x8878900478889004ull 109 #define ID_AHA_2940U_PRO 0x8778900478879004ull 110 #define ID_AHA_2940U_CN 0x0078900478009004ull 111 112 #define ID_AIC7895 0x7895900478959004ull 113 #define ID_AIC7895_ARO 0x7890900478939004ull 114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 116 #define ID_AHA_3940AU 0x7895900478929004ull 117 #define ID_AHA_3944AU 0x7895900478949004ull 118 119 #define ID_AIC7890 0x001F9005000F9005ull 120 #define ID_AIC7890_ARO 0x00139005000F9005ull 121 #define ID_AAA_131U2 0x0013900500039005ull 122 #define ID_AHA_2930U2 0x0011900501819005ull 123 #define ID_AHA_2940U2B 0x00109005A1009005ull 124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 125 #define ID_AHA_2940U2 0x00109005A1809005ull 126 #define ID_AHA_2950U2B 0x00109005E1009005ull 127 128 #define ID_AIC7892 0x008F9005FFFF9005ull 129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 130 #define ID_AHA_29160 0x00809005E2A09005ull 131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132 #define ID_AHA_29160N 0x0080900562A09005ull 133 #define ID_AHA_29160C 0x0080900562209005ull 134 #define ID_AHA_29160B 0x00809005E2209005ull 135 #define ID_AHA_19160B 0x0081900562A19005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 /* aic7895 based controllers */ 474 { 475 ID_AHA_2940U_DUAL, 476 ID_ALL_MASK, 477 "Adaptec 2940/DUAL Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AHA_3940AU, 482 ID_ALL_MASK, 483 "Adaptec 3940A Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3944AU, 488 ID_ALL_MASK, 489 "Adaptec 3944A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_ARO, 494 ID_AIC7895_ARO_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 496 ahc_aic7895_setup 497 }, 498 /* aic7896/97 based controllers */ 499 { 500 ID_AHA_3950U2B_0, 501 ID_ALL_MASK, 502 "Adaptec 3950B Ultra2 SCSI adapter", 503 ahc_aic7896_setup 504 }, 505 { 506 ID_AHA_3950U2B_1, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2D_0, 513 ID_ALL_MASK, 514 "Adaptec 3950D Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_1, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AIC7896_ARO, 525 ID_ALL_MASK, 526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 527 ahc_aic7896_setup 528 }, 529 /* aic7899 based controllers */ 530 { 531 ID_AHA_3960D, 532 ID_ALL_MASK, 533 "Adaptec 3960D Ultra160 SCSI adapter", 534 ahc_aic7899_setup 535 }, 536 { 537 ID_AHA_3960D_CPQ, 538 ID_ALL_MASK, 539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AIC7899_ARO, 544 ID_ALL_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 546 ahc_aic7899_setup 547 }, 548 /* Generic chip probes for devices we don't know 'exactly' */ 549 { 550 ID_AIC7850 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7850 SCSI adapter", 553 ahc_aic785X_setup 554 }, 555 { 556 ID_AIC7855 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7855 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7859 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7859 SCSI adapter", 565 ahc_aic7860_setup 566 }, 567 { 568 ID_AIC7860 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7860 Ultra SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7870 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7870 SCSI adapter", 577 ahc_aic7870_setup 578 }, 579 { 580 ID_AIC7880 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7880 Ultra SCSI adapter", 583 ahc_aic7880_setup 584 }, 585 { 586 ID_AIC7890 & ID_9005_GENERIC_MASK, 587 ID_9005_GENERIC_MASK, 588 "Adaptec aic7890/91 Ultra2 SCSI adapter", 589 ahc_aic7890_setup 590 }, 591 { 592 ID_AIC7892 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7892 Ultra160 SCSI adapter", 595 ahc_aic7892_setup 596 }, 597 { 598 ID_AIC7895 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7895 Ultra SCSI adapter", 601 ahc_aic7895_setup 602 }, 603 { 604 ID_AIC7896 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7896/97 Ultra2 SCSI adapter", 607 ahc_aic7896_setup 608 }, 609 { 610 ID_AIC7899 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7899 Ultra160 SCSI adapter", 613 ahc_aic7899_setup 614 }, 615 { 616 ID_AIC7810 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7810 RAID memory controller", 619 ahc_raid_setup 620 }, 621 { 622 ID_AIC7815 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7815 RAID memory controller", 625 ahc_raid_setup 626 } 627 }; 628 629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 630 631 #define AHC_394X_SLOT_CHANNEL_A 4 632 #define AHC_394X_SLOT_CHANNEL_B 5 633 634 #define AHC_398X_SLOT_CHANNEL_A 4 635 #define AHC_398X_SLOT_CHANNEL_B 8 636 #define AHC_398X_SLOT_CHANNEL_C 12 637 638 #define AHC_494X_SLOT_CHANNEL_A 4 639 #define AHC_494X_SLOT_CHANNEL_B 5 640 #define AHC_494X_SLOT_CHANNEL_C 6 641 #define AHC_494X_SLOT_CHANNEL_D 7 642 643 #define DEVCONFIG 0x40 644 #define PCIERRGENDIS 0x80000000ul 645 #define SCBSIZE32 0x00010000ul /* aic789X only */ 646 #define REXTVALID 0x00001000ul /* ultra cards only */ 647 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 648 #define RAMPSM 0x00000200ul /* aic7870+ only */ 649 #define VOLSENSE 0x00000100ul 650 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 651 #define SCBRAMSEL 0x00000080ul 652 #define MRDCEN 0x00000040ul 653 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 654 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 655 #define BERREN 0x00000008ul 656 #define DACEN 0x00000004ul 657 #define STPWLEVEL 0x00000002ul 658 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 659 660 #define CSIZE_LATTIME 0x0c 661 #define CACHESIZE 0x0000003ful /* only 5 bits */ 662 #define LATTIME 0x0000ff00ul 663 664 /* PCI STATUS definitions */ 665 #define DPE 0x80 666 #define SSE 0x40 667 #define RMA 0x20 668 #define RTA 0x10 669 #define STA 0x08 670 #define DPR 0x01 671 672 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 673 uint16_t subvendor, uint16_t subdevice); 674 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 675 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 676 int pcheck, int fast, int large); 677 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 678 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 679 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 680 struct seeprom_config *sc); 681 static void configure_termination(struct ahc_softc *ahc, 682 struct seeprom_descriptor *sd, 683 u_int adapter_control, 684 u_int *sxfrctl1); 685 686 static void ahc_new_term_detect(struct ahc_softc *ahc, 687 int *enableSEC_low, 688 int *enableSEC_high, 689 int *enablePRI_low, 690 int *enablePRI_high, 691 int *eeprom_present); 692 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 693 int *internal68_present, 694 int *externalcable_present, 695 int *eeprom_present); 696 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 697 int *externalcable_present, 698 int *eeprom_present); 699 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 700 static uint8_t read_brdctl(struct ahc_softc *ahc); 701 702 static int 703 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 704 uint16_t subdevice, uint16_t subvendor) 705 { 706 int result; 707 708 /* Default to invalid. */ 709 result = 0; 710 if (vendor == 0x9005 711 && subvendor == 0x9005 712 && subdevice != device 713 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 714 715 switch (SUBID_9005_TYPE(subdevice)) { 716 case SUBID_9005_TYPE_MB: 717 break; 718 case SUBID_9005_TYPE_CARD: 719 case SUBID_9005_TYPE_LCCARD: 720 /* 721 * Currently only trust Adaptec cards to 722 * get the sub device info correct. 723 */ 724 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 725 result = 1; 726 break; 727 case SUBID_9005_TYPE_RAID: 728 break; 729 default: 730 break; 731 } 732 } 733 return (result); 734 } 735 736 struct ahc_pci_identity * 737 ahc_find_pci_device(ahc_dev_softc_t pci) 738 { 739 uint64_t full_id; 740 uint16_t device; 741 uint16_t vendor; 742 uint16_t subdevice; 743 uint16_t subvendor; 744 struct ahc_pci_identity *entry; 745 u_int i; 746 747 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 748 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 749 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 750 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 751 full_id = ahc_compose_id(device, 752 vendor, 753 subdevice, 754 subvendor); 755 756 /* 757 * If the second function is not hooked up, ignore it. 758 * Unfortunately, not all MB vendors implement the 759 * subdevice ID as per the Adaptec spec, so do our best 760 * to sanity check it prior to accepting the subdevice 761 * ID as valid. 762 */ 763 if (ahc_get_pci_function(pci) > 0 764 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 765 && SUBID_9005_MFUNCENB(subdevice) == 0) 766 return (NULL); 767 768 for (i = 0; i < ahc_num_pci_devs; i++) { 769 entry = &ahc_pci_ident_table[i]; 770 if (entry->full_id == (full_id & entry->id_mask)) { 771 /* Honor exclusion entries. */ 772 if (entry->name == NULL) 773 return (NULL); 774 return (entry); 775 } 776 } 777 return (NULL); 778 } 779 780 int 781 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 782 { 783 u_long l; 784 u_int command; 785 u_int our_id; 786 u_int sxfrctl1; 787 u_int scsiseq; 788 u_int dscommand0; 789 uint32_t devconfig; 790 int error; 791 uint8_t sblkctl; 792 793 our_id = 0; 794 error = entry->setup(ahc); 795 if (error != 0) 796 return (error); 797 ahc->chip |= AHC_PCI; 798 ahc->description = entry->name; 799 800 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 801 802 error = ahc_pci_map_registers(ahc); 803 if (error != 0) 804 return (error); 805 806 /* 807 * Before we continue probing the card, ensure that 808 * its interrupts are *disabled*. We don't want 809 * a misstep to hang the machine in an interrupt 810 * storm. 811 */ 812 ahc_intr_enable(ahc, FALSE); 813 814 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 815 816 /* 817 * If we need to support high memory, enable dual 818 * address cycles. This bit must be set to enable 819 * high address bit generation even if we are on a 820 * 64bit bus (PCI64BIT set in devconfig). 821 */ 822 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 823 824 if (bootverbose) 825 printf("%s: Enabling 39Bit Addressing\n", 826 ahc_name(ahc)); 827 devconfig |= DACEN; 828 } 829 830 /* Ensure that pci error generation, a test feature, is disabled. */ 831 devconfig |= PCIERRGENDIS; 832 833 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 834 835 /* Ensure busmastering is enabled */ 836 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 837 command |= PCIM_CMD_BUSMASTEREN; 838 839 /* 840 * Disable PCI parity error reporting. Users typically 841 * do this to work around broken PCI chipsets that get 842 * the parity timing wrong and thus generate lots of spurious 843 * errors. 844 */ 845 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 846 command &= ~PCIM_CMD_PERRESPEN; 847 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 848 849 /* On all PCI adapters, we allow SCB paging */ 850 ahc->flags |= AHC_PAGESCBS; 851 852 error = ahc_softc_init(ahc); 853 if (error != 0) 854 return (error); 855 856 ahc->bus_intr = ahc_pci_intr; 857 858 /* Remeber how the card was setup in case there is no SEEPROM */ 859 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 860 ahc_pause(ahc); 861 if ((ahc->features & AHC_ULTRA2) != 0) 862 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 863 else 864 our_id = ahc_inb(ahc, SCSIID) & OID; 865 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 866 scsiseq = ahc_inb(ahc, SCSISEQ); 867 } else { 868 sxfrctl1 = STPWEN; 869 our_id = 7; 870 scsiseq = 0; 871 } 872 873 error = ahc_reset(ahc); 874 if (error != 0) 875 return (ENXIO); 876 877 if ((ahc->features & AHC_DT) != 0) { 878 u_int sfunct; 879 880 /* Perform ALT-Mode Setup */ 881 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 882 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 883 ahc_outb(ahc, OPTIONMODE, 884 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 885 ahc_outb(ahc, SFUNCT, sfunct); 886 887 /* Normal mode setup */ 888 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 889 |TARGCRCENDEN); 890 } 891 892 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 893 dscommand0 |= MPARCKEN|CACHETHEN; 894 if ((ahc->features & AHC_ULTRA2) != 0) { 895 896 /* 897 * DPARCKEN doesn't work correctly on 898 * some MBs so don't use it. 899 */ 900 dscommand0 &= ~DPARCKEN; 901 } 902 903 /* 904 * Handle chips that must have cache line 905 * streaming (dis/en)abled. 906 */ 907 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 908 dscommand0 |= CACHETHEN; 909 910 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 911 dscommand0 &= ~CACHETHEN; 912 913 ahc_outb(ahc, DSCOMMAND0, dscommand0); 914 915 ahc->pci_cachesize = 916 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 917 /*bytes*/1) & CACHESIZE; 918 ahc->pci_cachesize *= 4; 919 920 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 921 && ahc->pci_cachesize == 4) { 922 923 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 924 0, /*bytes*/1); 925 ahc->pci_cachesize = 0; 926 } 927 928 /* 929 * We cannot perform ULTRA speeds without the presense 930 * of the external precision resistor. 931 */ 932 if ((ahc->features & AHC_ULTRA) != 0) { 933 uint32_t devconfig; 934 935 devconfig = ahc_pci_read_config(ahc->dev_softc, 936 DEVCONFIG, /*bytes*/4); 937 if ((devconfig & REXTVALID) == 0) 938 ahc->features &= ~AHC_ULTRA; 939 } 940 941 /* See if we have a SEEPROM and perform auto-term */ 942 check_extport(ahc, &sxfrctl1); 943 944 /* 945 * Take the LED out of diagnostic mode 946 */ 947 sblkctl = ahc_inb(ahc, SBLKCTL); 948 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 949 950 if ((ahc->features & AHC_ULTRA2) != 0) { 951 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 952 } else { 953 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 954 } 955 956 if (ahc->flags & AHC_USEDEFAULTS) { 957 /* 958 * PCI Adapter default setup 959 * Should only be used if the adapter does not have 960 * a SEEPROM. 961 */ 962 /* See if someone else set us up already */ 963 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 964 && scsiseq != 0) { 965 printf("%s: Using left over BIOS settings\n", 966 ahc_name(ahc)); 967 ahc->flags &= ~AHC_USEDEFAULTS; 968 ahc->flags |= AHC_BIOS_ENABLED; 969 } else { 970 /* 971 * Assume only one connector and always turn 972 * on termination. 973 */ 974 our_id = 0x07; 975 sxfrctl1 = STPWEN; 976 } 977 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 978 979 ahc->our_id = our_id; 980 } 981 982 /* 983 * Take a look to see if we have external SRAM. 984 * We currently do not attempt to use SRAM that is 985 * shared among multiple controllers. 986 */ 987 ahc_probe_ext_scbram(ahc); 988 989 /* 990 * Record our termination setting for the 991 * generic initialization routine. 992 */ 993 if ((sxfrctl1 & STPWEN) != 0) 994 ahc->flags |= AHC_TERM_ENB_A; 995 996 /* Core initialization */ 997 error = ahc_init(ahc); 998 if (error != 0) 999 return (error); 1000 1001 /* 1002 * Allow interrupts now that we are completely setup. 1003 */ 1004 error = ahc_pci_map_int(ahc); 1005 if (error != 0) 1006 return (error); 1007 1008 ahc_list_lock(&l); 1009 /* 1010 * Link this softc in with all other ahc instances. 1011 */ 1012 ahc_softc_insert(ahc); 1013 ahc_list_unlock(&l); 1014 return (0); 1015 } 1016 1017 /* 1018 * Test for the presense of external sram in an 1019 * "unshared" configuration. 1020 */ 1021 static int 1022 ahc_ext_scbram_present(struct ahc_softc *ahc) 1023 { 1024 u_int chip; 1025 int ramps; 1026 int single_user; 1027 uint32_t devconfig; 1028 1029 chip = ahc->chip & AHC_CHIPID_MASK; 1030 devconfig = ahc_pci_read_config(ahc->dev_softc, 1031 DEVCONFIG, /*bytes*/4); 1032 single_user = (devconfig & MPORTMODE) != 0; 1033 1034 if ((ahc->features & AHC_ULTRA2) != 0) 1035 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1036 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1037 /* 1038 * External SCBRAM arbitration is flakey 1039 * on these chips. Unfortunately this means 1040 * we don't use the extra SCB ram space on the 1041 * 3940AUW. 1042 */ 1043 ramps = 0; 1044 else if (chip >= AHC_AIC7870) 1045 ramps = (devconfig & RAMPSM) != 0; 1046 else 1047 ramps = 0; 1048 1049 if (ramps && single_user) 1050 return (1); 1051 return (0); 1052 } 1053 1054 /* 1055 * Enable external scbram. 1056 */ 1057 static void 1058 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1059 int fast, int large) 1060 { 1061 uint32_t devconfig; 1062 1063 if (ahc->features & AHC_MULTI_FUNC) { 1064 /* 1065 * Set the SCB Base addr (highest address bit) 1066 * depending on which channel we are. 1067 */ 1068 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1069 } 1070 1071 ahc->flags &= ~AHC_LSCBS_ENABLED; 1072 if (large) 1073 ahc->flags |= AHC_LSCBS_ENABLED; 1074 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1075 if ((ahc->features & AHC_ULTRA2) != 0) { 1076 u_int dscommand0; 1077 1078 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1079 if (enable) 1080 dscommand0 &= ~INTSCBRAMSEL; 1081 else 1082 dscommand0 |= INTSCBRAMSEL; 1083 if (large) 1084 dscommand0 &= ~USCBSIZE32; 1085 else 1086 dscommand0 |= USCBSIZE32; 1087 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1088 } else { 1089 if (fast) 1090 devconfig &= ~EXTSCBTIME; 1091 else 1092 devconfig |= EXTSCBTIME; 1093 if (enable) 1094 devconfig &= ~SCBRAMSEL; 1095 else 1096 devconfig |= SCBRAMSEL; 1097 if (large) 1098 devconfig &= ~SCBSIZE32; 1099 else 1100 devconfig |= SCBSIZE32; 1101 } 1102 if (pcheck) 1103 devconfig |= EXTSCBPEN; 1104 else 1105 devconfig &= ~EXTSCBPEN; 1106 1107 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1108 } 1109 1110 /* 1111 * Take a look to see if we have external SRAM. 1112 * We currently do not attempt to use SRAM that is 1113 * shared among multiple controllers. 1114 */ 1115 static void 1116 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1117 { 1118 int num_scbs; 1119 int test_num_scbs; 1120 int enable; 1121 int pcheck; 1122 int fast; 1123 int large; 1124 1125 enable = FALSE; 1126 pcheck = FALSE; 1127 fast = FALSE; 1128 large = FALSE; 1129 num_scbs = 0; 1130 1131 if (ahc_ext_scbram_present(ahc) == 0) 1132 goto done; 1133 1134 /* 1135 * Probe for the best parameters to use. 1136 */ 1137 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1138 num_scbs = ahc_probe_scbs(ahc); 1139 if (num_scbs == 0) { 1140 /* The SRAM wasn't really present. */ 1141 goto done; 1142 } 1143 enable = TRUE; 1144 1145 /* 1146 * Clear any outstanding parity error 1147 * and ensure that parity error reporting 1148 * is enabled. 1149 */ 1150 ahc_outb(ahc, SEQCTL, 0); 1151 ahc_outb(ahc, CLRINT, CLRPARERR); 1152 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1153 1154 /* Now see if we can do parity */ 1155 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1156 num_scbs = ahc_probe_scbs(ahc); 1157 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1158 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1159 pcheck = TRUE; 1160 1161 /* Clear any resulting parity error */ 1162 ahc_outb(ahc, CLRINT, CLRPARERR); 1163 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1164 1165 /* Now see if we can do fast timing */ 1166 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1167 test_num_scbs = ahc_probe_scbs(ahc); 1168 if (test_num_scbs == num_scbs 1169 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1170 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1171 fast = TRUE; 1172 1173 /* 1174 * See if we can use large SCBs and still maintain 1175 * the same overall count of SCBs. 1176 */ 1177 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1178 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1179 test_num_scbs = ahc_probe_scbs(ahc); 1180 if (test_num_scbs >= num_scbs) { 1181 large = TRUE; 1182 num_scbs = test_num_scbs; 1183 if (num_scbs >= 64) { 1184 /* 1185 * We have enough space to move the 1186 * "busy targets table" into SCB space 1187 * and make it qualify all the way to the 1188 * lun level. 1189 */ 1190 ahc->flags |= AHC_SCB_BTT; 1191 } 1192 } 1193 } 1194 done: 1195 /* 1196 * Disable parity error reporting until we 1197 * can load instruction ram. 1198 */ 1199 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1200 /* Clear any latched parity error */ 1201 ahc_outb(ahc, CLRINT, CLRPARERR); 1202 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1203 if (bootverbose && enable) { 1204 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1205 ahc_name(ahc), fast ? "fast" : "slow", 1206 pcheck ? ", parity checking enabled" : "", 1207 large ? 64 : 32); 1208 } 1209 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1210 } 1211 1212 /* 1213 * Perform some simple tests that should catch situations where 1214 * our registers are invalidly mapped. 1215 */ 1216 int 1217 ahc_pci_test_register_access(struct ahc_softc *ahc) 1218 { 1219 int error; 1220 u_int status1; 1221 uint32_t cmd; 1222 uint8_t hcntrl; 1223 1224 error = EIO; 1225 1226 /* 1227 * Enable PCI error interrupt status, but suppress NMIs 1228 * generated by SERR raised due to target aborts. 1229 */ 1230 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1231 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1232 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1233 1234 /* 1235 * First a simple test to see if any 1236 * registers can be read. Reading 1237 * HCNTRL has no side effects and has 1238 * at least one bit that is guaranteed to 1239 * be zero so it is a good register to 1240 * use for this test. 1241 */ 1242 hcntrl = ahc_inb(ahc, HCNTRL); 1243 if (hcntrl == 0xFF) 1244 goto fail; 1245 1246 /* 1247 * Next create a situation where write combining 1248 * or read prefetching could be initiated by the 1249 * CPU or host bridge. Our device does not support 1250 * either, so look for data corruption and/or flagged 1251 * PCI errors. 1252 */ 1253 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1254 while (ahc_is_paused(ahc) == 0) 1255 ; 1256 ahc_outb(ahc, SEQCTL, PERRORDIS); 1257 ahc_outb(ahc, SCBPTR, 0); 1258 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1259 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1260 goto fail; 1261 1262 status1 = ahc_pci_read_config(ahc->dev_softc, 1263 PCIR_STATUS + 1, /*bytes*/1); 1264 if ((status1 & STA) != 0) 1265 goto fail; 1266 1267 error = 0; 1268 1269 fail: 1270 /* Silently clear any latched errors. */ 1271 status1 = ahc_pci_read_config(ahc->dev_softc, 1272 PCIR_STATUS + 1, /*bytes*/1); 1273 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1274 status1, /*bytes*/1); 1275 ahc_outb(ahc, CLRINT, CLRPARERR); 1276 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1277 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1278 return (error); 1279 } 1280 1281 /* 1282 * Check the external port logic for a serial eeprom 1283 * and termination/cable detection contrls. 1284 */ 1285 static void 1286 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1287 { 1288 struct seeprom_descriptor sd; 1289 struct seeprom_config *sc; 1290 int have_seeprom; 1291 int have_autoterm; 1292 1293 sd.sd_ahc = ahc; 1294 sd.sd_control_offset = SEECTL; 1295 sd.sd_status_offset = SEECTL; 1296 sd.sd_dataout_offset = SEECTL; 1297 sc = ahc->seep_config; 1298 1299 /* 1300 * For some multi-channel devices, the c46 is simply too 1301 * small to work. For the other controller types, we can 1302 * get our information from either SEEPROM type. Set the 1303 * type to start our probe with accordingly. 1304 */ 1305 if (ahc->flags & AHC_LARGE_SEEPROM) 1306 sd.sd_chip = C56_66; 1307 else 1308 sd.sd_chip = C46; 1309 1310 sd.sd_MS = SEEMS; 1311 sd.sd_RDY = SEERDY; 1312 sd.sd_CS = SEECS; 1313 sd.sd_CK = SEECK; 1314 sd.sd_DO = SEEDO; 1315 sd.sd_DI = SEEDI; 1316 1317 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1318 if (have_seeprom) { 1319 1320 if (bootverbose) 1321 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1322 1323 for (;;) { 1324 u_int start_addr; 1325 1326 start_addr = 32 * (ahc->channel - 'A'); 1327 1328 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1329 start_addr, 1330 sizeof(*sc)/2); 1331 1332 if (have_seeprom) 1333 have_seeprom = ahc_verify_cksum(sc); 1334 1335 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1336 if (bootverbose) { 1337 if (have_seeprom == 0) 1338 printf ("checksum error\n"); 1339 else 1340 printf ("done.\n"); 1341 } 1342 break; 1343 } 1344 sd.sd_chip = C56_66; 1345 } 1346 ahc_release_seeprom(&sd); 1347 } 1348 1349 if (!have_seeprom) { 1350 /* 1351 * Pull scratch ram settings and treat them as 1352 * if they are the contents of an seeprom if 1353 * the 'ADPT' signature is found in SCB2. 1354 * We manually compose the data as 16bit values 1355 * to avoid endian issues. 1356 */ 1357 ahc_outb(ahc, SCBPTR, 2); 1358 if (ahc_inb(ahc, SCB_BASE) == 'A' 1359 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1360 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1361 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1362 uint16_t *sc_data; 1363 int i; 1364 1365 sc_data = (uint16_t *)sc; 1366 for (i = 0; i < 32; i++, sc_data++) { 1367 int j; 1368 1369 j = i * 2; 1370 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1371 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1372 } 1373 have_seeprom = ahc_verify_cksum(sc); 1374 if (have_seeprom) 1375 ahc->flags |= AHC_SCB_CONFIG_USED; 1376 } 1377 /* 1378 * Clear any SCB parity errors in case this data and 1379 * its associated parity was not initialized by the BIOS 1380 */ 1381 ahc_outb(ahc, CLRINT, CLRPARERR); 1382 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1383 } 1384 1385 if (!have_seeprom) { 1386 if (bootverbose) 1387 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1388 ahc->flags |= AHC_USEDEFAULTS; 1389 free(ahc->seep_config, M_DEVBUF); 1390 ahc->seep_config = NULL; 1391 sc = NULL; 1392 } else { 1393 ahc_parse_pci_eeprom(ahc, sc); 1394 } 1395 1396 /* 1397 * Cards that have the external logic necessary to talk to 1398 * a SEEPROM, are almost certain to have the remaining logic 1399 * necessary for auto-termination control. This assumption 1400 * hasn't failed yet... 1401 */ 1402 have_autoterm = have_seeprom; 1403 1404 /* 1405 * Some low-cost chips have SEEPROM and auto-term control built 1406 * in, instead of using a GAL. They can tell us directly 1407 * if the termination logic is enabled. 1408 */ 1409 if ((ahc->features & AHC_SPIOCAP) != 0) { 1410 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1411 have_autoterm = FALSE; 1412 } 1413 1414 if (have_autoterm) { 1415 ahc_acquire_seeprom(ahc, &sd); 1416 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1417 ahc_release_seeprom(&sd); 1418 } else if (have_seeprom) { 1419 *sxfrctl1 &= ~STPWEN; 1420 if ((sc->adapter_control & CFSTERM) != 0) 1421 *sxfrctl1 |= STPWEN; 1422 if (bootverbose) 1423 printf("%s: Low byte termination %sabled\n", 1424 ahc_name(ahc), 1425 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1426 } 1427 } 1428 1429 static void 1430 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1431 { 1432 /* 1433 * Put the data we've collected down into SRAM 1434 * where ahc_init will find it. 1435 */ 1436 int i; 1437 int max_targ = sc->max_targets & CFMAXTARG; 1438 u_int scsi_conf; 1439 uint16_t discenable; 1440 uint16_t ultraenb; 1441 1442 discenable = 0; 1443 ultraenb = 0; 1444 if ((sc->adapter_control & CFULTRAEN) != 0) { 1445 /* 1446 * Determine if this adapter has a "newstyle" 1447 * SEEPROM format. 1448 */ 1449 for (i = 0; i < max_targ; i++) { 1450 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1451 ahc->flags |= AHC_NEWEEPROM_FMT; 1452 break; 1453 } 1454 } 1455 } 1456 1457 for (i = 0; i < max_targ; i++) { 1458 u_int scsirate; 1459 uint16_t target_mask; 1460 1461 target_mask = 0x01 << i; 1462 if (sc->device_flags[i] & CFDISC) 1463 discenable |= target_mask; 1464 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1465 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1466 ultraenb |= target_mask; 1467 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1468 ultraenb |= target_mask; 1469 } 1470 if ((sc->device_flags[i] & CFXFER) == 0x04 1471 && (ultraenb & target_mask) != 0) { 1472 /* Treat 10MHz as a non-ultra speed */ 1473 sc->device_flags[i] &= ~CFXFER; 1474 ultraenb &= ~target_mask; 1475 } 1476 if ((ahc->features & AHC_ULTRA2) != 0) { 1477 u_int offset; 1478 1479 if (sc->device_flags[i] & CFSYNCH) 1480 offset = MAX_OFFSET_ULTRA2; 1481 else 1482 offset = 0; 1483 ahc_outb(ahc, TARG_OFFSET + i, offset); 1484 1485 /* 1486 * The ultra enable bits contain the 1487 * high bit of the ultra2 sync rate 1488 * field. 1489 */ 1490 scsirate = (sc->device_flags[i] & CFXFER) 1491 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1492 if (sc->device_flags[i] & CFWIDEB) 1493 scsirate |= WIDEXFER; 1494 } else { 1495 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1496 if (sc->device_flags[i] & CFSYNCH) 1497 scsirate |= SOFS; 1498 if (sc->device_flags[i] & CFWIDEB) 1499 scsirate |= WIDEXFER; 1500 } 1501 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1502 } 1503 ahc->our_id = sc->brtime_id & CFSCSIID; 1504 1505 scsi_conf = (ahc->our_id & 0x7); 1506 if (sc->adapter_control & CFSPARITY) 1507 scsi_conf |= ENSPCHK; 1508 if (sc->adapter_control & CFRESETB) 1509 scsi_conf |= RESET_SCSI; 1510 1511 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1512 1513 if (sc->bios_control & CFEXTEND) 1514 ahc->flags |= AHC_EXTENDED_TRANS_A; 1515 1516 if (sc->bios_control & CFBIOSEN) 1517 ahc->flags |= AHC_BIOS_ENABLED; 1518 if (ahc->features & AHC_ULTRA 1519 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1520 /* Should we enable Ultra mode? */ 1521 if (!(sc->adapter_control & CFULTRAEN)) 1522 /* Treat us as a non-ultra card */ 1523 ultraenb = 0; 1524 } 1525 1526 if (sc->signature == CFSIGNATURE 1527 || sc->signature == CFSIGNATURE2) { 1528 uint32_t devconfig; 1529 1530 /* Honor the STPWLEVEL settings */ 1531 devconfig = ahc_pci_read_config(ahc->dev_softc, 1532 DEVCONFIG, /*bytes*/4); 1533 devconfig &= ~STPWLEVEL; 1534 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1535 devconfig |= STPWLEVEL; 1536 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1537 devconfig, /*bytes*/4); 1538 } 1539 /* Set SCSICONF info */ 1540 ahc_outb(ahc, SCSICONF, scsi_conf); 1541 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1542 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1543 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1544 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1545 } 1546 1547 static void 1548 configure_termination(struct ahc_softc *ahc, 1549 struct seeprom_descriptor *sd, 1550 u_int adapter_control, 1551 u_int *sxfrctl1) 1552 { 1553 uint8_t brddat; 1554 1555 brddat = 0; 1556 1557 /* 1558 * Update the settings in sxfrctl1 to match the 1559 * termination settings 1560 */ 1561 *sxfrctl1 = 0; 1562 1563 /* 1564 * SEECS must be on for the GALS to latch 1565 * the data properly. Be sure to leave MS 1566 * on or we will release the seeprom. 1567 */ 1568 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1569 if ((adapter_control & CFAUTOTERM) != 0 1570 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1571 int internal50_present; 1572 int internal68_present; 1573 int externalcable_present; 1574 int eeprom_present; 1575 int enableSEC_low; 1576 int enableSEC_high; 1577 int enablePRI_low; 1578 int enablePRI_high; 1579 int sum; 1580 1581 enableSEC_low = 0; 1582 enableSEC_high = 0; 1583 enablePRI_low = 0; 1584 enablePRI_high = 0; 1585 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1586 ahc_new_term_detect(ahc, &enableSEC_low, 1587 &enableSEC_high, 1588 &enablePRI_low, 1589 &enablePRI_high, 1590 &eeprom_present); 1591 if ((adapter_control & CFSEAUTOTERM) == 0) { 1592 if (bootverbose) 1593 printf("%s: Manual SE Termination\n", 1594 ahc_name(ahc)); 1595 enableSEC_low = (adapter_control & CFSELOWTERM); 1596 enableSEC_high = 1597 (adapter_control & CFSEHIGHTERM); 1598 } 1599 if ((adapter_control & CFAUTOTERM) == 0) { 1600 if (bootverbose) 1601 printf("%s: Manual LVD Termination\n", 1602 ahc_name(ahc)); 1603 enablePRI_low = (adapter_control & CFSTERM); 1604 enablePRI_high = (adapter_control & CFWSTERM); 1605 } 1606 /* Make the table calculations below happy */ 1607 internal50_present = 0; 1608 internal68_present = 1; 1609 externalcable_present = 1; 1610 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1611 aic785X_cable_detect(ahc, &internal50_present, 1612 &externalcable_present, 1613 &eeprom_present); 1614 /* Can never support a wide connector. */ 1615 internal68_present = 0; 1616 } else { 1617 aic787X_cable_detect(ahc, &internal50_present, 1618 &internal68_present, 1619 &externalcable_present, 1620 &eeprom_present); 1621 } 1622 1623 if ((ahc->features & AHC_WIDE) == 0) 1624 internal68_present = 0; 1625 1626 if (bootverbose 1627 && (ahc->features & AHC_ULTRA2) == 0) { 1628 printf("%s: internal 50 cable %s present", 1629 ahc_name(ahc), 1630 internal50_present ? "is":"not"); 1631 1632 if ((ahc->features & AHC_WIDE) != 0) 1633 printf(", internal 68 cable %s present", 1634 internal68_present ? "is":"not"); 1635 printf("\n%s: external cable %s present\n", 1636 ahc_name(ahc), 1637 externalcable_present ? "is":"not"); 1638 } 1639 if (bootverbose) 1640 printf("%s: BIOS eeprom %s present\n", 1641 ahc_name(ahc), eeprom_present ? "is" : "not"); 1642 1643 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1644 /* 1645 * The 50 pin connector is a separate bus, 1646 * so force it to always be terminated. 1647 * In the future, perform current sensing 1648 * to determine if we are in the middle of 1649 * a properly terminated bus. 1650 */ 1651 internal50_present = 0; 1652 } 1653 1654 /* 1655 * Now set the termination based on what 1656 * we found. 1657 * Flash Enable = BRDDAT7 1658 * Secondary High Term Enable = BRDDAT6 1659 * Secondary Low Term Enable = BRDDAT5 (7890) 1660 * Primary High Term Enable = BRDDAT4 (7890) 1661 */ 1662 if ((ahc->features & AHC_ULTRA2) == 0 1663 && (internal50_present != 0) 1664 && (internal68_present != 0) 1665 && (externalcable_present != 0)) { 1666 printf("%s: Illegal cable configuration!!. " 1667 "Only two connectors on the " 1668 "adapter may be used at a " 1669 "time!\n", ahc_name(ahc)); 1670 1671 /* 1672 * Pretend there are no cables in the hope 1673 * that having all of the termination on 1674 * gives us a more stable bus. 1675 */ 1676 internal50_present = 0; 1677 internal68_present = 0; 1678 externalcable_present = 0; 1679 } 1680 1681 if ((ahc->features & AHC_WIDE) != 0 1682 && ((externalcable_present == 0) 1683 || (internal68_present == 0) 1684 || (enableSEC_high != 0))) { 1685 brddat |= BRDDAT6; 1686 if (bootverbose) { 1687 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1688 printf("%s: 68 pin termination " 1689 "Enabled\n", ahc_name(ahc)); 1690 else 1691 printf("%s: %sHigh byte termination " 1692 "Enabled\n", ahc_name(ahc), 1693 enableSEC_high ? "Secondary " 1694 : ""); 1695 } 1696 } 1697 1698 sum = internal50_present + internal68_present 1699 + externalcable_present; 1700 if (sum < 2 || (enableSEC_low != 0)) { 1701 if ((ahc->features & AHC_ULTRA2) != 0) 1702 brddat |= BRDDAT5; 1703 else 1704 *sxfrctl1 |= STPWEN; 1705 if (bootverbose) { 1706 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1707 printf("%s: 50 pin termination " 1708 "Enabled\n", ahc_name(ahc)); 1709 else 1710 printf("%s: %sLow byte termination " 1711 "Enabled\n", ahc_name(ahc), 1712 enableSEC_low ? "Secondary " 1713 : ""); 1714 } 1715 } 1716 1717 if (enablePRI_low != 0) { 1718 *sxfrctl1 |= STPWEN; 1719 if (bootverbose) 1720 printf("%s: Primary Low Byte termination " 1721 "Enabled\n", ahc_name(ahc)); 1722 } 1723 1724 /* 1725 * Setup STPWEN before setting up the rest of 1726 * the termination per the tech note on the U160 cards. 1727 */ 1728 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1729 1730 if (enablePRI_high != 0) { 1731 brddat |= BRDDAT4; 1732 if (bootverbose) 1733 printf("%s: Primary High Byte " 1734 "termination Enabled\n", 1735 ahc_name(ahc)); 1736 } 1737 1738 write_brdctl(ahc, brddat); 1739 1740 } else { 1741 if ((adapter_control & CFSTERM) != 0) { 1742 *sxfrctl1 |= STPWEN; 1743 1744 if (bootverbose) 1745 printf("%s: %sLow byte termination Enabled\n", 1746 ahc_name(ahc), 1747 (ahc->features & AHC_ULTRA2) ? "Primary " 1748 : ""); 1749 } 1750 1751 if ((adapter_control & CFWSTERM) != 0 1752 && (ahc->features & AHC_WIDE) != 0) { 1753 brddat |= BRDDAT6; 1754 if (bootverbose) 1755 printf("%s: %sHigh byte termination Enabled\n", 1756 ahc_name(ahc), 1757 (ahc->features & AHC_ULTRA2) 1758 ? "Secondary " : ""); 1759 } 1760 1761 /* 1762 * Setup STPWEN before setting up the rest of 1763 * the termination per the tech note on the U160 cards. 1764 */ 1765 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1766 1767 if ((ahc->features & AHC_WIDE) != 0) 1768 write_brdctl(ahc, brddat); 1769 } 1770 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1771 } 1772 1773 static void 1774 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1775 int *enableSEC_high, int *enablePRI_low, 1776 int *enablePRI_high, int *eeprom_present) 1777 { 1778 uint8_t brdctl; 1779 1780 /* 1781 * BRDDAT7 = Eeprom 1782 * BRDDAT6 = Enable Secondary High Byte termination 1783 * BRDDAT5 = Enable Secondary Low Byte termination 1784 * BRDDAT4 = Enable Primary high byte termination 1785 * BRDDAT3 = Enable Primary low byte termination 1786 */ 1787 brdctl = read_brdctl(ahc); 1788 *eeprom_present = brdctl & BRDDAT7; 1789 *enableSEC_high = (brdctl & BRDDAT6); 1790 *enableSEC_low = (brdctl & BRDDAT5); 1791 *enablePRI_high = (brdctl & BRDDAT4); 1792 *enablePRI_low = (brdctl & BRDDAT3); 1793 } 1794 1795 static void 1796 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1797 int *internal68_present, int *externalcable_present, 1798 int *eeprom_present) 1799 { 1800 uint8_t brdctl; 1801 1802 /* 1803 * First read the status of our cables. 1804 * Set the rom bank to 0 since the 1805 * bank setting serves as a multiplexor 1806 * for the cable detection logic. 1807 * BRDDAT5 controls the bank switch. 1808 */ 1809 write_brdctl(ahc, 0); 1810 1811 /* 1812 * Now read the state of the internal 1813 * connectors. BRDDAT6 is INT50 and 1814 * BRDDAT7 is INT68. 1815 */ 1816 brdctl = read_brdctl(ahc); 1817 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1818 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1819 1820 /* 1821 * Set the rom bank to 1 and determine 1822 * the other signals. 1823 */ 1824 write_brdctl(ahc, BRDDAT5); 1825 1826 /* 1827 * Now read the state of the external 1828 * connectors. BRDDAT6 is EXT68 and 1829 * BRDDAT7 is EPROMPS. 1830 */ 1831 brdctl = read_brdctl(ahc); 1832 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1833 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1834 } 1835 1836 static void 1837 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1838 int *externalcable_present, int *eeprom_present) 1839 { 1840 uint8_t brdctl; 1841 uint8_t spiocap; 1842 1843 spiocap = ahc_inb(ahc, SPIOCAP); 1844 spiocap &= ~SOFTCMDEN; 1845 spiocap |= EXT_BRDCTL; 1846 ahc_outb(ahc, SPIOCAP, spiocap); 1847 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1848 ahc_outb(ahc, BRDCTL, 0); 1849 brdctl = ahc_inb(ahc, BRDCTL); 1850 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1851 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1852 1853 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1854 } 1855 1856 int 1857 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1858 { 1859 int wait; 1860 1861 if ((ahc->features & AHC_SPIOCAP) != 0 1862 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1863 return (0); 1864 1865 /* 1866 * Request access of the memory port. When access is 1867 * granted, SEERDY will go high. We use a 1 second 1868 * timeout which should be near 1 second more than 1869 * is needed. Reason: after the chip reset, there 1870 * should be no contention. 1871 */ 1872 SEEPROM_OUTB(sd, sd->sd_MS); 1873 wait = 1000; /* 1 second timeout in msec */ 1874 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1875 ahc_delay(1000); /* delay 1 msec */ 1876 } 1877 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1878 SEEPROM_OUTB(sd, 0); 1879 return (0); 1880 } 1881 return(1); 1882 } 1883 1884 void 1885 ahc_release_seeprom(struct seeprom_descriptor *sd) 1886 { 1887 /* Release access to the memory port and the serial EEPROM. */ 1888 SEEPROM_OUTB(sd, 0); 1889 } 1890 1891 static void 1892 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1893 { 1894 uint8_t brdctl; 1895 1896 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1897 brdctl = BRDSTB; 1898 if (ahc->channel == 'B') 1899 brdctl |= BRDCS; 1900 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1901 brdctl = 0; 1902 } else { 1903 brdctl = BRDSTB|BRDCS; 1904 } 1905 ahc_outb(ahc, BRDCTL, brdctl); 1906 ahc_flush_device_writes(ahc); 1907 brdctl |= value; 1908 ahc_outb(ahc, BRDCTL, brdctl); 1909 ahc_flush_device_writes(ahc); 1910 if ((ahc->features & AHC_ULTRA2) != 0) 1911 brdctl |= BRDSTB_ULTRA2; 1912 else 1913 brdctl &= ~BRDSTB; 1914 ahc_outb(ahc, BRDCTL, brdctl); 1915 ahc_flush_device_writes(ahc); 1916 if ((ahc->features & AHC_ULTRA2) != 0) 1917 brdctl = 0; 1918 else 1919 brdctl &= ~BRDCS; 1920 ahc_outb(ahc, BRDCTL, brdctl); 1921 } 1922 1923 static uint8_t 1924 read_brdctl(ahc) 1925 struct ahc_softc *ahc; 1926 { 1927 uint8_t brdctl; 1928 uint8_t value; 1929 1930 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1931 brdctl = BRDRW; 1932 if (ahc->channel == 'B') 1933 brdctl |= BRDCS; 1934 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1935 brdctl = BRDRW_ULTRA2; 1936 } else { 1937 brdctl = BRDRW|BRDCS; 1938 } 1939 ahc_outb(ahc, BRDCTL, brdctl); 1940 ahc_flush_device_writes(ahc); 1941 value = ahc_inb(ahc, BRDCTL); 1942 ahc_outb(ahc, BRDCTL, 0); 1943 return (value); 1944 } 1945 1946 void 1947 ahc_pci_intr(struct ahc_softc *ahc) 1948 { 1949 u_int error; 1950 u_int status1; 1951 1952 error = ahc_inb(ahc, ERROR); 1953 if ((error & PCIERRSTAT) == 0) 1954 return; 1955 1956 status1 = ahc_pci_read_config(ahc->dev_softc, 1957 PCIR_STATUS + 1, /*bytes*/1); 1958 1959 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1960 ahc_name(ahc), 1961 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1962 1963 if (status1 & DPE) { 1964 printf("%s: Data Parity Error Detected during address " 1965 "or write data phase\n", ahc_name(ahc)); 1966 } 1967 if (status1 & SSE) { 1968 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1969 } 1970 if (status1 & RMA) { 1971 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1972 } 1973 if (status1 & RTA) { 1974 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1975 } 1976 if (status1 & STA) { 1977 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1978 } 1979 if (status1 & DPR) { 1980 printf("%s: Data Parity Error has been reported via PERR#\n", 1981 ahc_name(ahc)); 1982 } 1983 1984 /* Clear latched errors. */ 1985 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1986 status1, /*bytes*/1); 1987 1988 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1989 printf("%s: Latched PCIERR interrupt with " 1990 "no status bits set\n", ahc_name(ahc)); 1991 } else { 1992 ahc_outb(ahc, CLRINT, CLRPARERR); 1993 } 1994 1995 ahc_unpause(ahc); 1996 } 1997 1998 static int 1999 ahc_aic785X_setup(struct ahc_softc *ahc) 2000 { 2001 ahc_dev_softc_t pci; 2002 uint8_t rev; 2003 2004 pci = ahc->dev_softc; 2005 ahc->channel = 'A'; 2006 ahc->chip = AHC_AIC7850; 2007 ahc->features = AHC_AIC7850_FE; 2008 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2009 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2010 if (rev >= 1) 2011 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2012 return (0); 2013 } 2014 2015 static int 2016 ahc_aic7860_setup(struct ahc_softc *ahc) 2017 { 2018 ahc_dev_softc_t pci; 2019 uint8_t rev; 2020 2021 pci = ahc->dev_softc; 2022 ahc->channel = 'A'; 2023 ahc->chip = AHC_AIC7860; 2024 ahc->features = AHC_AIC7860_FE; 2025 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2026 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2027 if (rev >= 1) 2028 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2029 return (0); 2030 } 2031 2032 static int 2033 ahc_apa1480_setup(struct ahc_softc *ahc) 2034 { 2035 int error; 2036 2037 error = ahc_aic7860_setup(ahc); 2038 if (error != 0) 2039 return (error); 2040 ahc->features |= AHC_REMOVABLE; 2041 return (0); 2042 } 2043 2044 static int 2045 ahc_aic7870_setup(struct ahc_softc *ahc) 2046 { 2047 2048 ahc->channel = 'A'; 2049 ahc->chip = AHC_AIC7870; 2050 ahc->features = AHC_AIC7870_FE; 2051 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2052 return (0); 2053 } 2054 2055 static int 2056 ahc_aha394X_setup(struct ahc_softc *ahc) 2057 { 2058 int error; 2059 2060 error = ahc_aic7870_setup(ahc); 2061 if (error == 0) 2062 error = ahc_aha394XX_setup(ahc); 2063 return (error); 2064 } 2065 2066 static int 2067 ahc_aha398X_setup(struct ahc_softc *ahc) 2068 { 2069 int error; 2070 2071 error = ahc_aic7870_setup(ahc); 2072 if (error == 0) 2073 error = ahc_aha398XX_setup(ahc); 2074 return (error); 2075 } 2076 2077 static int 2078 ahc_aha494X_setup(struct ahc_softc *ahc) 2079 { 2080 int error; 2081 2082 error = ahc_aic7870_setup(ahc); 2083 if (error == 0) 2084 error = ahc_aha494XX_setup(ahc); 2085 return (error); 2086 } 2087 2088 static int 2089 ahc_aic7880_setup(struct ahc_softc *ahc) 2090 { 2091 ahc_dev_softc_t pci; 2092 uint8_t rev; 2093 2094 pci = ahc->dev_softc; 2095 ahc->channel = 'A'; 2096 ahc->chip = AHC_AIC7880; 2097 ahc->features = AHC_AIC7880_FE; 2098 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2099 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2100 if (rev >= 1) { 2101 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2102 } else { 2103 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2104 } 2105 return (0); 2106 } 2107 2108 static int 2109 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2110 { 2111 2112 ahc->flags |= AHC_INT50_SPEEDFLEX; 2113 return (ahc_aic7880_setup(ahc)); 2114 } 2115 2116 static int 2117 ahc_aha394XU_setup(struct ahc_softc *ahc) 2118 { 2119 int error; 2120 2121 error = ahc_aic7880_setup(ahc); 2122 if (error == 0) 2123 error = ahc_aha394XX_setup(ahc); 2124 return (error); 2125 } 2126 2127 static int 2128 ahc_aha398XU_setup(struct ahc_softc *ahc) 2129 { 2130 int error; 2131 2132 error = ahc_aic7880_setup(ahc); 2133 if (error == 0) 2134 error = ahc_aha398XX_setup(ahc); 2135 return (error); 2136 } 2137 2138 static int 2139 ahc_aic7890_setup(struct ahc_softc *ahc) 2140 { 2141 ahc_dev_softc_t pci; 2142 uint8_t rev; 2143 2144 pci = ahc->dev_softc; 2145 ahc->channel = 'A'; 2146 ahc->chip = AHC_AIC7890; 2147 ahc->features = AHC_AIC7890_FE; 2148 ahc->flags |= AHC_NEWEEPROM_FMT; 2149 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2150 if (rev == 0) 2151 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2152 return (0); 2153 } 2154 2155 static int 2156 ahc_aic7892_setup(struct ahc_softc *ahc) 2157 { 2158 2159 ahc->channel = 'A'; 2160 ahc->chip = AHC_AIC7892; 2161 ahc->features = AHC_AIC7892_FE; 2162 ahc->flags |= AHC_NEWEEPROM_FMT; 2163 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2164 return (0); 2165 } 2166 2167 static int 2168 ahc_aic7895_setup(struct ahc_softc *ahc) 2169 { 2170 ahc_dev_softc_t pci; 2171 uint8_t rev; 2172 2173 pci = ahc->dev_softc; 2174 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2175 /* 2176 * The 'C' revision of the aic7895 has a few additional features. 2177 */ 2178 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2179 if (rev >= 4) { 2180 ahc->chip = AHC_AIC7895C; 2181 ahc->features = AHC_AIC7895C_FE; 2182 } else { 2183 u_int command; 2184 2185 ahc->chip = AHC_AIC7895; 2186 ahc->features = AHC_AIC7895_FE; 2187 2188 /* 2189 * The BIOS disables the use of MWI transactions 2190 * since it does not have the MWI bug work around 2191 * we have. Disabling MWI reduces performance, so 2192 * turn it on again. 2193 */ 2194 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2195 command |= PCIM_CMD_MWRICEN; 2196 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2197 ahc->bugs |= AHC_PCI_MWI_BUG; 2198 } 2199 /* 2200 * XXX Does CACHETHEN really not work??? What about PCI retry? 2201 * on C level chips. Need to test, but for now, play it safe. 2202 */ 2203 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2204 | AHC_CACHETHEN_BUG; 2205 2206 #if 0 2207 uint32_t devconfig; 2208 2209 /* 2210 * Cachesize must also be zero due to stray DAC 2211 * problem when sitting behind some bridges. 2212 */ 2213 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2214 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2215 devconfig |= MRDCEN; 2216 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2217 #endif 2218 ahc->flags |= AHC_NEWEEPROM_FMT; 2219 return (0); 2220 } 2221 2222 static int 2223 ahc_aic7896_setup(struct ahc_softc *ahc) 2224 { 2225 ahc_dev_softc_t pci; 2226 2227 pci = ahc->dev_softc; 2228 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2229 ahc->chip = AHC_AIC7896; 2230 ahc->features = AHC_AIC7896_FE; 2231 ahc->flags |= AHC_NEWEEPROM_FMT; 2232 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2233 return (0); 2234 } 2235 2236 static int 2237 ahc_aic7899_setup(struct ahc_softc *ahc) 2238 { 2239 ahc_dev_softc_t pci; 2240 2241 pci = ahc->dev_softc; 2242 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2243 ahc->chip = AHC_AIC7899; 2244 ahc->features = AHC_AIC7899_FE; 2245 ahc->flags |= AHC_NEWEEPROM_FMT; 2246 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2247 return (0); 2248 } 2249 2250 static int 2251 ahc_aha29160C_setup(struct ahc_softc *ahc) 2252 { 2253 int error; 2254 2255 error = ahc_aic7899_setup(ahc); 2256 if (error != 0) 2257 return (error); 2258 ahc->features |= AHC_REMOVABLE; 2259 return (0); 2260 } 2261 2262 static int 2263 ahc_raid_setup(struct ahc_softc *ahc) 2264 { 2265 printf("RAID functionality unsupported\n"); 2266 return (ENXIO); 2267 } 2268 2269 static int 2270 ahc_aha394XX_setup(struct ahc_softc *ahc) 2271 { 2272 ahc_dev_softc_t pci; 2273 2274 pci = ahc->dev_softc; 2275 switch (ahc_get_pci_slot(pci)) { 2276 case AHC_394X_SLOT_CHANNEL_A: 2277 ahc->channel = 'A'; 2278 break; 2279 case AHC_394X_SLOT_CHANNEL_B: 2280 ahc->channel = 'B'; 2281 break; 2282 default: 2283 printf("adapter at unexpected slot %d\n" 2284 "unable to map to a channel\n", 2285 ahc_get_pci_slot(pci)); 2286 ahc->channel = 'A'; 2287 } 2288 return (0); 2289 } 2290 2291 static int 2292 ahc_aha398XX_setup(struct ahc_softc *ahc) 2293 { 2294 ahc_dev_softc_t pci; 2295 2296 pci = ahc->dev_softc; 2297 switch (ahc_get_pci_slot(pci)) { 2298 case AHC_398X_SLOT_CHANNEL_A: 2299 ahc->channel = 'A'; 2300 break; 2301 case AHC_398X_SLOT_CHANNEL_B: 2302 ahc->channel = 'B'; 2303 break; 2304 case AHC_398X_SLOT_CHANNEL_C: 2305 ahc->channel = 'C'; 2306 break; 2307 default: 2308 printf("adapter at unexpected slot %d\n" 2309 "unable to map to a channel\n", 2310 ahc_get_pci_slot(pci)); 2311 ahc->channel = 'A'; 2312 break; 2313 } 2314 ahc->flags |= AHC_LARGE_SEEPROM; 2315 return (0); 2316 } 2317 2318 static int 2319 ahc_aha494XX_setup(struct ahc_softc *ahc) 2320 { 2321 ahc_dev_softc_t pci; 2322 2323 pci = ahc->dev_softc; 2324 switch (ahc_get_pci_slot(pci)) { 2325 case AHC_494X_SLOT_CHANNEL_A: 2326 ahc->channel = 'A'; 2327 break; 2328 case AHC_494X_SLOT_CHANNEL_B: 2329 ahc->channel = 'B'; 2330 break; 2331 case AHC_494X_SLOT_CHANNEL_C: 2332 ahc->channel = 'C'; 2333 break; 2334 case AHC_494X_SLOT_CHANNEL_D: 2335 ahc->channel = 'D'; 2336 break; 2337 default: 2338 printf("adapter at unexpected slot %d\n" 2339 "unable to map to a channel\n", 2340 ahc_get_pci_slot(pci)); 2341 ahc->channel = 'A'; 2342 } 2343 ahc->flags |= AHC_LARGE_SEEPROM; 2344 return (0); 2345 } 2346