1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#66 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 59 60 static __inline uint64_t 61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 77 #define ID_9005_SISL_ID 0x0005900500000000ull 78 #define ID_AIC7850 0x5078900400000000ull 79 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull 80 #define ID_AIC7855 0x5578900400000000ull 81 #define ID_AIC7859 0x3860900400000000ull 82 #define ID_AHA_2930CU 0x3860900438699004ull 83 #define ID_AIC7860 0x6078900400000000ull 84 #define ID_AIC7860C 0x6078900478609004ull 85 #define ID_AHA_1480A 0x6075900400000000ull 86 #define ID_AHA_2940AU_0 0x6178900400000000ull 87 #define ID_AHA_2940AU_1 0x6178900478619004ull 88 #define ID_AHA_2940AU_CN 0x2178900478219004ull 89 #define ID_AHA_2930C_VAR 0x6038900438689004ull 90 91 #define ID_AIC7870 0x7078900400000000ull 92 #define ID_AHA_2940 0x7178900400000000ull 93 #define ID_AHA_3940 0x7278900400000000ull 94 #define ID_AHA_398X 0x7378900400000000ull 95 #define ID_AHA_2944 0x7478900400000000ull 96 #define ID_AHA_3944 0x7578900400000000ull 97 #define ID_AHA_4944 0x7678900400000000ull 98 99 #define ID_AIC7880 0x8078900400000000ull 100 #define ID_AIC7880_B 0x8078900478809004ull 101 #define ID_AHA_2940U 0x8178900400000000ull 102 #define ID_AHA_3940U 0x8278900400000000ull 103 #define ID_AHA_2944U 0x8478900400000000ull 104 #define ID_AHA_3944U 0x8578900400000000ull 105 #define ID_AHA_398XU 0x8378900400000000ull 106 #define ID_AHA_4944U 0x8678900400000000ull 107 #define ID_AHA_2940UB 0x8178900478819004ull 108 #define ID_AHA_2930U 0x8878900478889004ull 109 #define ID_AHA_2940U_PRO 0x8778900478879004ull 110 #define ID_AHA_2940U_CN 0x0078900478009004ull 111 112 #define ID_AIC7895 0x7895900478959004ull 113 #define ID_AIC7895_ARO 0x7890900478939004ull 114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 116 #define ID_AHA_3940AU 0x7895900478929004ull 117 #define ID_AHA_3944AU 0x7895900478949004ull 118 119 #define ID_AIC7890 0x001F9005000F9005ull 120 #define ID_AIC7890_ARO 0x00139005000F9005ull 121 #define ID_AAA_131U2 0x0013900500039005ull 122 #define ID_AHA_2930U2 0x0011900501819005ull 123 #define ID_AHA_2940U2B 0x00109005A1009005ull 124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 125 #define ID_AHA_2940U2 0x00109005A1809005ull 126 #define ID_AHA_2950U2B 0x00109005E1009005ull 127 128 #define ID_AIC7892 0x008F9005FFFF9005ull 129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 130 #define ID_AHA_29160 0x00809005E2A09005ull 131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132 #define ID_AHA_29160N 0x0080900562A09005ull 133 #define ID_AHA_29160C 0x0080900562209005ull 134 #define ID_AHA_29160B 0x00809005E2209005ull 135 #define ID_AHA_19160B 0x0081900562A19005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20C_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 /* aic7895 based controllers */ 474 { 475 ID_AHA_2940U_DUAL, 476 ID_ALL_MASK, 477 "Adaptec 2940/DUAL Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AHA_3940AU, 482 ID_ALL_MASK, 483 "Adaptec 3940A Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3944AU, 488 ID_ALL_MASK, 489 "Adaptec 3944A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_ARO, 494 ID_AIC7895_ARO_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 496 ahc_aic7895_setup 497 }, 498 /* aic7896/97 based controllers */ 499 { 500 ID_AHA_3950U2B_0, 501 ID_ALL_MASK, 502 "Adaptec 3950B Ultra2 SCSI adapter", 503 ahc_aic7896_setup 504 }, 505 { 506 ID_AHA_3950U2B_1, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2D_0, 513 ID_ALL_MASK, 514 "Adaptec 3950D Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_1, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AIC7896_ARO, 525 ID_ALL_MASK, 526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 527 ahc_aic7896_setup 528 }, 529 /* aic7899 based controllers */ 530 { 531 ID_AHA_3960D, 532 ID_ALL_MASK, 533 "Adaptec 3960D Ultra160 SCSI adapter", 534 ahc_aic7899_setup 535 }, 536 { 537 ID_AHA_3960D_CPQ, 538 ID_ALL_MASK, 539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AIC7899_ARO, 544 ID_ALL_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 546 ahc_aic7899_setup 547 }, 548 /* Generic chip probes for devices we don't know 'exactly' */ 549 { 550 ID_AIC7850 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7850 SCSI adapter", 553 ahc_aic785X_setup 554 }, 555 { 556 ID_AIC7855 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7855 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7859 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7859 SCSI adapter", 565 ahc_aic7860_setup 566 }, 567 { 568 ID_AIC7860 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7860 Ultra SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7870 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7870 SCSI adapter", 577 ahc_aic7870_setup 578 }, 579 { 580 ID_AIC7880 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7880 Ultra SCSI adapter", 583 ahc_aic7880_setup 584 }, 585 { 586 ID_AIC7890 & ID_9005_GENERIC_MASK, 587 ID_9005_GENERIC_MASK, 588 "Adaptec aic7890/91 Ultra2 SCSI adapter", 589 ahc_aic7890_setup 590 }, 591 { 592 ID_AIC7892 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7892 Ultra160 SCSI adapter", 595 ahc_aic7892_setup 596 }, 597 { 598 ID_AIC7895 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7895 Ultra SCSI adapter", 601 ahc_aic7895_setup 602 }, 603 { 604 ID_AIC7896 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7896/97 Ultra2 SCSI adapter", 607 ahc_aic7896_setup 608 }, 609 { 610 ID_AIC7899 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7899 Ultra160 SCSI adapter", 613 ahc_aic7899_setup 614 }, 615 { 616 ID_AIC7810 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7810 RAID memory controller", 619 ahc_raid_setup 620 }, 621 { 622 ID_AIC7815 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7815 RAID memory controller", 625 ahc_raid_setup 626 } 627 }; 628 629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 630 631 #define AHC_394X_SLOT_CHANNEL_A 4 632 #define AHC_394X_SLOT_CHANNEL_B 5 633 634 #define AHC_398X_SLOT_CHANNEL_A 4 635 #define AHC_398X_SLOT_CHANNEL_B 8 636 #define AHC_398X_SLOT_CHANNEL_C 12 637 638 #define AHC_494X_SLOT_CHANNEL_A 4 639 #define AHC_494X_SLOT_CHANNEL_B 5 640 #define AHC_494X_SLOT_CHANNEL_C 6 641 #define AHC_494X_SLOT_CHANNEL_D 7 642 643 #define DEVCONFIG 0x40 644 #define PCIERRGENDIS 0x80000000ul 645 #define SCBSIZE32 0x00010000ul /* aic789X only */ 646 #define REXTVALID 0x00001000ul /* ultra cards only */ 647 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 648 #define RAMPSM 0x00000200ul /* aic7870+ only */ 649 #define VOLSENSE 0x00000100ul 650 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 651 #define SCBRAMSEL 0x00000080ul 652 #define MRDCEN 0x00000040ul 653 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 654 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 655 #define BERREN 0x00000008ul 656 #define DACEN 0x00000004ul 657 #define STPWLEVEL 0x00000002ul 658 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 659 660 #define CSIZE_LATTIME 0x0c 661 #define CACHESIZE 0x0000003ful /* only 5 bits */ 662 #define LATTIME 0x0000ff00ul 663 664 /* PCI STATUS definitions */ 665 #define DPE 0x80 666 #define SSE 0x40 667 #define RMA 0x20 668 #define RTA 0x10 669 #define STA 0x08 670 #define DPR 0x01 671 672 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 673 uint16_t subvendor, uint16_t subdevice); 674 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 675 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 676 int pcheck, int fast, int large); 677 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 678 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 679 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 680 struct seeprom_config *sc); 681 static void configure_termination(struct ahc_softc *ahc, 682 struct seeprom_descriptor *sd, 683 u_int adapter_control, 684 u_int *sxfrctl1); 685 686 static void ahc_new_term_detect(struct ahc_softc *ahc, 687 int *enableSEC_low, 688 int *enableSEC_high, 689 int *enablePRI_low, 690 int *enablePRI_high, 691 int *eeprom_present); 692 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 693 int *internal68_present, 694 int *externalcable_present, 695 int *eeprom_present); 696 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 697 int *externalcable_present, 698 int *eeprom_present); 699 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 700 static uint8_t read_brdctl(struct ahc_softc *ahc); 701 static void ahc_pci_intr(struct ahc_softc *ahc); 702 static int ahc_pci_chip_init(struct ahc_softc *ahc); 703 static int ahc_pci_suspend(struct ahc_softc *ahc); 704 static int ahc_pci_resume(struct ahc_softc *ahc); 705 706 static int 707 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 708 uint16_t subdevice, uint16_t subvendor) 709 { 710 int result; 711 712 /* Default to invalid. */ 713 result = 0; 714 if (vendor == 0x9005 715 && subvendor == 0x9005 716 && subdevice != device 717 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 718 719 switch (SUBID_9005_TYPE(subdevice)) { 720 case SUBID_9005_TYPE_MB: 721 break; 722 case SUBID_9005_TYPE_CARD: 723 case SUBID_9005_TYPE_LCCARD: 724 /* 725 * Currently only trust Adaptec cards to 726 * get the sub device info correct. 727 */ 728 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 729 result = 1; 730 break; 731 case SUBID_9005_TYPE_RAID: 732 break; 733 default: 734 break; 735 } 736 } 737 return (result); 738 } 739 740 struct ahc_pci_identity * 741 ahc_find_pci_device(ahc_dev_softc_t pci) 742 { 743 uint64_t full_id; 744 uint16_t device; 745 uint16_t vendor; 746 uint16_t subdevice; 747 uint16_t subvendor; 748 struct ahc_pci_identity *entry; 749 u_int i; 750 751 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 752 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 753 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 754 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 755 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 756 757 /* 758 * If the second function is not hooked up, ignore it. 759 * Unfortunately, not all MB vendors implement the 760 * subdevice ID as per the Adaptec spec, so do our best 761 * to sanity check it prior to accepting the subdevice 762 * ID as valid. 763 */ 764 if (ahc_get_pci_function(pci) > 0 765 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 766 && SUBID_9005_MFUNCENB(subdevice) == 0) 767 return (NULL); 768 769 for (i = 0; i < ahc_num_pci_devs; i++) { 770 entry = &ahc_pci_ident_table[i]; 771 if (entry->full_id == (full_id & entry->id_mask)) { 772 /* Honor exclusion entries. */ 773 if (entry->name == NULL) 774 return (NULL); 775 return (entry); 776 } 777 } 778 return (NULL); 779 } 780 781 int 782 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 783 { 784 u_long l; 785 u_int command; 786 u_int our_id; 787 u_int sxfrctl1; 788 u_int scsiseq; 789 u_int dscommand0; 790 uint32_t devconfig; 791 int error; 792 uint8_t sblkctl; 793 794 our_id = 0; 795 error = entry->setup(ahc); 796 if (error != 0) 797 return (error); 798 ahc->chip |= AHC_PCI; 799 ahc->description = entry->name; 800 801 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 802 803 error = ahc_pci_map_registers(ahc); 804 if (error != 0) 805 return (error); 806 807 /* 808 * Before we continue probing the card, ensure that 809 * its interrupts are *disabled*. We don't want 810 * a misstep to hang the machine in an interrupt 811 * storm. 812 */ 813 ahc_intr_enable(ahc, FALSE); 814 815 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 816 817 /* 818 * If we need to support high memory, enable dual 819 * address cycles. This bit must be set to enable 820 * high address bit generation even if we are on a 821 * 64bit bus (PCI64BIT set in devconfig). 822 */ 823 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 824 825 if (bootverbose) 826 printf("%s: Enabling 39Bit Addressing\n", 827 ahc_name(ahc)); 828 devconfig |= DACEN; 829 } 830 831 /* Ensure that pci error generation, a test feature, is disabled. */ 832 devconfig |= PCIERRGENDIS; 833 834 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 835 836 /* Ensure busmastering is enabled */ 837 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 838 command |= PCIM_CMD_BUSMASTEREN; 839 840 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 841 842 /* On all PCI adapters, we allow SCB paging */ 843 ahc->flags |= AHC_PAGESCBS; 844 845 error = ahc_softc_init(ahc); 846 if (error != 0) 847 return (error); 848 849 /* 850 * Disable PCI parity error checking. Users typically 851 * do this to work around broken PCI chipsets that get 852 * the parity timing wrong and thus generate lots of spurious 853 * errors. The chip only allows us to disable *all* parity 854 * error reporting when doing this, so CIO bus, scb ram, and 855 * scratch ram parity errors will be ignored too. 856 */ 857 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 858 ahc->seqctl |= FAILDIS; 859 860 ahc->bus_intr = ahc_pci_intr; 861 ahc->bus_chip_init = ahc_pci_chip_init; 862 ahc->bus_suspend = ahc_pci_suspend; 863 ahc->bus_resume = ahc_pci_resume; 864 865 /* Remeber how the card was setup in case there is no SEEPROM */ 866 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 867 ahc_pause(ahc); 868 if ((ahc->features & AHC_ULTRA2) != 0) 869 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 870 else 871 our_id = ahc_inb(ahc, SCSIID) & OID; 872 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 873 scsiseq = ahc_inb(ahc, SCSISEQ); 874 } else { 875 sxfrctl1 = STPWEN; 876 our_id = 7; 877 scsiseq = 0; 878 } 879 880 error = ahc_reset(ahc); 881 if (error != 0) 882 return (ENXIO); 883 884 if ((ahc->features & AHC_DT) != 0) { 885 u_int sfunct; 886 887 /* Perform ALT-Mode Setup */ 888 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 889 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 890 ahc_outb(ahc, OPTIONMODE, 891 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 892 ahc_outb(ahc, SFUNCT, sfunct); 893 894 /* Normal mode setup */ 895 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 896 |TARGCRCENDEN); 897 } 898 899 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 900 dscommand0 |= MPARCKEN|CACHETHEN; 901 if ((ahc->features & AHC_ULTRA2) != 0) { 902 903 /* 904 * DPARCKEN doesn't work correctly on 905 * some MBs so don't use it. 906 */ 907 dscommand0 &= ~DPARCKEN; 908 } 909 910 /* 911 * Handle chips that must have cache line 912 * streaming (dis/en)abled. 913 */ 914 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 915 dscommand0 |= CACHETHEN; 916 917 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 918 dscommand0 &= ~CACHETHEN; 919 920 ahc_outb(ahc, DSCOMMAND0, dscommand0); 921 922 ahc->pci_cachesize = 923 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 924 /*bytes*/1) & CACHESIZE; 925 ahc->pci_cachesize *= 4; 926 927 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 928 && ahc->pci_cachesize == 4) { 929 930 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 931 0, /*bytes*/1); 932 ahc->pci_cachesize = 0; 933 } 934 935 /* 936 * We cannot perform ULTRA speeds without the presense 937 * of the external precision resistor. 938 */ 939 if ((ahc->features & AHC_ULTRA) != 0) { 940 uint32_t devconfig; 941 942 devconfig = ahc_pci_read_config(ahc->dev_softc, 943 DEVCONFIG, /*bytes*/4); 944 if ((devconfig & REXTVALID) == 0) 945 ahc->features &= ~AHC_ULTRA; 946 } 947 948 /* See if we have a SEEPROM and perform auto-term */ 949 check_extport(ahc, &sxfrctl1); 950 951 /* 952 * Take the LED out of diagnostic mode 953 */ 954 sblkctl = ahc_inb(ahc, SBLKCTL); 955 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 956 957 if ((ahc->features & AHC_ULTRA2) != 0) { 958 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 959 } else { 960 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 961 } 962 963 if (ahc->flags & AHC_USEDEFAULTS) { 964 /* 965 * PCI Adapter default setup 966 * Should only be used if the adapter does not have 967 * a SEEPROM. 968 */ 969 /* See if someone else set us up already */ 970 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 971 && scsiseq != 0) { 972 printf("%s: Using left over BIOS settings\n", 973 ahc_name(ahc)); 974 ahc->flags &= ~AHC_USEDEFAULTS; 975 ahc->flags |= AHC_BIOS_ENABLED; 976 } else { 977 /* 978 * Assume only one connector and always turn 979 * on termination. 980 */ 981 our_id = 0x07; 982 sxfrctl1 = STPWEN; 983 } 984 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 985 986 ahc->our_id = our_id; 987 } 988 989 /* 990 * Take a look to see if we have external SRAM. 991 * We currently do not attempt to use SRAM that is 992 * shared among multiple controllers. 993 */ 994 ahc_probe_ext_scbram(ahc); 995 996 /* 997 * Record our termination setting for the 998 * generic initialization routine. 999 */ 1000 if ((sxfrctl1 & STPWEN) != 0) 1001 ahc->flags |= AHC_TERM_ENB_A; 1002 1003 /* 1004 * Save chip register configuration data for chip resets 1005 * that occur during runtime and resume events. 1006 */ 1007 ahc->bus_softc.pci_softc.devconfig = 1008 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1009 ahc->bus_softc.pci_softc.command = 1010 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 1011 ahc->bus_softc.pci_softc.csize_lattime = 1012 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 1013 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1014 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1015 if ((ahc->features & AHC_DT) != 0) { 1016 u_int sfunct; 1017 1018 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1019 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1020 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1021 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1022 ahc_outb(ahc, SFUNCT, sfunct); 1023 ahc->bus_softc.pci_softc.crccontrol1 = 1024 ahc_inb(ahc, CRCCONTROL1); 1025 } 1026 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1027 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1028 1029 if ((ahc->features & AHC_ULTRA2) != 0) 1030 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1031 1032 /* Core initialization */ 1033 error = ahc_init(ahc); 1034 if (error != 0) 1035 return (error); 1036 1037 /* 1038 * Allow interrupts now that we are completely setup. 1039 */ 1040 error = ahc_pci_map_int(ahc); 1041 if (error != 0) 1042 return (error); 1043 1044 ahc_list_lock(&l); 1045 /* 1046 * Link this softc in with all other ahc instances. 1047 */ 1048 ahc_softc_insert(ahc); 1049 ahc_list_unlock(&l); 1050 return (0); 1051 } 1052 1053 /* 1054 * Test for the presense of external sram in an 1055 * "unshared" configuration. 1056 */ 1057 static int 1058 ahc_ext_scbram_present(struct ahc_softc *ahc) 1059 { 1060 u_int chip; 1061 int ramps; 1062 int single_user; 1063 uint32_t devconfig; 1064 1065 chip = ahc->chip & AHC_CHIPID_MASK; 1066 devconfig = ahc_pci_read_config(ahc->dev_softc, 1067 DEVCONFIG, /*bytes*/4); 1068 single_user = (devconfig & MPORTMODE) != 0; 1069 1070 if ((ahc->features & AHC_ULTRA2) != 0) 1071 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1072 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1073 /* 1074 * External SCBRAM arbitration is flakey 1075 * on these chips. Unfortunately this means 1076 * we don't use the extra SCB ram space on the 1077 * 3940AUW. 1078 */ 1079 ramps = 0; 1080 else if (chip >= AHC_AIC7870) 1081 ramps = (devconfig & RAMPSM) != 0; 1082 else 1083 ramps = 0; 1084 1085 if (ramps && single_user) 1086 return (1); 1087 return (0); 1088 } 1089 1090 /* 1091 * Enable external scbram. 1092 */ 1093 static void 1094 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1095 int fast, int large) 1096 { 1097 uint32_t devconfig; 1098 1099 if (ahc->features & AHC_MULTI_FUNC) { 1100 /* 1101 * Set the SCB Base addr (highest address bit) 1102 * depending on which channel we are. 1103 */ 1104 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1105 } 1106 1107 ahc->flags &= ~AHC_LSCBS_ENABLED; 1108 if (large) 1109 ahc->flags |= AHC_LSCBS_ENABLED; 1110 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1111 if ((ahc->features & AHC_ULTRA2) != 0) { 1112 u_int dscommand0; 1113 1114 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1115 if (enable) 1116 dscommand0 &= ~INTSCBRAMSEL; 1117 else 1118 dscommand0 |= INTSCBRAMSEL; 1119 if (large) 1120 dscommand0 &= ~USCBSIZE32; 1121 else 1122 dscommand0 |= USCBSIZE32; 1123 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1124 } else { 1125 if (fast) 1126 devconfig &= ~EXTSCBTIME; 1127 else 1128 devconfig |= EXTSCBTIME; 1129 if (enable) 1130 devconfig &= ~SCBRAMSEL; 1131 else 1132 devconfig |= SCBRAMSEL; 1133 if (large) 1134 devconfig &= ~SCBSIZE32; 1135 else 1136 devconfig |= SCBSIZE32; 1137 } 1138 if (pcheck) 1139 devconfig |= EXTSCBPEN; 1140 else 1141 devconfig &= ~EXTSCBPEN; 1142 1143 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1144 } 1145 1146 /* 1147 * Take a look to see if we have external SRAM. 1148 * We currently do not attempt to use SRAM that is 1149 * shared among multiple controllers. 1150 */ 1151 static void 1152 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1153 { 1154 int num_scbs; 1155 int test_num_scbs; 1156 int enable; 1157 int pcheck; 1158 int fast; 1159 int large; 1160 1161 enable = FALSE; 1162 pcheck = FALSE; 1163 fast = FALSE; 1164 large = FALSE; 1165 num_scbs = 0; 1166 1167 if (ahc_ext_scbram_present(ahc) == 0) 1168 goto done; 1169 1170 /* 1171 * Probe for the best parameters to use. 1172 */ 1173 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1174 num_scbs = ahc_probe_scbs(ahc); 1175 if (num_scbs == 0) { 1176 /* The SRAM wasn't really present. */ 1177 goto done; 1178 } 1179 enable = TRUE; 1180 1181 /* 1182 * Clear any outstanding parity error 1183 * and ensure that parity error reporting 1184 * is enabled. 1185 */ 1186 ahc_outb(ahc, SEQCTL, 0); 1187 ahc_outb(ahc, CLRINT, CLRPARERR); 1188 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1189 1190 /* Now see if we can do parity */ 1191 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1192 num_scbs = ahc_probe_scbs(ahc); 1193 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1194 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1195 pcheck = TRUE; 1196 1197 /* Clear any resulting parity error */ 1198 ahc_outb(ahc, CLRINT, CLRPARERR); 1199 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1200 1201 /* Now see if we can do fast timing */ 1202 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1203 test_num_scbs = ahc_probe_scbs(ahc); 1204 if (test_num_scbs == num_scbs 1205 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1206 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1207 fast = TRUE; 1208 1209 /* 1210 * See if we can use large SCBs and still maintain 1211 * the same overall count of SCBs. 1212 */ 1213 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1214 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1215 test_num_scbs = ahc_probe_scbs(ahc); 1216 if (test_num_scbs >= num_scbs) { 1217 large = TRUE; 1218 num_scbs = test_num_scbs; 1219 if (num_scbs >= 64) { 1220 /* 1221 * We have enough space to move the 1222 * "busy targets table" into SCB space 1223 * and make it qualify all the way to the 1224 * lun level. 1225 */ 1226 ahc->flags |= AHC_SCB_BTT; 1227 } 1228 } 1229 } 1230 done: 1231 /* 1232 * Disable parity error reporting until we 1233 * can load instruction ram. 1234 */ 1235 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1236 /* Clear any latched parity error */ 1237 ahc_outb(ahc, CLRINT, CLRPARERR); 1238 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1239 if (bootverbose && enable) { 1240 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1241 ahc_name(ahc), fast ? "fast" : "slow", 1242 pcheck ? ", parity checking enabled" : "", 1243 large ? 64 : 32); 1244 } 1245 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1246 } 1247 1248 /* 1249 * Perform some simple tests that should catch situations where 1250 * our registers are invalidly mapped. 1251 */ 1252 int 1253 ahc_pci_test_register_access(struct ahc_softc *ahc) 1254 { 1255 int error; 1256 u_int status1; 1257 uint32_t cmd; 1258 uint8_t hcntrl; 1259 1260 error = EIO; 1261 1262 /* 1263 * Enable PCI error interrupt status, but suppress NMIs 1264 * generated by SERR raised due to target aborts. 1265 */ 1266 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1267 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1268 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1269 1270 /* 1271 * First a simple test to see if any 1272 * registers can be read. Reading 1273 * HCNTRL has no side effects and has 1274 * at least one bit that is guaranteed to 1275 * be zero so it is a good register to 1276 * use for this test. 1277 */ 1278 hcntrl = ahc_inb(ahc, HCNTRL); 1279 if (hcntrl == 0xFF) 1280 goto fail; 1281 1282 /* 1283 * Next create a situation where write combining 1284 * or read prefetching could be initiated by the 1285 * CPU or host bridge. Our device does not support 1286 * either, so look for data corruption and/or flagged 1287 * PCI errors. 1288 */ 1289 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1290 while (ahc_is_paused(ahc) == 0) 1291 ; 1292 ahc_outb(ahc, SEQCTL, PERRORDIS); 1293 ahc_outb(ahc, SCBPTR, 0); 1294 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1295 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1296 goto fail; 1297 1298 status1 = ahc_pci_read_config(ahc->dev_softc, 1299 PCIR_STATUS + 1, /*bytes*/1); 1300 if ((status1 & STA) != 0) 1301 goto fail; 1302 1303 error = 0; 1304 1305 fail: 1306 /* Silently clear any latched errors. */ 1307 status1 = ahc_pci_read_config(ahc->dev_softc, 1308 PCIR_STATUS + 1, /*bytes*/1); 1309 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1310 status1, /*bytes*/1); 1311 ahc_outb(ahc, CLRINT, CLRPARERR); 1312 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1313 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1314 return (error); 1315 } 1316 1317 /* 1318 * Check the external port logic for a serial eeprom 1319 * and termination/cable detection contrls. 1320 */ 1321 static void 1322 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1323 { 1324 struct seeprom_descriptor sd; 1325 struct seeprom_config *sc; 1326 int have_seeprom; 1327 int have_autoterm; 1328 1329 sd.sd_ahc = ahc; 1330 sd.sd_control_offset = SEECTL; 1331 sd.sd_status_offset = SEECTL; 1332 sd.sd_dataout_offset = SEECTL; 1333 sc = ahc->seep_config; 1334 1335 /* 1336 * For some multi-channel devices, the c46 is simply too 1337 * small to work. For the other controller types, we can 1338 * get our information from either SEEPROM type. Set the 1339 * type to start our probe with accordingly. 1340 */ 1341 if (ahc->flags & AHC_LARGE_SEEPROM) 1342 sd.sd_chip = C56_66; 1343 else 1344 sd.sd_chip = C46; 1345 1346 sd.sd_MS = SEEMS; 1347 sd.sd_RDY = SEERDY; 1348 sd.sd_CS = SEECS; 1349 sd.sd_CK = SEECK; 1350 sd.sd_DO = SEEDO; 1351 sd.sd_DI = SEEDI; 1352 1353 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1354 if (have_seeprom) { 1355 1356 if (bootverbose) 1357 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1358 1359 for (;;) { 1360 u_int start_addr; 1361 1362 start_addr = 32 * (ahc->channel - 'A'); 1363 1364 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1365 start_addr, 1366 sizeof(*sc)/2); 1367 1368 if (have_seeprom) 1369 have_seeprom = ahc_verify_cksum(sc); 1370 1371 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1372 if (bootverbose) { 1373 if (have_seeprom == 0) 1374 printf ("checksum error\n"); 1375 else 1376 printf ("done.\n"); 1377 } 1378 break; 1379 } 1380 sd.sd_chip = C56_66; 1381 } 1382 ahc_release_seeprom(&sd); 1383 } 1384 1385 if (!have_seeprom) { 1386 /* 1387 * Pull scratch ram settings and treat them as 1388 * if they are the contents of an seeprom if 1389 * the 'ADPT' signature is found in SCB2. 1390 * We manually compose the data as 16bit values 1391 * to avoid endian issues. 1392 */ 1393 ahc_outb(ahc, SCBPTR, 2); 1394 if (ahc_inb(ahc, SCB_BASE) == 'A' 1395 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1396 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1397 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1398 uint16_t *sc_data; 1399 int i; 1400 1401 sc_data = (uint16_t *)sc; 1402 for (i = 0; i < 32; i++, sc_data++) { 1403 int j; 1404 1405 j = i * 2; 1406 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1407 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1408 } 1409 have_seeprom = ahc_verify_cksum(sc); 1410 if (have_seeprom) 1411 ahc->flags |= AHC_SCB_CONFIG_USED; 1412 } 1413 /* 1414 * Clear any SCB parity errors in case this data and 1415 * its associated parity was not initialized by the BIOS 1416 */ 1417 ahc_outb(ahc, CLRINT, CLRPARERR); 1418 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1419 } 1420 1421 if (!have_seeprom) { 1422 if (bootverbose) 1423 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1424 ahc->flags |= AHC_USEDEFAULTS; 1425 free(ahc->seep_config, M_DEVBUF); 1426 ahc->seep_config = NULL; 1427 sc = NULL; 1428 } else { 1429 ahc_parse_pci_eeprom(ahc, sc); 1430 } 1431 1432 /* 1433 * Cards that have the external logic necessary to talk to 1434 * a SEEPROM, are almost certain to have the remaining logic 1435 * necessary for auto-termination control. This assumption 1436 * hasn't failed yet... 1437 */ 1438 have_autoterm = have_seeprom; 1439 1440 /* 1441 * Some low-cost chips have SEEPROM and auto-term control built 1442 * in, instead of using a GAL. They can tell us directly 1443 * if the termination logic is enabled. 1444 */ 1445 if ((ahc->features & AHC_SPIOCAP) != 0) { 1446 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1447 have_autoterm = FALSE; 1448 } 1449 1450 if (have_autoterm) { 1451 ahc->flags |= AHC_HAS_TERM_LOGIC; 1452 ahc_acquire_seeprom(ahc, &sd); 1453 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1454 ahc_release_seeprom(&sd); 1455 } else if (have_seeprom) { 1456 *sxfrctl1 &= ~STPWEN; 1457 if ((sc->adapter_control & CFSTERM) != 0) 1458 *sxfrctl1 |= STPWEN; 1459 if (bootverbose) 1460 printf("%s: Low byte termination %sabled\n", 1461 ahc_name(ahc), 1462 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1463 } 1464 } 1465 1466 static void 1467 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1468 { 1469 /* 1470 * Put the data we've collected down into SRAM 1471 * where ahc_init will find it. 1472 */ 1473 int i; 1474 int max_targ = sc->max_targets & CFMAXTARG; 1475 u_int scsi_conf; 1476 uint16_t discenable; 1477 uint16_t ultraenb; 1478 1479 discenable = 0; 1480 ultraenb = 0; 1481 if ((sc->adapter_control & CFULTRAEN) != 0) { 1482 /* 1483 * Determine if this adapter has a "newstyle" 1484 * SEEPROM format. 1485 */ 1486 for (i = 0; i < max_targ; i++) { 1487 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1488 ahc->flags |= AHC_NEWEEPROM_FMT; 1489 break; 1490 } 1491 } 1492 } 1493 1494 for (i = 0; i < max_targ; i++) { 1495 u_int scsirate; 1496 uint16_t target_mask; 1497 1498 target_mask = 0x01 << i; 1499 if (sc->device_flags[i] & CFDISC) 1500 discenable |= target_mask; 1501 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1502 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1503 ultraenb |= target_mask; 1504 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1505 ultraenb |= target_mask; 1506 } 1507 if ((sc->device_flags[i] & CFXFER) == 0x04 1508 && (ultraenb & target_mask) != 0) { 1509 /* Treat 10MHz as a non-ultra speed */ 1510 sc->device_flags[i] &= ~CFXFER; 1511 ultraenb &= ~target_mask; 1512 } 1513 if ((ahc->features & AHC_ULTRA2) != 0) { 1514 u_int offset; 1515 1516 if (sc->device_flags[i] & CFSYNCH) 1517 offset = MAX_OFFSET_ULTRA2; 1518 else 1519 offset = 0; 1520 ahc_outb(ahc, TARG_OFFSET + i, offset); 1521 1522 /* 1523 * The ultra enable bits contain the 1524 * high bit of the ultra2 sync rate 1525 * field. 1526 */ 1527 scsirate = (sc->device_flags[i] & CFXFER) 1528 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1529 if (sc->device_flags[i] & CFWIDEB) 1530 scsirate |= WIDEXFER; 1531 } else { 1532 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1533 if (sc->device_flags[i] & CFSYNCH) 1534 scsirate |= SOFS; 1535 if (sc->device_flags[i] & CFWIDEB) 1536 scsirate |= WIDEXFER; 1537 } 1538 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1539 } 1540 ahc->our_id = sc->brtime_id & CFSCSIID; 1541 1542 scsi_conf = (ahc->our_id & 0x7); 1543 if (sc->adapter_control & CFSPARITY) 1544 scsi_conf |= ENSPCHK; 1545 if (sc->adapter_control & CFRESETB) 1546 scsi_conf |= RESET_SCSI; 1547 1548 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1549 1550 if (sc->bios_control & CFEXTEND) 1551 ahc->flags |= AHC_EXTENDED_TRANS_A; 1552 1553 if (sc->bios_control & CFBIOSEN) 1554 ahc->flags |= AHC_BIOS_ENABLED; 1555 if (ahc->features & AHC_ULTRA 1556 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1557 /* Should we enable Ultra mode? */ 1558 if (!(sc->adapter_control & CFULTRAEN)) 1559 /* Treat us as a non-ultra card */ 1560 ultraenb = 0; 1561 } 1562 1563 if (sc->signature == CFSIGNATURE 1564 || sc->signature == CFSIGNATURE2) { 1565 uint32_t devconfig; 1566 1567 /* Honor the STPWLEVEL settings */ 1568 devconfig = ahc_pci_read_config(ahc->dev_softc, 1569 DEVCONFIG, /*bytes*/4); 1570 devconfig &= ~STPWLEVEL; 1571 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1572 devconfig |= STPWLEVEL; 1573 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1574 devconfig, /*bytes*/4); 1575 } 1576 /* Set SCSICONF info */ 1577 ahc_outb(ahc, SCSICONF, scsi_conf); 1578 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1579 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1580 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1581 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1582 } 1583 1584 static void 1585 configure_termination(struct ahc_softc *ahc, 1586 struct seeprom_descriptor *sd, 1587 u_int adapter_control, 1588 u_int *sxfrctl1) 1589 { 1590 uint8_t brddat; 1591 1592 brddat = 0; 1593 1594 /* 1595 * Update the settings in sxfrctl1 to match the 1596 * termination settings 1597 */ 1598 *sxfrctl1 = 0; 1599 1600 /* 1601 * SEECS must be on for the GALS to latch 1602 * the data properly. Be sure to leave MS 1603 * on or we will release the seeprom. 1604 */ 1605 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1606 if ((adapter_control & CFAUTOTERM) != 0 1607 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1608 int internal50_present; 1609 int internal68_present; 1610 int externalcable_present; 1611 int eeprom_present; 1612 int enableSEC_low; 1613 int enableSEC_high; 1614 int enablePRI_low; 1615 int enablePRI_high; 1616 int sum; 1617 1618 enableSEC_low = 0; 1619 enableSEC_high = 0; 1620 enablePRI_low = 0; 1621 enablePRI_high = 0; 1622 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1623 ahc_new_term_detect(ahc, &enableSEC_low, 1624 &enableSEC_high, 1625 &enablePRI_low, 1626 &enablePRI_high, 1627 &eeprom_present); 1628 if ((adapter_control & CFSEAUTOTERM) == 0) { 1629 if (bootverbose) 1630 printf("%s: Manual SE Termination\n", 1631 ahc_name(ahc)); 1632 enableSEC_low = (adapter_control & CFSELOWTERM); 1633 enableSEC_high = 1634 (adapter_control & CFSEHIGHTERM); 1635 } 1636 if ((adapter_control & CFAUTOTERM) == 0) { 1637 if (bootverbose) 1638 printf("%s: Manual LVD Termination\n", 1639 ahc_name(ahc)); 1640 enablePRI_low = (adapter_control & CFSTERM); 1641 enablePRI_high = (adapter_control & CFWSTERM); 1642 } 1643 /* Make the table calculations below happy */ 1644 internal50_present = 0; 1645 internal68_present = 1; 1646 externalcable_present = 1; 1647 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1648 aic785X_cable_detect(ahc, &internal50_present, 1649 &externalcable_present, 1650 &eeprom_present); 1651 /* Can never support a wide connector. */ 1652 internal68_present = 0; 1653 } else { 1654 aic787X_cable_detect(ahc, &internal50_present, 1655 &internal68_present, 1656 &externalcable_present, 1657 &eeprom_present); 1658 } 1659 1660 if ((ahc->features & AHC_WIDE) == 0) 1661 internal68_present = 0; 1662 1663 if (bootverbose 1664 && (ahc->features & AHC_ULTRA2) == 0) { 1665 printf("%s: internal 50 cable %s present", 1666 ahc_name(ahc), 1667 internal50_present ? "is":"not"); 1668 1669 if ((ahc->features & AHC_WIDE) != 0) 1670 printf(", internal 68 cable %s present", 1671 internal68_present ? "is":"not"); 1672 printf("\n%s: external cable %s present\n", 1673 ahc_name(ahc), 1674 externalcable_present ? "is":"not"); 1675 } 1676 if (bootverbose) 1677 printf("%s: BIOS eeprom %s present\n", 1678 ahc_name(ahc), eeprom_present ? "is" : "not"); 1679 1680 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1681 /* 1682 * The 50 pin connector is a separate bus, 1683 * so force it to always be terminated. 1684 * In the future, perform current sensing 1685 * to determine if we are in the middle of 1686 * a properly terminated bus. 1687 */ 1688 internal50_present = 0; 1689 } 1690 1691 /* 1692 * Now set the termination based on what 1693 * we found. 1694 * Flash Enable = BRDDAT7 1695 * Secondary High Term Enable = BRDDAT6 1696 * Secondary Low Term Enable = BRDDAT5 (7890) 1697 * Primary High Term Enable = BRDDAT4 (7890) 1698 */ 1699 if ((ahc->features & AHC_ULTRA2) == 0 1700 && (internal50_present != 0) 1701 && (internal68_present != 0) 1702 && (externalcable_present != 0)) { 1703 printf("%s: Illegal cable configuration!!. " 1704 "Only two connectors on the " 1705 "adapter may be used at a " 1706 "time!\n", ahc_name(ahc)); 1707 1708 /* 1709 * Pretend there are no cables in the hope 1710 * that having all of the termination on 1711 * gives us a more stable bus. 1712 */ 1713 internal50_present = 0; 1714 internal68_present = 0; 1715 externalcable_present = 0; 1716 } 1717 1718 if ((ahc->features & AHC_WIDE) != 0 1719 && ((externalcable_present == 0) 1720 || (internal68_present == 0) 1721 || (enableSEC_high != 0))) { 1722 brddat |= BRDDAT6; 1723 if (bootverbose) { 1724 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1725 printf("%s: 68 pin termination " 1726 "Enabled\n", ahc_name(ahc)); 1727 else 1728 printf("%s: %sHigh byte termination " 1729 "Enabled\n", ahc_name(ahc), 1730 enableSEC_high ? "Secondary " 1731 : ""); 1732 } 1733 } 1734 1735 sum = internal50_present + internal68_present 1736 + externalcable_present; 1737 if (sum < 2 || (enableSEC_low != 0)) { 1738 if ((ahc->features & AHC_ULTRA2) != 0) 1739 brddat |= BRDDAT5; 1740 else 1741 *sxfrctl1 |= STPWEN; 1742 if (bootverbose) { 1743 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1744 printf("%s: 50 pin termination " 1745 "Enabled\n", ahc_name(ahc)); 1746 else 1747 printf("%s: %sLow byte termination " 1748 "Enabled\n", ahc_name(ahc), 1749 enableSEC_low ? "Secondary " 1750 : ""); 1751 } 1752 } 1753 1754 if (enablePRI_low != 0) { 1755 *sxfrctl1 |= STPWEN; 1756 if (bootverbose) 1757 printf("%s: Primary Low Byte termination " 1758 "Enabled\n", ahc_name(ahc)); 1759 } 1760 1761 /* 1762 * Setup STPWEN before setting up the rest of 1763 * the termination per the tech note on the U160 cards. 1764 */ 1765 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1766 1767 if (enablePRI_high != 0) { 1768 brddat |= BRDDAT4; 1769 if (bootverbose) 1770 printf("%s: Primary High Byte " 1771 "termination Enabled\n", 1772 ahc_name(ahc)); 1773 } 1774 1775 write_brdctl(ahc, brddat); 1776 1777 } else { 1778 if ((adapter_control & CFSTERM) != 0) { 1779 *sxfrctl1 |= STPWEN; 1780 1781 if (bootverbose) 1782 printf("%s: %sLow byte termination Enabled\n", 1783 ahc_name(ahc), 1784 (ahc->features & AHC_ULTRA2) ? "Primary " 1785 : ""); 1786 } 1787 1788 if ((adapter_control & CFWSTERM) != 0 1789 && (ahc->features & AHC_WIDE) != 0) { 1790 brddat |= BRDDAT6; 1791 if (bootverbose) 1792 printf("%s: %sHigh byte termination Enabled\n", 1793 ahc_name(ahc), 1794 (ahc->features & AHC_ULTRA2) 1795 ? "Secondary " : ""); 1796 } 1797 1798 /* 1799 * Setup STPWEN before setting up the rest of 1800 * the termination per the tech note on the U160 cards. 1801 */ 1802 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1803 1804 if ((ahc->features & AHC_WIDE) != 0) 1805 write_brdctl(ahc, brddat); 1806 } 1807 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1808 } 1809 1810 static void 1811 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1812 int *enableSEC_high, int *enablePRI_low, 1813 int *enablePRI_high, int *eeprom_present) 1814 { 1815 uint8_t brdctl; 1816 1817 /* 1818 * BRDDAT7 = Eeprom 1819 * BRDDAT6 = Enable Secondary High Byte termination 1820 * BRDDAT5 = Enable Secondary Low Byte termination 1821 * BRDDAT4 = Enable Primary high byte termination 1822 * BRDDAT3 = Enable Primary low byte termination 1823 */ 1824 brdctl = read_brdctl(ahc); 1825 *eeprom_present = brdctl & BRDDAT7; 1826 *enableSEC_high = (brdctl & BRDDAT6); 1827 *enableSEC_low = (brdctl & BRDDAT5); 1828 *enablePRI_high = (brdctl & BRDDAT4); 1829 *enablePRI_low = (brdctl & BRDDAT3); 1830 } 1831 1832 static void 1833 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1834 int *internal68_present, int *externalcable_present, 1835 int *eeprom_present) 1836 { 1837 uint8_t brdctl; 1838 1839 /* 1840 * First read the status of our cables. 1841 * Set the rom bank to 0 since the 1842 * bank setting serves as a multiplexor 1843 * for the cable detection logic. 1844 * BRDDAT5 controls the bank switch. 1845 */ 1846 write_brdctl(ahc, 0); 1847 1848 /* 1849 * Now read the state of the internal 1850 * connectors. BRDDAT6 is INT50 and 1851 * BRDDAT7 is INT68. 1852 */ 1853 brdctl = read_brdctl(ahc); 1854 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1855 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1856 1857 /* 1858 * Set the rom bank to 1 and determine 1859 * the other signals. 1860 */ 1861 write_brdctl(ahc, BRDDAT5); 1862 1863 /* 1864 * Now read the state of the external 1865 * connectors. BRDDAT6 is EXT68 and 1866 * BRDDAT7 is EPROMPS. 1867 */ 1868 brdctl = read_brdctl(ahc); 1869 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1870 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1871 } 1872 1873 static void 1874 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1875 int *externalcable_present, int *eeprom_present) 1876 { 1877 uint8_t brdctl; 1878 uint8_t spiocap; 1879 1880 spiocap = ahc_inb(ahc, SPIOCAP); 1881 spiocap &= ~SOFTCMDEN; 1882 spiocap |= EXT_BRDCTL; 1883 ahc_outb(ahc, SPIOCAP, spiocap); 1884 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1885 ahc_flush_device_writes(ahc); 1886 ahc_delay(500); 1887 ahc_outb(ahc, BRDCTL, 0); 1888 ahc_flush_device_writes(ahc); 1889 ahc_delay(500); 1890 brdctl = ahc_inb(ahc, BRDCTL); 1891 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1892 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1893 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1894 } 1895 1896 int 1897 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1898 { 1899 int wait; 1900 1901 if ((ahc->features & AHC_SPIOCAP) != 0 1902 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1903 return (0); 1904 1905 /* 1906 * Request access of the memory port. When access is 1907 * granted, SEERDY will go high. We use a 1 second 1908 * timeout which should be near 1 second more than 1909 * is needed. Reason: after the chip reset, there 1910 * should be no contention. 1911 */ 1912 SEEPROM_OUTB(sd, sd->sd_MS); 1913 wait = 1000; /* 1 second timeout in msec */ 1914 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1915 ahc_delay(1000); /* delay 1 msec */ 1916 } 1917 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1918 SEEPROM_OUTB(sd, 0); 1919 return (0); 1920 } 1921 return(1); 1922 } 1923 1924 void 1925 ahc_release_seeprom(struct seeprom_descriptor *sd) 1926 { 1927 /* Release access to the memory port and the serial EEPROM. */ 1928 SEEPROM_OUTB(sd, 0); 1929 } 1930 1931 static void 1932 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1933 { 1934 uint8_t brdctl; 1935 1936 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1937 brdctl = BRDSTB; 1938 if (ahc->channel == 'B') 1939 brdctl |= BRDCS; 1940 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1941 brdctl = 0; 1942 } else { 1943 brdctl = BRDSTB|BRDCS; 1944 } 1945 ahc_outb(ahc, BRDCTL, brdctl); 1946 ahc_flush_device_writes(ahc); 1947 brdctl |= value; 1948 ahc_outb(ahc, BRDCTL, brdctl); 1949 ahc_flush_device_writes(ahc); 1950 if ((ahc->features & AHC_ULTRA2) != 0) 1951 brdctl |= BRDSTB_ULTRA2; 1952 else 1953 brdctl &= ~BRDSTB; 1954 ahc_outb(ahc, BRDCTL, brdctl); 1955 ahc_flush_device_writes(ahc); 1956 if ((ahc->features & AHC_ULTRA2) != 0) 1957 brdctl = 0; 1958 else 1959 brdctl &= ~BRDCS; 1960 ahc_outb(ahc, BRDCTL, brdctl); 1961 } 1962 1963 static uint8_t 1964 read_brdctl(struct ahc_softc *ahc) 1965 { 1966 uint8_t brdctl; 1967 uint8_t value; 1968 1969 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1970 brdctl = BRDRW; 1971 if (ahc->channel == 'B') 1972 brdctl |= BRDCS; 1973 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1974 brdctl = BRDRW_ULTRA2; 1975 } else { 1976 brdctl = BRDRW|BRDCS; 1977 } 1978 ahc_outb(ahc, BRDCTL, brdctl); 1979 ahc_flush_device_writes(ahc); 1980 value = ahc_inb(ahc, BRDCTL); 1981 ahc_outb(ahc, BRDCTL, 0); 1982 return (value); 1983 } 1984 1985 static void 1986 ahc_pci_intr(struct ahc_softc *ahc) 1987 { 1988 u_int error; 1989 u_int status1; 1990 1991 error = ahc_inb(ahc, ERROR); 1992 if ((error & PCIERRSTAT) == 0) 1993 return; 1994 1995 status1 = ahc_pci_read_config(ahc->dev_softc, 1996 PCIR_STATUS + 1, /*bytes*/1); 1997 1998 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1999 ahc_name(ahc), 2000 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 2001 2002 if (status1 & DPE) { 2003 ahc->pci_target_perr_count++; 2004 printf("%s: Data Parity Error Detected during address " 2005 "or write data phase\n", ahc_name(ahc)); 2006 } 2007 if (status1 & SSE) { 2008 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 2009 } 2010 if (status1 & RMA) { 2011 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 2012 } 2013 if (status1 & RTA) { 2014 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 2015 } 2016 if (status1 & STA) { 2017 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 2018 } 2019 if (status1 & DPR) { 2020 printf("%s: Data Parity Error has been reported via PERR#\n", 2021 ahc_name(ahc)); 2022 } 2023 2024 /* Clear latched errors. */ 2025 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 2026 status1, /*bytes*/1); 2027 2028 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 2029 printf("%s: Latched PCIERR interrupt with " 2030 "no status bits set\n", ahc_name(ahc)); 2031 } else { 2032 ahc_outb(ahc, CLRINT, CLRPARERR); 2033 } 2034 2035 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 2036 printf( 2037 "%s: WARNING WARNING WARNING WARNING\n" 2038 "%s: Too many PCI parity errors observed as a target.\n" 2039 "%s: Some device on this bus is generating bad parity.\n" 2040 "%s: This is an error *observed by*, not *generated by*, this controller.\n" 2041 "%s: PCI parity error checking has been disabled.\n" 2042 "%s: WARNING WARNING WARNING WARNING\n", 2043 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 2044 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 2045 ahc->seqctl |= FAILDIS; 2046 ahc_outb(ahc, SEQCTL, ahc->seqctl); 2047 } 2048 ahc_unpause(ahc); 2049 } 2050 2051 static int 2052 ahc_pci_chip_init(struct ahc_softc *ahc) 2053 { 2054 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 2055 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 2056 if ((ahc->features & AHC_DT) != 0) { 2057 u_int sfunct; 2058 2059 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 2060 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 2061 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 2062 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 2063 ahc_outb(ahc, SFUNCT, sfunct); 2064 ahc_outb(ahc, CRCCONTROL1, 2065 ahc->bus_softc.pci_softc.crccontrol1); 2066 } 2067 if ((ahc->features & AHC_MULTI_FUNC) != 0) 2068 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 2069 2070 if ((ahc->features & AHC_ULTRA2) != 0) 2071 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 2072 2073 return (ahc_chip_init(ahc)); 2074 } 2075 2076 static int 2077 ahc_pci_suspend(struct ahc_softc *ahc) 2078 { 2079 return (ahc_suspend(ahc)); 2080 } 2081 2082 static int 2083 ahc_pci_resume(struct ahc_softc *ahc) 2084 { 2085 2086 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 2087 2088 /* 2089 * We assume that the OS has restored our register 2090 * mappings, etc. Just update the config space registers 2091 * that the OS doesn't know about and rely on our chip 2092 * reset handler to handle the rest. 2093 */ 2094 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4, 2095 ahc->bus_softc.pci_softc.devconfig); 2096 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1, 2097 ahc->bus_softc.pci_softc.command); 2098 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1, 2099 ahc->bus_softc.pci_softc.csize_lattime); 2100 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2101 struct seeprom_descriptor sd; 2102 u_int sxfrctl1; 2103 2104 sd.sd_ahc = ahc; 2105 sd.sd_control_offset = SEECTL; 2106 sd.sd_status_offset = SEECTL; 2107 sd.sd_dataout_offset = SEECTL; 2108 2109 ahc_acquire_seeprom(ahc, &sd); 2110 configure_termination(ahc, &sd, 2111 ahc->seep_config->adapter_control, 2112 &sxfrctl1); 2113 ahc_release_seeprom(&sd); 2114 } 2115 return (ahc_resume(ahc)); 2116 } 2117 2118 static int 2119 ahc_aic785X_setup(struct ahc_softc *ahc) 2120 { 2121 ahc_dev_softc_t pci; 2122 uint8_t rev; 2123 2124 pci = ahc->dev_softc; 2125 ahc->channel = 'A'; 2126 ahc->chip = AHC_AIC7850; 2127 ahc->features = AHC_AIC7850_FE; 2128 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2129 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2130 if (rev >= 1) 2131 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2132 ahc->instruction_ram_size = 512; 2133 return (0); 2134 } 2135 2136 static int 2137 ahc_aic7860_setup(struct ahc_softc *ahc) 2138 { 2139 ahc_dev_softc_t pci; 2140 uint8_t rev; 2141 2142 pci = ahc->dev_softc; 2143 ahc->channel = 'A'; 2144 ahc->chip = AHC_AIC7860; 2145 ahc->features = AHC_AIC7860_FE; 2146 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2147 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2148 if (rev >= 1) 2149 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2150 ahc->instruction_ram_size = 512; 2151 return (0); 2152 } 2153 2154 static int 2155 ahc_apa1480_setup(struct ahc_softc *ahc) 2156 { 2157 int error; 2158 2159 error = ahc_aic7860_setup(ahc); 2160 if (error != 0) 2161 return (error); 2162 ahc->features |= AHC_REMOVABLE; 2163 return (0); 2164 } 2165 2166 static int 2167 ahc_aic7870_setup(struct ahc_softc *ahc) 2168 { 2169 2170 ahc->channel = 'A'; 2171 ahc->chip = AHC_AIC7870; 2172 ahc->features = AHC_AIC7870_FE; 2173 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2174 ahc->instruction_ram_size = 512; 2175 return (0); 2176 } 2177 2178 static int 2179 ahc_aha394X_setup(struct ahc_softc *ahc) 2180 { 2181 int error; 2182 2183 error = ahc_aic7870_setup(ahc); 2184 if (error == 0) 2185 error = ahc_aha394XX_setup(ahc); 2186 return (error); 2187 } 2188 2189 static int 2190 ahc_aha398X_setup(struct ahc_softc *ahc) 2191 { 2192 int error; 2193 2194 error = ahc_aic7870_setup(ahc); 2195 if (error == 0) 2196 error = ahc_aha398XX_setup(ahc); 2197 return (error); 2198 } 2199 2200 static int 2201 ahc_aha494X_setup(struct ahc_softc *ahc) 2202 { 2203 int error; 2204 2205 error = ahc_aic7870_setup(ahc); 2206 if (error == 0) 2207 error = ahc_aha494XX_setup(ahc); 2208 return (error); 2209 } 2210 2211 static int 2212 ahc_aic7880_setup(struct ahc_softc *ahc) 2213 { 2214 ahc_dev_softc_t pci; 2215 uint8_t rev; 2216 2217 pci = ahc->dev_softc; 2218 ahc->channel = 'A'; 2219 ahc->chip = AHC_AIC7880; 2220 ahc->features = AHC_AIC7880_FE; 2221 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2222 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2223 if (rev >= 1) { 2224 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2225 } else { 2226 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2227 } 2228 ahc->instruction_ram_size = 512; 2229 return (0); 2230 } 2231 2232 static int 2233 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2234 { 2235 2236 ahc->flags |= AHC_INT50_SPEEDFLEX; 2237 return (ahc_aic7880_setup(ahc)); 2238 } 2239 2240 static int 2241 ahc_aha394XU_setup(struct ahc_softc *ahc) 2242 { 2243 int error; 2244 2245 error = ahc_aic7880_setup(ahc); 2246 if (error == 0) 2247 error = ahc_aha394XX_setup(ahc); 2248 return (error); 2249 } 2250 2251 static int 2252 ahc_aha398XU_setup(struct ahc_softc *ahc) 2253 { 2254 int error; 2255 2256 error = ahc_aic7880_setup(ahc); 2257 if (error == 0) 2258 error = ahc_aha398XX_setup(ahc); 2259 return (error); 2260 } 2261 2262 static int 2263 ahc_aic7890_setup(struct ahc_softc *ahc) 2264 { 2265 ahc_dev_softc_t pci; 2266 uint8_t rev; 2267 2268 pci = ahc->dev_softc; 2269 ahc->channel = 'A'; 2270 ahc->chip = AHC_AIC7890; 2271 ahc->features = AHC_AIC7890_FE; 2272 ahc->flags |= AHC_NEWEEPROM_FMT; 2273 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2274 if (rev == 0) 2275 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2276 ahc->instruction_ram_size = 768; 2277 return (0); 2278 } 2279 2280 static int 2281 ahc_aic7892_setup(struct ahc_softc *ahc) 2282 { 2283 2284 ahc->channel = 'A'; 2285 ahc->chip = AHC_AIC7892; 2286 ahc->features = AHC_AIC7892_FE; 2287 ahc->flags |= AHC_NEWEEPROM_FMT; 2288 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2289 ahc->instruction_ram_size = 1024; 2290 return (0); 2291 } 2292 2293 static int 2294 ahc_aic7895_setup(struct ahc_softc *ahc) 2295 { 2296 ahc_dev_softc_t pci; 2297 uint8_t rev; 2298 2299 pci = ahc->dev_softc; 2300 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2301 /* 2302 * The 'C' revision of the aic7895 has a few additional features. 2303 */ 2304 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2305 if (rev >= 4) { 2306 ahc->chip = AHC_AIC7895C; 2307 ahc->features = AHC_AIC7895C_FE; 2308 } else { 2309 u_int command; 2310 2311 ahc->chip = AHC_AIC7895; 2312 ahc->features = AHC_AIC7895_FE; 2313 2314 /* 2315 * The BIOS disables the use of MWI transactions 2316 * since it does not have the MWI bug work around 2317 * we have. Disabling MWI reduces performance, so 2318 * turn it on again. 2319 */ 2320 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2321 command |= PCIM_CMD_MWRICEN; 2322 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2323 ahc->bugs |= AHC_PCI_MWI_BUG; 2324 } 2325 /* 2326 * XXX Does CACHETHEN really not work??? What about PCI retry? 2327 * on C level chips. Need to test, but for now, play it safe. 2328 */ 2329 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2330 | AHC_CACHETHEN_BUG; 2331 2332 #if 0 2333 uint32_t devconfig; 2334 2335 /* 2336 * Cachesize must also be zero due to stray DAC 2337 * problem when sitting behind some bridges. 2338 */ 2339 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2340 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2341 devconfig |= MRDCEN; 2342 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2343 #endif 2344 ahc->flags |= AHC_NEWEEPROM_FMT; 2345 ahc->instruction_ram_size = 512; 2346 return (0); 2347 } 2348 2349 static int 2350 ahc_aic7896_setup(struct ahc_softc *ahc) 2351 { 2352 ahc_dev_softc_t pci; 2353 2354 pci = ahc->dev_softc; 2355 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2356 ahc->chip = AHC_AIC7896; 2357 ahc->features = AHC_AIC7896_FE; 2358 ahc->flags |= AHC_NEWEEPROM_FMT; 2359 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2360 ahc->instruction_ram_size = 768; 2361 return (0); 2362 } 2363 2364 static int 2365 ahc_aic7899_setup(struct ahc_softc *ahc) 2366 { 2367 ahc_dev_softc_t pci; 2368 2369 pci = ahc->dev_softc; 2370 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2371 ahc->chip = AHC_AIC7899; 2372 ahc->features = AHC_AIC7899_FE; 2373 ahc->flags |= AHC_NEWEEPROM_FMT; 2374 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2375 ahc->instruction_ram_size = 1024; 2376 return (0); 2377 } 2378 2379 static int 2380 ahc_aha29160C_setup(struct ahc_softc *ahc) 2381 { 2382 int error; 2383 2384 error = ahc_aic7899_setup(ahc); 2385 if (error != 0) 2386 return (error); 2387 ahc->features |= AHC_REMOVABLE; 2388 return (0); 2389 } 2390 2391 static int 2392 ahc_raid_setup(struct ahc_softc *ahc) 2393 { 2394 printf("RAID functionality unsupported\n"); 2395 return (ENXIO); 2396 } 2397 2398 static int 2399 ahc_aha394XX_setup(struct ahc_softc *ahc) 2400 { 2401 ahc_dev_softc_t pci; 2402 2403 pci = ahc->dev_softc; 2404 switch (ahc_get_pci_slot(pci)) { 2405 case AHC_394X_SLOT_CHANNEL_A: 2406 ahc->channel = 'A'; 2407 break; 2408 case AHC_394X_SLOT_CHANNEL_B: 2409 ahc->channel = 'B'; 2410 break; 2411 default: 2412 printf("adapter at unexpected slot %d\n" 2413 "unable to map to a channel\n", 2414 ahc_get_pci_slot(pci)); 2415 ahc->channel = 'A'; 2416 } 2417 return (0); 2418 } 2419 2420 static int 2421 ahc_aha398XX_setup(struct ahc_softc *ahc) 2422 { 2423 ahc_dev_softc_t pci; 2424 2425 pci = ahc->dev_softc; 2426 switch (ahc_get_pci_slot(pci)) { 2427 case AHC_398X_SLOT_CHANNEL_A: 2428 ahc->channel = 'A'; 2429 break; 2430 case AHC_398X_SLOT_CHANNEL_B: 2431 ahc->channel = 'B'; 2432 break; 2433 case AHC_398X_SLOT_CHANNEL_C: 2434 ahc->channel = 'C'; 2435 break; 2436 default: 2437 printf("adapter at unexpected slot %d\n" 2438 "unable to map to a channel\n", 2439 ahc_get_pci_slot(pci)); 2440 ahc->channel = 'A'; 2441 break; 2442 } 2443 ahc->flags |= AHC_LARGE_SEEPROM; 2444 return (0); 2445 } 2446 2447 static int 2448 ahc_aha494XX_setup(struct ahc_softc *ahc) 2449 { 2450 ahc_dev_softc_t pci; 2451 2452 pci = ahc->dev_softc; 2453 switch (ahc_get_pci_slot(pci)) { 2454 case AHC_494X_SLOT_CHANNEL_A: 2455 ahc->channel = 'A'; 2456 break; 2457 case AHC_494X_SLOT_CHANNEL_B: 2458 ahc->channel = 'B'; 2459 break; 2460 case AHC_494X_SLOT_CHANNEL_C: 2461 ahc->channel = 'C'; 2462 break; 2463 case AHC_494X_SLOT_CHANNEL_D: 2464 ahc->channel = 'D'; 2465 break; 2466 default: 2467 printf("adapter at unexpected slot %d\n" 2468 "unable to map to a channel\n", 2469 ahc_get_pci_slot(pci)); 2470 ahc->channel = 'A'; 2471 } 2472 ahc->flags |= AHC_LARGE_SEEPROM; 2473 return (0); 2474 } 2475