1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#37 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 58 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 59 60 static __inline uint64_t 61 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 77 #define ID_9005_SISL_ID 0x0005900500000000ull 78 #define ID_AIC7850 0x5078900400000000ull 79 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 80 #define ID_AIC7855 0x5578900400000000ull 81 #define ID_AIC7859 0x3860900400000000ull 82 #define ID_AHA_2930CU 0x3860900438699004ull 83 #define ID_AIC7860 0x6078900400000000ull 84 #define ID_AIC7860C 0x6078900478609004ull 85 #define ID_AHA_1480A 0x6075900400000000ull 86 #define ID_AHA_2940AU_0 0x6178900400000000ull 87 #define ID_AHA_2940AU_1 0x6178900478619004ull 88 #define ID_AHA_2940AU_CN 0x2178900478219004ull 89 #define ID_AHA_2930C_VAR 0x6038900438689004ull 90 91 #define ID_AIC7870 0x7078900400000000ull 92 #define ID_AHA_2940 0x7178900400000000ull 93 #define ID_AHA_3940 0x7278900400000000ull 94 #define ID_AHA_398X 0x7378900400000000ull 95 #define ID_AHA_2944 0x7478900400000000ull 96 #define ID_AHA_3944 0x7578900400000000ull 97 #define ID_AHA_4944 0x7678900400000000ull 98 99 #define ID_AIC7880 0x8078900400000000ull 100 #define ID_AIC7880_B 0x8078900478809004ull 101 #define ID_AHA_2940U 0x8178900400000000ull 102 #define ID_AHA_3940U 0x8278900400000000ull 103 #define ID_AHA_2944U 0x8478900400000000ull 104 #define ID_AHA_3944U 0x8578900400000000ull 105 #define ID_AHA_398XU 0x8378900400000000ull 106 #define ID_AHA_4944U 0x8678900400000000ull 107 #define ID_AHA_2940UB 0x8178900478819004ull 108 #define ID_AHA_2930U 0x8878900478889004ull 109 #define ID_AHA_2940U_PRO 0x8778900478879004ull 110 #define ID_AHA_2940U_CN 0x0078900478009004ull 111 112 #define ID_AIC7895 0x7895900478959004ull 113 #define ID_AIC7895_ARO 0x7890900478939004ull 114 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 115 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 116 #define ID_AHA_3940AU 0x7895900478929004ull 117 #define ID_AHA_3944AU 0x7895900478949004ull 118 119 #define ID_AIC7890 0x001F9005000F9005ull 120 #define ID_AIC7890_ARO 0x00139005000F9005ull 121 #define ID_AAA_131U2 0x0013900500039005ull 122 #define ID_AHA_2930U2 0x0011900501819005ull 123 #define ID_AHA_2940U2B 0x00109005A1009005ull 124 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 125 #define ID_AHA_2940U2 0x00109005A1809005ull 126 #define ID_AHA_2950U2B 0x00109005E1009005ull 127 128 #define ID_AIC7892 0x008F9005FFFF9005ull 129 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 130 #define ID_AHA_29160 0x00809005E2A09005ull 131 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132 #define ID_AHA_29160N 0x0080900562A09005ull 133 #define ID_AHA_29160C 0x0080900562209005ull 134 #define ID_AHA_29160B 0x00809005E2209005ull 135 #define ID_AHA_19160B 0x0081900562A19005ull 136 137 #define ID_AIC7896 0x005F9005FFFF9005ull 138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 146 #define ID_AHA_3960D 0x00C09005F6209005ull 147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 148 149 #define ID_AIC7810 0x1078900400000000ull 150 #define ID_AIC7815 0x7815900400000000ull 151 152 #define DEVID_9005_TYPE(id) ((id) & 0xF) 153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 157 158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 159 #define DEVID_9005_MAXRATE_U160 0x0 160 #define DEVID_9005_MAXRATE_ULTRA2 0x1 161 #define DEVID_9005_MAXRATE_ULTRA 0x2 162 #define DEVID_9005_MAXRATE_FAST 0x3 163 164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 165 166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 168 169 #define SUBID_9005_TYPE(id) ((id) & 0xF) 170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 174 175 #define SUBID_9005_TYPE_KNOWN(id) \ 176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 180 181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define SUBID_9005_MAXRATE_ULTRA2 0x0 183 #define SUBID_9005_MAXRATE_ULTRA 0x1 184 #define SUBID_9005_MAXRATE_U160 0x2 185 #define SUBID_9005_MAXRATE_RESERVED 0x3 186 187 #define SUBID_9005_SEEPTYPE(id) \ 188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 189 ? ((id) & 0xC0) >> 6 \ 190 : ((id) & 0x300) >> 8) 191 #define SUBID_9005_SEEPTYPE_NONE 0x0 192 #define SUBID_9005_SEEPTYPE_1K 0x1 193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 195 #define SUBID_9005_AUTOTERM(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? (((id) & 0x400) >> 10) == 0 \ 198 : (((id) & 0x40) >> 6) == 0) 199 200 #define SUBID_9005_NUMCHAN(id) \ 201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 202 ? ((id) & 0x300) >> 8 \ 203 : ((id) & 0xC00) >> 10) 204 205 #define SUBID_9005_LEGACYCONN(id) \ 206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 207 ? 0 \ 208 : ((id) & 0x80) >> 7) 209 210 #define SUBID_9005_MFUNCENB(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0x800) >> 11 \ 213 : ((id) & 0x1000) >> 12) 214 /* 215 * Informational only. Should use chip register to be 216 * certain, but may be use in identification strings. 217 */ 218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 221 222 static ahc_device_setup_t ahc_aic785X_setup; 223 static ahc_device_setup_t ahc_aic7860_setup; 224 static ahc_device_setup_t ahc_apa1480_setup; 225 static ahc_device_setup_t ahc_aic7870_setup; 226 static ahc_device_setup_t ahc_aha394X_setup; 227 static ahc_device_setup_t ahc_aha494X_setup; 228 static ahc_device_setup_t ahc_aha398X_setup; 229 static ahc_device_setup_t ahc_aic7880_setup; 230 static ahc_device_setup_t ahc_aha2940Pro_setup; 231 static ahc_device_setup_t ahc_aha394XU_setup; 232 static ahc_device_setup_t ahc_aha398XU_setup; 233 static ahc_device_setup_t ahc_aic7890_setup; 234 static ahc_device_setup_t ahc_aic7892_setup; 235 static ahc_device_setup_t ahc_aic7895_setup; 236 static ahc_device_setup_t ahc_aic7896_setup; 237 static ahc_device_setup_t ahc_aic7899_setup; 238 static ahc_device_setup_t ahc_aha29160C_setup; 239 static ahc_device_setup_t ahc_raid_setup; 240 static ahc_device_setup_t ahc_aha394XX_setup; 241 static ahc_device_setup_t ahc_aha494XX_setup; 242 static ahc_device_setup_t ahc_aha398XX_setup; 243 244 struct ahc_pci_identity ahc_pci_ident_table [] = 245 { 246 /* aic7850 based controllers */ 247 { 248 ID_AHA_2902_04_10_15_20_30C, 249 ID_ALL_MASK, 250 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 251 ahc_aic785X_setup 252 }, 253 /* aic7860 based controllers */ 254 { 255 ID_AHA_2930CU, 256 ID_ALL_MASK, 257 "Adaptec 2930CU SCSI adapter", 258 ahc_aic7860_setup 259 }, 260 { 261 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 1480A Ultra SCSI adapter", 264 ahc_apa1480_setup 265 }, 266 { 267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 2940A Ultra SCSI adapter", 270 ahc_aic7860_setup 271 }, 272 { 273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 2940A/CN Ultra SCSI adapter", 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 "Adaptec 2930C Ultra SCSI adapter (VAR)", 282 ahc_aic7860_setup 283 }, 284 /* aic7870 based controllers */ 285 { 286 ID_AHA_2940, 287 ID_ALL_MASK, 288 "Adaptec 2940 SCSI adapter", 289 ahc_aic7870_setup 290 }, 291 { 292 ID_AHA_3940, 293 ID_ALL_MASK, 294 "Adaptec 3940 SCSI adapter", 295 ahc_aha394X_setup 296 }, 297 { 298 ID_AHA_398X, 299 ID_ALL_MASK, 300 "Adaptec 398X SCSI RAID adapter", 301 ahc_aha398X_setup 302 }, 303 { 304 ID_AHA_2944, 305 ID_ALL_MASK, 306 "Adaptec 2944 SCSI adapter", 307 ahc_aic7870_setup 308 }, 309 { 310 ID_AHA_3944, 311 ID_ALL_MASK, 312 "Adaptec 3944 SCSI adapter", 313 ahc_aha394X_setup 314 }, 315 { 316 ID_AHA_4944, 317 ID_ALL_MASK, 318 "Adaptec 4944 SCSI adapter", 319 ahc_aha494X_setup 320 }, 321 /* aic7880 based controllers */ 322 { 323 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 324 ID_DEV_VENDOR_MASK, 325 "Adaptec 2940 Ultra SCSI adapter", 326 ahc_aic7880_setup 327 }, 328 { 329 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 330 ID_DEV_VENDOR_MASK, 331 "Adaptec 3940 Ultra SCSI adapter", 332 ahc_aha394XU_setup 333 }, 334 { 335 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 336 ID_DEV_VENDOR_MASK, 337 "Adaptec 2944 Ultra SCSI adapter", 338 ahc_aic7880_setup 339 }, 340 { 341 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 "Adaptec 3944 Ultra SCSI adapter", 344 ahc_aha394XU_setup 345 }, 346 { 347 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 348 ID_DEV_VENDOR_MASK, 349 "Adaptec 398X Ultra SCSI RAID adapter", 350 ahc_aha398XU_setup 351 }, 352 { 353 /* 354 * XXX Don't know the slot numbers 355 * so we can't identify channels 356 */ 357 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec 4944 Ultra SCSI adapter", 360 ahc_aic7880_setup 361 }, 362 { 363 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec 2930 Ultra SCSI adapter", 366 ahc_aic7880_setup 367 }, 368 { 369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec 2940 Pro Ultra SCSI adapter", 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec 2940/CN Ultra SCSI adapter", 378 ahc_aic7880_setup 379 }, 380 /* Ignore all SISL (AAC on MB) based controllers. */ 381 { 382 ID_9005_SISL_ID, 383 ID_9005_SISL_MASK, 384 NULL, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 "Adaptec 2930 Ultra2 SCSI adapter", 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 "Adaptec 2940B Ultra2 SCSI adapter", 398 ahc_aic7890_setup 399 }, 400 { 401 ID_AHA_2940U2_OEM, 402 ID_ALL_MASK, 403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2940U2, 408 ID_ALL_MASK, 409 "Adaptec 2940 Ultra2 SCSI adapter", 410 ahc_aic7890_setup 411 }, 412 { 413 ID_AHA_2950U2B, 414 ID_ALL_MASK, 415 "Adaptec 2950 Ultra2 SCSI adapter", 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AIC7890_ARO, 420 ID_ALL_MASK, 421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 422 ahc_aic7890_setup 423 }, 424 { 425 ID_AAA_131U2, 426 ID_ALL_MASK, 427 "Adaptec AAA-131 Ultra2 RAID adapter", 428 ahc_aic7890_setup 429 }, 430 /* aic7892 based controllers */ 431 { 432 ID_AHA_29160, 433 ID_ALL_MASK, 434 "Adaptec 29160 Ultra160 SCSI adapter", 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160_CPQ, 439 ID_ALL_MASK, 440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 441 ahc_aic7892_setup 442 }, 443 { 444 ID_AHA_29160N, 445 ID_ALL_MASK, 446 "Adaptec 29160N Ultra160 SCSI adapter", 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_29160C, 451 ID_ALL_MASK, 452 "Adaptec 29160C Ultra160 SCSI adapter", 453 ahc_aha29160C_setup 454 }, 455 { 456 ID_AHA_29160B, 457 ID_ALL_MASK, 458 "Adaptec 29160B Ultra160 SCSI adapter", 459 ahc_aic7892_setup 460 }, 461 { 462 ID_AHA_19160B, 463 ID_ALL_MASK, 464 "Adaptec 19160B Ultra160 SCSI adapter", 465 ahc_aic7892_setup 466 }, 467 { 468 ID_AIC7892_ARO, 469 ID_ALL_MASK, 470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 471 ahc_aic7892_setup 472 }, 473 /* aic7895 based controllers */ 474 { 475 ID_AHA_2940U_DUAL, 476 ID_ALL_MASK, 477 "Adaptec 2940/DUAL Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AHA_3940AU, 482 ID_ALL_MASK, 483 "Adaptec 3940A Ultra SCSI adapter", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AHA_3944AU, 488 ID_ALL_MASK, 489 "Adaptec 3944A Ultra SCSI adapter", 490 ahc_aic7895_setup 491 }, 492 { 493 ID_AIC7895_ARO, 494 ID_AIC7895_ARO_MASK, 495 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 496 ahc_aic7895_setup 497 }, 498 /* aic7896/97 based controllers */ 499 { 500 ID_AHA_3950U2B_0, 501 ID_ALL_MASK, 502 "Adaptec 3950B Ultra2 SCSI adapter", 503 ahc_aic7896_setup 504 }, 505 { 506 ID_AHA_3950U2B_1, 507 ID_ALL_MASK, 508 "Adaptec 3950B Ultra2 SCSI adapter", 509 ahc_aic7896_setup 510 }, 511 { 512 ID_AHA_3950U2D_0, 513 ID_ALL_MASK, 514 "Adaptec 3950D Ultra2 SCSI adapter", 515 ahc_aic7896_setup 516 }, 517 { 518 ID_AHA_3950U2D_1, 519 ID_ALL_MASK, 520 "Adaptec 3950D Ultra2 SCSI adapter", 521 ahc_aic7896_setup 522 }, 523 { 524 ID_AIC7896_ARO, 525 ID_ALL_MASK, 526 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 527 ahc_aic7896_setup 528 }, 529 /* aic7899 based controllers */ 530 { 531 ID_AHA_3960D, 532 ID_ALL_MASK, 533 "Adaptec 3960D Ultra160 SCSI adapter", 534 ahc_aic7899_setup 535 }, 536 { 537 ID_AHA_3960D_CPQ, 538 ID_ALL_MASK, 539 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 540 ahc_aic7899_setup 541 }, 542 { 543 ID_AIC7899_ARO, 544 ID_ALL_MASK, 545 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 546 ahc_aic7899_setup 547 }, 548 /* Generic chip probes for devices we don't know 'exactly' */ 549 { 550 ID_AIC7850 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 "Adaptec aic7850 SCSI adapter", 553 ahc_aic785X_setup 554 }, 555 { 556 ID_AIC7855 & ID_DEV_VENDOR_MASK, 557 ID_DEV_VENDOR_MASK, 558 "Adaptec aic7855 SCSI adapter", 559 ahc_aic785X_setup 560 }, 561 { 562 ID_AIC7859 & ID_DEV_VENDOR_MASK, 563 ID_DEV_VENDOR_MASK, 564 "Adaptec aic7859 SCSI adapter", 565 ahc_aic7860_setup 566 }, 567 { 568 ID_AIC7860 & ID_DEV_VENDOR_MASK, 569 ID_DEV_VENDOR_MASK, 570 "Adaptec aic7860 Ultra SCSI adapter", 571 ahc_aic7860_setup 572 }, 573 { 574 ID_AIC7870 & ID_DEV_VENDOR_MASK, 575 ID_DEV_VENDOR_MASK, 576 "Adaptec aic7870 SCSI adapter", 577 ahc_aic7870_setup 578 }, 579 { 580 ID_AIC7880 & ID_DEV_VENDOR_MASK, 581 ID_DEV_VENDOR_MASK, 582 "Adaptec aic7880 Ultra SCSI adapter", 583 ahc_aic7880_setup 584 }, 585 { 586 ID_AIC7890 & ID_9005_GENERIC_MASK, 587 ID_9005_GENERIC_MASK, 588 "Adaptec aic7890/91 Ultra2 SCSI adapter", 589 ahc_aic7890_setup 590 }, 591 { 592 ID_AIC7892 & ID_9005_GENERIC_MASK, 593 ID_9005_GENERIC_MASK, 594 "Adaptec aic7892 Ultra160 SCSI adapter", 595 ahc_aic7892_setup 596 }, 597 { 598 ID_AIC7895 & ID_DEV_VENDOR_MASK, 599 ID_DEV_VENDOR_MASK, 600 "Adaptec aic7895 Ultra SCSI adapter", 601 ahc_aic7895_setup 602 }, 603 { 604 ID_AIC7896 & ID_9005_GENERIC_MASK, 605 ID_9005_GENERIC_MASK, 606 "Adaptec aic7896/97 Ultra2 SCSI adapter", 607 ahc_aic7896_setup 608 }, 609 { 610 ID_AIC7899 & ID_9005_GENERIC_MASK, 611 ID_9005_GENERIC_MASK, 612 "Adaptec aic7899 Ultra160 SCSI adapter", 613 ahc_aic7899_setup 614 }, 615 { 616 ID_AIC7810 & ID_DEV_VENDOR_MASK, 617 ID_DEV_VENDOR_MASK, 618 "Adaptec aic7810 RAID memory controller", 619 ahc_raid_setup 620 }, 621 { 622 ID_AIC7815 & ID_DEV_VENDOR_MASK, 623 ID_DEV_VENDOR_MASK, 624 "Adaptec aic7815 RAID memory controller", 625 ahc_raid_setup 626 } 627 }; 628 629 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 630 631 #define AHC_394X_SLOT_CHANNEL_A 4 632 #define AHC_394X_SLOT_CHANNEL_B 5 633 634 #define AHC_398X_SLOT_CHANNEL_A 4 635 #define AHC_398X_SLOT_CHANNEL_B 8 636 #define AHC_398X_SLOT_CHANNEL_C 12 637 638 #define AHC_494X_SLOT_CHANNEL_A 4 639 #define AHC_494X_SLOT_CHANNEL_B 5 640 #define AHC_494X_SLOT_CHANNEL_C 6 641 #define AHC_494X_SLOT_CHANNEL_D 7 642 643 #define DEVCONFIG 0x40 644 #define SCBSIZE32 0x00010000ul /* aic789X only */ 645 #define REXTVALID 0x00001000ul /* ultra cards only */ 646 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 647 #define RAMPSM 0x00000200ul /* aic7870+ only */ 648 #define VOLSENSE 0x00000100ul 649 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 650 #define SCBRAMSEL 0x00000080ul 651 #define MRDCEN 0x00000040ul 652 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 653 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 654 #define BERREN 0x00000008ul 655 #define DACEN 0x00000004ul 656 #define STPWLEVEL 0x00000002ul 657 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 658 659 #define CSIZE_LATTIME 0x0c 660 #define CACHESIZE 0x0000003ful /* only 5 bits */ 661 #define LATTIME 0x0000ff00ul 662 663 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 664 uint16_t subvendor, uint16_t subdevice); 665 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 666 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 667 int pcheck, int fast, int large); 668 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 669 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 670 static void configure_termination(struct ahc_softc *ahc, 671 struct seeprom_descriptor *sd, 672 u_int adapter_control, 673 u_int *sxfrctl1); 674 675 static void ahc_new_term_detect(struct ahc_softc *ahc, 676 int *enableSEC_low, 677 int *enableSEC_high, 678 int *enablePRI_low, 679 int *enablePRI_high, 680 int *eeprom_present); 681 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 682 int *internal68_present, 683 int *externalcable_present, 684 int *eeprom_present); 685 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 686 int *externalcable_present, 687 int *eeprom_present); 688 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 689 static uint8_t read_brdctl(struct ahc_softc *ahc); 690 691 static int 692 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 693 uint16_t subdevice, uint16_t subvendor) 694 { 695 int result; 696 697 /* Default to invalid. */ 698 result = 0; 699 if (vendor == 0x9005 700 && subvendor == 0x9005 701 && subdevice != device 702 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 703 704 switch (SUBID_9005_TYPE(subdevice)) { 705 case SUBID_9005_TYPE_MB: 706 break; 707 case SUBID_9005_TYPE_CARD: 708 case SUBID_9005_TYPE_LCCARD: 709 /* 710 * Currently only trust Adaptec cards to 711 * get the sub device info correct. 712 */ 713 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 714 result = 1; 715 break; 716 case SUBID_9005_TYPE_RAID: 717 break; 718 default: 719 break; 720 } 721 } 722 return (result); 723 } 724 725 struct ahc_pci_identity * 726 ahc_find_pci_device(ahc_dev_softc_t pci) 727 { 728 uint64_t full_id; 729 uint16_t device; 730 uint16_t vendor; 731 uint16_t subdevice; 732 uint16_t subvendor; 733 struct ahc_pci_identity *entry; 734 u_int i; 735 736 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 737 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 738 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 739 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 740 full_id = ahc_compose_id(device, 741 vendor, 742 subdevice, 743 subvendor); 744 745 /* 746 * If the second function is not hooked up, ignore it. 747 * Unfortunately, not all MB vendors implement the 748 * subdevice ID as per the Adaptec spec, so do our best 749 * to sanity check it prior to accepting the subdevice 750 * ID as valid. 751 */ 752 if (ahc_get_pci_function(pci) > 0 753 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 754 && SUBID_9005_MFUNCENB(subdevice) == 0) 755 return (NULL); 756 757 for (i = 0; i < ahc_num_pci_devs; i++) { 758 entry = &ahc_pci_ident_table[i]; 759 if (entry->full_id == (full_id & entry->id_mask)) { 760 /* Honor exclusion entries. */ 761 if (entry->name == NULL) 762 return (NULL); 763 return (entry); 764 } 765 } 766 return (NULL); 767 } 768 769 int 770 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 771 { 772 struct scb_data *shared_scb_data; 773 u_int command; 774 u_int our_id = 0; 775 u_int sxfrctl1; 776 u_int scsiseq; 777 u_int dscommand0; 778 int error; 779 uint8_t sblkctl; 780 781 shared_scb_data = NULL; 782 error = entry->setup(ahc); 783 if (error != 0) 784 return (error); 785 ahc->chip |= AHC_PCI; 786 ahc->description = entry->name; 787 788 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 789 790 error = ahc_pci_map_registers(ahc); 791 if (error != 0) 792 return (error); 793 794 /* 795 * Before we continue probing the card, ensure that 796 * its interrupts are *disabled*. We don't want 797 * a misstep to hang the machine in an interrupt 798 * storm. 799 */ 800 ahc_intr_enable(ahc, FALSE); 801 802 /* 803 * If we need to support high memory, enable dual 804 * address cycles. This bit must be set to enable 805 * high address bit generation even if we are on a 806 * 64bit bus (PCI64BIT set in devconfig). 807 */ 808 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 809 uint32_t devconfig; 810 811 if (bootverbose) 812 printf("%s: Enabling 39Bit Addressing\n", 813 ahc_name(ahc)); 814 devconfig = ahc_pci_read_config(ahc->dev_softc, 815 DEVCONFIG, /*bytes*/4); 816 devconfig |= DACEN; 817 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 818 devconfig, /*bytes*/4); 819 } 820 821 /* Ensure busmastering is enabled */ 822 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 823 command |= PCIM_CMD_BUSMASTEREN; 824 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 825 826 /* On all PCI adapters, we allow SCB paging */ 827 ahc->flags |= AHC_PAGESCBS; 828 829 error = ahc_softc_init(ahc); 830 if (error != 0) 831 return (error); 832 833 ahc->bus_intr = ahc_pci_intr; 834 835 /* Remeber how the card was setup in case there is no SEEPROM */ 836 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 837 ahc_pause(ahc); 838 if ((ahc->features & AHC_ULTRA2) != 0) 839 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 840 else 841 our_id = ahc_inb(ahc, SCSIID) & OID; 842 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 843 scsiseq = ahc_inb(ahc, SCSISEQ); 844 } else { 845 sxfrctl1 = STPWEN; 846 our_id = 7; 847 scsiseq = 0; 848 } 849 850 error = ahc_reset(ahc); 851 if (error != 0) 852 return (ENXIO); 853 854 if ((ahc->features & AHC_DT) != 0) { 855 u_int sfunct; 856 857 /* Perform ALT-Mode Setup */ 858 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 859 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 860 ahc_outb(ahc, OPTIONMODE, 861 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 862 ahc_outb(ahc, SFUNCT, sfunct); 863 864 /* Normal mode setup */ 865 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 866 |TARGCRCENDEN); 867 } 868 869 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 870 dscommand0 |= MPARCKEN|CACHETHEN; 871 if ((ahc->features & AHC_ULTRA2) != 0) { 872 873 /* 874 * DPARCKEN doesn't work correctly on 875 * some MBs so don't use it. 876 */ 877 dscommand0 &= ~DPARCKEN; 878 } 879 880 /* 881 * Handle chips that must have cache line 882 * streaming (dis/en)abled. 883 */ 884 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 885 dscommand0 |= CACHETHEN; 886 887 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 888 dscommand0 &= ~CACHETHEN; 889 890 ahc_outb(ahc, DSCOMMAND0, dscommand0); 891 892 ahc->pci_cachesize = 893 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 894 /*bytes*/1) & CACHESIZE; 895 ahc->pci_cachesize *= 4; 896 897 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 898 && ahc->pci_cachesize == 4) { 899 900 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 901 0, /*bytes*/1); 902 ahc->pci_cachesize = 0; 903 } 904 905 /* 906 * We cannot perform ULTRA speeds without the presense 907 * of the external precision resistor. 908 */ 909 if ((ahc->features & AHC_ULTRA) != 0) { 910 uint32_t devconfig; 911 912 devconfig = ahc_pci_read_config(ahc->dev_softc, 913 DEVCONFIG, /*bytes*/4); 914 if ((devconfig & REXTVALID) == 0) 915 ahc->features &= ~AHC_ULTRA; 916 } 917 918 /* See if we have a SEEPROM and perform auto-term */ 919 check_extport(ahc, &sxfrctl1); 920 921 /* 922 * Take the LED out of diagnostic mode 923 */ 924 sblkctl = ahc_inb(ahc, SBLKCTL); 925 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 926 927 if ((ahc->features & AHC_ULTRA2) != 0) { 928 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 929 } else { 930 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 931 } 932 933 if (ahc->flags & AHC_USEDEFAULTS) { 934 /* 935 * PCI Adapter default setup 936 * Should only be used if the adapter does not have 937 * a SEEPROM. 938 */ 939 /* See if someone else set us up already */ 940 if (scsiseq != 0) { 941 printf("%s: Using left over BIOS settings\n", 942 ahc_name(ahc)); 943 ahc->flags &= ~AHC_USEDEFAULTS; 944 ahc->flags |= AHC_BIOS_ENABLED; 945 } else { 946 /* 947 * Assume only one connector and always turn 948 * on termination. 949 */ 950 our_id = 0x07; 951 sxfrctl1 = STPWEN; 952 } 953 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 954 955 ahc->our_id = our_id; 956 } 957 958 /* 959 * Take a look to see if we have external SRAM. 960 * We currently do not attempt to use SRAM that is 961 * shared among multiple controllers. 962 */ 963 ahc_probe_ext_scbram(ahc); 964 965 /* 966 * Record our termination setting for the 967 * generic initialization routine. 968 */ 969 if ((sxfrctl1 & STPWEN) != 0) 970 ahc->flags |= AHC_TERM_ENB_A; 971 972 /* Core initialization */ 973 error = ahc_init(ahc); 974 if (error != 0) 975 return (error); 976 977 /* 978 * Link this softc in with all other ahc instances. 979 */ 980 ahc_softc_insert(ahc); 981 982 /* 983 * Allow interrupts now that we are completely setup. 984 */ 985 error = ahc_pci_map_int(ahc); 986 if (error != 0) 987 return (error); 988 989 ahc_intr_enable(ahc, TRUE); 990 991 return (0); 992 } 993 994 /* 995 * Test for the presense of external sram in an 996 * "unshared" configuration. 997 */ 998 static int 999 ahc_ext_scbram_present(struct ahc_softc *ahc) 1000 { 1001 u_int chip; 1002 int ramps; 1003 int single_user; 1004 uint32_t devconfig; 1005 1006 chip = ahc->chip & AHC_CHIPID_MASK; 1007 devconfig = ahc_pci_read_config(ahc->dev_softc, 1008 DEVCONFIG, /*bytes*/4); 1009 single_user = (devconfig & MPORTMODE) != 0; 1010 1011 if ((ahc->features & AHC_ULTRA2) != 0) 1012 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1013 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1014 /* 1015 * External SCBRAM arbitration is flakey 1016 * on these chips. Unfortunately this means 1017 * we don't use the extra SCB ram space on the 1018 * 3940AUW. 1019 */ 1020 ramps = 0; 1021 else if (chip >= AHC_AIC7870) 1022 ramps = (devconfig & RAMPSM) != 0; 1023 else 1024 ramps = 0; 1025 1026 if (ramps && single_user) 1027 return (1); 1028 return (0); 1029 } 1030 1031 /* 1032 * Enable external scbram. 1033 */ 1034 static void 1035 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1036 int fast, int large) 1037 { 1038 uint32_t devconfig; 1039 1040 if (ahc->features & AHC_MULTI_FUNC) { 1041 /* 1042 * Set the SCB Base addr (highest address bit) 1043 * depending on which channel we are. 1044 */ 1045 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1046 } 1047 1048 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1049 if ((ahc->features & AHC_ULTRA2) != 0) { 1050 u_int dscommand0; 1051 1052 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1053 if (enable) 1054 dscommand0 &= ~INTSCBRAMSEL; 1055 else 1056 dscommand0 |= INTSCBRAMSEL; 1057 if (large) 1058 dscommand0 &= ~USCBSIZE32; 1059 else 1060 dscommand0 |= USCBSIZE32; 1061 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1062 } else { 1063 if (fast) 1064 devconfig &= ~EXTSCBTIME; 1065 else 1066 devconfig |= EXTSCBTIME; 1067 if (enable) 1068 devconfig &= ~SCBRAMSEL; 1069 else 1070 devconfig |= SCBRAMSEL; 1071 if (large) 1072 devconfig &= ~SCBSIZE32; 1073 else 1074 devconfig |= SCBSIZE32; 1075 } 1076 if (pcheck) 1077 devconfig |= EXTSCBPEN; 1078 else 1079 devconfig &= ~EXTSCBPEN; 1080 1081 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1082 } 1083 1084 /* 1085 * Take a look to see if we have external SRAM. 1086 * We currently do not attempt to use SRAM that is 1087 * shared among multiple controllers. 1088 */ 1089 static void 1090 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1091 { 1092 int num_scbs; 1093 int test_num_scbs; 1094 int enable; 1095 int pcheck; 1096 int fast; 1097 int large; 1098 1099 enable = FALSE; 1100 pcheck = FALSE; 1101 fast = FALSE; 1102 large = FALSE; 1103 num_scbs = 0; 1104 1105 if (ahc_ext_scbram_present(ahc) == 0) 1106 goto done; 1107 1108 /* 1109 * Probe for the best parameters to use. 1110 */ 1111 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1112 num_scbs = ahc_probe_scbs(ahc); 1113 if (num_scbs == 0) { 1114 /* The SRAM wasn't really present. */ 1115 goto done; 1116 } 1117 enable = TRUE; 1118 1119 /* 1120 * Clear any outstanding parity error 1121 * and ensure that parity error reporting 1122 * is enabled. 1123 */ 1124 ahc_outb(ahc, SEQCTL, 0); 1125 ahc_outb(ahc, CLRINT, CLRPARERR); 1126 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1127 1128 /* Now see if we can do parity */ 1129 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1130 num_scbs = ahc_probe_scbs(ahc); 1131 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1132 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1133 pcheck = TRUE; 1134 1135 /* Clear any resulting parity error */ 1136 ahc_outb(ahc, CLRINT, CLRPARERR); 1137 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1138 1139 /* Now see if we can do fast timing */ 1140 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1141 test_num_scbs = ahc_probe_scbs(ahc); 1142 if (test_num_scbs == num_scbs 1143 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1144 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1145 fast = TRUE; 1146 1147 /* 1148 * See if we can use large SCBs and still maintain 1149 * the same overall count of SCBs. 1150 */ 1151 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1152 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1153 test_num_scbs = ahc_probe_scbs(ahc); 1154 if (test_num_scbs >= num_scbs) { 1155 large = TRUE; 1156 num_scbs = test_num_scbs; 1157 if (num_scbs >= 64) { 1158 /* 1159 * We have enough space to move the 1160 * "busy targets table" into SCB space 1161 * and make it qualify all the way to the 1162 * lun level. 1163 */ 1164 ahc->flags |= AHC_SCB_BTT; 1165 } 1166 } 1167 } 1168 done: 1169 /* 1170 * Disable parity error reporting until we 1171 * can load instruction ram. 1172 */ 1173 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1174 /* Clear any latched parity error */ 1175 ahc_outb(ahc, CLRINT, CLRPARERR); 1176 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1177 if (bootverbose && enable) { 1178 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1179 ahc_name(ahc), fast ? "fast" : "slow", 1180 pcheck ? ", parity checking enabled" : "", 1181 large ? 64 : 32); 1182 } 1183 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1184 } 1185 1186 /* 1187 * Check the external port logic for a serial eeprom 1188 * and termination/cable detection contrls. 1189 */ 1190 static void 1191 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1192 { 1193 struct seeprom_descriptor sd; 1194 struct seeprom_config sc; 1195 u_int scsi_conf; 1196 u_int adapter_control; 1197 int have_seeprom; 1198 int have_autoterm; 1199 1200 sd.sd_ahc = ahc; 1201 sd.sd_control_offset = SEECTL; 1202 sd.sd_status_offset = SEECTL; 1203 sd.sd_dataout_offset = SEECTL; 1204 1205 /* 1206 * For some multi-channel devices, the c46 is simply too 1207 * small to work. For the other controller types, we can 1208 * get our information from either SEEPROM type. Set the 1209 * type to start our probe with accordingly. 1210 */ 1211 if (ahc->flags & AHC_LARGE_SEEPROM) 1212 sd.sd_chip = C56_66; 1213 else 1214 sd.sd_chip = C46; 1215 1216 sd.sd_MS = SEEMS; 1217 sd.sd_RDY = SEERDY; 1218 sd.sd_CS = SEECS; 1219 sd.sd_CK = SEECK; 1220 sd.sd_DO = SEEDO; 1221 sd.sd_DI = SEEDI; 1222 1223 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1224 if (have_seeprom) { 1225 1226 if (bootverbose) 1227 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1228 1229 for (;;) { 1230 u_int start_addr; 1231 1232 start_addr = 32 * (ahc->channel - 'A'); 1233 1234 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)&sc, 1235 start_addr, 1236 sizeof(sc)/2); 1237 1238 if (have_seeprom) 1239 have_seeprom = ahc_verify_cksum(&sc); 1240 1241 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1242 if (bootverbose) { 1243 if (have_seeprom == 0) 1244 printf ("checksum error\n"); 1245 else 1246 printf ("done.\n"); 1247 } 1248 break; 1249 } 1250 sd.sd_chip = C56_66; 1251 } 1252 ahc_release_seeprom(&sd); 1253 } 1254 1255 if (!have_seeprom) { 1256 /* 1257 * Pull scratch ram settings and treat them as 1258 * if they are the contents of an seeprom if 1259 * the 'ADPT' signature is found in SCB2. 1260 * We manually compose the data as 16bit values 1261 * to avoid endian issues. 1262 */ 1263 ahc_outb(ahc, SCBPTR, 2); 1264 if (ahc_inb(ahc, SCB_BASE) == 'A' 1265 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1266 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1267 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1268 uint16_t *sc_data; 1269 int i; 1270 1271 sc_data = (uint16_t *)≻ 1272 for (i = 0; i < 32; i++) { 1273 uint16_t val; 1274 int j; 1275 1276 j = i * 2; 1277 val = ahc_inb(ahc, SRAM_BASE + j) 1278 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1279 } 1280 have_seeprom = ahc_verify_cksum(&sc); 1281 } 1282 /* 1283 * Clear any SCB parity errors in case this data and 1284 * its associated parity was not initialized by the BIOS 1285 */ 1286 ahc_outb(ahc, CLRINT, CLRPARERR); 1287 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1288 } 1289 1290 if (!have_seeprom) { 1291 if (bootverbose) 1292 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1293 ahc->flags |= AHC_USEDEFAULTS; 1294 } else { 1295 /* 1296 * Put the data we've collected down into SRAM 1297 * where ahc_init will find it. 1298 */ 1299 int i; 1300 int max_targ = sc.max_targets & CFMAXTARG; 1301 uint16_t discenable; 1302 uint16_t ultraenb; 1303 1304 discenable = 0; 1305 ultraenb = 0; 1306 if ((sc.adapter_control & CFULTRAEN) != 0) { 1307 /* 1308 * Determine if this adapter has a "newstyle" 1309 * SEEPROM format. 1310 */ 1311 for (i = 0; i < max_targ; i++) { 1312 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1313 ahc->flags |= AHC_NEWEEPROM_FMT; 1314 break; 1315 } 1316 } 1317 } 1318 1319 for (i = 0; i < max_targ; i++) { 1320 u_int scsirate; 1321 uint16_t target_mask; 1322 1323 target_mask = 0x01 << i; 1324 if (sc.device_flags[i] & CFDISC) 1325 discenable |= target_mask; 1326 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1327 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1328 ultraenb |= target_mask; 1329 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1330 ultraenb |= target_mask; 1331 } 1332 if ((sc.device_flags[i] & CFXFER) == 0x04 1333 && (ultraenb & target_mask) != 0) { 1334 /* Treat 10MHz as a non-ultra speed */ 1335 sc.device_flags[i] &= ~CFXFER; 1336 ultraenb &= ~target_mask; 1337 } 1338 if ((ahc->features & AHC_ULTRA2) != 0) { 1339 u_int offset; 1340 1341 if (sc.device_flags[i] & CFSYNCH) 1342 offset = MAX_OFFSET_ULTRA2; 1343 else 1344 offset = 0; 1345 ahc_outb(ahc, TARG_OFFSET + i, offset); 1346 1347 /* 1348 * The ultra enable bits contain the 1349 * high bit of the ultra2 sync rate 1350 * field. 1351 */ 1352 scsirate = (sc.device_flags[i] & CFXFER) 1353 | ((ultraenb & target_mask) 1354 ? 0x8 : 0x0); 1355 if (sc.device_flags[i] & CFWIDEB) 1356 scsirate |= WIDEXFER; 1357 } else { 1358 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1359 if (sc.device_flags[i] & CFSYNCH) 1360 scsirate |= SOFS; 1361 if (sc.device_flags[i] & CFWIDEB) 1362 scsirate |= WIDEXFER; 1363 } 1364 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1365 } 1366 ahc->our_id = sc.brtime_id & CFSCSIID; 1367 1368 scsi_conf = (ahc->our_id & 0x7); 1369 if (sc.adapter_control & CFSPARITY) 1370 scsi_conf |= ENSPCHK; 1371 if (sc.adapter_control & CFRESETB) 1372 scsi_conf |= RESET_SCSI; 1373 1374 ahc->flags |= 1375 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1376 1377 if (sc.bios_control & CFEXTEND) 1378 ahc->flags |= AHC_EXTENDED_TRANS_A; 1379 1380 if (sc.bios_control & CFBIOSEN) 1381 ahc->flags |= AHC_BIOS_ENABLED; 1382 if (ahc->features & AHC_ULTRA 1383 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1384 /* Should we enable Ultra mode? */ 1385 if (!(sc.adapter_control & CFULTRAEN)) 1386 /* Treat us as a non-ultra card */ 1387 ultraenb = 0; 1388 } 1389 1390 if (sc.signature == CFSIGNATURE 1391 || sc.signature == CFSIGNATURE2) { 1392 uint32_t devconfig; 1393 1394 /* Honor the STPWLEVEL settings */ 1395 devconfig = ahc_pci_read_config(ahc->dev_softc, 1396 DEVCONFIG, /*bytes*/4); 1397 devconfig &= ~STPWLEVEL; 1398 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1399 devconfig |= STPWLEVEL; 1400 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1401 devconfig, /*bytes*/4); 1402 } 1403 /* Set SCSICONF info */ 1404 ahc_outb(ahc, SCSICONF, scsi_conf); 1405 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1406 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1407 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1408 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1409 } 1410 1411 /* 1412 * Cards that have the external logic necessary to talk to 1413 * a SEEPROM, are almost certain to have the remaining logic 1414 * necessary for auto-termination control. This assumption 1415 * hasn't failed yet... 1416 */ 1417 have_autoterm = have_seeprom; 1418 if (have_seeprom) 1419 adapter_control = sc.adapter_control; 1420 else 1421 adapter_control = CFAUTOTERM; 1422 1423 /* 1424 * Some low-cost chips have SEEPROM and auto-term control built 1425 * in, instead of using a GAL. They can tell us directly 1426 * if the termination logic is enabled. 1427 */ 1428 if ((ahc->features & AHC_SPIOCAP) != 0) { 1429 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1430 have_autoterm = TRUE; 1431 else 1432 have_autoterm = FALSE; 1433 } 1434 1435 if (have_autoterm) { 1436 ahc_acquire_seeprom(ahc, &sd); 1437 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1438 ahc_release_seeprom(&sd); 1439 } 1440 } 1441 1442 static void 1443 configure_termination(struct ahc_softc *ahc, 1444 struct seeprom_descriptor *sd, 1445 u_int adapter_control, 1446 u_int *sxfrctl1) 1447 { 1448 uint8_t brddat; 1449 1450 brddat = 0; 1451 1452 /* 1453 * Update the settings in sxfrctl1 to match the 1454 * termination settings 1455 */ 1456 *sxfrctl1 = 0; 1457 1458 /* 1459 * SEECS must be on for the GALS to latch 1460 * the data properly. Be sure to leave MS 1461 * on or we will release the seeprom. 1462 */ 1463 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1464 if ((adapter_control & CFAUTOTERM) != 0 1465 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1466 int internal50_present; 1467 int internal68_present; 1468 int externalcable_present; 1469 int eeprom_present; 1470 int enableSEC_low; 1471 int enableSEC_high; 1472 int enablePRI_low; 1473 int enablePRI_high; 1474 int sum; 1475 1476 enableSEC_low = 0; 1477 enableSEC_high = 0; 1478 enablePRI_low = 0; 1479 enablePRI_high = 0; 1480 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1481 ahc_new_term_detect(ahc, &enableSEC_low, 1482 &enableSEC_high, 1483 &enablePRI_low, 1484 &enablePRI_high, 1485 &eeprom_present); 1486 if ((adapter_control & CFSEAUTOTERM) == 0) { 1487 if (bootverbose) 1488 printf("%s: Manual SE Termination\n", 1489 ahc_name(ahc)); 1490 enableSEC_low = (adapter_control & CFSELOWTERM); 1491 enableSEC_high = 1492 (adapter_control & CFSEHIGHTERM); 1493 } 1494 if ((adapter_control & CFAUTOTERM) == 0) { 1495 if (bootverbose) 1496 printf("%s: Manual LVD Termination\n", 1497 ahc_name(ahc)); 1498 enablePRI_low = (adapter_control & CFSTERM); 1499 enablePRI_high = (adapter_control & CFWSTERM); 1500 } 1501 /* Make the table calculations below happy */ 1502 internal50_present = 0; 1503 internal68_present = 1; 1504 externalcable_present = 1; 1505 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1506 aic785X_cable_detect(ahc, &internal50_present, 1507 &externalcable_present, 1508 &eeprom_present); 1509 } else { 1510 aic787X_cable_detect(ahc, &internal50_present, 1511 &internal68_present, 1512 &externalcable_present, 1513 &eeprom_present); 1514 } 1515 1516 if ((ahc->features & AHC_WIDE) == 0) 1517 internal68_present = 0; 1518 1519 if (bootverbose 1520 && (ahc->features & AHC_ULTRA2) == 0) { 1521 printf("%s: internal 50 cable %s present", 1522 ahc_name(ahc), 1523 internal50_present ? "is":"not"); 1524 1525 if ((ahc->features & AHC_WIDE) != 0) 1526 printf(", internal 68 cable %s present", 1527 internal68_present ? "is":"not"); 1528 printf("\n%s: external cable %s present\n", 1529 ahc_name(ahc), 1530 externalcable_present ? "is":"not"); 1531 } 1532 if (bootverbose) 1533 printf("%s: BIOS eeprom %s present\n", 1534 ahc_name(ahc), eeprom_present ? "is" : "not"); 1535 1536 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1537 /* 1538 * The 50 pin connector is a separate bus, 1539 * so force it to always be terminated. 1540 * In the future, perform current sensing 1541 * to determine if we are in the middle of 1542 * a properly terminated bus. 1543 */ 1544 internal50_present = 0; 1545 } 1546 1547 /* 1548 * Now set the termination based on what 1549 * we found. 1550 * Flash Enable = BRDDAT7 1551 * Secondary High Term Enable = BRDDAT6 1552 * Secondary Low Term Enable = BRDDAT5 (7890) 1553 * Primary High Term Enable = BRDDAT4 (7890) 1554 */ 1555 if ((ahc->features & AHC_ULTRA2) == 0 1556 && (internal50_present != 0) 1557 && (internal68_present != 0) 1558 && (externalcable_present != 0)) { 1559 printf("%s: Illegal cable configuration!!. " 1560 "Only two connectors on the " 1561 "adapter may be used at a " 1562 "time!\n", ahc_name(ahc)); 1563 1564 /* 1565 * Pretend there are no cables in the hope 1566 * that having all of the termination on 1567 * gives us a more stable bus. 1568 */ 1569 internal50_present = 0; 1570 internal68_present = 0; 1571 externalcable_present = 0; 1572 } 1573 1574 if ((ahc->features & AHC_WIDE) != 0 1575 && ((externalcable_present == 0) 1576 || (internal68_present == 0) 1577 || (enableSEC_high != 0))) { 1578 brddat |= BRDDAT6; 1579 if (bootverbose) { 1580 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1581 printf("%s: 68 pin termination " 1582 "Enabled\n", ahc_name(ahc)); 1583 else 1584 printf("%s: %sHigh byte termination " 1585 "Enabled\n", ahc_name(ahc), 1586 enableSEC_high ? "Secondary " 1587 : ""); 1588 } 1589 } 1590 1591 sum = internal50_present + internal68_present 1592 + externalcable_present; 1593 if (sum < 2 || (enableSEC_low != 0)) { 1594 if ((ahc->features & AHC_ULTRA2) != 0) 1595 brddat |= BRDDAT5; 1596 else 1597 *sxfrctl1 |= STPWEN; 1598 if (bootverbose) { 1599 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1600 printf("%s: 50 pin termination " 1601 "Enabled\n", ahc_name(ahc)); 1602 else 1603 printf("%s: %sLow byte termination " 1604 "Enabled\n", ahc_name(ahc), 1605 enableSEC_low ? "Secondary " 1606 : ""); 1607 } 1608 } 1609 1610 if (enablePRI_low != 0) { 1611 *sxfrctl1 |= STPWEN; 1612 if (bootverbose) 1613 printf("%s: Primary Low Byte termination " 1614 "Enabled\n", ahc_name(ahc)); 1615 } 1616 1617 /* 1618 * Setup STPWEN before setting up the rest of 1619 * the termination per the tech note on the U160 cards. 1620 */ 1621 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1622 1623 if (enablePRI_high != 0) { 1624 brddat |= BRDDAT4; 1625 if (bootverbose) 1626 printf("%s: Primary High Byte " 1627 "termination Enabled\n", 1628 ahc_name(ahc)); 1629 } 1630 1631 write_brdctl(ahc, brddat); 1632 1633 } else { 1634 if ((adapter_control & CFSTERM) != 0) { 1635 *sxfrctl1 |= STPWEN; 1636 1637 if (bootverbose) 1638 printf("%s: %sLow byte termination Enabled\n", 1639 ahc_name(ahc), 1640 (ahc->features & AHC_ULTRA2) ? "Primary " 1641 : ""); 1642 } 1643 1644 if ((adapter_control & CFWSTERM) != 0 1645 && (ahc->features & AHC_WIDE) != 0) { 1646 brddat |= BRDDAT6; 1647 if (bootverbose) 1648 printf("%s: %sHigh byte termination Enabled\n", 1649 ahc_name(ahc), 1650 (ahc->features & AHC_ULTRA2) 1651 ? "Secondary " : ""); 1652 } 1653 1654 /* 1655 * Setup STPWEN before setting up the rest of 1656 * the termination per the tech note on the U160 cards. 1657 */ 1658 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1659 1660 if ((ahc->features & AHC_WIDE) != 0) 1661 write_brdctl(ahc, brddat); 1662 } 1663 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1664 } 1665 1666 static void 1667 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1668 int *enableSEC_high, int *enablePRI_low, 1669 int *enablePRI_high, int *eeprom_present) 1670 { 1671 uint8_t brdctl; 1672 1673 /* 1674 * BRDDAT7 = Eeprom 1675 * BRDDAT6 = Enable Secondary High Byte termination 1676 * BRDDAT5 = Enable Secondary Low Byte termination 1677 * BRDDAT4 = Enable Primary high byte termination 1678 * BRDDAT3 = Enable Primary low byte termination 1679 */ 1680 brdctl = read_brdctl(ahc); 1681 *eeprom_present = brdctl & BRDDAT7; 1682 *enableSEC_high = (brdctl & BRDDAT6); 1683 *enableSEC_low = (brdctl & BRDDAT5); 1684 *enablePRI_high = (brdctl & BRDDAT4); 1685 *enablePRI_low = (brdctl & BRDDAT3); 1686 } 1687 1688 static void 1689 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1690 int *internal68_present, int *externalcable_present, 1691 int *eeprom_present) 1692 { 1693 uint8_t brdctl; 1694 1695 /* 1696 * First read the status of our cables. 1697 * Set the rom bank to 0 since the 1698 * bank setting serves as a multiplexor 1699 * for the cable detection logic. 1700 * BRDDAT5 controls the bank switch. 1701 */ 1702 write_brdctl(ahc, 0); 1703 1704 /* 1705 * Now read the state of the internal 1706 * connectors. BRDDAT6 is INT50 and 1707 * BRDDAT7 is INT68. 1708 */ 1709 brdctl = read_brdctl(ahc); 1710 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1711 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1712 1713 /* 1714 * Set the rom bank to 1 and determine 1715 * the other signals. 1716 */ 1717 write_brdctl(ahc, BRDDAT5); 1718 1719 /* 1720 * Now read the state of the external 1721 * connectors. BRDDAT6 is EXT68 and 1722 * BRDDAT7 is EPROMPS. 1723 */ 1724 brdctl = read_brdctl(ahc); 1725 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1726 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1727 } 1728 1729 static void 1730 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1731 int *externalcable_present, int *eeprom_present) 1732 { 1733 uint8_t brdctl; 1734 1735 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1736 ahc_outb(ahc, BRDCTL, 0); 1737 brdctl = ahc_inb(ahc, BRDCTL); 1738 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1739 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1740 1741 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1742 } 1743 1744 int 1745 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1746 { 1747 int wait; 1748 1749 if ((ahc->features & AHC_SPIOCAP) != 0 1750 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1751 return (0); 1752 1753 /* 1754 * Request access of the memory port. When access is 1755 * granted, SEERDY will go high. We use a 1 second 1756 * timeout which should be near 1 second more than 1757 * is needed. Reason: after the chip reset, there 1758 * should be no contention. 1759 */ 1760 SEEPROM_OUTB(sd, sd->sd_MS); 1761 wait = 1000; /* 1 second timeout in msec */ 1762 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1763 ahc_delay(1000); /* delay 1 msec */ 1764 } 1765 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1766 SEEPROM_OUTB(sd, 0); 1767 return (0); 1768 } 1769 return(1); 1770 } 1771 1772 void 1773 ahc_release_seeprom(struct seeprom_descriptor *sd) 1774 { 1775 /* Release access to the memory port and the serial EEPROM. */ 1776 SEEPROM_OUTB(sd, 0); 1777 } 1778 1779 static void 1780 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1781 { 1782 uint8_t brdctl; 1783 1784 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1785 brdctl = BRDSTB; 1786 if (ahc->channel == 'B') 1787 brdctl |= BRDCS; 1788 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1789 brdctl = 0; 1790 } else { 1791 brdctl = BRDSTB|BRDCS; 1792 } 1793 ahc_outb(ahc, BRDCTL, brdctl); 1794 ahc_flush_device_writes(ahc); 1795 brdctl |= value; 1796 ahc_outb(ahc, BRDCTL, brdctl); 1797 ahc_flush_device_writes(ahc); 1798 if ((ahc->features & AHC_ULTRA2) != 0) 1799 brdctl |= BRDSTB_ULTRA2; 1800 else 1801 brdctl &= ~BRDSTB; 1802 ahc_outb(ahc, BRDCTL, brdctl); 1803 ahc_flush_device_writes(ahc); 1804 if ((ahc->features & AHC_ULTRA2) != 0) 1805 brdctl = 0; 1806 else 1807 brdctl &= ~BRDCS; 1808 ahc_outb(ahc, BRDCTL, brdctl); 1809 } 1810 1811 static uint8_t 1812 read_brdctl(ahc) 1813 struct ahc_softc *ahc; 1814 { 1815 uint8_t brdctl; 1816 uint8_t value; 1817 1818 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1819 brdctl = BRDRW; 1820 if (ahc->channel == 'B') 1821 brdctl |= BRDCS; 1822 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1823 brdctl = BRDRW_ULTRA2; 1824 } else { 1825 brdctl = BRDRW|BRDCS; 1826 } 1827 ahc_outb(ahc, BRDCTL, brdctl); 1828 ahc_flush_device_writes(ahc); 1829 value = ahc_inb(ahc, BRDCTL); 1830 ahc_outb(ahc, BRDCTL, 0); 1831 return (value); 1832 } 1833 1834 #define DPE 0x80 1835 #define SSE 0x40 1836 #define RMA 0x20 1837 #define RTA 0x10 1838 #define STA 0x08 1839 #define DPR 0x01 1840 1841 void 1842 ahc_pci_intr(struct ahc_softc *ahc) 1843 { 1844 u_int error; 1845 u_int status1; 1846 1847 error = ahc_inb(ahc, ERROR); 1848 if ((error & PCIERRSTAT) == 0) 1849 return; 1850 1851 status1 = ahc_pci_read_config(ahc->dev_softc, 1852 PCIR_STATUS + 1, /*bytes*/1); 1853 1854 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1855 ahc_name(ahc), 1856 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1857 1858 if (status1 & DPE) { 1859 printf("%s: Data Parity Error Detected during address " 1860 "or write data phase\n", ahc_name(ahc)); 1861 } 1862 if (status1 & SSE) { 1863 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1864 } 1865 if (status1 & RMA) { 1866 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1867 } 1868 if (status1 & RTA) { 1869 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1870 } 1871 if (status1 & STA) { 1872 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1873 } 1874 if (status1 & DPR) { 1875 printf("%s: Data Parity Error has been reported via PERR#\n", 1876 ahc_name(ahc)); 1877 } 1878 1879 /* Clear latched errors. */ 1880 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1881 status1, /*bytes*/1); 1882 1883 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1884 printf("%s: Latched PCIERR interrupt with " 1885 "no status bits set\n", ahc_name(ahc)); 1886 } else { 1887 ahc_outb(ahc, CLRINT, CLRPARERR); 1888 } 1889 1890 ahc_unpause(ahc); 1891 } 1892 1893 static int 1894 ahc_aic785X_setup(struct ahc_softc *ahc) 1895 { 1896 ahc_dev_softc_t pci; 1897 uint8_t rev; 1898 1899 pci = ahc->dev_softc; 1900 ahc->channel = 'A'; 1901 ahc->chip = AHC_AIC7850; 1902 ahc->features = AHC_AIC7850_FE; 1903 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1904 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1905 if (rev >= 1) 1906 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1907 return (0); 1908 } 1909 1910 static int 1911 ahc_aic7860_setup(struct ahc_softc *ahc) 1912 { 1913 ahc_dev_softc_t pci; 1914 uint8_t rev; 1915 1916 pci = ahc->dev_softc; 1917 ahc->channel = 'A'; 1918 ahc->chip = AHC_AIC7860; 1919 ahc->features = AHC_AIC7860_FE; 1920 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1921 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1922 if (rev >= 1) 1923 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1924 return (0); 1925 } 1926 1927 static int 1928 ahc_apa1480_setup(struct ahc_softc *ahc) 1929 { 1930 ahc_dev_softc_t pci; 1931 int error; 1932 1933 pci = ahc->dev_softc; 1934 error = ahc_aic7860_setup(ahc); 1935 if (error != 0) 1936 return (error); 1937 ahc->features |= AHC_REMOVABLE; 1938 return (0); 1939 } 1940 1941 static int 1942 ahc_aic7870_setup(struct ahc_softc *ahc) 1943 { 1944 ahc_dev_softc_t pci; 1945 1946 pci = ahc->dev_softc; 1947 ahc->channel = 'A'; 1948 ahc->chip = AHC_AIC7870; 1949 ahc->features = AHC_AIC7870_FE; 1950 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1951 return (0); 1952 } 1953 1954 static int 1955 ahc_aha394X_setup(struct ahc_softc *ahc) 1956 { 1957 int error; 1958 1959 error = ahc_aic7870_setup(ahc); 1960 if (error == 0) 1961 error = ahc_aha394XX_setup(ahc); 1962 return (error); 1963 } 1964 1965 static int 1966 ahc_aha398X_setup(struct ahc_softc *ahc) 1967 { 1968 int error; 1969 1970 error = ahc_aic7870_setup(ahc); 1971 if (error == 0) 1972 error = ahc_aha398XX_setup(ahc); 1973 return (error); 1974 } 1975 1976 static int 1977 ahc_aha494X_setup(struct ahc_softc *ahc) 1978 { 1979 int error; 1980 1981 error = ahc_aic7870_setup(ahc); 1982 if (error == 0) 1983 error = ahc_aha494XX_setup(ahc); 1984 return (error); 1985 } 1986 1987 static int 1988 ahc_aic7880_setup(struct ahc_softc *ahc) 1989 { 1990 ahc_dev_softc_t pci; 1991 uint8_t rev; 1992 1993 pci = ahc->dev_softc; 1994 ahc->channel = 'A'; 1995 ahc->chip = AHC_AIC7880; 1996 ahc->features = AHC_AIC7880_FE; 1997 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1998 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1999 if (rev >= 1) { 2000 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2001 } else { 2002 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2003 } 2004 return (0); 2005 } 2006 2007 static int 2008 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2009 { 2010 ahc_dev_softc_t pci; 2011 int error; 2012 2013 pci = ahc->dev_softc; 2014 ahc->flags |= AHC_INT50_SPEEDFLEX; 2015 error = ahc_aic7880_setup(ahc); 2016 return (0); 2017 } 2018 2019 static int 2020 ahc_aha394XU_setup(struct ahc_softc *ahc) 2021 { 2022 int error; 2023 2024 error = ahc_aic7880_setup(ahc); 2025 if (error == 0) 2026 error = ahc_aha394XX_setup(ahc); 2027 return (error); 2028 } 2029 2030 static int 2031 ahc_aha398XU_setup(struct ahc_softc *ahc) 2032 { 2033 int error; 2034 2035 error = ahc_aic7880_setup(ahc); 2036 if (error == 0) 2037 error = ahc_aha398XX_setup(ahc); 2038 return (error); 2039 } 2040 2041 static int 2042 ahc_aic7890_setup(struct ahc_softc *ahc) 2043 { 2044 ahc_dev_softc_t pci; 2045 uint8_t rev; 2046 2047 pci = ahc->dev_softc; 2048 ahc->channel = 'A'; 2049 ahc->chip = AHC_AIC7890; 2050 ahc->features = AHC_AIC7890_FE; 2051 ahc->flags |= AHC_NEWEEPROM_FMT; 2052 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2053 if (rev == 0) 2054 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2055 return (0); 2056 } 2057 2058 static int 2059 ahc_aic7892_setup(struct ahc_softc *ahc) 2060 { 2061 ahc_dev_softc_t pci; 2062 2063 pci = ahc->dev_softc; 2064 ahc->channel = 'A'; 2065 ahc->chip = AHC_AIC7892; 2066 ahc->features = AHC_AIC7892_FE; 2067 ahc->flags |= AHC_NEWEEPROM_FMT; 2068 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2069 return (0); 2070 } 2071 2072 static int 2073 ahc_aic7895_setup(struct ahc_softc *ahc) 2074 { 2075 ahc_dev_softc_t pci; 2076 uint8_t rev; 2077 2078 pci = ahc->dev_softc; 2079 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2080 /* 2081 * The 'C' revision of the aic7895 has a few additional features. 2082 */ 2083 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2084 if (rev >= 4) { 2085 ahc->chip = AHC_AIC7895C; 2086 ahc->features = AHC_AIC7895C_FE; 2087 } else { 2088 u_int command; 2089 2090 ahc->chip = AHC_AIC7895; 2091 ahc->features = AHC_AIC7895_FE; 2092 2093 /* 2094 * The BIOS disables the use of MWI transactions 2095 * since it does not have the MWI bug work around 2096 * we have. Disabling MWI reduces performance, so 2097 * turn it on again. 2098 */ 2099 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2100 command |= PCIM_CMD_MWRICEN; 2101 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2102 ahc->bugs |= AHC_PCI_MWI_BUG; 2103 } 2104 /* 2105 * XXX Does CACHETHEN really not work??? What about PCI retry? 2106 * on C level chips. Need to test, but for now, play it safe. 2107 */ 2108 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2109 | AHC_CACHETHEN_BUG; 2110 2111 #if 0 2112 uint32_t devconfig; 2113 2114 /* 2115 * Cachesize must also be zero due to stray DAC 2116 * problem when sitting behind some bridges. 2117 */ 2118 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2119 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2120 devconfig |= MRDCEN; 2121 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2122 #endif 2123 ahc->flags |= AHC_NEWEEPROM_FMT; 2124 return (0); 2125 } 2126 2127 static int 2128 ahc_aic7896_setup(struct ahc_softc *ahc) 2129 { 2130 ahc_dev_softc_t pci; 2131 2132 pci = ahc->dev_softc; 2133 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2134 ahc->chip = AHC_AIC7896; 2135 ahc->features = AHC_AIC7896_FE; 2136 ahc->flags |= AHC_NEWEEPROM_FMT; 2137 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2138 return (0); 2139 } 2140 2141 static int 2142 ahc_aic7899_setup(struct ahc_softc *ahc) 2143 { 2144 ahc_dev_softc_t pci; 2145 2146 pci = ahc->dev_softc; 2147 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2148 ahc->chip = AHC_AIC7899; 2149 ahc->features = AHC_AIC7899_FE; 2150 ahc->flags |= AHC_NEWEEPROM_FMT; 2151 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2152 return (0); 2153 } 2154 2155 static int 2156 ahc_aha29160C_setup(struct ahc_softc *ahc) 2157 { 2158 int error; 2159 2160 error = ahc_aic7899_setup(ahc); 2161 if (error != 0) 2162 return (error); 2163 ahc->features |= AHC_REMOVABLE; 2164 return (0); 2165 } 2166 2167 static int 2168 ahc_raid_setup(struct ahc_softc *ahc) 2169 { 2170 printf("RAID functionality unsupported\n"); 2171 return (ENXIO); 2172 } 2173 2174 static int 2175 ahc_aha394XX_setup(struct ahc_softc *ahc) 2176 { 2177 ahc_dev_softc_t pci; 2178 2179 pci = ahc->dev_softc; 2180 switch (ahc_get_pci_slot(pci)) { 2181 case AHC_394X_SLOT_CHANNEL_A: 2182 ahc->channel = 'A'; 2183 break; 2184 case AHC_394X_SLOT_CHANNEL_B: 2185 ahc->channel = 'B'; 2186 break; 2187 default: 2188 printf("adapter at unexpected slot %d\n" 2189 "unable to map to a channel\n", 2190 ahc_get_pci_slot(pci)); 2191 ahc->channel = 'A'; 2192 } 2193 return (0); 2194 } 2195 2196 static int 2197 ahc_aha398XX_setup(struct ahc_softc *ahc) 2198 { 2199 ahc_dev_softc_t pci; 2200 2201 pci = ahc->dev_softc; 2202 switch (ahc_get_pci_slot(pci)) { 2203 case AHC_398X_SLOT_CHANNEL_A: 2204 ahc->channel = 'A'; 2205 break; 2206 case AHC_398X_SLOT_CHANNEL_B: 2207 ahc->channel = 'B'; 2208 break; 2209 case AHC_398X_SLOT_CHANNEL_C: 2210 ahc->channel = 'C'; 2211 break; 2212 default: 2213 printf("adapter at unexpected slot %d\n" 2214 "unable to map to a channel\n", 2215 ahc_get_pci_slot(pci)); 2216 ahc->channel = 'A'; 2217 break; 2218 } 2219 ahc->flags |= AHC_LARGE_SEEPROM; 2220 return (0); 2221 } 2222 2223 static int 2224 ahc_aha494XX_setup(struct ahc_softc *ahc) 2225 { 2226 ahc_dev_softc_t pci; 2227 2228 pci = ahc->dev_softc; 2229 switch (ahc_get_pci_slot(pci)) { 2230 case AHC_494X_SLOT_CHANNEL_A: 2231 ahc->channel = 'A'; 2232 break; 2233 case AHC_494X_SLOT_CHANNEL_B: 2234 ahc->channel = 'B'; 2235 break; 2236 case AHC_494X_SLOT_CHANNEL_C: 2237 ahc->channel = 'C'; 2238 break; 2239 case AHC_494X_SLOT_CHANNEL_D: 2240 ahc->channel = 'D'; 2241 break; 2242 default: 2243 printf("adapter at unexpected slot %d\n" 2244 "unable to map to a channel\n", 2245 ahc_get_pci_slot(pci)); 2246 ahc->channel = 'A'; 2247 } 2248 ahc->flags |= AHC_LARGE_SEEPROM; 2249 return (0); 2250 } 2251