1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995-2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#28 $ 34 * 35 * $FreeBSD$ 36 */ 37 38 #include <dev/aic7xxx/aic7xxx_freebsd.h> 39 #include <dev/aic7xxx/aic7xxx_inline.h> 40 #include <dev/aic7xxx/aic7xxx_93cx6.h> 41 42 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 43 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 44 45 static __inline uint64_t 46 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 47 { 48 uint64_t id; 49 50 id = subvendor 51 | (subdevice << 16) 52 | ((uint64_t)vendor << 32) 53 | ((uint64_t)device << 48); 54 55 return (id); 56 } 57 58 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 59 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 60 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 61 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 62 #define ID_9005_SISL_ID 0x0005900500000000ull 63 #define ID_AIC7850 0x5078900400000000ull 64 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 65 #define ID_AIC7855 0x5578900400000000ull 66 #define ID_AIC7859 0x3860900400000000ull 67 #define ID_AHA_2930CU 0x3860900438699004ull 68 #define ID_AIC7860 0x6078900400000000ull 69 #define ID_AIC7860C 0x6078900478609004ull 70 #define ID_AHA_1480A 0x6075900400000000ull 71 #define ID_AHA_2940AU_0 0x6178900400000000ull 72 #define ID_AHA_2940AU_1 0x6178900478619004ull 73 #define ID_AHA_2940AU_CN 0x2178900478219004ull 74 #define ID_AHA_2930C_VAR 0x6038900438689004ull 75 76 #define ID_AIC7870 0x7078900400000000ull 77 #define ID_AHA_2940 0x7178900400000000ull 78 #define ID_AHA_3940 0x7278900400000000ull 79 #define ID_AHA_398X 0x7378900400000000ull 80 #define ID_AHA_2944 0x7478900400000000ull 81 #define ID_AHA_3944 0x7578900400000000ull 82 #define ID_AHA_4944 0x7678900400000000ull 83 84 #define ID_AIC7880 0x8078900400000000ull 85 #define ID_AIC7880_B 0x8078900478809004ull 86 #define ID_AHA_2940U 0x8178900400000000ull 87 #define ID_AHA_3940U 0x8278900400000000ull 88 #define ID_AHA_2944U 0x8478900400000000ull 89 #define ID_AHA_3944U 0x8578900400000000ull 90 #define ID_AHA_398XU 0x8378900400000000ull 91 #define ID_AHA_4944U 0x8678900400000000ull 92 #define ID_AHA_2940UB 0x8178900478819004ull 93 #define ID_AHA_2930U 0x8878900478889004ull 94 #define ID_AHA_2940U_PRO 0x8778900478879004ull 95 #define ID_AHA_2940U_CN 0x0078900478009004ull 96 97 #define ID_AIC7895 0x7895900478959004ull 98 #define ID_AIC7895_ARO 0x7890900478939004ull 99 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 100 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 101 #define ID_AHA_3940AU 0x7895900478929004ull 102 #define ID_AHA_3944AU 0x7895900478949004ull 103 104 #define ID_AIC7890 0x001F9005000F9005ull 105 #define ID_AIC7890_ARO 0x00139005000F9005ull 106 #define ID_AAA_131U2 0x0013900500039005ull 107 #define ID_AHA_2930U2 0x0011900501819005ull 108 #define ID_AHA_2940U2B 0x00109005A1009005ull 109 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 110 #define ID_AHA_2940U2 0x00109005A1809005ull 111 #define ID_AHA_2950U2B 0x00109005E1009005ull 112 113 #define ID_AIC7892 0x008F9005FFFF9005ull 114 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 115 #define ID_AHA_29160 0x00809005E2A09005ull 116 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 117 #define ID_AHA_29160N 0x0080900562A09005ull 118 #define ID_AHA_29160C 0x0080900562209005ull 119 #define ID_AHA_29160B 0x00809005E2209005ull 120 #define ID_AHA_19160B 0x0081900562A19005ull 121 122 #define ID_AIC7896 0x005F9005FFFF9005ull 123 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 124 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 125 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 126 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 127 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 128 129 #define ID_AIC7899 0x00CF9005FFFF9005ull 130 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 131 #define ID_AHA_3960D 0x00C09005F6209005ull 132 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 133 134 #define ID_AIC7810 0x1078900400000000ull 135 #define ID_AIC7815 0x7815900400000000ull 136 137 #define DEVID_9005_TYPE(id) ((id) & 0xF) 138 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 139 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 140 #define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */ 141 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 142 143 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 144 #define DEVID_9005_MAXRATE_U160 0x0 145 #define DEVID_9005_MAXRATE_ULTRA2 0x1 146 #define DEVID_9005_MAXRATE_ULTRA 0x2 147 #define DEVID_9005_MAXRATE_FAST 0x3 148 149 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 150 151 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 152 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 153 154 #define SUBID_9005_TYPE(id) ((id) & 0xF) 155 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 156 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 157 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 158 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 159 160 #define SUBID_9005_TYPE_KNOWN(id) \ 161 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 162 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 163 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 164 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 165 166 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 167 #define SUBID_9005_MAXRATE_ULTRA2 0x0 168 #define SUBID_9005_MAXRATE_ULTRA 0x1 169 #define SUBID_9005_MAXRATE_U160 0x2 170 #define SUBID_9005_MAXRATE_RESERVED 0x3 171 172 #define SUBID_9005_SEEPTYPE(id) \ 173 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 174 ? ((id) & 0xC0) >> 6 \ 175 : ((id) & 0x300) >> 8) 176 #define SUBID_9005_SEEPTYPE_NONE 0x0 177 #define SUBID_9005_SEEPTYPE_1K 0x1 178 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 179 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 180 #define SUBID_9005_AUTOTERM(id) \ 181 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 182 ? (((id) & 0x400) >> 10) == 0 \ 183 : (((id) & 0x40) >> 6) == 0) 184 185 #define SUBID_9005_NUMCHAN(id) \ 186 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 187 ? ((id) & 0x300) >> 8 \ 188 : ((id) & 0xC00) >> 10) 189 190 #define SUBID_9005_LEGACYCONN(id) \ 191 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 192 ? 0 \ 193 : ((id) & 0x80) >> 7) 194 195 #define SUBID_9005_MFUNCENB(id) \ 196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 197 ? ((id) & 0x800) >> 11 \ 198 : ((id) & 0x1000) >> 12) 199 /* 200 * Informational only. Should use chip register to be 201 * ceratian, but may be use in identification strings. 202 */ 203 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 204 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 205 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 206 207 static ahc_device_setup_t ahc_aic785X_setup; 208 static ahc_device_setup_t ahc_aic7860_setup; 209 static ahc_device_setup_t ahc_apa1480_setup; 210 static ahc_device_setup_t ahc_aic7870_setup; 211 static ahc_device_setup_t ahc_aha394X_setup; 212 static ahc_device_setup_t ahc_aha494X_setup; 213 static ahc_device_setup_t ahc_aha398X_setup; 214 static ahc_device_setup_t ahc_aic7880_setup; 215 static ahc_device_setup_t ahc_aha2940Pro_setup; 216 static ahc_device_setup_t ahc_aha394XU_setup; 217 static ahc_device_setup_t ahc_aha398XU_setup; 218 static ahc_device_setup_t ahc_aic7890_setup; 219 static ahc_device_setup_t ahc_aic7892_setup; 220 static ahc_device_setup_t ahc_aic7895_setup; 221 static ahc_device_setup_t ahc_aic7896_setup; 222 static ahc_device_setup_t ahc_aic7899_setup; 223 static ahc_device_setup_t ahc_aha29160C_setup; 224 static ahc_device_setup_t ahc_raid_setup; 225 static ahc_device_setup_t ahc_aha394XX_setup; 226 static ahc_device_setup_t ahc_aha494XX_setup; 227 static ahc_device_setup_t ahc_aha398XX_setup; 228 229 struct ahc_pci_identity ahc_pci_ident_table [] = 230 { 231 /* aic7850 based controllers */ 232 { 233 ID_AHA_2902_04_10_15_20_30C, 234 ID_ALL_MASK, 235 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 236 ahc_aic785X_setup 237 }, 238 /* aic7860 based controllers */ 239 { 240 ID_AHA_2930CU, 241 ID_ALL_MASK, 242 "Adaptec 2930CU SCSI adapter", 243 ahc_aic7860_setup 244 }, 245 { 246 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 247 ID_DEV_VENDOR_MASK, 248 "Adaptec 1480A Ultra SCSI adapter", 249 ahc_apa1480_setup 250 }, 251 { 252 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 253 ID_DEV_VENDOR_MASK, 254 "Adaptec 2940A Ultra SCSI adapter", 255 ahc_aic7860_setup 256 }, 257 { 258 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 259 ID_DEV_VENDOR_MASK, 260 "Adaptec 2940A/CN Ultra SCSI adapter", 261 ahc_aic7860_setup 262 }, 263 { 264 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 265 ID_DEV_VENDOR_MASK, 266 "Adaptec 2930C Ultra SCSI adapter (VAR)", 267 ahc_aic7860_setup 268 }, 269 /* aic7870 based controllers */ 270 { 271 ID_AHA_2940, 272 ID_ALL_MASK, 273 "Adaptec 2940 SCSI adapter", 274 ahc_aic7870_setup 275 }, 276 { 277 ID_AHA_3940, 278 ID_ALL_MASK, 279 "Adaptec 3940 SCSI adapter", 280 ahc_aha394X_setup 281 }, 282 { 283 ID_AHA_398X, 284 ID_ALL_MASK, 285 "Adaptec 398X SCSI RAID adapter", 286 ahc_aha398X_setup 287 }, 288 { 289 ID_AHA_2944, 290 ID_ALL_MASK, 291 "Adaptec 2944 SCSI adapter", 292 ahc_aic7870_setup 293 }, 294 { 295 ID_AHA_3944, 296 ID_ALL_MASK, 297 "Adaptec 3944 SCSI adapter", 298 ahc_aha394X_setup 299 }, 300 { 301 ID_AHA_4944, 302 ID_ALL_MASK, 303 "Adaptec 4944 SCSI adapter", 304 ahc_aha494X_setup 305 }, 306 /* aic7880 based controllers */ 307 { 308 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 309 ID_DEV_VENDOR_MASK, 310 "Adaptec 2940 Ultra SCSI adapter", 311 ahc_aic7880_setup 312 }, 313 { 314 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 315 ID_DEV_VENDOR_MASK, 316 "Adaptec 3940 Ultra SCSI adapter", 317 ahc_aha394XU_setup 318 }, 319 { 320 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 321 ID_DEV_VENDOR_MASK, 322 "Adaptec 2944 Ultra SCSI adapter", 323 ahc_aic7880_setup 324 }, 325 { 326 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 327 ID_DEV_VENDOR_MASK, 328 "Adaptec 3944 Ultra SCSI adapter", 329 ahc_aha394XU_setup 330 }, 331 { 332 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 333 ID_DEV_VENDOR_MASK, 334 "Adaptec 398X Ultra SCSI RAID adapter", 335 ahc_aha398XU_setup 336 }, 337 { 338 /* 339 * XXX Don't know the slot numbers 340 * so we can't identify channels 341 */ 342 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 343 ID_DEV_VENDOR_MASK, 344 "Adaptec 4944 Ultra SCSI adapter", 345 ahc_aic7880_setup 346 }, 347 { 348 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2930 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 2940 Pro Ultra SCSI adapter", 357 ahc_aha2940Pro_setup 358 }, 359 { 360 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2940/CN Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 /* Ignore all SISL (AAC on MB) based controllers. */ 366 { 367 ID_9005_SISL_ID, 368 ID_9005_SISL_MASK, 369 NULL, 370 NULL 371 }, 372 /* aic7890 based controllers */ 373 { 374 ID_AHA_2930U2, 375 ID_ALL_MASK, 376 "Adaptec 2930 Ultra2 SCSI adapter", 377 ahc_aic7890_setup 378 }, 379 { 380 ID_AHA_2940U2B, 381 ID_ALL_MASK, 382 "Adaptec 2940B Ultra2 SCSI adapter", 383 ahc_aic7890_setup 384 }, 385 { 386 ID_AHA_2940U2_OEM, 387 ID_ALL_MASK, 388 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 389 ahc_aic7890_setup 390 }, 391 { 392 ID_AHA_2940U2, 393 ID_ALL_MASK, 394 "Adaptec 2940 Ultra2 SCSI adapter", 395 ahc_aic7890_setup 396 }, 397 { 398 ID_AHA_2950U2B, 399 ID_ALL_MASK, 400 "Adaptec 2950 Ultra2 SCSI adapter", 401 ahc_aic7890_setup 402 }, 403 { 404 ID_AIC7890_ARO, 405 ID_ALL_MASK, 406 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 407 ahc_aic7890_setup 408 }, 409 { 410 ID_AAA_131U2, 411 ID_ALL_MASK, 412 "Adaptec AAA-131 Ultra2 RAID adapter", 413 ahc_aic7890_setup 414 }, 415 /* aic7892 based controllers */ 416 { 417 ID_AHA_29160, 418 ID_ALL_MASK, 419 "Adaptec 29160 Ultra160 SCSI adapter", 420 ahc_aic7892_setup 421 }, 422 { 423 ID_AHA_29160_CPQ, 424 ID_ALL_MASK, 425 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 426 ahc_aic7892_setup 427 }, 428 { 429 ID_AHA_29160N, 430 ID_ALL_MASK, 431 "Adaptec 29160N Ultra160 SCSI adapter", 432 ahc_aic7892_setup 433 }, 434 { 435 ID_AHA_29160C, 436 ID_ALL_MASK, 437 "Adaptec 29160C Ultra160 SCSI adapter", 438 ahc_aha29160C_setup 439 }, 440 { 441 ID_AHA_29160B, 442 ID_ALL_MASK, 443 "Adaptec 29160B Ultra160 SCSI adapter", 444 ahc_aic7892_setup 445 }, 446 { 447 ID_AHA_19160B, 448 ID_ALL_MASK, 449 "Adaptec 19160B Ultra160 SCSI adapter", 450 ahc_aic7892_setup 451 }, 452 { 453 ID_AIC7892_ARO, 454 ID_ALL_MASK, 455 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 456 ahc_aic7892_setup 457 }, 458 /* aic7895 based controllers */ 459 { 460 ID_AHA_2940U_DUAL, 461 ID_ALL_MASK, 462 "Adaptec 2940/DUAL Ultra SCSI adapter", 463 ahc_aic7895_setup 464 }, 465 { 466 ID_AHA_3940AU, 467 ID_ALL_MASK, 468 "Adaptec 3940A Ultra SCSI adapter", 469 ahc_aic7895_setup 470 }, 471 { 472 ID_AHA_3944AU, 473 ID_ALL_MASK, 474 "Adaptec 3944A Ultra SCSI adapter", 475 ahc_aic7895_setup 476 }, 477 { 478 ID_AIC7895_ARO, 479 ID_AIC7895_ARO_MASK, 480 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 481 ahc_aic7895_setup 482 }, 483 /* aic7896/97 based controllers */ 484 { 485 ID_AHA_3950U2B_0, 486 ID_ALL_MASK, 487 "Adaptec 3950B Ultra2 SCSI adapter", 488 ahc_aic7896_setup 489 }, 490 { 491 ID_AHA_3950U2B_1, 492 ID_ALL_MASK, 493 "Adaptec 3950B Ultra2 SCSI adapter", 494 ahc_aic7896_setup 495 }, 496 { 497 ID_AHA_3950U2D_0, 498 ID_ALL_MASK, 499 "Adaptec 3950D Ultra2 SCSI adapter", 500 ahc_aic7896_setup 501 }, 502 { 503 ID_AHA_3950U2D_1, 504 ID_ALL_MASK, 505 "Adaptec 3950D Ultra2 SCSI adapter", 506 ahc_aic7896_setup 507 }, 508 { 509 ID_AIC7896_ARO, 510 ID_ALL_MASK, 511 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 512 ahc_aic7896_setup 513 }, 514 /* aic7899 based controllers */ 515 { 516 ID_AHA_3960D, 517 ID_ALL_MASK, 518 "Adaptec 3960D Ultra160 SCSI adapter", 519 ahc_aic7899_setup 520 }, 521 { 522 ID_AHA_3960D_CPQ, 523 ID_ALL_MASK, 524 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 525 ahc_aic7899_setup 526 }, 527 { 528 ID_AIC7899_ARO, 529 ID_ALL_MASK, 530 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 531 ahc_aic7899_setup 532 }, 533 /* Generic chip probes for devices we don't know 'exactly' */ 534 { 535 ID_AIC7850 & ID_DEV_VENDOR_MASK, 536 ID_DEV_VENDOR_MASK, 537 "Adaptec aic7850 SCSI adapter", 538 ahc_aic785X_setup 539 }, 540 { 541 ID_AIC7855 & ID_DEV_VENDOR_MASK, 542 ID_DEV_VENDOR_MASK, 543 "Adaptec aic7855 SCSI adapter", 544 ahc_aic785X_setup 545 }, 546 { 547 ID_AIC7859 & ID_DEV_VENDOR_MASK, 548 ID_DEV_VENDOR_MASK, 549 "Adaptec aic7859 SCSI adapter", 550 ahc_aic7860_setup 551 }, 552 { 553 ID_AIC7860 & ID_DEV_VENDOR_MASK, 554 ID_DEV_VENDOR_MASK, 555 "Adaptec aic7860 Ultra SCSI adapter", 556 ahc_aic7860_setup 557 }, 558 { 559 ID_AIC7870 & ID_DEV_VENDOR_MASK, 560 ID_DEV_VENDOR_MASK, 561 "Adaptec aic7870 SCSI adapter", 562 ahc_aic7870_setup 563 }, 564 { 565 ID_AIC7880 & ID_DEV_VENDOR_MASK, 566 ID_DEV_VENDOR_MASK, 567 "Adaptec aic7880 Ultra SCSI adapter", 568 ahc_aic7880_setup 569 }, 570 { 571 ID_AIC7890 & ID_9005_GENERIC_MASK, 572 ID_9005_GENERIC_MASK, 573 "Adaptec aic7890/91 Ultra2 SCSI adapter", 574 ahc_aic7890_setup 575 }, 576 { 577 ID_AIC7892 & ID_9005_GENERIC_MASK, 578 ID_9005_GENERIC_MASK, 579 "Adaptec aic7892 Ultra160 SCSI adapter", 580 ahc_aic7892_setup 581 }, 582 { 583 ID_AIC7895 & ID_DEV_VENDOR_MASK, 584 ID_DEV_VENDOR_MASK, 585 "Adaptec aic7895 Ultra SCSI adapter", 586 ahc_aic7895_setup 587 }, 588 { 589 ID_AIC7896 & ID_9005_GENERIC_MASK, 590 ID_9005_GENERIC_MASK, 591 "Adaptec aic7896/97 Ultra2 SCSI adapter", 592 ahc_aic7896_setup 593 }, 594 { 595 ID_AIC7899 & ID_9005_GENERIC_MASK, 596 ID_9005_GENERIC_MASK, 597 "Adaptec aic7899 Ultra160 SCSI adapter", 598 ahc_aic7899_setup 599 }, 600 { 601 ID_AIC7810 & ID_DEV_VENDOR_MASK, 602 ID_DEV_VENDOR_MASK, 603 "Adaptec aic7810 RAID memory controller", 604 ahc_raid_setup 605 }, 606 { 607 ID_AIC7815 & ID_DEV_VENDOR_MASK, 608 ID_DEV_VENDOR_MASK, 609 "Adaptec aic7815 RAID memory controller", 610 ahc_raid_setup 611 } 612 }; 613 614 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 615 616 #define AHC_394X_SLOT_CHANNEL_A 4 617 #define AHC_394X_SLOT_CHANNEL_B 5 618 619 #define AHC_398X_SLOT_CHANNEL_A 4 620 #define AHC_398X_SLOT_CHANNEL_B 8 621 #define AHC_398X_SLOT_CHANNEL_C 12 622 623 #define AHC_494X_SLOT_CHANNEL_A 4 624 #define AHC_494X_SLOT_CHANNEL_B 5 625 #define AHC_494X_SLOT_CHANNEL_C 6 626 #define AHC_494X_SLOT_CHANNEL_D 7 627 628 #define DEVCONFIG 0x40 629 #define SCBSIZE32 0x00010000ul /* aic789X only */ 630 #define REXTVALID 0x00001000ul /* ultra cards only */ 631 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 632 #define RAMPSM 0x00000200ul /* aic7870+ only */ 633 #define VOLSENSE 0x00000100ul 634 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 635 #define SCBRAMSEL 0x00000080ul 636 #define MRDCEN 0x00000040ul 637 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 638 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 639 #define BERREN 0x00000008ul 640 #define DACEN 0x00000004ul 641 #define STPWLEVEL 0x00000002ul 642 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 643 644 #define CSIZE_LATTIME 0x0c 645 #define CACHESIZE 0x0000003ful /* only 5 bits */ 646 #define LATTIME 0x0000ff00ul 647 648 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 649 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 650 int pcheck, int fast, int large); 651 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 652 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 653 static void configure_termination(struct ahc_softc *ahc, 654 struct seeprom_descriptor *sd, 655 u_int adapter_control, 656 u_int *sxfrctl1); 657 658 static void ahc_new_term_detect(struct ahc_softc *ahc, 659 int *enableSEC_low, 660 int *enableSEC_high, 661 int *enablePRI_low, 662 int *enablePRI_high, 663 int *eeprom_present); 664 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 665 int *internal68_present, 666 int *externalcable_present, 667 int *eeprom_present); 668 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 669 int *externalcable_present, 670 int *eeprom_present); 671 static int acquire_seeprom(struct ahc_softc *ahc, 672 struct seeprom_descriptor *sd); 673 static void release_seeprom(struct seeprom_descriptor *sd); 674 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 675 static uint8_t read_brdctl(struct ahc_softc *ahc); 676 677 struct ahc_pci_identity * 678 ahc_find_pci_device(ahc_dev_softc_t pci) 679 { 680 uint64_t full_id; 681 uint16_t device; 682 uint16_t vendor; 683 uint16_t subdevice; 684 uint16_t subvendor; 685 struct ahc_pci_identity *entry; 686 u_int i; 687 688 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 689 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 690 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 691 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 692 full_id = ahc_compose_id(device, 693 vendor, 694 subdevice, 695 subvendor); 696 697 /* 698 * If the second function is not hooked up, ignore it. 699 * Unfortunately, not all MB vendors implement the 700 * subdevice ID as per the Adaptec spec, so do our best 701 * to sanity check it prior to accepting the subdevice 702 * ID as valid. 703 */ 704 if (ahc_get_pci_function(pci) > 0 705 && subvendor == 0x9005 706 && subdevice != device 707 && SUBID_9005_TYPE_KNOWN(subdevice) != 0 708 && SUBID_9005_MFUNCENB(subdevice) == 0) 709 return (NULL); 710 711 for (i = 0; i < ahc_num_pci_devs; i++) { 712 entry = &ahc_pci_ident_table[i]; 713 if (entry->full_id == (full_id & entry->id_mask)) { 714 /* Honor exclusion entries. */ 715 if (entry->name == NULL) 716 return (NULL); 717 return (entry); 718 } 719 } 720 return (NULL); 721 } 722 723 int 724 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 725 { 726 struct scb_data *shared_scb_data; 727 u_int command; 728 u_int our_id = 0; 729 u_int sxfrctl1; 730 u_int scsiseq; 731 u_int dscommand0; 732 int error; 733 uint8_t sblkctl; 734 735 shared_scb_data = NULL; 736 error = entry->setup(ahc); 737 if (error != 0) 738 return (error); 739 ahc->chip |= AHC_PCI; 740 ahc->description = entry->name; 741 742 error = ahc_pci_map_registers(ahc); 743 if (error != 0) 744 return (error); 745 746 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 747 748 /* 749 * If we need to support high memory, enable dual 750 * address cycles. This bit must be set to enable 751 * high address bit generation even if we are on a 752 * 64bit bus (PCI64BIT set in devconfig). 753 */ 754 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 755 uint32_t devconfig; 756 757 if (bootverbose) 758 printf("%s: Enabling 39Bit Addressing\n", 759 ahc_name(ahc)); 760 devconfig = ahc_pci_read_config(ahc->dev_softc, 761 DEVCONFIG, /*bytes*/4); 762 devconfig |= DACEN; 763 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 764 devconfig, /*bytes*/4); 765 } 766 767 /* Ensure busmastering is enabled */ 768 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 769 command |= PCIM_CMD_BUSMASTEREN; 770 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 771 772 /* On all PCI adapters, we allow SCB paging */ 773 ahc->flags |= AHC_PAGESCBS; 774 775 error = ahc_softc_init(ahc); 776 if (error != 0) 777 return (error); 778 779 ahc->bus_intr = ahc_pci_intr; 780 781 /* Remeber how the card was setup in case there is no SEEPROM */ 782 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 783 ahc_pause(ahc); 784 if ((ahc->features & AHC_ULTRA2) != 0) 785 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 786 else 787 our_id = ahc_inb(ahc, SCSIID) & OID; 788 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 789 scsiseq = ahc_inb(ahc, SCSISEQ); 790 } else { 791 sxfrctl1 = STPWEN; 792 our_id = 7; 793 scsiseq = 0; 794 } 795 796 error = ahc_reset(ahc); 797 if (error != 0) 798 return (ENXIO); 799 800 if ((ahc->features & AHC_DT) != 0) { 801 u_int sfunct; 802 803 /* Perform ALT-Mode Setup */ 804 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 805 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 806 ahc_outb(ahc, OPTIONMODE, 807 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 808 ahc_outb(ahc, SFUNCT, sfunct); 809 810 /* Normal mode setup */ 811 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 812 |TARGCRCENDEN); 813 } 814 815 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 816 dscommand0 |= MPARCKEN|CACHETHEN; 817 if ((ahc->features & AHC_ULTRA2) != 0) { 818 819 /* 820 * DPARCKEN doesn't work correctly on 821 * some MBs so don't use it. 822 */ 823 dscommand0 &= ~DPARCKEN; 824 } 825 826 /* 827 * Handle chips that must have cache line 828 * streaming (dis/en)abled. 829 */ 830 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 831 dscommand0 |= CACHETHEN; 832 833 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 834 dscommand0 &= ~CACHETHEN; 835 836 ahc_outb(ahc, DSCOMMAND0, dscommand0); 837 838 ahc->pci_cachesize = 839 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 840 /*bytes*/1) & CACHESIZE; 841 ahc->pci_cachesize *= 4; 842 843 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 844 && ahc->pci_cachesize == 4) { 845 846 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 847 0, /*bytes*/1); 848 ahc->pci_cachesize = 0; 849 } 850 851 /* 852 * We cannot perform ULTRA speeds without the presense 853 * of the external precision resistor. 854 */ 855 if ((ahc->features & AHC_ULTRA) != 0) { 856 uint32_t devconfig; 857 858 devconfig = ahc_pci_read_config(ahc->dev_softc, 859 DEVCONFIG, /*bytes*/4); 860 if ((devconfig & REXTVALID) == 0) 861 ahc->features &= ~AHC_ULTRA; 862 } 863 864 /* See if we have a SEEPROM and perform auto-term */ 865 check_extport(ahc, &sxfrctl1); 866 867 /* 868 * Take the LED out of diagnostic mode 869 */ 870 sblkctl = ahc_inb(ahc, SBLKCTL); 871 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 872 873 if ((ahc->features & AHC_ULTRA2) != 0) { 874 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 875 } else { 876 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 877 } 878 879 if (ahc->flags & AHC_USEDEFAULTS) { 880 /* 881 * PCI Adapter default setup 882 * Should only be used if the adapter does not have 883 * a SEEPROM. 884 */ 885 /* See if someone else set us up already */ 886 if (scsiseq != 0) { 887 printf("%s: Using left over BIOS settings\n", 888 ahc_name(ahc)); 889 ahc->flags &= ~AHC_USEDEFAULTS; 890 ahc->flags |= AHC_BIOS_ENABLED; 891 } else { 892 /* 893 * Assume only one connector and always turn 894 * on termination. 895 */ 896 our_id = 0x07; 897 sxfrctl1 = STPWEN; 898 } 899 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 900 901 ahc->our_id = our_id; 902 } 903 904 /* 905 * Take a look to see if we have external SRAM. 906 * We currently do not attempt to use SRAM that is 907 * shared among multiple controllers. 908 */ 909 ahc_probe_ext_scbram(ahc); 910 911 /* 912 * Record our termination setting for the 913 * generic initialization routine. 914 */ 915 if ((sxfrctl1 & STPWEN) != 0) 916 ahc->flags |= AHC_TERM_ENB_A; 917 918 /* Core initialization */ 919 error = ahc_init(ahc); 920 if (error != 0) 921 return (error); 922 923 /* 924 * Link this softc in with all other ahc instances. 925 */ 926 ahc_softc_insert(ahc); 927 928 /* 929 * Allow interrupts now that we are completely setup. 930 */ 931 error = ahc_pci_map_int(ahc); 932 if (error != 0) 933 return (error); 934 935 ahc_intr_enable(ahc, TRUE); 936 937 return (0); 938 } 939 940 /* 941 * Test for the presense of external sram in an 942 * "unshared" configuration. 943 */ 944 static int 945 ahc_ext_scbram_present(struct ahc_softc *ahc) 946 { 947 u_int chip; 948 int ramps; 949 int single_user; 950 uint32_t devconfig; 951 952 chip = ahc->chip & AHC_CHIPID_MASK; 953 devconfig = ahc_pci_read_config(ahc->dev_softc, 954 DEVCONFIG, /*bytes*/4); 955 single_user = (devconfig & MPORTMODE) != 0; 956 957 if ((ahc->features & AHC_ULTRA2) != 0) 958 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 959 else if (chip >= AHC_AIC7870) 960 ramps = (devconfig & RAMPSM) != 0; 961 else 962 ramps = 0; 963 964 if (ramps && single_user) 965 return (1); 966 return (0); 967 } 968 969 /* 970 * Enable external scbram. 971 */ 972 static void 973 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 974 int fast, int large) 975 { 976 uint32_t devconfig; 977 978 if (ahc->features & AHC_MULTI_FUNC) { 979 /* 980 * Set the SCB Base addr (highest address bit) 981 * depending on which channel we are. 982 */ 983 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 984 } 985 986 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 987 if ((ahc->features & AHC_ULTRA2) != 0) { 988 u_int dscommand0; 989 990 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 991 if (enable) 992 dscommand0 &= ~INTSCBRAMSEL; 993 else 994 dscommand0 |= INTSCBRAMSEL; 995 if (large) 996 dscommand0 &= ~USCBSIZE32; 997 else 998 dscommand0 |= USCBSIZE32; 999 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1000 } else { 1001 if (fast) 1002 devconfig &= ~EXTSCBTIME; 1003 else 1004 devconfig |= EXTSCBTIME; 1005 if (enable) 1006 devconfig &= ~SCBRAMSEL; 1007 else 1008 devconfig |= SCBRAMSEL; 1009 if (large) 1010 devconfig &= ~SCBSIZE32; 1011 else 1012 devconfig |= SCBSIZE32; 1013 } 1014 if (pcheck) 1015 devconfig |= EXTSCBPEN; 1016 else 1017 devconfig &= ~EXTSCBPEN; 1018 1019 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1020 } 1021 1022 /* 1023 * Take a look to see if we have external SRAM. 1024 * We currently do not attempt to use SRAM that is 1025 * shared among multiple controllers. 1026 */ 1027 static void 1028 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1029 { 1030 int num_scbs; 1031 int test_num_scbs; 1032 int enable; 1033 int pcheck; 1034 int fast; 1035 int large; 1036 1037 enable = FALSE; 1038 pcheck = FALSE; 1039 fast = FALSE; 1040 large = FALSE; 1041 num_scbs = 0; 1042 1043 if (ahc_ext_scbram_present(ahc) == 0) 1044 goto done; 1045 1046 /* 1047 * Probe for the best parameters to use. 1048 */ 1049 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1050 num_scbs = ahc_probe_scbs(ahc); 1051 if (num_scbs == 0) { 1052 /* The SRAM wasn't really present. */ 1053 goto done; 1054 } 1055 enable = TRUE; 1056 1057 /* 1058 * Clear any outstanding parity error 1059 * and ensure that parity error reporting 1060 * is enabled. 1061 */ 1062 ahc_outb(ahc, SEQCTL, 0); 1063 ahc_outb(ahc, CLRINT, CLRPARERR); 1064 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1065 1066 /* Now see if we can do parity */ 1067 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1068 num_scbs = ahc_probe_scbs(ahc); 1069 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1070 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1071 pcheck = TRUE; 1072 1073 /* Clear any resulting parity error */ 1074 ahc_outb(ahc, CLRINT, CLRPARERR); 1075 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1076 1077 /* Now see if we can do fast timing */ 1078 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1079 test_num_scbs = ahc_probe_scbs(ahc); 1080 if (test_num_scbs == num_scbs 1081 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1082 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1083 fast = TRUE; 1084 1085 /* 1086 * See if we can use large SCBs and still maintain 1087 * the same overall count of SCBs. 1088 */ 1089 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1090 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1091 test_num_scbs = ahc_probe_scbs(ahc); 1092 if (test_num_scbs >= num_scbs) { 1093 large = TRUE; 1094 num_scbs = test_num_scbs; 1095 if (num_scbs >= 64) { 1096 /* 1097 * We have enough space to move the 1098 * "busy targets table" into SCB space 1099 * and make it qualify all the way to the 1100 * lun level. 1101 */ 1102 ahc->flags |= AHC_SCB_BTT; 1103 } 1104 } 1105 } 1106 done: 1107 /* 1108 * Disable parity error reporting until we 1109 * can load instruction ram. 1110 */ 1111 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1112 /* Clear any latched parity error */ 1113 ahc_outb(ahc, CLRINT, CLRPARERR); 1114 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1115 if (bootverbose && enable) { 1116 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1117 ahc_name(ahc), fast ? "fast" : "slow", 1118 pcheck ? ", parity checking enabled" : "", 1119 large ? 64 : 32); 1120 } 1121 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1122 } 1123 1124 /* 1125 * Check the external port logic for a serial eeprom 1126 * and termination/cable detection contrls. 1127 */ 1128 static void 1129 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1130 { 1131 struct seeprom_descriptor sd; 1132 struct seeprom_config sc; 1133 u_int scsi_conf; 1134 u_int adapter_control; 1135 int have_seeprom; 1136 int have_autoterm; 1137 1138 sd.sd_ahc = ahc; 1139 sd.sd_control_offset = SEECTL; 1140 sd.sd_status_offset = SEECTL; 1141 sd.sd_dataout_offset = SEECTL; 1142 1143 /* 1144 * For some multi-channel devices, the c46 is simply too 1145 * small to work. For the other controller types, we can 1146 * get our information from either SEEPROM type. Set the 1147 * type to start our probe with accordingly. 1148 */ 1149 if (ahc->flags & AHC_LARGE_SEEPROM) 1150 sd.sd_chip = C56_66; 1151 else 1152 sd.sd_chip = C46; 1153 1154 sd.sd_MS = SEEMS; 1155 sd.sd_RDY = SEERDY; 1156 sd.sd_CS = SEECS; 1157 sd.sd_CK = SEECK; 1158 sd.sd_DO = SEEDO; 1159 sd.sd_DI = SEEDI; 1160 1161 have_seeprom = acquire_seeprom(ahc, &sd); 1162 if (have_seeprom) { 1163 1164 if (bootverbose) 1165 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1166 1167 for (;;) { 1168 u_int start_addr; 1169 1170 start_addr = 32 * (ahc->channel - 'A'); 1171 1172 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1173 start_addr, sizeof(sc)/2); 1174 1175 if (have_seeprom) 1176 have_seeprom = verify_cksum(&sc); 1177 1178 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1179 if (bootverbose) { 1180 if (have_seeprom == 0) 1181 printf ("checksum error\n"); 1182 else 1183 printf ("done.\n"); 1184 } 1185 break; 1186 } 1187 sd.sd_chip = C56_66; 1188 } 1189 release_seeprom(&sd); 1190 } 1191 1192 if (!have_seeprom) { 1193 /* 1194 * Pull scratch ram settings and treat them as 1195 * if they are the contents of an seeprom if 1196 * the 'ADPT' signature is found in SCB2. 1197 * We manually compose the data as 16bit values 1198 * to avoid endian issues. 1199 */ 1200 ahc_outb(ahc, SCBPTR, 2); 1201 if (ahc_inb(ahc, SCB_BASE) == 'A' 1202 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1203 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1204 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1205 uint16_t *sc_data; 1206 int i; 1207 1208 sc_data = (uint16_t *)≻ 1209 for (i = 0; i < 32; i++) { 1210 uint16_t val; 1211 int j; 1212 1213 j = i * 2; 1214 val = ahc_inb(ahc, SRAM_BASE + j) 1215 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1216 } 1217 have_seeprom = verify_cksum(&sc); 1218 } 1219 } 1220 1221 if (!have_seeprom) { 1222 if (bootverbose) 1223 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1224 ahc->flags |= AHC_USEDEFAULTS; 1225 } else { 1226 /* 1227 * Put the data we've collected down into SRAM 1228 * where ahc_init will find it. 1229 */ 1230 int i; 1231 int max_targ = sc.max_targets & CFMAXTARG; 1232 uint16_t discenable; 1233 uint16_t ultraenb; 1234 1235 discenable = 0; 1236 ultraenb = 0; 1237 if ((sc.adapter_control & CFULTRAEN) != 0) { 1238 /* 1239 * Determine if this adapter has a "newstyle" 1240 * SEEPROM format. 1241 */ 1242 for (i = 0; i < max_targ; i++) { 1243 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1244 ahc->flags |= AHC_NEWEEPROM_FMT; 1245 break; 1246 } 1247 } 1248 } 1249 1250 for (i = 0; i < max_targ; i++) { 1251 u_int scsirate; 1252 uint16_t target_mask; 1253 1254 target_mask = 0x01 << i; 1255 if (sc.device_flags[i] & CFDISC) 1256 discenable |= target_mask; 1257 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1258 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1259 ultraenb |= target_mask; 1260 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1261 ultraenb |= target_mask; 1262 } 1263 if ((sc.device_flags[i] & CFXFER) == 0x04 1264 && (ultraenb & target_mask) != 0) { 1265 /* Treat 10MHz as a non-ultra speed */ 1266 sc.device_flags[i] &= ~CFXFER; 1267 ultraenb &= ~target_mask; 1268 } 1269 if ((ahc->features & AHC_ULTRA2) != 0) { 1270 u_int offset; 1271 1272 if (sc.device_flags[i] & CFSYNCH) 1273 offset = MAX_OFFSET_ULTRA2; 1274 else 1275 offset = 0; 1276 ahc_outb(ahc, TARG_OFFSET + i, offset); 1277 1278 /* 1279 * The ultra enable bits contain the 1280 * high bit of the ultra2 sync rate 1281 * field. 1282 */ 1283 scsirate = (sc.device_flags[i] & CFXFER) 1284 | ((ultraenb & target_mask) 1285 ? 0x8 : 0x0); 1286 if (sc.device_flags[i] & CFWIDEB) 1287 scsirate |= WIDEXFER; 1288 } else { 1289 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1290 if (sc.device_flags[i] & CFSYNCH) 1291 scsirate |= SOFS; 1292 if (sc.device_flags[i] & CFWIDEB) 1293 scsirate |= WIDEXFER; 1294 } 1295 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1296 } 1297 ahc->our_id = sc.brtime_id & CFSCSIID; 1298 1299 scsi_conf = (ahc->our_id & 0x7); 1300 if (sc.adapter_control & CFSPARITY) 1301 scsi_conf |= ENSPCHK; 1302 if (sc.adapter_control & CFRESETB) 1303 scsi_conf |= RESET_SCSI; 1304 1305 ahc->flags |= 1306 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1307 1308 if (sc.bios_control & CFEXTEND) 1309 ahc->flags |= AHC_EXTENDED_TRANS_A; 1310 1311 if (sc.bios_control & CFBIOSEN) 1312 ahc->flags |= AHC_BIOS_ENABLED; 1313 if (ahc->features & AHC_ULTRA 1314 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1315 /* Should we enable Ultra mode? */ 1316 if (!(sc.adapter_control & CFULTRAEN)) 1317 /* Treat us as a non-ultra card */ 1318 ultraenb = 0; 1319 } 1320 1321 if (sc.signature == CFSIGNATURE 1322 || sc.signature == CFSIGNATURE2) { 1323 uint32_t devconfig; 1324 1325 /* Honor the STPWLEVEL settings */ 1326 devconfig = ahc_pci_read_config(ahc->dev_softc, 1327 DEVCONFIG, /*bytes*/4); 1328 devconfig &= ~STPWLEVEL; 1329 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1330 devconfig |= STPWLEVEL; 1331 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1332 devconfig, /*bytes*/4); 1333 } 1334 /* Set SCSICONF info */ 1335 ahc_outb(ahc, SCSICONF, scsi_conf); 1336 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1337 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1338 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1339 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1340 } 1341 1342 /* 1343 * Cards that have the external logic necessary to talk to 1344 * a SEEPROM, are almost certain to have the remaining logic 1345 * necessary for auto-termination control. This assumption 1346 * hasn't failed yet... 1347 */ 1348 have_autoterm = have_seeprom; 1349 if (have_seeprom) 1350 adapter_control = sc.adapter_control; 1351 else 1352 adapter_control = CFAUTOTERM; 1353 1354 /* 1355 * Some low-cost chips have SEEPROM and auto-term control built 1356 * in, instead of using a GAL. They can tell us directly 1357 * if the termination logic is enabled. 1358 */ 1359 if ((ahc->features & AHC_SPIOCAP) != 0) { 1360 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1361 have_autoterm = TRUE; 1362 else 1363 have_autoterm = FALSE; 1364 } 1365 1366 if (have_autoterm) { 1367 acquire_seeprom(ahc, &sd); 1368 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1369 release_seeprom(&sd); 1370 } 1371 } 1372 1373 static void 1374 configure_termination(struct ahc_softc *ahc, 1375 struct seeprom_descriptor *sd, 1376 u_int adapter_control, 1377 u_int *sxfrctl1) 1378 { 1379 uint8_t brddat; 1380 1381 brddat = 0; 1382 1383 /* 1384 * Update the settings in sxfrctl1 to match the 1385 * termination settings 1386 */ 1387 *sxfrctl1 = 0; 1388 1389 /* 1390 * SEECS must be on for the GALS to latch 1391 * the data properly. Be sure to leave MS 1392 * on or we will release the seeprom. 1393 */ 1394 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1395 if ((adapter_control & CFAUTOTERM) != 0 1396 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1397 int internal50_present; 1398 int internal68_present; 1399 int externalcable_present; 1400 int eeprom_present; 1401 int enableSEC_low; 1402 int enableSEC_high; 1403 int enablePRI_low; 1404 int enablePRI_high; 1405 int sum; 1406 1407 enableSEC_low = 0; 1408 enableSEC_high = 0; 1409 enablePRI_low = 0; 1410 enablePRI_high = 0; 1411 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1412 ahc_new_term_detect(ahc, &enableSEC_low, 1413 &enableSEC_high, 1414 &enablePRI_low, 1415 &enablePRI_high, 1416 &eeprom_present); 1417 if ((adapter_control & CFSEAUTOTERM) == 0) { 1418 if (bootverbose) 1419 printf("%s: Manual SE Termination\n", 1420 ahc_name(ahc)); 1421 enableSEC_low = (adapter_control & CFSELOWTERM); 1422 enableSEC_high = 1423 (adapter_control & CFSEHIGHTERM); 1424 } 1425 if ((adapter_control & CFAUTOTERM) == 0) { 1426 if (bootverbose) 1427 printf("%s: Manual LVD Termination\n", 1428 ahc_name(ahc)); 1429 enablePRI_low = (adapter_control & CFSTERM); 1430 enablePRI_high = (adapter_control & CFWSTERM); 1431 } 1432 /* Make the table calculations below happy */ 1433 internal50_present = 0; 1434 internal68_present = 1; 1435 externalcable_present = 1; 1436 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1437 aic785X_cable_detect(ahc, &internal50_present, 1438 &externalcable_present, 1439 &eeprom_present); 1440 } else { 1441 aic787X_cable_detect(ahc, &internal50_present, 1442 &internal68_present, 1443 &externalcable_present, 1444 &eeprom_present); 1445 } 1446 1447 if ((ahc->features & AHC_WIDE) == 0) 1448 internal68_present = 0; 1449 1450 if (bootverbose 1451 && (ahc->features & AHC_ULTRA2) == 0) { 1452 printf("%s: internal 50 cable %s present", 1453 ahc_name(ahc), 1454 internal50_present ? "is":"not"); 1455 1456 if ((ahc->features & AHC_WIDE) != 0) 1457 printf(", internal 68 cable %s present", 1458 internal68_present ? "is":"not"); 1459 printf("\n%s: external cable %s present\n", 1460 ahc_name(ahc), 1461 externalcable_present ? "is":"not"); 1462 } 1463 if (bootverbose) 1464 printf("%s: BIOS eeprom %s present\n", 1465 ahc_name(ahc), eeprom_present ? "is" : "not"); 1466 1467 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1468 /* 1469 * The 50 pin connector is a separate bus, 1470 * so force it to always be terminated. 1471 * In the future, perform current sensing 1472 * to determine if we are in the middle of 1473 * a properly terminated bus. 1474 */ 1475 internal50_present = 0; 1476 } 1477 1478 /* 1479 * Now set the termination based on what 1480 * we found. 1481 * Flash Enable = BRDDAT7 1482 * Secondary High Term Enable = BRDDAT6 1483 * Secondary Low Term Enable = BRDDAT5 (7890) 1484 * Primary High Term Enable = BRDDAT4 (7890) 1485 */ 1486 if ((ahc->features & AHC_ULTRA2) == 0 1487 && (internal50_present != 0) 1488 && (internal68_present != 0) 1489 && (externalcable_present != 0)) { 1490 printf("%s: Illegal cable configuration!!. " 1491 "Only two connectors on the " 1492 "adapter may be used at a " 1493 "time!\n", ahc_name(ahc)); 1494 } 1495 1496 if ((ahc->features & AHC_WIDE) != 0 1497 && ((externalcable_present == 0) 1498 || (internal68_present == 0) 1499 || (enableSEC_high != 0))) { 1500 brddat |= BRDDAT6; 1501 if (bootverbose) { 1502 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1503 printf("%s: 68 pin termination " 1504 "Enabled\n", ahc_name(ahc)); 1505 else 1506 printf("%s: %sHigh byte termination " 1507 "Enabled\n", ahc_name(ahc), 1508 enableSEC_high ? "Secondary " 1509 : ""); 1510 } 1511 } 1512 1513 sum = internal50_present + internal68_present 1514 + externalcable_present; 1515 if (sum < 2 || (enableSEC_low != 0)) { 1516 if ((ahc->features & AHC_ULTRA2) != 0) 1517 brddat |= BRDDAT5; 1518 else 1519 *sxfrctl1 |= STPWEN; 1520 if (bootverbose) { 1521 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1522 printf("%s: 50 pin termination " 1523 "Enabled\n", ahc_name(ahc)); 1524 else 1525 printf("%s: %sLow byte termination " 1526 "Enabled\n", ahc_name(ahc), 1527 enableSEC_low ? "Secondary " 1528 : ""); 1529 } 1530 } 1531 1532 if (enablePRI_low != 0) { 1533 *sxfrctl1 |= STPWEN; 1534 if (bootverbose) 1535 printf("%s: Primary Low Byte termination " 1536 "Enabled\n", ahc_name(ahc)); 1537 } 1538 1539 /* 1540 * Setup STPWEN before setting up the rest of 1541 * the termination per the tech note on the U160 cards. 1542 */ 1543 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1544 1545 if (enablePRI_high != 0) { 1546 brddat |= BRDDAT4; 1547 if (bootverbose) 1548 printf("%s: Primary High Byte " 1549 "termination Enabled\n", 1550 ahc_name(ahc)); 1551 } 1552 1553 write_brdctl(ahc, brddat); 1554 1555 } else { 1556 if ((adapter_control & CFSTERM) != 0) { 1557 *sxfrctl1 |= STPWEN; 1558 1559 if (bootverbose) 1560 printf("%s: %sLow byte termination Enabled\n", 1561 ahc_name(ahc), 1562 (ahc->features & AHC_ULTRA2) ? "Primary " 1563 : ""); 1564 } 1565 1566 if ((adapter_control & CFWSTERM) != 0 1567 && (ahc->features & AHC_WIDE) != 0) { 1568 brddat |= BRDDAT6; 1569 if (bootverbose) 1570 printf("%s: %sHigh byte termination Enabled\n", 1571 ahc_name(ahc), 1572 (ahc->features & AHC_ULTRA2) 1573 ? "Secondary " : ""); 1574 } 1575 1576 /* 1577 * Setup STPWEN before setting up the rest of 1578 * the termination per the tech note on the U160 cards. 1579 */ 1580 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1581 1582 if ((ahc->features & AHC_WIDE) != 0) 1583 write_brdctl(ahc, brddat); 1584 } 1585 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1586 } 1587 1588 static void 1589 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1590 int *enableSEC_high, int *enablePRI_low, 1591 int *enablePRI_high, int *eeprom_present) 1592 { 1593 uint8_t brdctl; 1594 1595 /* 1596 * BRDDAT7 = Eeprom 1597 * BRDDAT6 = Enable Secondary High Byte termination 1598 * BRDDAT5 = Enable Secondary Low Byte termination 1599 * BRDDAT4 = Enable Primary high byte termination 1600 * BRDDAT3 = Enable Primary low byte termination 1601 */ 1602 brdctl = read_brdctl(ahc); 1603 *eeprom_present = brdctl & BRDDAT7; 1604 *enableSEC_high = (brdctl & BRDDAT6); 1605 *enableSEC_low = (brdctl & BRDDAT5); 1606 *enablePRI_high = (brdctl & BRDDAT4); 1607 *enablePRI_low = (brdctl & BRDDAT3); 1608 } 1609 1610 static void 1611 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1612 int *internal68_present, int *externalcable_present, 1613 int *eeprom_present) 1614 { 1615 uint8_t brdctl; 1616 1617 /* 1618 * First read the status of our cables. 1619 * Set the rom bank to 0 since the 1620 * bank setting serves as a multiplexor 1621 * for the cable detection logic. 1622 * BRDDAT5 controls the bank switch. 1623 */ 1624 write_brdctl(ahc, 0); 1625 1626 /* 1627 * Now read the state of the internal 1628 * connectors. BRDDAT6 is INT50 and 1629 * BRDDAT7 is INT68. 1630 */ 1631 brdctl = read_brdctl(ahc); 1632 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1633 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1634 1635 /* 1636 * Set the rom bank to 1 and determine 1637 * the other signals. 1638 */ 1639 write_brdctl(ahc, BRDDAT5); 1640 1641 /* 1642 * Now read the state of the external 1643 * connectors. BRDDAT6 is EXT68 and 1644 * BRDDAT7 is EPROMPS. 1645 */ 1646 brdctl = read_brdctl(ahc); 1647 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1648 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1649 } 1650 1651 static void 1652 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1653 int *externalcable_present, int *eeprom_present) 1654 { 1655 uint8_t brdctl; 1656 1657 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1658 ahc_outb(ahc, BRDCTL, 0); 1659 brdctl = ahc_inb(ahc, BRDCTL); 1660 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1661 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1662 1663 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1664 } 1665 1666 static int 1667 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1668 { 1669 int wait; 1670 1671 if ((ahc->features & AHC_SPIOCAP) != 0 1672 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1673 return (0); 1674 1675 /* 1676 * Request access of the memory port. When access is 1677 * granted, SEERDY will go high. We use a 1 second 1678 * timeout which should be near 1 second more than 1679 * is needed. Reason: after the chip reset, there 1680 * should be no contention. 1681 */ 1682 SEEPROM_OUTB(sd, sd->sd_MS); 1683 wait = 1000; /* 1 second timeout in msec */ 1684 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1685 ahc_delay(1000); /* delay 1 msec */ 1686 } 1687 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1688 SEEPROM_OUTB(sd, 0); 1689 return (0); 1690 } 1691 return(1); 1692 } 1693 1694 static void 1695 release_seeprom(struct seeprom_descriptor *sd) 1696 { 1697 /* Release access to the memory port and the serial EEPROM. */ 1698 SEEPROM_OUTB(sd, 0); 1699 } 1700 1701 static void 1702 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1703 { 1704 uint8_t brdctl; 1705 1706 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1707 brdctl = BRDSTB; 1708 if (ahc->channel == 'B') 1709 brdctl |= BRDCS; 1710 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1711 brdctl = 0; 1712 } else { 1713 brdctl = BRDSTB|BRDCS; 1714 } 1715 ahc_outb(ahc, BRDCTL, brdctl); 1716 ahc_flush_device_writes(ahc); 1717 brdctl |= value; 1718 ahc_outb(ahc, BRDCTL, brdctl); 1719 ahc_flush_device_writes(ahc); 1720 if ((ahc->features & AHC_ULTRA2) != 0) 1721 brdctl |= BRDSTB_ULTRA2; 1722 else 1723 brdctl &= ~BRDSTB; 1724 ahc_outb(ahc, BRDCTL, brdctl); 1725 ahc_flush_device_writes(ahc); 1726 if ((ahc->features & AHC_ULTRA2) != 0) 1727 brdctl = 0; 1728 else 1729 brdctl &= ~BRDCS; 1730 ahc_outb(ahc, BRDCTL, brdctl); 1731 } 1732 1733 static uint8_t 1734 read_brdctl(ahc) 1735 struct ahc_softc *ahc; 1736 { 1737 uint8_t brdctl; 1738 uint8_t value; 1739 1740 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1741 brdctl = BRDRW; 1742 if (ahc->channel == 'B') 1743 brdctl |= BRDCS; 1744 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1745 brdctl = BRDRW_ULTRA2; 1746 } else { 1747 brdctl = BRDRW|BRDCS; 1748 } 1749 ahc_outb(ahc, BRDCTL, brdctl); 1750 ahc_flush_device_writes(ahc); 1751 value = ahc_inb(ahc, BRDCTL); 1752 ahc_outb(ahc, BRDCTL, 0); 1753 return (value); 1754 } 1755 1756 #define DPE 0x80 1757 #define SSE 0x40 1758 #define RMA 0x20 1759 #define RTA 0x10 1760 #define STA 0x08 1761 #define DPR 0x01 1762 1763 void 1764 ahc_pci_intr(struct ahc_softc *ahc) 1765 { 1766 u_int error; 1767 u_int status1; 1768 1769 error = ahc_inb(ahc, ERROR); 1770 if ((error & PCIERRSTAT) == 0) 1771 return; 1772 1773 status1 = ahc_pci_read_config(ahc->dev_softc, 1774 PCIR_STATUS + 1, /*bytes*/1); 1775 1776 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1777 ahc_name(ahc), 1778 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1779 1780 if (status1 & DPE) { 1781 printf("%s: Data Parity Error Detected during address " 1782 "or write data phase\n", ahc_name(ahc)); 1783 } 1784 if (status1 & SSE) { 1785 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1786 } 1787 if (status1 & RMA) { 1788 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1789 } 1790 if (status1 & RTA) { 1791 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1792 } 1793 if (status1 & STA) { 1794 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1795 } 1796 if (status1 & DPR) { 1797 printf("%s: Data Parity Error has been reported via PERR#\n", 1798 ahc_name(ahc)); 1799 } 1800 1801 /* Clear latched errors. */ 1802 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1803 status1, /*bytes*/1); 1804 1805 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1806 printf("%s: Latched PCIERR interrupt with " 1807 "no status bits set\n", ahc_name(ahc)); 1808 } else { 1809 ahc_outb(ahc, CLRINT, CLRPARERR); 1810 } 1811 1812 ahc_unpause(ahc); 1813 } 1814 1815 static int 1816 ahc_aic785X_setup(struct ahc_softc *ahc) 1817 { 1818 ahc_dev_softc_t pci; 1819 uint8_t rev; 1820 1821 pci = ahc->dev_softc; 1822 ahc->channel = 'A'; 1823 ahc->chip = AHC_AIC7850; 1824 ahc->features = AHC_AIC7850_FE; 1825 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1826 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1827 if (rev >= 1) 1828 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1829 return (0); 1830 } 1831 1832 static int 1833 ahc_aic7860_setup(struct ahc_softc *ahc) 1834 { 1835 ahc_dev_softc_t pci; 1836 uint8_t rev; 1837 1838 pci = ahc->dev_softc; 1839 ahc->channel = 'A'; 1840 ahc->chip = AHC_AIC7860; 1841 ahc->features = AHC_AIC7860_FE; 1842 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1843 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1844 if (rev >= 1) 1845 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1846 return (0); 1847 } 1848 1849 static int 1850 ahc_apa1480_setup(struct ahc_softc *ahc) 1851 { 1852 ahc_dev_softc_t pci; 1853 int error; 1854 1855 pci = ahc->dev_softc; 1856 error = ahc_aic7860_setup(ahc); 1857 if (error != 0) 1858 return (error); 1859 ahc->features |= AHC_REMOVABLE; 1860 return (0); 1861 } 1862 1863 static int 1864 ahc_aic7870_setup(struct ahc_softc *ahc) 1865 { 1866 ahc_dev_softc_t pci; 1867 1868 pci = ahc->dev_softc; 1869 ahc->channel = 'A'; 1870 ahc->chip = AHC_AIC7870; 1871 ahc->features = AHC_AIC7870_FE; 1872 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1873 return (0); 1874 } 1875 1876 static int 1877 ahc_aha394X_setup(struct ahc_softc *ahc) 1878 { 1879 int error; 1880 1881 error = ahc_aic7870_setup(ahc); 1882 if (error == 0) 1883 error = ahc_aha394XX_setup(ahc); 1884 return (error); 1885 } 1886 1887 static int 1888 ahc_aha398X_setup(struct ahc_softc *ahc) 1889 { 1890 int error; 1891 1892 error = ahc_aic7870_setup(ahc); 1893 if (error == 0) 1894 error = ahc_aha398XX_setup(ahc); 1895 return (error); 1896 } 1897 1898 static int 1899 ahc_aha494X_setup(struct ahc_softc *ahc) 1900 { 1901 int error; 1902 1903 error = ahc_aic7870_setup(ahc); 1904 if (error == 0) 1905 error = ahc_aha494XX_setup(ahc); 1906 return (error); 1907 } 1908 1909 static int 1910 ahc_aic7880_setup(struct ahc_softc *ahc) 1911 { 1912 ahc_dev_softc_t pci; 1913 uint8_t rev; 1914 1915 pci = ahc->dev_softc; 1916 ahc->channel = 'A'; 1917 ahc->chip = AHC_AIC7880; 1918 ahc->features = AHC_AIC7880_FE; 1919 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1920 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1921 if (rev >= 1) { 1922 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1923 } else { 1924 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1925 } 1926 return (0); 1927 } 1928 1929 static int 1930 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1931 { 1932 ahc_dev_softc_t pci; 1933 int error; 1934 1935 pci = ahc->dev_softc; 1936 ahc->flags |= AHC_INT50_SPEEDFLEX; 1937 error = ahc_aic7880_setup(ahc); 1938 return (0); 1939 } 1940 1941 static int 1942 ahc_aha394XU_setup(struct ahc_softc *ahc) 1943 { 1944 int error; 1945 1946 error = ahc_aic7880_setup(ahc); 1947 if (error == 0) 1948 error = ahc_aha394XX_setup(ahc); 1949 return (error); 1950 } 1951 1952 static int 1953 ahc_aha398XU_setup(struct ahc_softc *ahc) 1954 { 1955 int error; 1956 1957 error = ahc_aic7880_setup(ahc); 1958 if (error == 0) 1959 error = ahc_aha398XX_setup(ahc); 1960 return (error); 1961 } 1962 1963 static int 1964 ahc_aic7890_setup(struct ahc_softc *ahc) 1965 { 1966 ahc_dev_softc_t pci; 1967 uint8_t rev; 1968 1969 pci = ahc->dev_softc; 1970 ahc->channel = 'A'; 1971 ahc->chip = AHC_AIC7890; 1972 ahc->features = AHC_AIC7890_FE; 1973 ahc->flags |= AHC_NEWEEPROM_FMT; 1974 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1975 if (rev == 0) 1976 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1977 return (0); 1978 } 1979 1980 static int 1981 ahc_aic7892_setup(struct ahc_softc *ahc) 1982 { 1983 ahc_dev_softc_t pci; 1984 1985 pci = ahc->dev_softc; 1986 ahc->channel = 'A'; 1987 ahc->chip = AHC_AIC7892; 1988 ahc->features = AHC_AIC7892_FE; 1989 ahc->flags |= AHC_NEWEEPROM_FMT; 1990 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1991 return (0); 1992 } 1993 1994 static int 1995 ahc_aic7895_setup(struct ahc_softc *ahc) 1996 { 1997 ahc_dev_softc_t pci; 1998 uint8_t rev; 1999 2000 pci = ahc->dev_softc; 2001 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2002 /* 2003 * The 'C' revision of the aic7895 has a few additional features. 2004 */ 2005 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2006 if (rev >= 4) { 2007 ahc->chip = AHC_AIC7895C; 2008 ahc->features = AHC_AIC7895C_FE; 2009 } else { 2010 u_int command; 2011 2012 ahc->chip = AHC_AIC7895; 2013 ahc->features = AHC_AIC7895_FE; 2014 2015 /* 2016 * The BIOS disables the use of MWI transactions 2017 * since it does not have the MWI bug work around 2018 * we have. Disabling MWI reduces performance, so 2019 * turn it on again. 2020 */ 2021 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2022 command |= PCIM_CMD_MWRICEN; 2023 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2024 ahc->bugs |= AHC_PCI_MWI_BUG; 2025 } 2026 /* 2027 * XXX Does CACHETHEN really not work??? What about PCI retry? 2028 * on C level chips. Need to test, but for now, play it safe. 2029 */ 2030 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2031 | AHC_CACHETHEN_BUG; 2032 2033 #if 0 2034 uint32_t devconfig; 2035 2036 /* 2037 * Cachesize must also be zero due to stray DAC 2038 * problem when sitting behind some bridges. 2039 */ 2040 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2041 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2042 devconfig |= MRDCEN; 2043 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2044 #endif 2045 ahc->flags |= AHC_NEWEEPROM_FMT; 2046 return (0); 2047 } 2048 2049 static int 2050 ahc_aic7896_setup(struct ahc_softc *ahc) 2051 { 2052 ahc_dev_softc_t pci; 2053 2054 pci = ahc->dev_softc; 2055 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2056 ahc->chip = AHC_AIC7896; 2057 ahc->features = AHC_AIC7896_FE; 2058 ahc->flags |= AHC_NEWEEPROM_FMT; 2059 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2060 return (0); 2061 } 2062 2063 static int 2064 ahc_aic7899_setup(struct ahc_softc *ahc) 2065 { 2066 ahc_dev_softc_t pci; 2067 2068 pci = ahc->dev_softc; 2069 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2070 ahc->chip = AHC_AIC7899; 2071 ahc->features = AHC_AIC7899_FE; 2072 ahc->flags |= AHC_NEWEEPROM_FMT; 2073 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2074 return (0); 2075 } 2076 2077 static int 2078 ahc_aha29160C_setup(struct ahc_softc *ahc) 2079 { 2080 int error; 2081 2082 error = ahc_aic7899_setup(ahc); 2083 if (error != 0) 2084 return (error); 2085 ahc->features |= AHC_REMOVABLE; 2086 return (0); 2087 } 2088 2089 static int 2090 ahc_raid_setup(struct ahc_softc *ahc) 2091 { 2092 printf("RAID functionality unsupported\n"); 2093 return (ENXIO); 2094 } 2095 2096 static int 2097 ahc_aha394XX_setup(struct ahc_softc *ahc) 2098 { 2099 ahc_dev_softc_t pci; 2100 2101 pci = ahc->dev_softc; 2102 switch (ahc_get_pci_slot(pci)) { 2103 case AHC_394X_SLOT_CHANNEL_A: 2104 ahc->channel = 'A'; 2105 break; 2106 case AHC_394X_SLOT_CHANNEL_B: 2107 ahc->channel = 'B'; 2108 break; 2109 default: 2110 printf("adapter at unexpected slot %d\n" 2111 "unable to map to a channel\n", 2112 ahc_get_pci_slot(pci)); 2113 ahc->channel = 'A'; 2114 } 2115 return (0); 2116 } 2117 2118 static int 2119 ahc_aha398XX_setup(struct ahc_softc *ahc) 2120 { 2121 ahc_dev_softc_t pci; 2122 2123 pci = ahc->dev_softc; 2124 switch (ahc_get_pci_slot(pci)) { 2125 case AHC_398X_SLOT_CHANNEL_A: 2126 ahc->channel = 'A'; 2127 break; 2128 case AHC_398X_SLOT_CHANNEL_B: 2129 ahc->channel = 'B'; 2130 break; 2131 case AHC_398X_SLOT_CHANNEL_C: 2132 ahc->channel = 'C'; 2133 break; 2134 default: 2135 printf("adapter at unexpected slot %d\n" 2136 "unable to map to a channel\n", 2137 ahc_get_pci_slot(pci)); 2138 ahc->channel = 'A'; 2139 break; 2140 } 2141 ahc->flags |= AHC_LARGE_SEEPROM; 2142 return (0); 2143 } 2144 2145 static int 2146 ahc_aha494XX_setup(struct ahc_softc *ahc) 2147 { 2148 ahc_dev_softc_t pci; 2149 2150 pci = ahc->dev_softc; 2151 switch (ahc_get_pci_slot(pci)) { 2152 case AHC_494X_SLOT_CHANNEL_A: 2153 ahc->channel = 'A'; 2154 break; 2155 case AHC_494X_SLOT_CHANNEL_B: 2156 ahc->channel = 'B'; 2157 break; 2158 case AHC_494X_SLOT_CHANNEL_C: 2159 ahc->channel = 'C'; 2160 break; 2161 case AHC_494X_SLOT_CHANNEL_D: 2162 ahc->channel = 'D'; 2163 break; 2164 default: 2165 printf("adapter at unexpected slot %d\n" 2166 "unable to map to a channel\n", 2167 ahc_get_pci_slot(pci)); 2168 ahc->channel = 'A'; 2169 } 2170 ahc->flags |= AHC_LARGE_SEEPROM; 2171 return (0); 2172 } 2173