1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD$ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#27 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic7xxx driver. 48 * 49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 50 * Adaptec's Technical Documents Department 1-800-934-2766 51 */ 52 53/* 54 * SCSI Sequence Control (p. 3-11). 55 * Each bit, when set starts a specific SCSI sequence on the bus 56 */ 57register SCSISEQ { 58 address 0x000 59 access_mode RW 60 bit TEMODE 0x80 61 bit ENSELO 0x40 62 bit ENSELI 0x20 63 bit ENRSELI 0x10 64 bit ENAUTOATNO 0x08 65 bit ENAUTOATNI 0x04 66 bit ENAUTOATNP 0x02 67 bit SCSIRSTO 0x01 68} 69 70/* 71 * SCSI Transfer Control 0 Register (pp. 3-13). 72 * Controls the SCSI module data path. 73 */ 74register SXFRCTL0 { 75 address 0x001 76 access_mode RW 77 bit DFON 0x80 78 bit DFPEXP 0x40 79 bit FAST20 0x20 80 bit CLRSTCNT 0x10 81 bit SPIOEN 0x08 82 bit SCAMEN 0x04 83 bit CLRCHN 0x02 84} 85 86/* 87 * SCSI Transfer Control 1 Register (pp. 3-14,15). 88 * Controls the SCSI module data path. 89 */ 90register SXFRCTL1 { 91 address 0x002 92 access_mode RW 93 bit BITBUCKET 0x80 94 bit SWRAPEN 0x40 95 bit ENSPCHK 0x20 96 mask STIMESEL 0x18 97 bit ENSTIMER 0x04 98 bit ACTNEGEN 0x02 99 bit STPWEN 0x01 /* Powered Termination */ 100} 101 102/* 103 * SCSI Control Signal Read Register (p. 3-15). 104 * Reads the actual state of the SCSI bus pins 105 */ 106register SCSISIGI { 107 address 0x003 108 access_mode RO 109 bit CDI 0x80 110 bit IOI 0x40 111 bit MSGI 0x20 112 bit ATNI 0x10 113 bit SELI 0x08 114 bit BSYI 0x04 115 bit REQI 0x02 116 bit ACKI 0x01 117/* 118 * Possible phases in SCSISIGI 119 */ 120 mask PHASE_MASK CDI|IOI|MSGI 121 mask P_DATAOUT 0x00 122 mask P_DATAIN IOI 123 mask P_DATAOUT_DT P_DATAOUT|MSGI 124 mask P_DATAIN_DT P_DATAIN|MSGI 125 mask P_COMMAND CDI 126 mask P_MESGOUT CDI|MSGI 127 mask P_STATUS CDI|IOI 128 mask P_MESGIN CDI|IOI|MSGI 129} 130 131/* 132 * SCSI Control Signal Write Register (p. 3-16). 133 * Writing to this register modifies the control signals on the bus. Only 134 * those signals that are allowed in the current mode (Initiator/Target) are 135 * asserted. 136 */ 137register SCSISIGO { 138 address 0x003 139 access_mode WO 140 bit CDO 0x80 141 bit IOO 0x40 142 bit MSGO 0x20 143 bit ATNO 0x10 144 bit SELO 0x08 145 bit BSYO 0x04 146 bit REQO 0x02 147 bit ACKO 0x01 148/* 149 * Possible phases to write into SCSISIG0 150 */ 151 mask PHASE_MASK CDI|IOI|MSGI 152 mask P_DATAOUT 0x00 153 mask P_DATAIN IOI 154 mask P_COMMAND CDI 155 mask P_MESGOUT CDI|MSGI 156 mask P_STATUS CDI|IOI 157 mask P_MESGIN CDI|IOI|MSGI 158} 159 160/* 161 * SCSI Rate Control (p. 3-17). 162 * Contents of this register determine the Synchronous SCSI data transfer 163 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 164 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 165 * greater than 0 enables synchronous transfers. 166 */ 167register SCSIRATE { 168 address 0x004 169 access_mode RW 170 bit WIDEXFER 0x80 /* Wide transfer control */ 171 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 172 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 173 mask SXFR 0x70 /* Sync transfer rate */ 174 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 175 mask SOFS 0x0f /* Sync offset */ 176} 177 178/* 179 * SCSI ID (p. 3-18). 180 * Contains the ID of the board and the current target on the 181 * selected channel. 182 */ 183register SCSIID { 184 address 0x005 185 access_mode RW 186 mask TID 0xf0 /* Target ID mask */ 187 mask TWIN_TID 0x70 188 bit TWIN_CHNLB 0x80 189 mask OID 0x0f /* Our ID mask */ 190 /* 191 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 192 * The aic7890/91 allow an offset of up to 127 transfers in both wide 193 * and narrow mode. 194 */ 195 alias SCSIOFFSET 196 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 197} 198 199/* 200 * SCSI Latched Data (p. 3-19). 201 * Read/Write latches used to transfer data on the SCSI bus during 202 * Automatic or Manual PIO mode. SCSIDATH can be used for the 203 * upper byte of a 16bit wide asynchronouse data phase transfer. 204 */ 205register SCSIDATL { 206 address 0x006 207 access_mode RW 208} 209 210register SCSIDATH { 211 address 0x007 212 access_mode RW 213} 214 215/* 216 * SCSI Transfer Count (pp. 3-19,20) 217 * These registers count down the number of bytes transferred 218 * across the SCSI bus. The counter is decremented only once 219 * the data has been safely transferred. SDONE in SSTAT0 is 220 * set when STCNT goes to 0 221 */ 222register STCNT { 223 address 0x008 224 size 3 225 access_mode RW 226} 227 228/* ALT_MODE register on Ultra160 chips */ 229register OPTIONMODE { 230 address 0x008 231 access_mode RW 232 bit AUTORATEEN 0x80 233 bit AUTOACKEN 0x40 234 bit ATNMGMNTEN 0x20 235 bit BUSFREEREV 0x10 236 bit EXPPHASEDIS 0x08 237 bit SCSIDATL_IMGEN 0x04 238 bit AUTO_MSGOUT_DE 0x02 239 bit DIS_MSGIN_DUALEDGE 0x01 240 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 241} 242 243/* ALT_MODE register on Ultra160 chips */ 244register TARGCRCCNT { 245 address 0x00a 246 size 2 247 access_mode RW 248} 249 250/* 251 * Clear SCSI Interrupt 0 (p. 3-20) 252 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 253 */ 254register CLRSINT0 { 255 address 0x00b 256 access_mode WO 257 bit CLRSELDO 0x40 258 bit CLRSELDI 0x20 259 bit CLRSELINGO 0x10 260 bit CLRSWRAP 0x08 261 bit CLRIOERR 0x08 /* Ultra2 Only */ 262 bit CLRSPIORDY 0x02 263} 264 265/* 266 * SCSI Status 0 (p. 3-21) 267 * Contains one set of SCSI Interrupt codes 268 * These are most likely of interest to the sequencer 269 */ 270register SSTAT0 { 271 address 0x00b 272 access_mode RO 273 bit TARGET 0x80 /* Board acting as target */ 274 bit SELDO 0x40 /* Selection Done */ 275 bit SELDI 0x20 /* Board has been selected */ 276 bit SELINGO 0x10 /* Selection In Progress */ 277 bit SWRAP 0x08 /* 24bit counter wrap */ 278 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 279 bit SDONE 0x04 /* STCNT = 0x000000 */ 280 bit SPIORDY 0x02 /* SCSI PIO Ready */ 281 bit DMADONE 0x01 /* DMA transfer completed */ 282} 283 284/* 285 * Clear SCSI Interrupt 1 (p. 3-23) 286 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 287 */ 288register CLRSINT1 { 289 address 0x00c 290 access_mode WO 291 bit CLRSELTIMEO 0x80 292 bit CLRATNO 0x40 293 bit CLRSCSIRSTI 0x20 294 bit CLRBUSFREE 0x08 295 bit CLRSCSIPERR 0x04 296 bit CLRPHASECHG 0x02 297 bit CLRREQINIT 0x01 298} 299 300/* 301 * SCSI Status 1 (p. 3-24) 302 */ 303register SSTAT1 { 304 address 0x00c 305 access_mode RO 306 bit SELTO 0x80 307 bit ATNTARG 0x40 308 bit SCSIRSTI 0x20 309 bit PHASEMIS 0x10 310 bit BUSFREE 0x08 311 bit SCSIPERR 0x04 312 bit PHASECHG 0x02 313 bit REQINIT 0x01 314} 315 316/* 317 * SCSI Status 2 (pp. 3-25,26) 318 */ 319register SSTAT2 { 320 address 0x00d 321 access_mode RO 322 bit OVERRUN 0x80 323 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 324 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 325 bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 326 bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 327 bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 328 bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 329 mask SFCNT 0x1f 330} 331 332/* 333 * SCSI Status 3 (p. 3-26) 334 */ 335register SSTAT3 { 336 address 0x00e 337 access_mode RO 338 mask SCSICNT 0xf0 339 mask OFFCNT 0x0f 340 mask U2OFFCNT 0x7f 341} 342 343/* 344 * SCSI ID for the aic7890/91 chips 345 */ 346register SCSIID_ULTRA2 { 347 address 0x00f 348 access_mode RW 349 mask TID 0xf0 /* Target ID mask */ 350 mask OID 0x0f /* Our ID mask */ 351} 352 353/* 354 * SCSI Interrupt Mode 1 (p. 3-28) 355 * Setting any bit will enable the corresponding function 356 * in SIMODE0 to interrupt via the IRQ pin. 357 */ 358register SIMODE0 { 359 address 0x010 360 access_mode RW 361 bit ENSELDO 0x40 362 bit ENSELDI 0x20 363 bit ENSELINGO 0x10 364 bit ENSWRAP 0x08 365 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 366 bit ENSDONE 0x04 367 bit ENSPIORDY 0x02 368 bit ENDMADONE 0x01 369} 370 371/* 372 * SCSI Interrupt Mode 1 (pp. 3-28,29) 373 * Setting any bit will enable the corresponding function 374 * in SIMODE1 to interrupt via the IRQ pin. 375 */ 376register SIMODE1 { 377 address 0x011 378 access_mode RW 379 bit ENSELTIMO 0x80 380 bit ENATNTARG 0x40 381 bit ENSCSIRST 0x20 382 bit ENPHASEMIS 0x10 383 bit ENBUSFREE 0x08 384 bit ENSCSIPERR 0x04 385 bit ENPHASECHG 0x02 386 bit ENREQINIT 0x01 387} 388 389/* 390 * SCSI Data Bus (High) (p. 3-29) 391 * This register reads data on the SCSI Data bus directly. 392 */ 393register SCSIBUSL { 394 address 0x012 395 access_mode RW 396} 397 398register SCSIBUSH { 399 address 0x013 400 access_mode RW 401} 402 403/* 404 * SCSI/Host Address (p. 3-30) 405 * These registers hold the host address for the byte about to be 406 * transferred on the SCSI bus. They are counted up in the same 407 * manner as STCNT is counted down. SHADDR should always be used 408 * to determine the address of the last byte transferred since HADDR 409 * can be skewed by write ahead. 410 */ 411register SHADDR { 412 address 0x014 413 size 4 414 access_mode RO 415} 416 417/* 418 * Selection Timeout Timer (p. 3-30) 419 */ 420register SELTIMER { 421 address 0x018 422 access_mode RW 423 bit STAGE6 0x20 424 bit STAGE5 0x10 425 bit STAGE4 0x08 426 bit STAGE3 0x04 427 bit STAGE2 0x02 428 bit STAGE1 0x01 429 alias TARGIDIN 430} 431 432/* 433 * Selection/Reselection ID (p. 3-31) 434 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 435 * device did not set its own ID. 436 */ 437register SELID { 438 address 0x019 439 access_mode RW 440 mask SELID_MASK 0xf0 441 bit ONEBIT 0x08 442} 443 444register SCAMCTL { 445 address 0x01a 446 access_mode RW 447 bit ENSCAMSELO 0x80 448 bit CLRSCAMSELID 0x40 449 bit ALTSTIM 0x20 450 bit DFLTTID 0x10 451 mask SCAMLVL 0x03 452} 453 454/* 455 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 456 */ 457register TARGID { 458 address 0x01b 459 size 2 460 access_mode RW 461} 462 463/* 464 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 465 * Indicates if external logic has been attached to the chip to 466 * perform the tasks of accessing a serial eeprom, testing termination 467 * strength, and performing cable detection. On the aic7860, most of 468 * these features are handled on chip, but on the aic7855 an attached 469 * aic3800 does the grunt work. 470 */ 471register SPIOCAP { 472 address 0x01b 473 access_mode RW 474 bit SOFT1 0x80 475 bit SOFT0 0x40 476 bit SOFTCMDEN 0x20 477 bit HAS_BRDCTL 0x10 /* External Board control */ 478 bit SEEPROM 0x08 /* External serial eeprom logic */ 479 bit EEPROM 0x04 /* Writable external BIOS ROM */ 480 bit ROM 0x02 /* Logic for accessing external ROM */ 481 bit SSPIOCPS 0x01 /* Termination and cable detection */ 482} 483 484register BRDCTL { 485 address 0x01d 486 bit BRDDAT7 0x80 487 bit BRDDAT6 0x40 488 bit BRDDAT5 0x20 489 bit BRDSTB 0x10 490 bit BRDCS 0x08 491 bit BRDRW 0x04 492 bit BRDCTL1 0x02 493 bit BRDCTL0 0x01 494 /* 7890 Definitions */ 495 bit BRDDAT4 0x10 496 bit BRDDAT3 0x08 497 bit BRDDAT2 0x04 498 bit BRDRW_ULTRA2 0x02 499 bit BRDSTB_ULTRA2 0x01 500} 501 502/* 503 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 504 * Controls the reading and writing of an external serial 1-bit 505 * EEPROM Device. In order to access the serial EEPROM, you must 506 * first set the SEEMS bit that generates a request to the memory 507 * port for access to the serial EEPROM device. When the memory 508 * port is not busy servicing another request, it reconfigures 509 * to allow access to the serial EEPROM. When this happens, SEERDY 510 * gets set high to verify that the memory port access has been 511 * granted. 512 * 513 * After successful arbitration for the memory port, the SEECS bit of 514 * the SEECTL register is connected to the chip select. The SEECK, 515 * SEEDO, and SEEDI are connected to the clock, data out, and data in 516 * lines respectively. The SEERDY bit of SEECTL is useful in that it 517 * gives us an 800 nsec timer. After a write to the SEECTL register, 518 * the SEERDY goes high 800 nsec later. The one exception to this is 519 * when we first request access to the memory port. The SEERDY goes 520 * high to signify that access has been granted and, for this case, has 521 * no implied timing. 522 * 523 * See 93cx6.c for detailed information on the protocol necessary to 524 * read the serial EEPROM. 525 */ 526register SEECTL { 527 address 0x01e 528 bit EXTARBACK 0x80 529 bit EXTARBREQ 0x40 530 bit SEEMS 0x20 531 bit SEERDY 0x10 532 bit SEECS 0x08 533 bit SEECK 0x04 534 bit SEEDO 0x02 535 bit SEEDI 0x01 536} 537/* 538 * SCSI Block Control (p. 3-32) 539 * Controls Bus type and channel selection. In a twin channel configuration 540 * addresses 0x00-0x1e are gated to the appropriate channel based on this 541 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 542 * on a wide bus. 543 */ 544register SBLKCTL { 545 address 0x01f 546 access_mode RW 547 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 548 bit DIAGLEDON 0x40 /* Aic78X0 only */ 549 bit AUTOFLUSHDIS 0x20 550 bit SELBUSB 0x08 551 bit ENAB40 0x08 /* LVD transceiver active */ 552 bit ENAB20 0x04 /* SE/HVD transceiver active */ 553 bit SELWIDE 0x02 554 bit XCVR 0x01 /* External transceiver active */ 555} 556 557/* 558 * Sequencer Control (p. 3-33) 559 * Error detection mode and speed configuration 560 */ 561register SEQCTL { 562 address 0x060 563 access_mode RW 564 bit PERRORDIS 0x80 565 bit PAUSEDIS 0x40 566 bit FAILDIS 0x20 567 bit FASTMODE 0x10 568 bit BRKADRINTEN 0x08 569 bit STEP 0x04 570 bit SEQRESET 0x02 571 bit LOADRAM 0x01 572} 573 574/* 575 * Sequencer RAM Data (p. 3-34) 576 * Single byte window into the Scratch Ram area starting at the address 577 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 578 * four bytes in succession. The SEQADDRs will increment after the most 579 * significant byte is written 580 */ 581register SEQRAM { 582 address 0x061 583 access_mode RW 584} 585 586/* 587 * Sequencer Address Registers (p. 3-35) 588 * Only the first bit of SEQADDR1 holds addressing information 589 */ 590register SEQADDR0 { 591 address 0x062 592 access_mode RW 593} 594 595register SEQADDR1 { 596 address 0x063 597 access_mode RW 598 mask SEQADDR1_MASK 0x01 599} 600 601/* 602 * Accumulator 603 * We cheat by passing arguments in the Accumulator up to the kernel driver 604 */ 605register ACCUM { 606 address 0x064 607 access_mode RW 608 accumulator 609} 610 611register SINDEX { 612 address 0x065 613 access_mode RW 614 sindex 615} 616 617register DINDEX { 618 address 0x066 619 access_mode RW 620} 621 622register ALLONES { 623 address 0x069 624 access_mode RO 625 allones 626} 627 628register ALLZEROS { 629 address 0x06a 630 access_mode RO 631 allzeros 632} 633 634register NONE { 635 address 0x06a 636 access_mode WO 637 none 638} 639 640register FLAGS { 641 address 0x06b 642 access_mode RO 643 bit ZERO 0x02 644 bit CARRY 0x01 645} 646 647register SINDIR { 648 address 0x06c 649 access_mode RO 650} 651 652register DINDIR { 653 address 0x06d 654 access_mode WO 655} 656 657register FUNCTION1 { 658 address 0x06e 659 access_mode RW 660} 661 662register STACK { 663 address 0x06f 664 access_mode RO 665} 666 667/* 668 * Board Control (p. 3-43) 669 */ 670register BCTL { 671 address 0x084 672 access_mode RW 673 bit ACE 0x08 674 bit ENABLE 0x01 675} 676 677/* 678 * On the aic78X0 chips, Board Control is replaced by the DSCommand 679 * register (p. 4-64) 680 */ 681register DSCOMMAND0 { 682 address 0x084 683 access_mode RW 684 bit CACHETHEN 0x80 /* Cache Threshold enable */ 685 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 686 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 687 bit EXTREQLCK 0x10 /* External Request Lock */ 688 /* aic7890/91/96/97 only */ 689 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 690 bit RAMPS 0x04 /* External SCB RAM Present */ 691 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 692 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 693} 694 695register DSCOMMAND1 { 696 address 0x085 697 access_mode RW 698 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 699 bit HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 700 bit HADDLDSEL0 0x01 701} 702 703/* 704 * Bus On/Off Time (p. 3-44) aic7770 only 705 */ 706register BUSTIME { 707 address 0x085 708 access_mode RW 709 mask BOFF 0xf0 710 mask BON 0x0f 711} 712 713/* 714 * Bus Speed (p. 3-45) aic7770 only 715 */ 716register BUSSPD { 717 address 0x086 718 access_mode RW 719 mask DFTHRSH 0xc0 720 mask STBOFF 0x38 721 mask STBON 0x07 722 mask DFTHRSH_100 0xc0 723 mask DFTHRSH_75 0x80 724} 725 726/* aic7850/55/60/70/80/95 only */ 727register DSPCISTATUS { 728 address 0x086 729 mask DFTHRSH_100 0xc0 730} 731 732/* aic7890/91/96/97 only */ 733register HS_MAILBOX { 734 address 0x086 735 mask HOST_MAILBOX 0xF0 736 mask SEQ_MAILBOX 0x0F 737 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 738} 739 740const HOST_MAILBOX_SHIFT 4 741const SEQ_MAILBOX_SHIFT 0 742 743/* 744 * Host Control (p. 3-47) R/W 745 * Overall host control of the device. 746 */ 747register HCNTRL { 748 address 0x087 749 access_mode RW 750 bit POWRDN 0x40 751 bit SWINT 0x10 752 bit IRQMS 0x08 753 bit PAUSE 0x04 754 bit INTEN 0x02 755 bit CHIPRST 0x01 756 bit CHIPRSTACK 0x01 757} 758 759/* 760 * Host Address (p. 3-48) 761 * This register contains the address of the byte about 762 * to be transferred across the host bus. 763 */ 764register HADDR { 765 address 0x088 766 size 4 767 access_mode RW 768} 769 770register HCNT { 771 address 0x08c 772 size 3 773 access_mode RW 774} 775 776/* 777 * SCB Pointer (p. 3-49) 778 * Gate one of the SCBs into the SCBARRAY window. 779 */ 780register SCBPTR { 781 address 0x090 782 access_mode RW 783} 784 785/* 786 * Interrupt Status (p. 3-50) 787 * Status for system interrupts 788 */ 789register INTSTAT { 790 address 0x091 791 access_mode RW 792 bit BRKADRINT 0x08 793 bit SCSIINT 0x04 794 bit CMDCMPLT 0x02 795 bit SEQINT 0x01 796 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 797 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 798 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 799 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 800 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 801 mask PDATA_REINIT 0x50|SEQINT /* 802 * Returned to data phase 803 * that requires data 804 * transfer pointers to be 805 * recalculated from the 806 * transfer residual. 807 */ 808 mask HOST_MSG_LOOP 0x60|SEQINT /* 809 * The bus is ready for the 810 * host to perform another 811 * message transaction. This 812 * mechanism is used for things 813 * like sync/wide negotiation 814 * that require a kernel based 815 * message state engine. 816 */ 817 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 818 mask PERR_DETECTED 0x80|SEQINT /* 819 * Either the phase_lock 820 * or inb_next routine has 821 * noticed a parity error. 822 */ 823 mask DATA_OVERRUN 0x90|SEQINT /* 824 * Target attempted to write 825 * beyond the bounds of its 826 * command. 827 */ 828 mask MKMSG_FAILED 0xa0|SEQINT /* 829 * Target completed command 830 * without honoring our ATN 831 * request to issue a message. 832 */ 833 mask MISSED_BUSFREE 0xb0|SEQINT /* 834 * The sequencer never saw 835 * the bus go free after 836 * either a command complete 837 * or disconnect message. 838 */ 839 mask SCB_MISMATCH 0xc0|SEQINT /* 840 * Downloaded SCB's tag does 841 * not match the entry we 842 * intended to download. 843 */ 844 mask NO_FREE_SCB 0xd0|SEQINT /* 845 * get_free_or_disc_scb failed. 846 */ 847 mask OUT_OF_RANGE 0xe0|SEQINT 848 849 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 850 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 851} 852 853/* 854 * Hard Error (p. 3-53) 855 * Reporting of catastrophic errors. You usually cannot recover from 856 * these without a full board reset. 857 */ 858register ERROR { 859 address 0x092 860 access_mode RO 861 bit CIOPARERR 0x80 /* Ultra2 only */ 862 bit PCIERRSTAT 0x40 /* PCI only */ 863 bit MPARERR 0x20 /* PCI only */ 864 bit DPARERR 0x10 /* PCI only */ 865 bit SQPARERR 0x08 866 bit ILLOPCODE 0x04 867 bit ILLSADDR 0x02 868 bit ILLHADDR 0x01 869} 870 871/* 872 * Clear Interrupt Status (p. 3-52) 873 */ 874register CLRINT { 875 address 0x092 876 access_mode WO 877 bit CLRPARERR 0x10 /* PCI only */ 878 bit CLRBRKADRINT 0x08 879 bit CLRSCSIINT 0x04 880 bit CLRCMDINT 0x02 881 bit CLRSEQINT 0x01 882} 883 884register DFCNTRL { 885 address 0x093 886 access_mode RW 887 bit PRELOADEN 0x80 /* aic7890 only */ 888 bit WIDEODD 0x40 889 bit SCSIEN 0x20 890 bit SDMAEN 0x10 891 bit SDMAENACK 0x10 892 bit HDMAEN 0x08 893 bit HDMAENACK 0x08 894 bit DIRECTION 0x04 895 bit FIFOFLUSH 0x02 896 bit FIFORESET 0x01 897} 898 899register DFSTATUS { 900 address 0x094 901 access_mode RO 902 bit PRELOAD_AVAIL 0x80 903 bit DFCACHETH 0x40 904 bit FIFOQWDEMP 0x20 905 bit MREQPEND 0x10 906 bit HDONE 0x08 907 bit DFTHRESH 0x04 908 bit FIFOFULL 0x02 909 bit FIFOEMP 0x01 910} 911 912register DFWADDR { 913 address 0x95 914 access_mode RW 915} 916 917register DFRADDR { 918 address 0x97 919 access_mode RW 920} 921 922register DFDAT { 923 address 0x099 924 access_mode RW 925} 926 927/* 928 * SCB Auto Increment (p. 3-59) 929 * Byte offset into the SCB Array and an optional bit to allow auto 930 * incrementing of the address during download and upload operations 931 */ 932register SCBCNT { 933 address 0x09a 934 access_mode RW 935 bit SCBAUTO 0x80 936 mask SCBCNT_MASK 0x1f 937} 938 939/* 940 * Queue In FIFO (p. 3-60) 941 * Input queue for queued SCBs (commands that the seqencer has yet to start) 942 */ 943register QINFIFO { 944 address 0x09b 945 access_mode RW 946} 947 948/* 949 * Queue In Count (p. 3-60) 950 * Number of queued SCBs 951 */ 952register QINCNT { 953 address 0x09c 954 access_mode RO 955} 956 957/* 958 * Queue Out FIFO (p. 3-61) 959 * Queue of SCBs that have completed and await the host 960 */ 961register QOUTFIFO { 962 address 0x09d 963 access_mode WO 964} 965 966register CRCCONTROL1 { 967 address 0x09d 968 access_mode RW 969 bit CRCONSEEN 0x80 970 bit CRCVALCHKEN 0x40 971 bit CRCENDCHKEN 0x20 972 bit CRCREQCHKEN 0x10 973 bit TARGCRCENDEN 0x08 974 bit TARGCRCCNTEN 0x04 975} 976 977 978/* 979 * Queue Out Count (p. 3-61) 980 * Number of queued SCBs in the Out FIFO 981 */ 982register QOUTCNT { 983 address 0x09e 984 access_mode RO 985} 986 987register SCSIPHASE { 988 address 0x09e 989 access_mode RO 990 bit STATUS_PHASE 0x20 991 bit COMMAND_PHASE 0x10 992 bit MSG_IN_PHASE 0x08 993 bit MSG_OUT_PHASE 0x04 994 bit DATA_IN_PHASE 0x02 995 bit DATA_OUT_PHASE 0x01 996 mask DATA_PHASE_MASK 0x03 997} 998 999/* 1000 * Special Function 1001 */ 1002register SFUNCT { 1003 address 0x09f 1004 access_mode RW 1005 bit ALT_MODE 0x80 1006} 1007 1008/* 1009 * SCB Definition (p. 5-4) 1010 */ 1011scb { 1012 address 0x0a0 1013 size 64 1014 1015 SCB_CDB_PTR { 1016 size 4 1017 alias SCB_RESIDUAL_DATACNT 1018 alias SCB_CDB_STORE 1019 } 1020 SCB_RESIDUAL_SGPTR { 1021 size 4 1022 } 1023 SCB_SCSI_STATUS { 1024 size 1 1025 } 1026 SCB_TARGET_PHASES { 1027 size 1 1028 } 1029 SCB_TARGET_DATA_DIR { 1030 size 1 1031 } 1032 SCB_TARGET_ITAG { 1033 size 1 1034 } 1035 SCB_DATAPTR { 1036 size 4 1037 } 1038 SCB_DATACNT { 1039 /* 1040 * The last byte is really the high address bits for 1041 * the data address. 1042 */ 1043 size 4 1044 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 1045 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1046 } 1047 SCB_SGPTR { 1048 size 4 1049 bit SG_RESID_VALID 0x04 /* In the first byte */ 1050 bit SG_FULL_RESID 0x02 /* In the first byte */ 1051 bit SG_LIST_NULL 0x01 /* In the first byte */ 1052 } 1053 SCB_CONTROL { 1054 size 1 1055 bit TARGET_SCB 0x80 1056 bit DISCENB 0x40 1057 bit TAG_ENB 0x20 1058 bit MK_MESSAGE 0x10 1059 bit ULTRAENB 0x08 1060 bit DISCONNECTED 0x04 1061 mask SCB_TAG_TYPE 0x03 1062 } 1063 SCB_SCSIID { 1064 size 1 1065 bit TWIN_CHNLB 0x80 1066 mask TWIN_TID 0x70 1067 mask TID 0xf0 1068 mask OID 0x0f 1069 } 1070 SCB_LUN { 1071 mask LID 0xff 1072 size 1 1073 } 1074 SCB_TAG { 1075 size 1 1076 } 1077 SCB_CDB_LEN { 1078 size 1 1079 } 1080 SCB_SCSIRATE { 1081 size 1 1082 } 1083 SCB_SCSIOFFSET { 1084 size 1 1085 } 1086 SCB_NEXT { 1087 size 1 1088 } 1089 SCB_64_SPARE { 1090 size 16 1091 } 1092 SCB_64_BTT { 1093 size 16 1094 } 1095} 1096 1097const SCB_UPLOAD_SIZE 32 1098const SCB_DOWNLOAD_SIZE 32 1099const SCB_DOWNLOAD_SIZE_64 48 1100 1101const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1102 1103/* --------------------- AHA-2840-only definitions -------------------- */ 1104 1105register SEECTL_2840 { 1106 address 0x0c0 1107 access_mode RW 1108 bit CS_2840 0x04 1109 bit CK_2840 0x02 1110 bit DO_2840 0x01 1111} 1112 1113register STATUS_2840 { 1114 address 0x0c1 1115 access_mode RW 1116 bit EEPROM_TF 0x80 1117 mask BIOS_SEL 0x60 1118 mask ADSEL 0x1e 1119 bit DI_2840 0x01 1120} 1121 1122/* --------------------- AIC-7870-only definitions -------------------- */ 1123 1124register CCHADDR { 1125 address 0x0E0 1126 size 8 1127} 1128 1129register CCHCNT { 1130 address 0x0E8 1131} 1132 1133register CCSGRAM { 1134 address 0x0E9 1135} 1136 1137register CCSGADDR { 1138 address 0x0EA 1139} 1140 1141register CCSGCTL { 1142 address 0x0EB 1143 bit CCSGDONE 0x80 1144 bit CCSGEN 0x08 1145 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1146 bit CCSGRESET 0x01 1147} 1148 1149register CCSCBCNT { 1150 address 0xEF 1151} 1152 1153register CCSCBCTL { 1154 address 0x0EE 1155 bit CCSCBDONE 0x80 1156 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1157 bit CCARREN 0x10 1158 bit CCSCBEN 0x08 1159 bit CCSCBDIR 0x04 1160 bit CCSCBRESET 0x01 1161} 1162 1163register CCSCBADDR { 1164 address 0x0ED 1165} 1166 1167register CCSCBRAM { 1168 address 0xEC 1169} 1170 1171/* 1172 * SCB bank address (7895/7896/97 only) 1173 */ 1174register SCBBADDR { 1175 address 0x0F0 1176 access_mode RW 1177} 1178 1179register CCSCBPTR { 1180 address 0x0F1 1181} 1182 1183register HNSCB_QOFF { 1184 address 0x0F4 1185} 1186 1187register SNSCB_QOFF { 1188 address 0x0F6 1189} 1190 1191register SDSCB_QOFF { 1192 address 0x0F8 1193} 1194 1195register QOFF_CTLSTA { 1196 address 0x0FA 1197 bit SCB_AVAIL 0x40 1198 bit SNSCB_ROLLOVER 0x20 1199 bit SDSCB_ROLLOVER 0x10 1200 mask SCB_QSIZE 0x07 1201 mask SCB_QSIZE_256 0x06 1202} 1203 1204register DFF_THRSH { 1205 address 0x0FB 1206 mask WR_DFTHRSH 0x70 1207 mask RD_DFTHRSH 0x07 1208 mask RD_DFTHRSH_MIN 0x00 1209 mask RD_DFTHRSH_25 0x01 1210 mask RD_DFTHRSH_50 0x02 1211 mask RD_DFTHRSH_63 0x03 1212 mask RD_DFTHRSH_75 0x04 1213 mask RD_DFTHRSH_85 0x05 1214 mask RD_DFTHRSH_90 0x06 1215 mask RD_DFTHRSH_MAX 0x07 1216 mask WR_DFTHRSH_MIN 0x00 1217 mask WR_DFTHRSH_25 0x10 1218 mask WR_DFTHRSH_50 0x20 1219 mask WR_DFTHRSH_63 0x30 1220 mask WR_DFTHRSH_75 0x40 1221 mask WR_DFTHRSH_85 0x50 1222 mask WR_DFTHRSH_90 0x60 1223 mask WR_DFTHRSH_MAX 0x70 1224} 1225 1226register SG_CACHE_PRE { 1227 access_mode WO 1228 address 0x0fc 1229 mask SG_ADDR_MASK 0xf8 1230 bit ODD_SEG 0x04 1231 bit LAST_SEG 0x02 1232 bit LAST_SEG_DONE 0x01 1233} 1234 1235register SG_CACHE_SHADOW { 1236 access_mode RO 1237 address 0x0fc 1238 mask SG_ADDR_MASK 0xf8 1239 bit ODD_SEG 0x04 1240 bit LAST_SEG 0x02 1241 bit LAST_SEG_DONE 0x01 1242} 1243/* ---------------------- Scratch RAM Offsets ------------------------- */ 1244/* These offsets are either to values that are initialized by the board's 1245 * BIOS or are specified by the sequencer code. 1246 * 1247 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1248 * device information, 32-33 and 5a-5f as well. As it turns out, the 1249 * BIOS trashes 20-2f, writing the synchronous negotiation results 1250 * on top of the BIOS values, so we re-use those for our per-target 1251 * scratchspace (actually a value that can be copied directly into 1252 * SCSIRATE). The kernel driver will enable synchronous negotiation 1253 * for all targets that have a value other than 0 in the lower four 1254 * bits of the target scratch space. This should work regardless of 1255 * whether the bios has been installed. 1256 */ 1257 1258scratch_ram { 1259 address 0x020 1260 size 58 1261 1262 /* 1263 * 1 byte per target starting at this address for configuration values 1264 */ 1265 BUSY_TARGETS { 1266 alias TARG_SCSIRATE 1267 size 16 1268 } 1269 /* 1270 * Bit vector of targets that have ULTRA enabled as set by 1271 * the BIOS. The Sequencer relies on a per-SCB field to 1272 * control whether to enable Ultra transfers or not. During 1273 * initialization, we read this field and reuse it for 2 1274 * entries in the busy target table. 1275 */ 1276 ULTRA_ENB { 1277 alias CMDSIZE_TABLE 1278 size 2 1279 } 1280 /* 1281 * Bit vector of targets that have disconnection disabled as set by 1282 * the BIOS. The Sequencer relies in a per-SCB field to control the 1283 * disconnect priveldge. During initialization, we read this field 1284 * and reuse it for 2 entries in the busy target table. 1285 */ 1286 DISC_DSB { 1287 size 2 1288 } 1289 CMDSIZE_TABLE_TAIL { 1290 size 4 1291 } 1292 /* 1293 * Partial transfer past cacheline end to be 1294 * transferred using an extra S/G. 1295 */ 1296 MWI_RESIDUAL { 1297 size 1 1298 } 1299 /* 1300 * SCBID of the next SCB to be started by the controller. 1301 */ 1302 NEXT_QUEUED_SCB { 1303 size 1 1304 } 1305 /* 1306 * Single byte buffer used to designate the type or message 1307 * to send to a target. 1308 */ 1309 MSG_OUT { 1310 size 1 1311 } 1312 /* Parameters for DMA Logic */ 1313 DMAPARAMS { 1314 size 1 1315 bit PRELOADEN 0x80 1316 bit WIDEODD 0x40 1317 bit SCSIEN 0x20 1318 bit SDMAEN 0x10 1319 bit SDMAENACK 0x10 1320 bit HDMAEN 0x08 1321 bit HDMAENACK 0x08 1322 bit DIRECTION 0x04 /* Set indicates PCI->SCSI */ 1323 bit FIFOFLUSH 0x02 1324 bit FIFORESET 0x01 1325 } 1326 SEQ_FLAGS { 1327 size 1 1328 bit IDENTIFY_SEEN 0x80 1329 bit TARGET_CMD_IS_TAGGED 0x40 1330 bit DPHASE 0x20 1331 /* Target flags */ 1332 bit TARG_CMD_PENDING 0x10 1333 bit CMDPHASE_PENDING 0x08 1334 bit DPHASE_PENDING 0x04 1335 bit SPHASE_PENDING 0x02 1336 bit NO_DISCONNECT 0x01 1337 } 1338 /* 1339 * Temporary storage for the 1340 * target/channel/lun of a 1341 * reconnecting target 1342 */ 1343 SAVED_SCSIID { 1344 size 1 1345 } 1346 SAVED_LUN { 1347 size 1 1348 } 1349 /* 1350 * The last bus phase as seen by the sequencer. 1351 */ 1352 LASTPHASE { 1353 size 1 1354 bit CDI 0x80 1355 bit IOI 0x40 1356 bit MSGI 0x20 1357 mask PHASE_MASK CDI|IOI|MSGI 1358 mask P_DATAOUT 0x00 1359 mask P_DATAIN IOI 1360 mask P_COMMAND CDI 1361 mask P_MESGOUT CDI|MSGI 1362 mask P_STATUS CDI|IOI 1363 mask P_MESGIN CDI|IOI|MSGI 1364 mask P_BUSFREE 0x01 1365 } 1366 /* 1367 * head of list of SCBs awaiting 1368 * selection 1369 */ 1370 WAITING_SCBH { 1371 size 1 1372 } 1373 /* 1374 * head of list of SCBs that are 1375 * disconnected. Used for SCB 1376 * paging. 1377 */ 1378 DISCONNECTED_SCBH { 1379 size 1 1380 } 1381 /* 1382 * head of list of SCBs that are 1383 * not in use. Used for SCB paging. 1384 */ 1385 FREE_SCBH { 1386 size 1 1387 } 1388 /* 1389 * head of list of SCBs that have 1390 * completed but have not been 1391 * put into the qoutfifo. 1392 */ 1393 COMPLETE_SCBH { 1394 size 1 1395 } 1396 /* 1397 * Address of the hardware scb array in the host. 1398 */ 1399 HSCB_ADDR { 1400 size 4 1401 } 1402 /* 1403 * Base address of our shared data with the kernel driver in host 1404 * memory. This includes the qoutfifo and target mode 1405 * incoming command queue. 1406 */ 1407 SHARED_DATA_ADDR { 1408 size 4 1409 } 1410 KERNEL_QINPOS { 1411 size 1 1412 } 1413 QINPOS { 1414 size 1 1415 } 1416 QOUTPOS { 1417 size 1 1418 } 1419 /* 1420 * Kernel and sequencer offsets into the queue of 1421 * incoming target mode command descriptors. The 1422 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1423 */ 1424 KERNEL_TQINPOS { 1425 size 1 1426 } 1427 TQINPOS { 1428 size 1 1429 } 1430 ARG_1 { 1431 size 1 1432 mask SEND_MSG 0x80 1433 mask SEND_SENSE 0x40 1434 mask SEND_REJ 0x20 1435 mask MSGOUT_PHASEMIS 0x10 1436 mask EXIT_MSG_LOOP 0x08 1437 mask CONT_MSG_LOOP 0x04 1438 mask CONT_TARG_SESSION 0x02 1439 alias RETURN_1 1440 } 1441 ARG_2 { 1442 size 1 1443 alias RETURN_2 1444 } 1445 1446 /* 1447 * Snapshot of MSG_OUT taken after each message is sent. 1448 */ 1449 LAST_MSG { 1450 size 1 1451 } 1452 1453 /* 1454 * Sequences the kernel driver has okayed for us. This allows 1455 * the driver to do things like prevent initiator or target 1456 * operations. 1457 */ 1458 SCSISEQ_TEMPLATE { 1459 size 1 1460 bit ENSELO 0x40 1461 bit ENSELI 0x20 1462 bit ENRSELI 0x10 1463 bit ENAUTOATNO 0x08 1464 bit ENAUTOATNI 0x04 1465 bit ENAUTOATNP 0x02 1466 } 1467 1468 /* 1469 * Track whether the transfer byte count for 1470 * the current data phase is odd. 1471 */ 1472 DATA_COUNT_ODD { 1473 size 1 1474 } 1475 1476 /* 1477 * The initiator specified tag for this target mode transaction. 1478 */ 1479 INITIATOR_TAG { 1480 size 1 1481 } 1482 1483 SEQ_FLAGS2 { 1484 size 1 1485 bit SCB_DMA 0x01 1486 bit TARGET_MSG_PENDING 0x02 1487 } 1488} 1489 1490scratch_ram { 1491 address 0x05a 1492 size 6 1493 /* 1494 * These are reserved registers in the card's scratch ram. Some of 1495 * the values are specified in the AHA2742 technical reference manual 1496 * and are initialized by the BIOS at boot time. 1497 */ 1498 SCSICONF { 1499 size 1 1500 bit TERM_ENB 0x80 1501 bit RESET_SCSI 0x40 1502 bit ENSPCHK 0x20 1503 mask HSCSIID 0x07 /* our SCSI ID */ 1504 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1505 } 1506 INTDEF { 1507 address 0x05c 1508 size 1 1509 bit EDGE_TRIG 0x80 1510 mask VECTOR 0x0f 1511 } 1512 HOSTCONF { 1513 address 0x05d 1514 size 1 1515 } 1516 HA_274_BIOSCTRL { 1517 address 0x05f 1518 size 1 1519 mask BIOSMODE 0x30 1520 mask BIOSDISABLED 0x30 1521 bit CHANNEL_B_PRIMARY 0x08 1522 } 1523} 1524 1525scratch_ram { 1526 address 0x070 1527 size 16 1528 1529 /* 1530 * Per target SCSI offset values for Ultra2 controllers. 1531 */ 1532 TARG_OFFSET { 1533 size 16 1534 } 1535} 1536 1537const TID_SHIFT 4 1538const SCB_LIST_NULL 0xff 1539const TARGET_CMD_CMPLT 0xfe 1540 1541const CCSGADDR_MAX 0x80 1542const CCSGRAM_MAXSEGS 16 1543 1544/* WDTR Message values */ 1545const BUS_8_BIT 0x00 1546const BUS_16_BIT 0x01 1547const BUS_32_BIT 0x02 1548 1549/* Offset maximums */ 1550const MAX_OFFSET_8BIT 0x0f 1551const MAX_OFFSET_16BIT 0x08 1552const MAX_OFFSET_ULTRA2 0x7f 1553const HOST_MSG 0xff 1554 1555/* Target mode command processing constants */ 1556const CMD_GROUP_CODE_SHIFT 0x05 1557 1558const STATUS_BUSY 0x08 1559const STATUS_QUEUE_FULL 0x28 1560const TARGET_DATA_IN 1 1561 1562/* 1563 * Downloaded (kernel inserted) constants 1564 */ 1565/* Offsets into the SCBID array where different data is stored */ 1566const QOUTFIFO_OFFSET download 1567const QINFIFO_OFFSET download 1568const CACHESIZE_MASK download 1569const INVERTED_CACHESIZE_MASK download 1570const SG_PREFETCH_CNT download 1571const SG_PREFETCH_ALIGN_MASK download 1572const SG_PREFETCH_ADDR_MASK download 1573