1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2000 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * the GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34/* 35 * This file is processed by the aic7xxx_asm utility for use in assembling 36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 37 * a C header file for use in the kernel portion of the Aic7xxx driver. 38 * 39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 40 * Adaptec's Technical Documents Department 1-800-934-2766 41 */ 42 43/* 44 * SCSI Sequence Control (p. 3-11). 45 * Each bit, when set starts a specific SCSI sequence on the bus 46 */ 47register SCSISEQ { 48 address 0x000 49 access_mode RW 50 bit TEMODE 0x80 51 bit ENSELO 0x40 52 bit ENSELI 0x20 53 bit ENRSELI 0x10 54 bit ENAUTOATNO 0x08 55 bit ENAUTOATNI 0x04 56 bit ENAUTOATNP 0x02 57 bit SCSIRSTO 0x01 58} 59 60/* 61 * SCSI Transfer Control 0 Register (pp. 3-13). 62 * Controls the SCSI module data path. 63 */ 64register SXFRCTL0 { 65 address 0x001 66 access_mode RW 67 bit DFON 0x80 68 bit DFPEXP 0x40 69 bit FAST20 0x20 70 bit CLRSTCNT 0x10 71 bit SPIOEN 0x08 72 bit SCAMEN 0x04 73 bit CLRCHN 0x02 74} 75 76/* 77 * SCSI Transfer Control 1 Register (pp. 3-14,15). 78 * Controls the SCSI module data path. 79 */ 80register SXFRCTL1 { 81 address 0x002 82 access_mode RW 83 bit BITBUCKET 0x80 84 bit SWRAPEN 0x40 85 bit ENSPCHK 0x20 86 mask STIMESEL 0x18 87 bit ENSTIMER 0x04 88 bit ACTNEGEN 0x02 89 bit STPWEN 0x01 /* Powered Termination */ 90} 91 92/* 93 * SCSI Control Signal Read Register (p. 3-15). 94 * Reads the actual state of the SCSI bus pins 95 */ 96register SCSISIGI { 97 address 0x003 98 access_mode RO 99 bit CDI 0x80 100 bit IOI 0x40 101 bit MSGI 0x20 102 bit ATNI 0x10 103 bit SELI 0x08 104 bit BSYI 0x04 105 bit REQI 0x02 106 bit ACKI 0x01 107/* 108 * Possible phases in SCSISIGI 109 */ 110 mask PHASE_MASK CDI|IOI|MSGI 111 mask P_DATAOUT 0x00 112 mask P_DATAIN IOI 113 mask P_COMMAND CDI 114 mask P_MESGOUT CDI|MSGI 115 mask P_STATUS CDI|IOI 116 mask P_MESGIN CDI|IOI|MSGI 117} 118 119/* 120 * SCSI Control Signal Write Register (p. 3-16). 121 * Writing to this register modifies the control signals on the bus. Only 122 * those signals that are allowed in the current mode (Initiator/Target) are 123 * asserted. 124 */ 125register SCSISIGO { 126 address 0x003 127 access_mode WO 128 bit CDO 0x80 129 bit IOO 0x40 130 bit MSGO 0x20 131 bit ATNO 0x10 132 bit SELO 0x08 133 bit BSYO 0x04 134 bit REQO 0x02 135 bit ACKO 0x01 136/* 137 * Possible phases to write into SCSISIG0 138 */ 139 mask PHASE_MASK CDI|IOI|MSGI 140 mask P_DATAOUT 0x00 141 mask P_DATAIN IOI 142 mask P_COMMAND CDI 143 mask P_MESGOUT CDI|MSGI 144 mask P_STATUS CDI|IOI 145 mask P_MESGIN CDI|IOI|MSGI 146} 147 148/* 149 * SCSI Rate Control (p. 3-17). 150 * Contents of this register determine the Synchronous SCSI data transfer 151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 153 * greater than 0 enables synchronous transfers. 154 */ 155register SCSIRATE { 156 address 0x004 157 access_mode RW 158 bit WIDEXFER 0x80 /* Wide transfer control */ 159 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 160 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 161 mask SXFR 0x70 /* Sync transfer rate */ 162 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 163 mask SOFS 0x0f /* Sync offset */ 164} 165 166/* 167 * SCSI ID (p. 3-18). 168 * Contains the ID of the board and the current target on the 169 * selected channel. 170 */ 171register SCSIID { 172 address 0x005 173 access_mode RW 174 mask TID 0xf0 /* Target ID mask */ 175 mask OID 0x0f /* Our ID mask */ 176 /* 177 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 178 * The aic7890/91 allow an offset of up to 127 transfers in both wide 179 * and narrow mode. 180 */ 181 alias SCSIOFFSET 182 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 183} 184 185/* 186 * SCSI Latched Data (p. 3-19). 187 * Read/Write latches used to transfer data on the SCSI bus during 188 * Automatic or Manual PIO mode. SCSIDATH can be used for the 189 * upper byte of a 16bit wide asynchronouse data phase transfer. 190 */ 191register SCSIDATL { 192 address 0x006 193 access_mode RW 194} 195 196register SCSIDATH { 197 address 0x007 198 access_mode RW 199} 200 201/* 202 * SCSI Transfer Count (pp. 3-19,20) 203 * These registers count down the number of bytes transferred 204 * across the SCSI bus. The counter is decremented only once 205 * the data has been safely transferred. SDONE in SSTAT0 is 206 * set when STCNT goes to 0 207 */ 208register STCNT { 209 address 0x008 210 size 3 211 access_mode RW 212} 213 214/* ALT_MODE register on Ultra160 chips */ 215register OPTIONMODE { 216 address 0x008 217 access_mode RW 218 bit AUTORATEEN 0x80 219 bit AUTOACKEN 0x40 220 bit ATNMGMNTEN 0x20 221 bit BUSFREEREV 0x10 222 bit EXPPHASEDIS 0x08 223 bit SCSIDATL_IMGEN 0x04 224 bit AUTO_MSGOUT_DE 0x02 225 bit DIS_MSGIN_DUALEDGE 0x01 226 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 227} 228 229/* ALT_MODE register on Ultra160 chips */ 230register TARGCRCCNT { 231 address 0x00a 232 size 2 233 access_mode RW 234} 235 236/* 237 * Clear SCSI Interrupt 0 (p. 3-20) 238 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 239 */ 240register CLRSINT0 { 241 address 0x00b 242 access_mode WO 243 bit CLRSELDO 0x40 244 bit CLRSELDI 0x20 245 bit CLRSELINGO 0x10 246 bit CLRSWRAP 0x08 247 bit CLRSPIORDY 0x02 248} 249 250/* 251 * SCSI Status 0 (p. 3-21) 252 * Contains one set of SCSI Interrupt codes 253 * These are most likely of interest to the sequencer 254 */ 255register SSTAT0 { 256 address 0x00b 257 access_mode RO 258 bit TARGET 0x80 /* Board acting as target */ 259 bit SELDO 0x40 /* Selection Done */ 260 bit SELDI 0x20 /* Board has been selected */ 261 bit SELINGO 0x10 /* Selection In Progress */ 262 bit SWRAP 0x08 /* 24bit counter wrap */ 263 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 264 bit SDONE 0x04 /* STCNT = 0x000000 */ 265 bit SPIORDY 0x02 /* SCSI PIO Ready */ 266 bit DMADONE 0x01 /* DMA transfer completed */ 267} 268 269/* 270 * Clear SCSI Interrupt 1 (p. 3-23) 271 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 272 */ 273register CLRSINT1 { 274 address 0x00c 275 access_mode WO 276 bit CLRSELTIMEO 0x80 277 bit CLRATNO 0x40 278 bit CLRSCSIRSTI 0x20 279 bit CLRBUSFREE 0x08 280 bit CLRSCSIPERR 0x04 281 bit CLRPHASECHG 0x02 282 bit CLRREQINIT 0x01 283} 284 285/* 286 * SCSI Status 1 (p. 3-24) 287 */ 288register SSTAT1 { 289 address 0x00c 290 access_mode RO 291 bit SELTO 0x80 292 bit ATNTARG 0x40 293 bit SCSIRSTI 0x20 294 bit PHASEMIS 0x10 295 bit BUSFREE 0x08 296 bit SCSIPERR 0x04 297 bit PHASECHG 0x02 298 bit REQINIT 0x01 299} 300 301/* 302 * SCSI Status 2 (pp. 3-25,26) 303 */ 304register SSTAT2 { 305 address 0x00d 306 access_mode RO 307 bit OVERRUN 0x80 308 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 309 mask SFCNT 0x1f 310} 311 312/* 313 * SCSI Status 3 (p. 3-26) 314 */ 315register SSTAT3 { 316 address 0x00e 317 access_mode RO 318 mask SCSICNT 0xf0 319 mask OFFCNT 0x0f 320} 321 322/* 323 * SCSI ID for the aic7890/91 chips 324 */ 325register SCSIID_ULTRA2 { 326 address 0x00f 327 access_mode RW 328 mask TID 0xf0 /* Target ID mask */ 329 mask OID 0x0f /* Our ID mask */ 330} 331 332/* 333 * SCSI Interrupt Mode 1 (p. 3-28) 334 * Setting any bit will enable the corresponding function 335 * in SIMODE0 to interrupt via the IRQ pin. 336 */ 337register SIMODE0 { 338 address 0x010 339 access_mode RW 340 bit ENSELDO 0x40 341 bit ENSELDI 0x20 342 bit ENSELINGO 0x10 343 bit ENSWRAP 0x08 344 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 345 bit ENSDONE 0x04 346 bit ENSPIORDY 0x02 347 bit ENDMADONE 0x01 348} 349 350/* 351 * SCSI Interrupt Mode 1 (pp. 3-28,29) 352 * Setting any bit will enable the corresponding function 353 * in SIMODE1 to interrupt via the IRQ pin. 354 */ 355register SIMODE1 { 356 address 0x011 357 access_mode RW 358 bit ENSELTIMO 0x80 359 bit ENATNTARG 0x40 360 bit ENSCSIRST 0x20 361 bit ENPHASEMIS 0x10 362 bit ENBUSFREE 0x08 363 bit ENSCSIPERR 0x04 364 bit ENPHASECHG 0x02 365 bit ENREQINIT 0x01 366} 367 368/* 369 * SCSI Data Bus (High) (p. 3-29) 370 * This register reads data on the SCSI Data bus directly. 371 */ 372register SCSIBUSL { 373 address 0x012 374 access_mode RO 375} 376 377register SCSIBUSH { 378 address 0x013 379 access_mode RO 380} 381 382/* 383 * SCSI/Host Address (p. 3-30) 384 * These registers hold the host address for the byte about to be 385 * transferred on the SCSI bus. They are counted up in the same 386 * manner as STCNT is counted down. SHADDR should always be used 387 * to determine the address of the last byte transferred since HADDR 388 * can be skewed by write ahead. 389 */ 390register SHADDR { 391 address 0x014 392 size 4 393 access_mode RO 394} 395 396/* 397 * Selection Timeout Timer (p. 3-30) 398 */ 399register SELTIMER { 400 address 0x018 401 access_mode RW 402 bit STAGE6 0x20 403 bit STAGE5 0x10 404 bit STAGE4 0x08 405 bit STAGE3 0x04 406 bit STAGE2 0x02 407 bit STAGE1 0x01 408 alias TARGIDIN 409} 410 411/* 412 * Selection/Reselection ID (p. 3-31) 413 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 414 * device did not set its own ID. 415 */ 416register SELID { 417 address 0x019 418 access_mode RW 419 mask SELID_MASK 0xf0 420 bit ONEBIT 0x08 421} 422 423register SCAMCTL { 424 address 0x01a 425 access_mode RW 426 bit ENSCAMSELO 0x80 427 bit CLRSCAMSELID 0x40 428 bit ALTSTIM 0x20 429 bit DFLTTID 0x10 430 mask SCAMLVL 0x03 431} 432 433/* 434 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 435 */ 436register TARGID { 437 address 0x01b 438 size 2 439 access_mode RW 440} 441 442/* 443 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 444 * Indicates if external logic has been attached to the chip to 445 * perform the tasks of accessing a serial eeprom, testing termination 446 * strength, and performing cable detection. On the aic7860, most of 447 * these features are handled on chip, but on the aic7855 an attached 448 * aic3800 does the grunt work. 449 */ 450register SPIOCAP { 451 address 0x01b 452 access_mode RW 453 bit SOFT1 0x80 454 bit SOFT0 0x40 455 bit SOFTCMDEN 0x20 456 bit HAS_BRDCTL 0x10 /* External Board control */ 457 bit SEEPROM 0x08 /* External serial eeprom logic */ 458 bit EEPROM 0x04 /* Writable external BIOS ROM */ 459 bit ROM 0x02 /* Logic for accessing external ROM */ 460 bit SSPIOCPS 0x01 /* Termination and cable detection */ 461} 462 463register BRDCTL { 464 address 0x01d 465 bit BRDDAT7 0x80 466 bit BRDDAT6 0x40 467 bit BRDDAT5 0x20 468 bit BRDSTB 0x10 469 bit BRDCS 0x08 470 bit BRDRW 0x04 471 bit BRDCTL1 0x02 472 bit BRDCTL0 0x01 473 /* 7890 Definitions */ 474 bit BRDDAT4 0x10 475 bit BRDDAT3 0x08 476 bit BRDDAT2 0x04 477 bit BRDRW_ULTRA2 0x02 478 bit BRDSTB_ULTRA2 0x01 479} 480 481/* 482 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 483 * Controls the reading and writing of an external serial 1-bit 484 * EEPROM Device. In order to access the serial EEPROM, you must 485 * first set the SEEMS bit that generates a request to the memory 486 * port for access to the serial EEPROM device. When the memory 487 * port is not busy servicing another request, it reconfigures 488 * to allow access to the serial EEPROM. When this happens, SEERDY 489 * gets set high to verify that the memory port access has been 490 * granted. 491 * 492 * After successful arbitration for the memory port, the SEECS bit of 493 * the SEECTL register is connected to the chip select. The SEECK, 494 * SEEDO, and SEEDI are connected to the clock, data out, and data in 495 * lines respectively. The SEERDY bit of SEECTL is useful in that it 496 * gives us an 800 nsec timer. After a write to the SEECTL register, 497 * the SEERDY goes high 800 nsec later. The one exception to this is 498 * when we first request access to the memory port. The SEERDY goes 499 * high to signify that access has been granted and, for this case, has 500 * no implied timing. 501 * 502 * See 93cx6.c for detailed information on the protocol necessary to 503 * read the serial EEPROM. 504 */ 505register SEECTL { 506 address 0x01e 507 bit EXTARBACK 0x80 508 bit EXTARBREQ 0x40 509 bit SEEMS 0x20 510 bit SEERDY 0x10 511 bit SEECS 0x08 512 bit SEECK 0x04 513 bit SEEDO 0x02 514 bit SEEDI 0x01 515} 516/* 517 * SCSI Block Control (p. 3-32) 518 * Controls Bus type and channel selection. In a twin channel configuration 519 * addresses 0x00-0x1e are gated to the appropriate channel based on this 520 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 521 * on a wide bus. 522 */ 523register SBLKCTL { 524 address 0x01f 525 access_mode RW 526 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 527 bit DIAGLEDON 0x40 /* Aic78X0 only */ 528 bit AUTOFLUSHDIS 0x20 529 bit SELBUSB 0x08 530 bit ENAB40 0x08 /* LVD transceiver active */ 531 bit ENAB20 0x04 /* SE/HVD transceiver active */ 532 bit SELWIDE 0x02 533 bit XCVR 0x01 /* External transceiver active */ 534} 535 536/* 537 * Sequencer Control (p. 3-33) 538 * Error detection mode and speed configuration 539 */ 540register SEQCTL { 541 address 0x060 542 access_mode RW 543 bit PERRORDIS 0x80 544 bit PAUSEDIS 0x40 545 bit FAILDIS 0x20 546 bit FASTMODE 0x10 547 bit BRKADRINTEN 0x08 548 bit STEP 0x04 549 bit SEQRESET 0x02 550 bit LOADRAM 0x01 551} 552 553/* 554 * Sequencer RAM Data (p. 3-34) 555 * Single byte window into the Scratch Ram area starting at the address 556 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 557 * four bytes in succession. The SEQADDRs will increment after the most 558 * significant byte is written 559 */ 560register SEQRAM { 561 address 0x061 562 access_mode RW 563} 564 565/* 566 * Sequencer Address Registers (p. 3-35) 567 * Only the first bit of SEQADDR1 holds addressing information 568 */ 569register SEQADDR0 { 570 address 0x062 571 access_mode RW 572} 573 574register SEQADDR1 { 575 address 0x063 576 access_mode RW 577 mask SEQADDR1_MASK 0x01 578} 579 580/* 581 * Accumulator 582 * We cheat by passing arguments in the Accumulator up to the kernel driver 583 */ 584register ACCUM { 585 address 0x064 586 access_mode RW 587 accumulator 588} 589 590register SINDEX { 591 address 0x065 592 access_mode RW 593 sindex 594} 595 596register DINDEX { 597 address 0x066 598 access_mode RW 599} 600 601register ALLONES { 602 address 0x069 603 access_mode RO 604 allones 605} 606 607register ALLZEROS { 608 address 0x06a 609 access_mode RO 610 allzeros 611} 612 613register NONE { 614 address 0x06a 615 access_mode WO 616 none 617} 618 619register FLAGS { 620 address 0x06b 621 access_mode RO 622 bit ZERO 0x02 623 bit CARRY 0x01 624} 625 626register SINDIR { 627 address 0x06c 628 access_mode RO 629} 630 631register DINDIR { 632 address 0x06d 633 access_mode WO 634} 635 636register FUNCTION1 { 637 address 0x06e 638 access_mode RW 639} 640 641register STACK { 642 address 0x06f 643 access_mode RO 644} 645 646/* 647 * Board Control (p. 3-43) 648 */ 649register BCTL { 650 address 0x084 651 access_mode RW 652 bit ACE 0x08 653 bit ENABLE 0x01 654} 655 656/* 657 * On the aic78X0 chips, Board Control is replaced by the DSCommand 658 * register (p. 4-64) 659 */ 660register DSCOMMAND0 { 661 address 0x084 662 access_mode RW 663 bit CACHETHEN 0x80 /* Cache Threshold enable */ 664 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 665 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 666 bit EXTREQLCK 0x10 /* External Request Lock */ 667 /* aic7890/91/96/97 only */ 668 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 669 bit RAMPS 0x04 /* External SCB RAM Present */ 670 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 671 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 672} 673 674/* 675 * Bus On/Off Time (p. 3-44) 676 */ 677register BUSTIME { 678 address 0x085 679 access_mode RW 680 mask BOFF 0xf0 681 mask BON 0x0f 682} 683 684/* 685 * Bus Speed (p. 3-45) aic7770 only 686 */ 687register BUSSPD { 688 address 0x086 689 access_mode RW 690 mask DFTHRSH 0xc0 691 mask STBOFF 0x38 692 mask STBON 0x07 693 mask DFTHRSH_100 0xc0 694} 695 696/* aic7850/55/60/70/80/95 only */ 697register DSPCISTATUS { 698 address 0x086 699 mask DFTHRSH_100 0xc0 700} 701 702/* aic7890/91/96/97 only */ 703register HS_MAILBOX { 704 address 0x086 705 mask HOST_MAILBOX 0xF0 706 mask SEQ_MAILBOX 0x0F 707} 708 709const HOST_MAILBOX_SHIFT 4 710const SEQ_MAILBOX_SHIFT 0 711 712/* 713 * Host Control (p. 3-47) R/W 714 * Overall host control of the device. 715 */ 716register HCNTRL { 717 address 0x087 718 access_mode RW 719 bit POWRDN 0x40 720 bit SWINT 0x10 721 bit IRQMS 0x08 722 bit PAUSE 0x04 723 bit INTEN 0x02 724 bit CHIPRST 0x01 725 bit CHIPRSTACK 0x01 726} 727 728/* 729 * Host Address (p. 3-48) 730 * This register contains the address of the byte about 731 * to be transferred across the host bus. 732 */ 733register HADDR { 734 address 0x088 735 size 4 736 access_mode RW 737} 738 739register HCNT { 740 address 0x08c 741 size 3 742 access_mode RW 743} 744 745/* 746 * SCB Pointer (p. 3-49) 747 * Gate one of the four SCBs into the SCBARRAY window. 748 */ 749register SCBPTR { 750 address 0x090 751 access_mode RW 752} 753 754/* 755 * Interrupt Status (p. 3-50) 756 * Status for system interrupts 757 */ 758register INTSTAT { 759 address 0x091 760 access_mode RW 761 bit BRKADRINT 0x08 762 bit SCSIINT 0x04 763 bit CMDCMPLT 0x02 764 bit SEQINT 0x01 765 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 766 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 767 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 768 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 769 mask UPDATE_TMSG_REQ 0x60|SEQINT /* Update TMSG_REQ values */ 770 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 771 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ 772 mask TRACE_POINT 0x90|SEQINT 773 mask HOST_MSG_LOOP 0xa0|SEQINT /* 774 * The bus is ready for the 775 * host to perform another 776 * message transaction. This 777 * mechanism is used for things 778 * like sync/wide negotiation 779 * that require a kernel based 780 * message state engine. 781 */ 782 mask PERR_DETECTED 0xb0|SEQINT /* 783 * Either the phase_lock 784 * or inb_next routine has 785 * noticed a parity error. 786 */ 787 mask TRACEPOINT 0xd0|SEQINT 788 mask MSGIN_PHASEMIS 0xe0|SEQINT /* 789 * Target changed phase on us 790 * when we were expecting 791 * another msgin byte. 792 */ 793 mask DATA_OVERRUN 0xf0|SEQINT /* 794 * Target attempted to write 795 * beyond the bounds of its 796 * command. 797 */ 798 799 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 800 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 801} 802 803/* 804 * Hard Error (p. 3-53) 805 * Reporting of catastrophic errors. You usually cannot recover from 806 * these without a full board reset. 807 */ 808register ERROR { 809 address 0x092 810 access_mode RO 811 bit CIOPARERR 0x80 /* Ultra2 only */ 812 bit PCIERRSTAT 0x40 /* PCI only */ 813 bit MPARERR 0x20 /* PCI only */ 814 bit DPARERR 0x10 /* PCI only */ 815 bit SQPARERR 0x08 816 bit ILLOPCODE 0x04 817 bit ILLSADDR 0x02 818 bit ILLHADDR 0x01 819} 820 821/* 822 * Clear Interrupt Status (p. 3-52) 823 */ 824register CLRINT { 825 address 0x092 826 access_mode WO 827 bit CLRPARERR 0x10 /* PCI only */ 828 bit CLRBRKADRINT 0x08 829 bit CLRSCSIINT 0x04 830 bit CLRCMDINT 0x02 831 bit CLRSEQINT 0x01 832} 833 834register DFCNTRL { 835 address 0x093 836 access_mode RW 837 bit PRELOADEN 0x80 /* aic7890 only */ 838 bit WIDEODD 0x40 839 bit SCSIEN 0x20 840 bit SDMAEN 0x10 841 bit SDMAENACK 0x10 842 bit HDMAEN 0x08 843 bit HDMAENACK 0x08 844 bit DIRECTION 0x04 845 bit FIFOFLUSH 0x02 846 bit FIFORESET 0x01 847} 848 849register DFSTATUS { 850 address 0x094 851 access_mode RO 852 bit PRELOAD_AVAIL 0x80 853 bit DWORDEMP 0x20 854 bit MREQPEND 0x10 855 bit HDONE 0x08 856 bit DFTHRESH 0x04 857 bit FIFOFULL 0x02 858 bit FIFOEMP 0x01 859} 860 861register DFWADDR { 862 address 0x95 863 access_mode RW 864} 865 866register DFRADDR { 867 address 0x97 868 access_mode RW 869} 870 871register DFDAT { 872 address 0x099 873 access_mode RW 874} 875 876/* 877 * SCB Auto Increment (p. 3-59) 878 * Byte offset into the SCB Array and an optional bit to allow auto 879 * incrementing of the address during download and upload operations 880 */ 881register SCBCNT { 882 address 0x09a 883 access_mode RW 884 bit SCBAUTO 0x80 885 mask SCBCNT_MASK 0x1f 886} 887 888/* 889 * Queue In FIFO (p. 3-60) 890 * Input queue for queued SCBs (commands that the seqencer has yet to start) 891 */ 892register QINFIFO { 893 address 0x09b 894 access_mode RW 895} 896 897/* 898 * Queue In Count (p. 3-60) 899 * Number of queued SCBs 900 */ 901register QINCNT { 902 address 0x09c 903 access_mode RO 904} 905 906/* 907 * Queue Out FIFO (p. 3-61) 908 * Queue of SCBs that have completed and await the host 909 */ 910register QOUTFIFO { 911 address 0x09d 912 access_mode WO 913} 914 915register CRCCONTROL1 { 916 address 0x09d 917 access_mode RW 918 bit CRCONSEEN 0x80 919 bit CRCVALCHKEN 0x40 920 bit CRCENDCHKEN 0x20 921 bit CRCREQCHKEN 0x10 922 bit TARGCRCENDEN 0x08 923 bit TARGCRCCNTEN 0x04 924} 925 926 927/* 928 * Queue Out Count (p. 3-61) 929 * Number of queued SCBs in the Out FIFO 930 */ 931register QOUTCNT { 932 address 0x09e 933 access_mode RO 934} 935 936register SCSIPHASE { 937 address 0x09e 938 access_mode RO 939 bit STATUS_PHASE 0x20 940 bit COMMAND_PHASE 0x10 941 bit MSG_IN_PHASE 0x08 942 bit MSG_OUT_PHASE 0x04 943 bit DATA_IN_PHASE 0x02 944 bit DATA_OUT_PHASE 0x01 945} 946 947/* 948 * Special Function 949 */ 950register SFUNCT { 951 address 0x09f 952 access_mode RW 953 bit ALT_MODE 0x80 954} 955 956/* 957 * SCB Definition (p. 5-4) 958 */ 959scb { 960 address 0x0a0 961 SCB_CONTROL { 962 size 1 963 bit TARGET_SCB 0x80 964 bit DISCENB 0x40 965 bit TAG_ENB 0x20 966 bit MK_MESSAGE 0x10 967 bit ULTRAENB 0x08 968 bit DISCONNECTED 0x04 969 mask SCB_TAG_TYPE 0x03 970 } 971 SCB_TCL { 972 size 1 973 bit SELBUSB 0x08 974 mask TID 0xf0 975 mask LID 0x07 976 } 977 SCB_TARGET_STATUS { 978 size 1 979 } 980 SCB_SGCOUNT { 981 size 1 982 } 983 SCB_SGPTR { 984 size 4 985 } 986 SCB_RESID_SGCNT { 987 size 1 988 } 989 SCB_RESID_DCNT { 990 size 3 991 } 992 SCB_DATAPTR { 993 size 4 994 } 995 SCB_DATACNT { 996 /* 997 * Really only 3 bytes, but padded to make 998 * the kernel's job easier. 999 */ 1000 size 4 1001 } 1002 SCB_CMDPTR { 1003 alias SCB_TARGET_PHASES 1004 bit TARGET_DATA_IN 0x1 /* In the second byte */ 1005 size 4 1006 } 1007 SCB_CMDLEN { 1008 alias SCB_INITIATOR_TAG 1009 size 1 1010 } 1011 SCB_TAG { 1012 size 1 1013 } 1014 SCB_NEXT { 1015 size 1 1016 } 1017 SCB_SCSIRATE { 1018 size 1 1019 } 1020 SCB_SCSIOFFSET { 1021 size 1 1022 } 1023 SCB_SPARE { 1024 size 3 1025 } 1026 SCB_CMDSTORE { 1027 size 16 1028 } 1029 SCB_CMDSTORE_BUSADDR { 1030 size 4 1031 } 1032 SCB_64BYTE_SPARE { 1033 size 12 1034 } 1035} 1036 1037const SCB_32BYTE_SIZE 28 1038const SCB_64BYTE_SIZE 48 1039 1040const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1041 1042/* --------------------- AHA-2840-only definitions -------------------- */ 1043 1044register SEECTL_2840 { 1045 address 0x0c0 1046 access_mode RW 1047 bit CS_2840 0x04 1048 bit CK_2840 0x02 1049 bit DO_2840 0x01 1050} 1051 1052register STATUS_2840 { 1053 address 0x0c1 1054 access_mode RW 1055 bit EEPROM_TF 0x80 1056 mask BIOS_SEL 0x60 1057 mask ADSEL 0x1e 1058 bit DI_2840 0x01 1059} 1060 1061/* --------------------- AIC-7870-only definitions -------------------- */ 1062 1063register CCHADDR { 1064 address 0x0E0 1065 size 8 1066} 1067 1068register CCHCNT { 1069 address 0x0E8 1070} 1071 1072register CCSGRAM { 1073 address 0x0E9 1074} 1075 1076register CCSGADDR { 1077 address 0x0EA 1078} 1079 1080register CCSGCTL { 1081 address 0x0EB 1082 bit CCSGDONE 0x80 1083 bit CCSGEN 0x08 1084 bit FLAG 0x02 1085 bit CCSGRESET 0x01 1086} 1087 1088register CCSCBCNT { 1089 address 0xEF 1090} 1091 1092register CCSCBCTL { 1093 address 0x0EE 1094 bit CCSCBDONE 0x80 1095 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1096 bit CCARREN 0x10 1097 bit CCSCBEN 0x08 1098 bit CCSCBDIR 0x04 1099 bit CCSCBRESET 0x01 1100} 1101 1102register CCSCBADDR { 1103 address 0x0ED 1104} 1105 1106register CCSCBRAM { 1107 address 0xEC 1108} 1109 1110/* 1111 * SCB bank address (7895/7896/97 only) 1112 */ 1113register SCBBADDR { 1114 address 0x0F0 1115 access_mode RW 1116} 1117 1118register CCSCBPTR { 1119 address 0x0F1 1120} 1121 1122register HNSCB_QOFF { 1123 address 0x0F4 1124} 1125 1126register SNSCB_QOFF { 1127 address 0x0F6 1128} 1129 1130register SDSCB_QOFF { 1131 address 0x0F8 1132} 1133 1134register QOFF_CTLSTA { 1135 address 0x0FA 1136 bit SCB_AVAIL 0x40 1137 bit SNSCB_ROLLOVER 0x20 1138 bit SDSCB_ROLLOVER 0x10 1139 mask SCB_QSIZE 0x07 1140 mask SCB_QSIZE_256 0x06 1141} 1142 1143register DFF_THRSH { 1144 address 0x0FB 1145 mask WR_DFTHRSH 0x70 1146 mask RD_DFTHRSH 0x07 1147 mask RD_DFTHRSH_MIN 0x00 1148 mask RD_DFTHRSH_25 0x01 1149 mask RD_DFTHRSH_50 0x02 1150 mask RD_DFTHRSH_63 0x03 1151 mask RD_DFTHRSH_75 0x04 1152 mask RD_DFTHRSH_85 0x05 1153 mask RD_DFTHRSH_90 0x06 1154 mask RD_DFTHRSH_MAX 0x07 1155 mask WR_DFTHRSH_MIN 0x00 1156 mask WR_DFTHRSH_25 0x10 1157 mask WR_DFTHRSH_50 0x20 1158 mask WR_DFTHRSH_63 0x30 1159 mask WR_DFTHRSH_75 0x40 1160 mask WR_DFTHRSH_85 0x50 1161 mask WR_DFTHRSH_90 0x60 1162 mask WR_DFTHRSH_MAX 0x70 1163} 1164 1165register SG_CACHEPTR { 1166 access_mode RW 1167 address 0x0fc 1168 mask SG_USER_DATA 0xfc 1169 bit LAST_SEG 0x02 1170 bit LAST_SEG_DONE 0x01 1171} 1172 1173/* ---------------------- Scratch RAM Offsets ------------------------- */ 1174/* These offsets are either to values that are initialized by the board's 1175 * BIOS or are specified by the sequencer code. 1176 * 1177 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1178 * device information, 32-33 and 5a-5f as well. As it turns out, the 1179 * BIOS trashes 20-2f, writing the synchronous negotiation results 1180 * on top of the BIOS values, so we re-use those for our per-target 1181 * scratchspace (actually a value that can be copied directly into 1182 * SCSIRATE). The kernel driver will enable synchronous negotiation 1183 * for all targets that have a value other than 0 in the lower four 1184 * bits of the target scratch space. This should work regardless of 1185 * whether the bios has been installed. 1186 */ 1187 1188scratch_ram { 1189 address 0x020 1190 1191 /* 1192 * 1 byte per target starting at this address for configuration values 1193 */ 1194 TARG_SCSIRATE { 1195 alias CMDSIZE_TABLE 1196 size 16 1197 } 1198 /* 1199 * Bit vector of targets that have ULTRA enabled. 1200 */ 1201 ULTRA_ENB { 1202 size 2 1203 } 1204 /* 1205 * Bit vector of targets that have disconnection disabled. 1206 */ 1207 DISC_DSB { 1208 size 2 1209 } 1210 /* 1211 * Single byte buffer used to designate the type or message 1212 * to send to a target. 1213 */ 1214 MSG_OUT { 1215 size 1 1216 } 1217 /* Parameters for DMA Logic */ 1218 DMAPARAMS { 1219 size 1 1220 bit PRELOADEN 0x80 1221 bit WIDEODD 0x40 1222 bit SCSIEN 0x20 1223 bit SDMAEN 0x10 1224 bit SDMAENACK 0x10 1225 bit HDMAEN 0x08 1226 bit HDMAENACK 0x08 1227 bit DIRECTION 0x04 1228 bit FIFOFLUSH 0x02 1229 bit FIFORESET 0x01 1230 } 1231 SEQ_FLAGS { 1232 size 1 1233 bit IDENTIFY_SEEN 0x80 1234 bit SCBPTR_VALID 0x40 1235 bit DPHASE 0x20 1236 /* Target flags */ 1237 bit TARG_CMD_PENDING 0x10 1238 bit CMDPHASE_PENDING 0x08 1239 bit DPHASE_PENDING 0x04 1240 bit SPHASE_PENDING 0x02 1241 bit NO_DISCONNECT 0x01 1242 } 1243 /* 1244 * Temporary storage for the 1245 * target/channel/lun of a 1246 * reconnecting target 1247 */ 1248 SAVED_TCL { 1249 size 1 1250 } 1251 /* Working value of the number of SG segments left */ 1252 SG_COUNT { 1253 size 1 1254 } 1255 /* Working value of SG pointer */ 1256 SG_NEXT { 1257 size 4 1258 } 1259 /* 1260 * The last bus phase as seen by the sequencer. 1261 */ 1262 LASTPHASE { 1263 size 1 1264 bit CDI 0x80 1265 bit IOI 0x40 1266 bit MSGI 0x20 1267 mask PHASE_MASK CDI|IOI|MSGI 1268 mask P_DATAOUT 0x00 1269 mask P_DATAIN IOI 1270 mask P_COMMAND CDI 1271 mask P_MESGOUT CDI|MSGI 1272 mask P_STATUS CDI|IOI 1273 mask P_MESGIN CDI|IOI|MSGI 1274 mask P_BUSFREE 0x01 1275 } 1276 /* 1277 * head of list of SCBs awaiting 1278 * selection 1279 */ 1280 WAITING_SCBH { 1281 size 1 1282 } 1283 /* 1284 * head of list of SCBs that are 1285 * disconnected. Used for SCB 1286 * paging. 1287 */ 1288 DISCONNECTED_SCBH { 1289 size 1 1290 } 1291 /* 1292 * head of list of SCBs that are 1293 * not in use. Used for SCB paging. 1294 */ 1295 FREE_SCBH { 1296 size 1 1297 } 1298 /* 1299 * Address of the hardware scb array in the host. 1300 */ 1301 HSCB_ADDR { 1302 size 4 1303 } 1304 /* 1305 * Address of the 256 byte array storing the SCBID of outstanding 1306 * untagged SCBs indexed by TCL. 1307 */ 1308 SCBID_ADDR { 1309 size 4 1310 } 1311 /* 1312 * Address of the array of command descriptors used to store 1313 * information about incoming selections. 1314 */ 1315 TMODE_CMDADDR { 1316 size 4 1317 } 1318 KERNEL_QINPOS { 1319 size 1 1320 } 1321 QINPOS { 1322 size 1 1323 } 1324 QOUTPOS { 1325 size 1 1326 } 1327 /* 1328 * Kernel and sequencer offsets into the queue of 1329 * incoming target mode command descriptors. The 1330 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1331 */ 1332 KERNEL_TQINPOS { 1333 size 1 1334 } 1335 TQINPOS { 1336 size 1 1337 } 1338 ARG_1 { 1339 size 1 1340 mask SEND_MSG 0x80 1341 mask SEND_SENSE 0x40 1342 mask SEND_REJ 0x20 1343 mask MSGOUT_PHASEMIS 0x10 1344 mask EXIT_MSG_LOOP 0x08 1345 mask CONT_MSG_LOOP 0x04 1346 mask CONT_TARG_SESSION 0x02 1347 alias RETURN_1 1348 } 1349 ARG_2 { 1350 size 1 1351 alias RETURN_2 1352 } 1353 1354 /* 1355 * Snapshot of MSG_OUT taken after each message is sent. 1356 */ 1357 LAST_MSG { 1358 size 1 1359 } 1360 1361 /* 1362 * Number of times we have filled the CCSGRAM with prefetched 1363 * SG elements. 1364 */ 1365 PREFETCH_CNT { 1366 size 1 1367 } 1368 1369 /* 1370 * Interrupt kernel for a message to this target on 1371 * the next transaction. This is usually used for 1372 * negotiation requests. 1373 */ 1374 TARGET_MSG_REQUEST { 1375 size 2 1376 } 1377 1378 /* 1379 * Sequences the kernel driver has okayed for us. This allows 1380 * the driver to do things like prevent initiator or target 1381 * operations. 1382 */ 1383 SCSISEQ_TEMPLATE { 1384 size 1 1385 bit ENSELO 0x40 1386 bit ENSELI 0x20 1387 bit ENRSELI 0x10 1388 bit ENAUTOATNO 0x08 1389 bit ENAUTOATNI 0x04 1390 bit ENAUTOATNP 0x02 1391 } 1392 1393 /* 1394 * Track whether the transfer byte count for 1395 * the current data phase is odd. 1396 */ 1397 DATA_COUNT_ODD { 1398 size 1 1399 } 1400 1401 /* 1402 * The initiator specified tag for this target mode transaction. 1403 */ 1404 INITIATOR_TAG { 1405 size 1 1406 } 1407 1408 /* 1409 * These are reserved registers in the card's scratch ram. Some of 1410 * the values are specified in the AHA2742 technical reference manual 1411 * and are initialized by the BIOS at boot time. 1412 */ 1413 SCSICONF { 1414 address 0x05a 1415 size 1 1416 bit TERM_ENB 0x80 1417 bit RESET_SCSI 0x40 1418 bit ENSPCHK 0x20 1419 mask HSCSIID 0x07 /* our SCSI ID */ 1420 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1421 } 1422 HOSTCONF { 1423 address 0x05d 1424 size 1 1425 } 1426 HA_274_BIOSCTRL { 1427 address 0x05f 1428 size 1 1429 mask BIOSMODE 0x30 1430 mask BIOSDISABLED 0x30 1431 bit CHANNEL_B_PRIMARY 0x08 1432 } 1433 /* 1434 * Per target SCSI offset values for Ultra2 controllers. 1435 */ 1436 TARG_OFFSET { 1437 address 0x070 1438 size 16 1439 } 1440} 1441 1442const SCB_LIST_NULL 0xff 1443const TARGET_CMD_CMPLT 0xfe 1444 1445const CCSGADDR_MAX 0x80 1446const CCSGRAM_MAXSEGS 16 1447 1448/* Offsets into the SCBID array where different data is stored */ 1449const QOUTFIFO_OFFSET 0 1450const QINFIFO_OFFSET 1 1451const UNTAGGEDSCB_OFFSET 2 1452 1453/* WDTR Message values */ 1454const BUS_8_BIT 0x00 1455const BUS_16_BIT 0x01 1456const BUS_32_BIT 0x02 1457 1458/* Offset maximums */ 1459const MAX_OFFSET_8BIT 0x0f 1460const MAX_OFFSET_16BIT 0x08 1461const MAX_OFFSET_ULTRA2 0x7f 1462const HOST_MSG 0xff 1463 1464/* Target mode command processing constants */ 1465const CMD_GROUP_CODE_SHIFT 0x05 1466 1467const TCL_TARGET_SHIFT 4 1468/* The update interval must be a power of 2 */ 1469const TQINFIFO_UPDATE_CNT 32 1470 1471const STATUS_BUSY 0x08 1472const STATUS_QUEUE_FULL 0x28 1473 1474/* 1475 * Downloaded (kernel inserted) constants 1476 */ 1477 1478/* 1479 * Number of command descriptors in the command descriptor array. 1480 * No longer used, but left here as an example for how downloaded 1481 * constantants can be defined. 1482const TMODE_NUMCMDS download 1483 */ 1484