xref: /freebsd/sys/dev/aic7xxx/aic7xxx.reg (revision a8445737e740901f5f2c8d24c12ef7fc8b00134e)
1/*
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-1998 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions, and the following disclaimer,
12 *    without modification, immediately at the beginning of the file.
13 * 2. The name of the author may not be used to endorse or promote products
14 *    derived from this software without specific prior written permission.
15 *
16 * Where this Software is combined with software released under the terms of
17 * the GNU Public License ("GPL") and the terms of the GPL would require the
18 * combined work to also be released under the terms of the GPL, the terms
19 * and conditions of this License will apply in addition to those of the
20 * GPL with the exception of any terms or conditions of this License that
21 * conflict with, or are expressly prohibited by, the GPL.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 *	$Id: aic7xxx.reg,v 1.4 1997/06/27 19:38:39 gibbs Exp $
36 */
37
38/*
39 * This file is processed by the aic7xxx_asm utility for use in assembling
40 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
41 * a C header file for use in the kernel portion of the Aic7xxx driver.
42 *
43 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
44 * Adaptec's Technical Documents Department 1-800-934-2766
45 */
46
47/*
48 * SCSI Sequence Control (p. 3-11).
49 * Each bit, when set starts a specific SCSI sequence on the bus
50 */
51register SCSISEQ {
52	address			0x000
53	access_mode RW
54	bit	TEMODE		0x80
55	bit	ENSELO		0x40
56	bit	ENSELI		0x20
57	bit	ENRSELI		0x10
58	bit	ENAUTOATNO	0x08
59	bit	ENAUTOATNI	0x04
60	bit	ENAUTOATNP	0x02
61	bit	SCSIRSTO	0x01
62}
63
64/*
65 * SCSI Transfer Control 0 Register (pp. 3-13).
66 * Controls the SCSI module data path.
67 */
68register SXFRCTL0 {
69	address			0x001
70	access_mode RW
71	bit	DFON		0x80
72	bit	DFPEXP		0x40
73	bit	FAST20		0x20
74	bit	CLRSTCNT	0x10
75	bit	SPIOEN		0x08
76	bit	SCAMEN		0x04
77	bit	CLRCHN		0x02
78}
79
80/*
81 * SCSI Transfer Control 1 Register (pp. 3-14,15).
82 * Controls the SCSI module data path.
83 */
84register SXFRCTL1 {
85	address			0x002
86	access_mode RW
87	bit	BITBUCKET	0x80
88	bit	SWRAPEN		0x40
89	bit	ENSPCHK		0x20
90	mask	STIMESEL	0x18
91	bit	ENSTIMER	0x04
92	bit	ACTNEGEN	0x02
93	bit	STPWEN		0x01	/* Powered Termination */
94}
95
96/*
97 * SCSI Control Signal Read Register (p. 3-15).
98 * Reads the actual state of the SCSI bus pins
99 */
100register SCSISIGI {
101	address			0x003
102	access_mode RO
103	bit	CDI		0x80
104	bit	IOI		0x40
105	bit	MSGI		0x20
106	bit	ATNI		0x10
107	bit	SELI		0x08
108	bit	BSYI		0x04
109	bit	REQI		0x02
110	bit	ACKI		0x01
111/*
112 * Possible phases in SCSISIGI
113 */
114	mask	PHASE_MASK	CDI|IOI|MSGI
115	mask	P_DATAOUT	0x00
116	mask	P_DATAIN	IOI
117	mask	P_COMMAND	CDI
118	mask	P_MESGOUT	CDI|MSGI
119	mask	P_STATUS	CDI|IOI
120	mask	P_MESGIN	CDI|IOI|MSGI
121}
122
123/*
124 * SCSI Control Signal Write Register (p. 3-16).
125 * Writing to this register modifies the control signals on the bus.  Only
126 * those signals that are allowed in the current mode (Initiator/Target) are
127 * asserted.
128 */
129register SCSISIGO {
130	address			0x003
131	access_mode WO
132	bit	CDO		0x80
133	bit	IOO		0x40
134	bit	MSGO		0x20
135	bit	ATNO		0x10
136	bit	SELO		0x08
137	bit	BSYO		0x04
138	bit	REQO		0x02
139	bit	ACKO		0x01
140/*
141 * Possible phases to write into SCSISIG0
142 */
143	mask	PHASE_MASK	CDI|IOI|MSGI
144	mask	P_DATAOUT	0x00
145	mask	P_DATAIN	IOI
146	mask	P_COMMAND	CDI
147	mask	P_MESGOUT	CDI|MSGI
148	mask	P_STATUS	CDI|IOI
149	mask	P_MESGIN	CDI|IOI|MSGI
150}
151
152/*
153 * SCSI Rate Control (p. 3-17).
154 * Contents of this register determine the Synchronous SCSI data transfer
155 * rate and the maximum synchronous Req/Ack offset.  An offset of 0 in the
156 * SOFS (3:0) bits disables synchronous data transfers.  Any offset value
157 * greater than 0 enables synchronous transfers.
158 */
159register SCSIRATE {
160	address			0x004
161	access_mode RW
162	bit	WIDEXFER	0x80		/* Wide transfer control */
163	mask	SXFR		0x70		/* Sync transfer rate */
164	mask	SXFR_ULTRA2	0x7f		/* Sync transfer rate */
165	mask	SOFS		0x0f		/* Sync offset */
166}
167
168/*
169 * SCSI ID (p. 3-18).
170 * Contains the ID of the board and the current target on the
171 * selected channel.
172 */
173register SCSIID	{
174	address			0x005
175	access_mode RW
176	mask	TID		0xf0		/* Target ID mask */
177	mask	OID		0x0f		/* Our ID mask */
178	/*
179	 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
180	 * The aic7890/91 allow an offset of up to 127 transfers in both wide
181	 * and narrow mode.
182	 */
183	alias	SCSIOFFSET
184	mask	SOFS_ULTRA2	0x7f		/* Sync offset U2 chips */
185}
186
187/*
188 * SCSI Latched Data (p. 3-19).
189 * Read/Write latches used to transfer data on the SCSI bus during
190 * Automatic or Manual PIO mode.  SCSIDATH can be used for the
191 * upper byte of a 16bit wide asynchronouse data phase transfer.
192 */
193register SCSIDATL {
194	address			0x006
195	access_mode RW
196}
197
198register SCSIDATH {
199	address			0x007
200	access_mode RW
201}
202
203/*
204 * SCSI Transfer Count (pp. 3-19,20)
205 * These registers count down the number of bytes transferred
206 * across the SCSI bus.  The counter is decremented only once
207 * the data has been safely transferred.  SDONE in SSTAT0 is
208 * set when STCNT goes to 0
209 */
210register STCNT {
211	address			0x008
212	size	3
213	access_mode RW
214}
215
216/*
217 * Clear SCSI Interrupt 0 (p. 3-20)
218 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
219 */
220register CLRSINT0 {
221	address			0x00b
222	access_mode WO
223	bit	CLRSELDO	0x40
224	bit	CLRSELDI	0x20
225	bit	CLRSELINGO	0x10
226	bit	CLRSWRAP	0x08
227	bit	CLRSPIORDY	0x02
228}
229
230/*
231 * SCSI Status 0 (p. 3-21)
232 * Contains one set of SCSI Interrupt codes
233 * These are most likely of interest to the sequencer
234 */
235register SSTAT0	{
236	address			0x00b
237	access_mode RO
238	bit	TARGET		0x80	/* Board acting as target */
239	bit	SELDO		0x40	/* Selection Done */
240	bit	SELDI		0x20	/* Board has been selected */
241	bit	SELINGO		0x10	/* Selection In Progress */
242	bit	SWRAP		0x08	/* 24bit counter wrap */
243	bit	IOERR		0x08	/* LVD Tranceiver mode changed */
244	bit	SDONE		0x04	/* STCNT = 0x000000 */
245	bit	SPIORDY		0x02	/* SCSI PIO Ready */
246	bit	DMADONE		0x01	/* DMA transfer completed */
247}
248
249/*
250 * Clear SCSI Interrupt 1 (p. 3-23)
251 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
252 */
253register CLRSINT1 {
254	address			0x00c
255	access_mode WO
256	bit	CLRSELTIMEO	0x80
257	bit	CLRATNO		0x40
258	bit	CLRSCSIRSTI	0x20
259	bit	CLRBUSFREE	0x08
260	bit	CLRSCSIPERR	0x04
261	bit	CLRPHASECHG	0x02
262	bit	CLRREQINIT	0x01
263}
264
265/*
266 * SCSI Status 1 (p. 3-24)
267 */
268register SSTAT1	{
269	address			0x00c
270	access_mode RO
271	bit	SELTO		0x80
272	bit	ATNTARG 	0x40
273	bit	SCSIRSTI	0x20
274	bit	PHASEMIS	0x10
275	bit	BUSFREE		0x08
276	bit	SCSIPERR	0x04
277	bit	PHASECHG	0x02
278	bit	REQINIT		0x01
279}
280
281/*
282 * SCSI Status 2 (pp. 3-25,26)
283 */
284register SSTAT2 {
285	address			0x00d
286	access_mode RO
287	bit	OVERRUN		0x80
288	bit	EXP_ACTIVE	0x10	/* SCSI Expander Active */
289	mask	SFCNT		0x1f
290}
291
292/*
293 * SCSI Status 3 (p. 3-26)
294 */
295register SSTAT3 {
296	address			0x00e
297	access_mode RO
298	mask	SCSICNT		0xf0
299	mask	OFFCNT		0x0f
300}
301
302/*
303 * SCSI ID for the aic7890/91 chips
304 */
305register SCSIID_ULTRA2 {
306	address			0x00f
307	access_mode RW
308	mask	TID		0xf0		/* Target ID mask */
309	mask	OID		0x0f		/* Our ID mask */
310}
311
312/*
313 * SCSI Interrupt Mode 1 (p. 3-28)
314 * Setting any bit will enable the corresponding function
315 * in SIMODE0 to interrupt via the IRQ pin.
316 */
317register SIMODE0 {
318	address			0x010
319	access_mode RW
320	bit	ENSELDO		0x40
321	bit	ENSELDI		0x20
322	bit	ENSELINGO	0x10
323	bit	ENSWRAP		0x08
324	bit	ENIOERR		0x08	/* LVD Tranceiver mode changes */
325	bit	ENSDONE		0x04
326	bit	ENSPIORDY	0x02
327	bit	ENDMADONE	0x01
328}
329
330/*
331 * SCSI Interrupt Mode 1 (pp. 3-28,29)
332 * Setting any bit will enable the corresponding function
333 * in SIMODE1 to interrupt via the IRQ pin.
334 */
335register SIMODE1 {
336	address			0x011
337	access_mode RW
338	bit	ENSELTIMO	0x80
339	bit	ENATNTARG	0x40
340	bit	ENSCSIRST	0x20
341	bit	ENPHASEMIS	0x10
342	bit	ENBUSFREE	0x08
343	bit	ENSCSIPERR	0x04
344	bit	ENPHASECHG	0x02
345	bit	ENREQINIT	0x01
346}
347
348/*
349 * SCSI Data Bus (High) (p. 3-29)
350 * This register reads data on the SCSI Data bus directly.
351 */
352register SCSIBUSL {
353	address			0x012
354	access_mode RO
355}
356
357register SCSIBUSH {
358	address			0x013
359	access_mode RO
360}
361
362/*
363 * SCSI/Host Address (p. 3-30)
364 * These registers hold the host address for the byte about to be
365 * transferred on the SCSI bus.  They are counted up in the same
366 * manner as STCNT is counted down.  SHADDR should always be used
367 * to determine the address of the last byte transferred since HADDR
368 * can be skewed by write ahead.
369 */
370register SHADDR {
371	address			0x014
372	size	4
373	access_mode RO
374}
375
376/*
377 * Selection Timeout Timer (p. 3-30)
378 */
379register SELTIMER {
380	address			0x018
381	access_mode RW
382	bit	STAGE6		0x20
383	bit	STAGE5		0x10
384	bit	STAGE4		0x08
385	bit	STAGE3		0x04
386	bit	STAGE2		0x02
387	bit	STAGE1		0x01
388	alias	TARGIDIN
389}
390
391/*
392 * Selection/Reselection ID (p. 3-31)
393 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
394 * device did not set its own ID.
395 */
396register SELID {
397	address			0x019
398	access_mode RW
399	mask	SELID_MASK	0xf0
400	bit	ONEBIT		0x08
401}
402
403/*
404 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
405 */
406register TARGID {
407	address			0x01b
408	size			2
409	access_mode RW
410}
411
412/*
413 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
414 * Indicates if external logic has been attached to the chip to
415 * perform the tasks of accessing a serial eeprom, testing termination
416 * strength, and performing cable detection.  On the aic7860, most of
417 * these features are handled on chip, but on the aic7855 an attached
418 * aic3800 does the grunt work.
419 */
420register SPIOCAP {
421	address			0x01b
422	access_mode RW
423	bit	SOFT1		0x80
424	bit	SOFT0		0x40
425	bit	SOFTCMDEN	0x20
426	bit	HAS_BRDCTL	0x10	/* External Board control */
427	bit	SEEPROM		0x08	/* External serial eeprom logic */
428	bit	EEPROM		0x04	/* Writable external BIOS ROM */
429	bit	ROM		0x02	/* Logic for accessing external ROM */
430	bit	SSPIOCPS	0x01	/* Termination and cable detection */
431}
432
433/*
434 * SCSI Block Control (p. 3-32)
435 * Controls Bus type and channel selection.  In a twin channel configuration
436 * addresses 0x00-0x1e are gated to the appropriate channel based on this
437 * register.  SELWIDE allows for the coexistence of 8bit and 16bit devices
438 * on a wide bus.
439 */
440register SBLKCTL {
441	address			0x01f
442	access_mode RW
443	bit	DIAGLEDEN	0x80	/* Aic78X0 only */
444	bit	DIAGLEDON	0x40	/* Aic78X0 only */
445	bit	AUTOFLUSHDIS	0x20
446	bit	SELBUSB		0x08
447	bit	ENAB40		0x08	/* LVD transceiver active */
448	bit	ENAB20		0x04	/* SE/HVD transceiver active */
449	bit	SELWIDE		0x02
450	bit	XCVR		0x01	/* External transceiver active */
451}
452
453/*
454 * Sequencer Control (p. 3-33)
455 * Error detection mode and speed configuration
456 */
457register SEQCTL {
458	address			0x060
459	access_mode RW
460	bit	PERRORDIS	0x80
461	bit	PAUSEDIS	0x40
462	bit	FAILDIS		0x20
463	bit	FASTMODE	0x10
464	bit	BRKADRINTEN	0x08
465	bit	STEP		0x04
466	bit	SEQRESET	0x02
467	bit	LOADRAM		0x01
468}
469
470/*
471 * Sequencer RAM Data (p. 3-34)
472 * Single byte window into the Scratch Ram area starting at the address
473 * specified by SEQADDR0 and SEQADDR1.  To write a full word, simply write
474 * four bytes in sucessesion.  The SEQADDRs will increment after the most
475 * significant byte is written
476 */
477register SEQRAM {
478	address			0x061
479	access_mode RW
480}
481
482/*
483 * Sequencer Address Registers (p. 3-35)
484 * Only the first bit of SEQADDR1 holds addressing information
485 */
486register SEQADDR0 {
487	address			0x062
488	access_mode RW
489}
490
491register SEQADDR1 {
492	address			0x063
493	access_mode RW
494	mask	SEQADDR1_MASK	0x01
495}
496
497/*
498 * Accumulator
499 * We cheat by passing arguments in the Accumulator up to the kernel driver
500 */
501register ACCUM {
502	address			0x064
503	access_mode RW
504	accumulator
505}
506
507register SINDEX	{
508	address			0x065
509	access_mode RW
510	sindex
511}
512
513register DINDEX {
514	address			0x066
515	access_mode RW
516}
517
518register ALLONES {
519	address			0x069
520	access_mode RO
521	allones
522}
523
524register ALLZEROS {
525	address			0x06a
526	access_mode RO
527	allzeros
528}
529
530register NONE {
531	address			0x06a
532	access_mode WO
533	none
534}
535
536register FLAGS {
537	address			0x06b
538	access_mode RO
539	bit	ZERO		0x02
540	bit	CARRY		0x01
541}
542
543register SINDIR	{
544	address			0x06c
545	access_mode RO
546}
547
548register DINDIR	 {
549	address			0x06d
550	access_mode WO
551}
552
553register FUNCTION1 {
554	address			0x06e
555	access_mode RW
556}
557
558register STACK {
559	address			0x06f
560	access_mode RO
561}
562
563/*
564 * Board Control (p. 3-43)
565 */
566register BCTL {
567	address			0x084
568	access_mode RW
569	bit	ACE		0x08
570	bit	ENABLE		0x01
571}
572
573register DSCOMMAND0 {
574	address			0x084
575	access_mode RW
576	bit	CACHETHEN	0x80
577	bit	DPARCKEN	0x40
578	bit	MPARCKEN	0x20
579	bit	EXTREQLCK	0x10
580	bit	INTSCBRAMSEL	0x08
581	bit	RAMPS		0x04
582	bit	USCBSIZE32	0x02
583	bit	CIOPARCKEN	0x01
584}
585
586/*
587 * On the aic78X0 chips, Board Control is replaced by the DSCommand
588 * register (p. 4-64)
589 */
590register DSCOMMAND {
591	address			0x084
592	access_mode RW
593	bit	CACHETHEN	0x80	/* Cache Threshold enable */
594	bit	DPARCKEN	0x40	/* Data Parity Check Enable */
595	bit	MPARCKEN	0x20	/* Memory Parity Check Enable */
596	bit	EXTREQLCK	0x10	/* External Request Lock */
597}
598
599/*
600 * Bus On/Off Time (p. 3-44)
601 */
602register BUSTIME {
603	address			0x085
604	access_mode RW
605	mask	BOFF		0xf0
606	mask	BON		0x0f
607}
608
609/*
610 * Bus Speed (p. 3-45)
611 */
612register BUSSPD {
613	address			0x086
614	access_mode RW
615	mask	DFTHRSH		0xc0
616	mask	STBOFF		0x38
617	mask	STBON		0x07
618	mask	DFTHRSH_100	0xc0
619}
620
621/*
622 * Host Control (p. 3-47) R/W
623 * Overall host control of the device.
624 */
625register HCNTRL {
626	address			0x087
627	access_mode RW
628	bit	POWRDN		0x40
629	bit	SWINT		0x10
630	bit	IRQMS		0x08
631	bit	PAUSE		0x04
632	bit	INTEN		0x02
633	bit	CHIPRST		0x01
634	bit	CHIPRSTACK	0x01
635}
636
637/*
638 * Host Address (p. 3-48)
639 * This register contains the address of the byte about
640 * to be transferred across the host bus.
641 */
642register HADDR {
643	address			0x088
644	size	4
645	access_mode RW
646}
647
648register HCNT {
649	address			0x08c
650	size	3
651	access_mode RW
652}
653
654/*
655 * SCB Pointer (p. 3-49)
656 * Gate one of the four SCBs into the SCBARRAY window.
657 */
658register SCBPTR {
659	address			0x090
660	access_mode RW
661}
662
663/*
664 * Interrupt Status (p. 3-50)
665 * Status for system interrupts
666 */
667register INTSTAT {
668	address			0x091
669	access_mode RW
670	bit	BRKADRINT 0x08
671	bit	SCSIINT	  0x04
672	bit	CMDCMPLT  0x02
673	bit	SEQINT    0x01
674	mask	BAD_PHASE	SEQINT		/* unknown scsi bus phase */
675	mask	SEND_REJECT	0x10|SEQINT	/* sending a message reject */
676	mask	NO_IDENT	0x20|SEQINT	/* no IDENTIFY after reconnect*/
677	mask	NO_MATCH	0x30|SEQINT	/* no cmd match for reconnect */
678	mask	EXTENDED_MSG	0x40|SEQINT	/* Extended message received */
679	mask	ABORT_REQUESTED 0x50|SEQINT	/* Reconect of aborted SCB */
680	mask	REJECT_MSG	0x60|SEQINT	/* Reject message received */
681	mask	BAD_STATUS	0x70|SEQINT	/* Bad status from target */
682	mask	RESIDUAL	0x80|SEQINT	/* Residual byte count != 0 */
683	mask	AWAITING_MSG	0xa0|SEQINT	/*
684						 * Kernel requested to specify
685						 * a message to this target
686						 * (command was null), so tell
687						 * it that it can fill the
688						 * message buffer.
689						 */
690	mask	TARGET_MSG_HELP	0xb0|SEQINT
691	mask	TARGET_SYNC_CMD	0xc0|SEQINT
692	mask	TRACEPOINT	0xd0|SEQINT
693	mask	MSGIN_PHASEMIS	0xe0|SEQINT	/*
694						 * Target changed phase on us
695						 * when we were expecting
696						 * another msgin byte.
697						 */
698	mask	DATA_OVERRUN	0xf0|SEQINT	/*
699						 * Target attempted to write
700						 * beyond the bounds of its
701						 * command.
702						 */
703
704	mask	SEQINT_MASK	0xf0|SEQINT	/* SEQINT Status Codes */
705	mask	INT_PEND  (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
706}
707
708/*
709 * Hard Error (p. 3-53)
710 * Reporting of catastrophic errors.  You usually cannot recover from
711 * these without a full board reset.
712 */
713register ERROR {
714	address			0x092
715	access_mode RO
716	bit	CIOPARERR	0x80	/* Ultra2 only */
717	bit	PCIERRSTAT	0x40	/* PCI only */
718	bit	MPARERR		0x20	/* PCI only */
719	bit	DPARERR		0x10	/* PCI only */
720	bit	SQPARERR	0x08
721	bit	ILLOPCODE	0x04
722	bit	ILLSADDR	0x02
723	bit	ILLHADDR	0x01
724}
725
726/*
727 * Clear Interrupt Status (p. 3-52)
728 */
729register CLRINT {
730	address			0x092
731	access_mode WO
732	bit	CLRPARERR	0x10	/* PCI only */
733	bit	CLRBRKADRINT	0x08
734	bit	CLRSCSIINT      0x04
735	bit	CLRCMDINT 	0x02
736	bit	CLRSEQINT 	0x01
737}
738
739register DFCNTRL {
740	address			0x093
741	access_mode RW
742	bit	PRELOADEN	0x80	/* aic7890 only */
743	bit	WIDEODD		0x40
744	bit	SCSIEN		0x20
745	bit	SDMAEN		0x10
746	bit	SDMAENACK	0x10
747	bit	HDMAEN		0x08
748	bit	HDMAENACK	0x08
749	bit	DIRECTION	0x04
750	bit	FIFOFLUSH	0x02
751	bit	FIFORESET	0x01
752}
753
754register DFSTATUS {
755	address			0x094
756	access_mode RO
757	bit	PRELOAD_AVAIL	0x80
758	bit	DWORDEMP	0x20
759	bit	MREQPEND	0x10
760	bit	HDONE		0x08
761	bit	DFTHRESH	0x04
762	bit	FIFOFULL	0x02
763	bit	FIFOEMP		0x01
764}
765
766register DFDAT {
767	address			0x099
768	access_mode RW
769}
770
771/*
772 * SCB Auto Increment (p. 3-59)
773 * Byte offset into the SCB Array and an optional bit to allow auto
774 * incrementing of the address during download and upload operations
775 */
776register SCBCNT {
777	address			0x09a
778	access_mode RW
779	bit	SCBAUTO		0x80
780	mask	SCBCNT_MASK	0x1f
781}
782
783/*
784 * Queue In FIFO (p. 3-60)
785 * Input queue for queued SCBs (commands that the seqencer has yet to start)
786 */
787register QINFIFO {
788	address			0x09b
789	access_mode RW
790}
791
792/*
793 * Queue In Count (p. 3-60)
794 * Number of queued SCBs
795 */
796register QINCNT	{
797	address			0x09c
798	access_mode RO
799}
800
801/*
802 * Queue Out FIFO (p. 3-61)
803 * Queue of SCBs that have completed and await the host
804 */
805register QOUTFIFO {
806	address			0x09d
807	access_mode WO
808}
809
810/*
811 * Queue Out Count (p. 3-61)
812 * Number of queued SCBs in the Out FIFO
813 */
814register QOUTCNT {
815	address			0x09e
816	access_mode RO
817}
818
819/*
820 * Special Function
821 */
822register SFUNCT {
823	address			0x09f
824	access_mode RW
825}
826
827/*
828 * SCB Definition (p. 5-4)
829 */
830scb {
831	address			0x0a0
832	SCB_CONTROL {
833		size	1
834		bit	TARGET_SCB	0x80
835		bit	DISCENB         0x40
836		bit	TAG_ENB		0x20
837		bit	MK_MESSAGE      0x10
838		bit	ULTRAENB	0x08
839		bit	DISCONNECTED	0x04
840		mask	SCB_TAG_TYPE	0x03
841	}
842	SCB_TCL {
843		size	1
844		bit	SELBUSB		0x08
845		mask	TID		0xf0
846		mask	LID		0x07
847	}
848	SCB_TARGET_STATUS {
849		size	1
850	}
851	SCB_SGCOUNT {
852		size	1
853	}
854	SCB_SGPTR {
855		size	4
856	}
857	SCB_RESID_SGCNT {
858		size	1
859	}
860	SCB_RESID_DCNT	{
861		size	3
862	}
863	SCB_DATAPTR {
864		size	4
865	}
866	SCB_DATACNT {
867		/*
868		 * Really only 3 bytes, but padded to make
869		 * the kernel's job easier.
870		 */
871		size	4
872	}
873	SCB_CMDPTR {
874		alias	SCB_TARGET_PHASES
875		alias	SCB_TARGET_ID		/* Byte 2 */
876		bit	TARGET_DATA_IN	0x1	/* In the second byte */
877		size	4
878	}
879	SCB_CMDLEN {
880		alias	SCB_INITIATOR_TAG
881		size	1
882	}
883	SCB_TAG {
884		size	1
885	}
886	SCB_NEXT {
887		size	1
888	}
889	SCB_SCSIRATE {
890		size	1
891	}
892	SCB_SCSIOFFSET {
893		size	1
894	}
895	SCB_SPARE	{
896		size	3
897	}
898	SCB_CMDSTORE	{
899		size	16
900	}
901	SCB_CMDSTORE_BUSADDR {
902		size	4
903	}
904	SCB_64BYTE_SPARE {
905		size	12
906	}
907}
908
909const	SCB_32BYTE_SIZE	28
910const	SCB_64BYTE_SIZE	48
911
912const	SG_SIZEOF	0x08		/* sizeof(struct ahc_dma) */
913
914/* --------------------- AHA-2840-only definitions -------------------- */
915
916register SEECTL_2840 {
917	address			0x0c0
918	access_mode RW
919	bit	CS_2840		0x04
920	bit	CK_2840		0x02
921	bit	DO_2840		0x01
922}
923
924register STATUS_2840 {
925	address			0x0c1
926	access_mode RW
927	bit	EEPROM_TF	0x80
928	mask	BIOS_SEL	0x60
929	mask	ADSEL		0x1e
930	bit	DI_2840		0x01
931}
932
933/* --------------------- AIC-7870-only definitions -------------------- */
934
935register DSPCISTATUS {
936	address			0x086
937	mask	DFTHRSH_100	0xc0
938}
939
940register CCHADDR {
941	address			0x0E0
942	size 8
943}
944
945register CCHCNT {
946	address			0x0E8
947}
948
949register CCSGRAM {
950	address			0x0E9
951}
952
953register CCSGADDR {
954	address			0x0EA
955}
956
957register CCSGCTL {
958	address			0x0EB
959	bit	CCSGDONE	0x80
960	bit	CCSGEN		0x08
961	bit	FLAG		0x02
962	bit	CCSGRESET	0x01
963}
964
965register CCSCBCNT {
966	address			0xEF
967}
968
969register CCSCBCTL {
970	address			0x0EE
971	bit	CCSCBDONE	0x80
972	bit	ARRDONE		0x40	/* SCB Array prefetch done */
973	bit	CCARREN		0x10
974	bit	CCSCBEN		0x08
975	bit	CCSCBDIR	0x04
976	bit	CCSCBRESET	0x01
977}
978
979register CCSCBADDR {
980	address			0x0ED
981}
982
983register CCSCBRAM {
984	address			0xEC
985}
986
987/*
988 * SCB bank address (7895/7896/97 only)
989 */
990register SCBBADDR {
991	address			0x0F0
992	access_mode RW
993}
994
995register CCSCBPTR {
996	address			0x0F1
997}
998
999register HNSCB_QOFF {
1000	address			0x0F4
1001}
1002
1003register SNSCB_QOFF {
1004	address			0x0F6
1005}
1006
1007register SDSCB_QOFF {
1008	address			0x0F8
1009}
1010
1011register QOFF_CTLSTA {
1012	address			0x0FA
1013	bit	SCB_AVAIL	0x40
1014	bit	SNSCB_ROLLOVER	0x20
1015	bit	SDSCB_ROLLOVER	0x10
1016	mask	SCB_QSIZE	0x07
1017	mask	SCB_QSIZE_256	0x06
1018}
1019
1020register DFF_THRSH {
1021	address			0x0FB
1022	mask	WR_DFTHRSH	0x70
1023	mask	RD_DFTHRSH	0x07
1024	mask	RD_DFTHRSH_MIN	0x00
1025	mask	RD_DFTHRSH_25	0x01
1026	mask	RD_DFTHRSH_50	0x02
1027	mask	RD_DFTHRSH_63	0x03
1028	mask	RD_DFTHRSH_75	0x04
1029	mask	RD_DFTHRSH_85	0x05
1030	mask	RD_DFTHRSH_90	0x06
1031	mask	RD_DFTHRSH_MAX	0x07
1032	mask	WR_DFTHRSH_MIN	0x00
1033	mask	WR_DFTHRSH_25	0x10
1034	mask	WR_DFTHRSH_50	0x20
1035	mask	WR_DFTHRSH_63	0x30
1036	mask	WR_DFTHRSH_75	0x40
1037	mask	WR_DFTHRSH_85	0x50
1038	mask	WR_DFTHRSH_90	0x60
1039	mask	WR_DFTHRSH_MAX	0x70
1040}
1041
1042register SG_CACHEPTR {
1043	access_mode RW
1044	address			0x0fc
1045	mask	SG_USER_DATA	0xfc
1046	bit	LAST_SEG	0x02
1047	bit	LAST_SEG_DONE	0x01
1048}
1049
1050register BRDCTL	{
1051	address			0x01d
1052	bit	BRDDAT7		0x80
1053	bit	BRDDAT6		0x40
1054	bit	BRDDAT5		0x20
1055	bit	BRDSTB		0x10
1056	bit	BRDCS		0x08
1057	bit	BRDRW		0x04
1058	bit	BRDCTL1		0x02
1059	bit	BRDCTL0		0x01
1060	/* 7890 Definitions */
1061	bit	BRDDAT4		0x10
1062	bit	BRDDAT3		0x08
1063	bit	BRDDAT2		0x04
1064	bit	BRDRW_ULTRA2	0x02
1065	bit	BRDSTB_ULTRA2	0x01
1066}
1067
1068/*
1069 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
1070 * Controls the reading and writing of an external serial 1-bit
1071 * EEPROM Device.  In order to access the serial EEPROM, you must
1072 * first set the SEEMS bit that generates a request to the memory
1073 * port for access to the serial EEPROM device.  When the memory
1074 * port is not busy servicing another request, it reconfigures
1075 * to allow access to the serial EEPROM.  When this happens, SEERDY
1076 * gets set high to verify that the memory port access has been
1077 * granted.
1078 *
1079 * After successful arbitration for the memory port, the SEECS bit of
1080 * the SEECTL register is connected to the chip select.  The SEECK,
1081 * SEEDO, and SEEDI are connected to the clock, data out, and data in
1082 * lines respectively.  The SEERDY bit of SEECTL is useful in that it
1083 * gives us an 800 nsec timer.  After a write to the SEECTL register,
1084 * the SEERDY goes high 800 nsec later.  The one exception to this is
1085 * when we first request access to the memory port.  The SEERDY goes
1086 * high to signify that access has been granted and, for this case, has
1087 * no implied timing.
1088 *
1089 * See 93cx6.c for detailed information on the protocol necessary to
1090 * read the serial EEPROM.
1091 */
1092register SEECTL {
1093	address			0x01e
1094	bit	EXTARBACK	0x80
1095	bit	EXTARBREQ	0x40
1096	bit	SEEMS		0x20
1097	bit	SEERDY		0x10
1098	bit	SEECS		0x08
1099	bit	SEECK		0x04
1100	bit	SEEDO		0x02
1101	bit	SEEDI		0x01
1102}
1103/* ---------------------- Scratch RAM Offsets ------------------------- */
1104/* These offsets are either to values that are initialized by the board's
1105 * BIOS or are specified by the sequencer code.
1106 *
1107 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1108 * device information, 32-33 and 5a-5f as well. As it turns out, the
1109 * BIOS trashes 20-2f, writing the synchronous negotiation results
1110 * on top of the BIOS values, so we re-use those for our per-target
1111 * scratchspace (actually a value that can be copied directly into
1112 * SCSIRATE).  The kernel driver will enable synchronous negotiation
1113 * for all targets that have a value other than 0 in the lower four
1114 * bits of the target scratch space.  This should work regardless of
1115 * whether the bios has been installed.
1116 */
1117
1118scratch_ram {
1119	address			0x020
1120
1121	/*
1122	 * 1 byte per target starting at this address for configuration values
1123	 */
1124	TARG_SCSIRATE {
1125		alias		CMDSIZE_TABLE
1126		size		16
1127	}
1128	/*
1129	 * Bit vector of targets that have ULTRA enabled.
1130	 */
1131	ULTRA_ENB {
1132		size		2
1133	}
1134	/*
1135	 * Bit vector of targets that have disconnection disabled.
1136	 */
1137	DISC_DSB {
1138		size		2
1139	}
1140	/*
1141	 * Single byte buffer used to designate the type or message
1142	 * to send to a target.
1143	 */
1144	MSG_OUT {
1145		size		1
1146	}
1147	/* Parameters for DMA Logic */
1148	DMAPARAMS {
1149		size		1
1150		bit	PRELOADEN	0x80
1151		bit	WIDEODD		0x40
1152		bit	SCSIEN		0x20
1153		bit	SDMAEN		0x10
1154		bit	SDMAENACK	0x10
1155		bit	HDMAEN		0x08
1156		bit	HDMAENACK	0x08
1157		bit	DIRECTION	0x04
1158		bit	FIFOFLUSH	0x02
1159		bit	FIFORESET	0x01
1160	}
1161	SEQ_FLAGS {
1162		size		1
1163		bit	IDENTIFY_SEEN		0x80
1164		bit	SCBPTR_VALID		0x40
1165		bit	DPHASE			0x20
1166		/* Target flags */
1167		bit	TARG_CMD_PENDING	0x10
1168		bit	CMDPHASE_PENDING	0x08
1169		bit	DPHASE_PENDING		0x04
1170		bit	SPHASE_PENDING		0x02
1171		bit	NO_DISCONNECT		0x01
1172	}
1173	/*
1174	 * Temporary storage for the
1175	 * target/channel/lun of a
1176	 * reconnecting target
1177	 */
1178	SAVED_TCL {
1179		size		1
1180	}
1181	/* Working value of the number of SG segments left */
1182	SG_COUNT {
1183		size		1
1184	}
1185	/* Working value of SG pointer */
1186	SG_NEXT	{
1187		size		4
1188	}
1189	/*
1190	 * The last bus phase as seen by the sequencer.
1191	 */
1192	LASTPHASE {
1193		size		1
1194		bit	CDI		0x80
1195		bit	IOI		0x40
1196		bit	MSGI		0x20
1197		mask	PHASE_MASK	CDI|IOI|MSGI
1198		mask	P_DATAOUT	0x00
1199		mask	P_DATAIN	IOI
1200		mask	P_COMMAND	CDI
1201		mask	P_MESGOUT	CDI|MSGI
1202		mask	P_STATUS	CDI|IOI
1203		mask	P_MESGIN	CDI|IOI|MSGI
1204		mask	P_BUSFREE	0x01
1205	}
1206	/*
1207	 * head of list of SCBs awaiting
1208	 * selection
1209	 */
1210	WAITING_SCBH {
1211		size		1
1212	}
1213	/*
1214	 * head of list of SCBs that are
1215	 * disconnected.  Used for SCB
1216	 * paging.
1217	 */
1218	DISCONNECTED_SCBH {
1219		size		1
1220	}
1221	/*
1222	 * head of list of SCBs that are
1223	 * not in use.  Used for SCB paging.
1224	 */
1225	FREE_SCBH {
1226		size		1
1227	}
1228	/*
1229	 * Address of the hardware scb array in the host.
1230	 */
1231	HSCB_ADDR {
1232		size		4
1233	}
1234	/*
1235	 * Address of the 256 byte array storing the SCBID of outstanding
1236	 * untagged SCBs indexed by TCL.
1237	 */
1238	SCBID_ADDR {
1239		size		4
1240	}
1241	/*
1242	 * Address of the array of command descriptors used to store
1243	 * information about incoming selections.
1244	 */
1245	TMODE_CMDADDR {
1246		size		4
1247	}
1248	KERNEL_QINPOS {
1249		size		1
1250	}
1251	QINPOS {
1252		size		1
1253	}
1254	QOUTPOS {
1255		size		1
1256	}
1257	/*
1258	 * Offset into the command descriptor array for the next
1259	 * available desciptor to use.
1260	 */
1261	TMODE_CMDADDR_NEXT {
1262		size		1
1263	}
1264	ARG_1 {
1265		size		1
1266		mask	SEND_MSG	0x80
1267		mask	SEND_SENSE	0x40
1268		mask	SEND_REJ	0x20
1269		mask	MSGOUT_PHASEMIS	0x10
1270		alias	RETURN_1
1271	}
1272	ARG_2 {
1273		size		1
1274		alias	RETURN_2
1275	}
1276
1277	/*
1278	 * Snapshot of MSG_OUT taken after each message is sent.
1279	 */
1280	LAST_MSG {
1281		size		1
1282	}
1283
1284	/*
1285	 * Number of times we have filled the CCSGRAM with prefetched
1286	 * SG elements.
1287	 */
1288	PREFETCH_CNT {
1289		size		1
1290	}
1291
1292
1293	/*
1294	 * These are reserved registers in the card's scratch ram.  Some of
1295	 * the values are specified in the AHA2742 technical reference manual
1296	 * and are initialized by the BIOS at boot time.
1297	 */
1298	SCSICONF {
1299		address		0x05a
1300		size		1
1301		bit	TERM_ENB	0x80
1302		bit	RESET_SCSI	0x40
1303		mask	HSCSIID		0x07	/* our SCSI ID */
1304		mask	HWSCSIID	0x0f	/* our SCSI ID if Wide Bus */
1305	}
1306	HOSTCONF {
1307		address		0x05d
1308		size		1
1309	}
1310	HA_274_BIOSCTRL	{
1311		address		0x05f
1312		size		1
1313		mask	BIOSMODE		0x30
1314		mask	BIOSDISABLED		0x30
1315		bit	CHANNEL_B_PRIMARY	0x08
1316	}
1317	/*
1318	 * Per target SCSI offset values for Ultra2 controllers.
1319	 */
1320	TARG_OFFSET {
1321		address		0x070
1322		size		16
1323	}
1324}
1325
1326const SCB_LIST_NULL	0xff
1327const TARGET_CMD_CMPLT	0xfe
1328
1329const CCSGADDR_MAX	0x80
1330const CCSGRAM_MAXSEGS	16
1331
1332/* Offsets into the SCBID array where different data is stored */
1333const QOUTFIFO_OFFSET		0
1334const QINFIFO_OFFSET		1
1335const UNTAGGEDSCB_OFFSET	2
1336
1337/* WDTR Message values */
1338const BUS_8_BIT			0x00
1339const BUS_16_BIT		0x01
1340const BUS_32_BIT		0x02
1341
1342/* Offset maximums */
1343const MAX_OFFSET_8BIT		0x0f
1344const MAX_OFFSET_16BIT		0x08
1345const MAX_OFFSET_ULTRA2		0x7f
1346const HOST_MSG			0xff
1347
1348/* Target mode command processing constants */
1349const CMD_GROUP_CODE_SHIFT	0x05
1350const CMD_GROUP0_BYTE_DELTA	-4
1351const CMD_GROUP2_BYTE_DELTA	9
1352const CMD_GROUP3_BYTE_DELTA	-15
1353const CMD_GROUP4_BYTE_DELTA	4
1354const CMD_GROUP5_BYTE_DELTA	11
1355
1356
1357/*
1358 * Downloaded (kernel inserted) constants
1359 */
1360
1361/*
1362 * Number of command descriptors in the command descriptor array.
1363 */
1364const TMODE_NUMCMDS	download
1365