1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD$ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#34 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic7xxx driver. 48 * 49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 50 * Adaptec's Technical Documents Department 1-800-934-2766 51 */ 52 53/* 54 * SCSI Sequence Control (p. 3-11). 55 * Each bit, when set starts a specific SCSI sequence on the bus 56 */ 57register SCSISEQ { 58 address 0x000 59 access_mode RW 60 field TEMODE 0x80 61 field ENSELO 0x40 62 field ENSELI 0x20 63 field ENRSELI 0x10 64 field ENAUTOATNO 0x08 65 field ENAUTOATNI 0x04 66 field ENAUTOATNP 0x02 67 field SCSIRSTO 0x01 68} 69 70/* 71 * SCSI Transfer Control 0 Register (pp. 3-13). 72 * Controls the SCSI module data path. 73 */ 74register SXFRCTL0 { 75 address 0x001 76 access_mode RW 77 field DFON 0x80 78 field DFPEXP 0x40 79 field FAST20 0x20 80 field CLRSTCNT 0x10 81 field SPIOEN 0x08 82 field SCAMEN 0x04 83 field CLRCHN 0x02 84} 85 86/* 87 * SCSI Transfer Control 1 Register (pp. 3-14,15). 88 * Controls the SCSI module data path. 89 */ 90register SXFRCTL1 { 91 address 0x002 92 access_mode RW 93 field BITBUCKET 0x80 94 field SWRAPEN 0x40 95 field ENSPCHK 0x20 96 mask STIMESEL 0x18 97 field ENSTIMER 0x04 98 field ACTNEGEN 0x02 99 field STPWEN 0x01 /* Powered Termination */ 100} 101 102/* 103 * SCSI Control Signal Read Register (p. 3-15). 104 * Reads the actual state of the SCSI bus pins 105 */ 106register SCSISIGI { 107 address 0x003 108 access_mode RO 109 field CDI 0x80 110 field IOI 0x40 111 field MSGI 0x20 112 field ATNI 0x10 113 field SELI 0x08 114 field BSYI 0x04 115 field REQI 0x02 116 field ACKI 0x01 117/* 118 * Possible phases in SCSISIGI 119 */ 120 mask PHASE_MASK CDI|IOI|MSGI 121 mask P_DATAOUT 0x00 122 mask P_DATAIN IOI 123 mask P_DATAOUT_DT P_DATAOUT|MSGI 124 mask P_DATAIN_DT P_DATAIN|MSGI 125 mask P_COMMAND CDI 126 mask P_MESGOUT CDI|MSGI 127 mask P_STATUS CDI|IOI 128 mask P_MESGIN CDI|IOI|MSGI 129} 130 131/* 132 * SCSI Control Signal Write Register (p. 3-16). 133 * Writing to this register modifies the control signals on the bus. Only 134 * those signals that are allowed in the current mode (Initiator/Target) are 135 * asserted. 136 */ 137register SCSISIGO { 138 address 0x003 139 access_mode WO 140 field CDO 0x80 141 field IOO 0x40 142 field MSGO 0x20 143 field ATNO 0x10 144 field SELO 0x08 145 field BSYO 0x04 146 field REQO 0x02 147 field ACKO 0x01 148/* 149 * Possible phases to write into SCSISIG0 150 */ 151 mask PHASE_MASK CDI|IOI|MSGI 152 mask P_DATAOUT 0x00 153 mask P_DATAIN IOI 154 mask P_COMMAND CDI 155 mask P_MESGOUT CDI|MSGI 156 mask P_STATUS CDI|IOI 157 mask P_MESGIN CDI|IOI|MSGI 158} 159 160/* 161 * SCSI Rate Control (p. 3-17). 162 * Contents of this register determine the Synchronous SCSI data transfer 163 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 164 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 165 * greater than 0 enables synchronous transfers. 166 */ 167register SCSIRATE { 168 address 0x004 169 access_mode RW 170 field WIDEXFER 0x80 /* Wide transfer control */ 171 field ENABLE_CRC 0x40 /* CRC for D-Phases */ 172 field SINGLE_EDGE 0x10 /* Disable DT Transfers */ 173 mask SXFR 0x70 /* Sync transfer rate */ 174 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 175 mask SOFS 0x0f /* Sync offset */ 176} 177 178/* 179 * SCSI ID (p. 3-18). 180 * Contains the ID of the board and the current target on the 181 * selected channel. 182 */ 183register SCSIID { 184 address 0x005 185 access_mode RW 186 mask TID 0xf0 /* Target ID mask */ 187 mask TWIN_TID 0x70 188 field TWIN_CHNLB 0x80 189 mask OID 0x0f /* Our ID mask */ 190 /* 191 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 192 * The aic7890/91 allow an offset of up to 127 transfers in both wide 193 * and narrow mode. 194 */ 195 alias SCSIOFFSET 196 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 197} 198 199/* 200 * SCSI Latched Data (p. 3-19). 201 * Read/Write latches used to transfer data on the SCSI bus during 202 * Automatic or Manual PIO mode. SCSIDATH can be used for the 203 * upper byte of a 16bit wide asynchronouse data phase transfer. 204 */ 205register SCSIDATL { 206 address 0x006 207 access_mode RW 208} 209 210register SCSIDATH { 211 address 0x007 212 access_mode RW 213} 214 215/* 216 * SCSI Transfer Count (pp. 3-19,20) 217 * These registers count down the number of bytes transferred 218 * across the SCSI bus. The counter is decremented only once 219 * the data has been safely transferred. SDONE in SSTAT0 is 220 * set when STCNT goes to 0 221 */ 222register STCNT { 223 address 0x008 224 size 3 225 access_mode RW 226} 227 228/* ALT_MODE registers (Ultra2 and Ultra160 chips) */ 229register SXFRCTL2 { 230 address 0x013 231 access_mode RW 232 field AUTORSTDIS 0x10 233 field CMDDMAEN 0x08 234 mask ASYNC_SETUP 0x07 235} 236 237/* ALT_MODE register on Ultra160 chips */ 238register OPTIONMODE { 239 address 0x008 240 access_mode RW 241 field AUTORATEEN 0x80 242 field AUTOACKEN 0x40 243 field ATNMGMNTEN 0x20 244 field BUSFREEREV 0x10 245 field EXPPHASEDIS 0x08 246 field SCSIDATL_IMGEN 0x04 247 field AUTO_MSGOUT_DE 0x02 248 field DIS_MSGIN_DUALEDGE 0x01 249 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 250} 251 252/* ALT_MODE register on Ultra160 chips */ 253register TARGCRCCNT { 254 address 0x00a 255 size 2 256 access_mode RW 257} 258 259/* 260 * Clear SCSI Interrupt 0 (p. 3-20) 261 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 262 */ 263register CLRSINT0 { 264 address 0x00b 265 access_mode WO 266 field CLRSELDO 0x40 267 field CLRSELDI 0x20 268 field CLRSELINGO 0x10 269 field CLRSWRAP 0x08 270 field CLRIOERR 0x08 /* Ultra2 Only */ 271 field CLRSPIORDY 0x02 272} 273 274/* 275 * SCSI Status 0 (p. 3-21) 276 * Contains one set of SCSI Interrupt codes 277 * These are most likely of interest to the sequencer 278 */ 279register SSTAT0 { 280 address 0x00b 281 access_mode RO 282 field TARGET 0x80 /* Board acting as target */ 283 field SELDO 0x40 /* Selection Done */ 284 field SELDI 0x20 /* Board has been selected */ 285 field SELINGO 0x10 /* Selection In Progress */ 286 field SWRAP 0x08 /* 24bit counter wrap */ 287 field IOERR 0x08 /* LVD Tranceiver mode changed */ 288 field SDONE 0x04 /* STCNT = 0x000000 */ 289 field SPIORDY 0x02 /* SCSI PIO Ready */ 290 field DMADONE 0x01 /* DMA transfer completed */ 291} 292 293/* 294 * Clear SCSI Interrupt 1 (p. 3-23) 295 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 296 */ 297register CLRSINT1 { 298 address 0x00c 299 access_mode WO 300 field CLRSELTIMEO 0x80 301 field CLRATNO 0x40 302 field CLRSCSIRSTI 0x20 303 field CLRBUSFREE 0x08 304 field CLRSCSIPERR 0x04 305 field CLRPHASECHG 0x02 306 field CLRREQINIT 0x01 307} 308 309/* 310 * SCSI Status 1 (p. 3-24) 311 */ 312register SSTAT1 { 313 address 0x00c 314 access_mode RO 315 field SELTO 0x80 316 field ATNTARG 0x40 317 field SCSIRSTI 0x20 318 field PHASEMIS 0x10 319 field BUSFREE 0x08 320 field SCSIPERR 0x04 321 field PHASECHG 0x02 322 field REQINIT 0x01 323} 324 325/* 326 * SCSI Status 2 (pp. 3-25,26) 327 */ 328register SSTAT2 { 329 address 0x00d 330 access_mode RO 331 field OVERRUN 0x80 332 field SHVALID 0x40 /* Shaddow Layer non-zero */ 333 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 334 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 335 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 336 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 337 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 338 mask SFCNT 0x1f 339} 340 341/* 342 * SCSI Status 3 (p. 3-26) 343 */ 344register SSTAT3 { 345 address 0x00e 346 access_mode RO 347 mask SCSICNT 0xf0 348 mask OFFCNT 0x0f 349 mask U2OFFCNT 0x7f 350} 351 352/* 353 * SCSI ID for the aic7890/91 chips 354 */ 355register SCSIID_ULTRA2 { 356 address 0x00f 357 access_mode RW 358 mask TID 0xf0 /* Target ID mask */ 359 mask OID 0x0f /* Our ID mask */ 360} 361 362/* 363 * SCSI Interrupt Mode 1 (p. 3-28) 364 * Setting any bit will enable the corresponding function 365 * in SIMODE0 to interrupt via the IRQ pin. 366 */ 367register SIMODE0 { 368 address 0x010 369 access_mode RW 370 field ENSELDO 0x40 371 field ENSELDI 0x20 372 field ENSELINGO 0x10 373 field ENSWRAP 0x08 374 field ENIOERR 0x08 /* LVD Tranceiver mode changes */ 375 field ENSDONE 0x04 376 field ENSPIORDY 0x02 377 field ENDMADONE 0x01 378} 379 380/* 381 * SCSI Interrupt Mode 1 (pp. 3-28,29) 382 * Setting any bit will enable the corresponding function 383 * in SIMODE1 to interrupt via the IRQ pin. 384 */ 385register SIMODE1 { 386 address 0x011 387 access_mode RW 388 field ENSELTIMO 0x80 389 field ENATNTARG 0x40 390 field ENSCSIRST 0x20 391 field ENPHASEMIS 0x10 392 field ENBUSFREE 0x08 393 field ENSCSIPERR 0x04 394 field ENPHASECHG 0x02 395 field ENREQINIT 0x01 396} 397 398/* 399 * SCSI Data Bus (High) (p. 3-29) 400 * This register reads data on the SCSI Data bus directly. 401 */ 402register SCSIBUSL { 403 address 0x012 404 access_mode RW 405} 406 407register SCSIBUSH { 408 address 0x013 409 access_mode RW 410} 411 412/* 413 * SCSI/Host Address (p. 3-30) 414 * These registers hold the host address for the byte about to be 415 * transferred on the SCSI bus. They are counted up in the same 416 * manner as STCNT is counted down. SHADDR should always be used 417 * to determine the address of the last byte transferred since HADDR 418 * can be skewed by write ahead. 419 */ 420register SHADDR { 421 address 0x014 422 size 4 423 access_mode RO 424} 425 426/* 427 * Selection Timeout Timer (p. 3-30) 428 */ 429register SELTIMER { 430 address 0x018 431 access_mode RW 432 field STAGE6 0x20 433 field STAGE5 0x10 434 field STAGE4 0x08 435 field STAGE3 0x04 436 field STAGE2 0x02 437 field STAGE1 0x01 438 alias TARGIDIN 439} 440 441/* 442 * Selection/Reselection ID (p. 3-31) 443 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 444 * device did not set its own ID. 445 */ 446register SELID { 447 address 0x019 448 access_mode RW 449 mask SELID_MASK 0xf0 450 field ONEBIT 0x08 451} 452 453register SCAMCTL { 454 address 0x01a 455 access_mode RW 456 field ENSCAMSELO 0x80 457 field CLRSCAMSELID 0x40 458 field ALTSTIM 0x20 459 field DFLTTID 0x10 460 mask SCAMLVL 0x03 461} 462 463/* 464 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 465 */ 466register TARGID { 467 address 0x01b 468 size 2 469 access_mode RW 470} 471 472/* 473 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 474 * Indicates if external logic has been attached to the chip to 475 * perform the tasks of accessing a serial eeprom, testing termination 476 * strength, and performing cable detection. On the aic7860, most of 477 * these features are handled on chip, but on the aic7855 an attached 478 * aic3800 does the grunt work. 479 */ 480register SPIOCAP { 481 address 0x01b 482 access_mode RW 483 field SOFT1 0x80 484 field SOFT0 0x40 485 field SOFTCMDEN 0x20 486 field EXT_BRDCTL 0x10 /* External Board control */ 487 field SEEPROM 0x08 /* External serial eeprom logic */ 488 field EEPROM 0x04 /* Writable external BIOS ROM */ 489 field ROM 0x02 /* Logic for accessing external ROM */ 490 field SSPIOCPS 0x01 /* Termination and cable detection */ 491} 492 493register BRDCTL { 494 address 0x01d 495 field BRDDAT7 0x80 496 field BRDDAT6 0x40 497 field BRDDAT5 0x20 498 field BRDSTB 0x10 499 field BRDCS 0x08 500 field BRDRW 0x04 501 field BRDCTL1 0x02 502 field BRDCTL0 0x01 503 /* 7890 Definitions */ 504 field BRDDAT4 0x10 505 field BRDDAT3 0x08 506 field BRDDAT2 0x04 507 field BRDRW_ULTRA2 0x02 508 field BRDSTB_ULTRA2 0x01 509} 510 511/* 512 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 513 * Controls the reading and writing of an external serial 1-bit 514 * EEPROM Device. In order to access the serial EEPROM, you must 515 * first set the SEEMS bit that generates a request to the memory 516 * port for access to the serial EEPROM device. When the memory 517 * port is not busy servicing another request, it reconfigures 518 * to allow access to the serial EEPROM. When this happens, SEERDY 519 * gets set high to verify that the memory port access has been 520 * granted. 521 * 522 * After successful arbitration for the memory port, the SEECS bit of 523 * the SEECTL register is connected to the chip select. The SEECK, 524 * SEEDO, and SEEDI are connected to the clock, data out, and data in 525 * lines respectively. The SEERDY bit of SEECTL is useful in that it 526 * gives us an 800 nsec timer. After a write to the SEECTL register, 527 * the SEERDY goes high 800 nsec later. The one exception to this is 528 * when we first request access to the memory port. The SEERDY goes 529 * high to signify that access has been granted and, for this case, has 530 * no implied timing. 531 * 532 * See 93cx6.c for detailed information on the protocol necessary to 533 * read the serial EEPROM. 534 */ 535register SEECTL { 536 address 0x01e 537 field EXTARBACK 0x80 538 field EXTARBREQ 0x40 539 field SEEMS 0x20 540 field SEERDY 0x10 541 field SEECS 0x08 542 field SEECK 0x04 543 field SEEDO 0x02 544 field SEEDI 0x01 545} 546/* 547 * SCSI Block Control (p. 3-32) 548 * Controls Bus type and channel selection. In a twin channel configuration 549 * addresses 0x00-0x1e are gated to the appropriate channel based on this 550 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 551 * on a wide bus. 552 */ 553register SBLKCTL { 554 address 0x01f 555 access_mode RW 556 field DIAGLEDEN 0x80 /* Aic78X0 only */ 557 field DIAGLEDON 0x40 /* Aic78X0 only */ 558 field AUTOFLUSHDIS 0x20 559 field SELBUSB 0x08 560 field ENAB40 0x08 /* LVD transceiver active */ 561 field ENAB20 0x04 /* SE/HVD transceiver active */ 562 field SELWIDE 0x02 563 field XCVR 0x01 /* External transceiver active */ 564} 565 566/* 567 * Sequencer Control (p. 3-33) 568 * Error detection mode and speed configuration 569 */ 570register SEQCTL { 571 address 0x060 572 access_mode RW 573 field PERRORDIS 0x80 574 field PAUSEDIS 0x40 575 field FAILDIS 0x20 576 field FASTMODE 0x10 577 field BRKADRINTEN 0x08 578 field STEP 0x04 579 field SEQRESET 0x02 580 field LOADRAM 0x01 581} 582 583/* 584 * Sequencer RAM Data (p. 3-34) 585 * Single byte window into the Scratch Ram area starting at the address 586 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 587 * four bytes in succession. The SEQADDRs will increment after the most 588 * significant byte is written 589 */ 590register SEQRAM { 591 address 0x061 592 access_mode RW 593} 594 595/* 596 * Sequencer Address Registers (p. 3-35) 597 * Only the first bit of SEQADDR1 holds addressing information 598 */ 599register SEQADDR0 { 600 address 0x062 601 access_mode RW 602} 603 604register SEQADDR1 { 605 address 0x063 606 access_mode RW 607 mask SEQADDR1_MASK 0x01 608} 609 610/* 611 * Accumulator 612 * We cheat by passing arguments in the Accumulator up to the kernel driver 613 */ 614register ACCUM { 615 address 0x064 616 access_mode RW 617 accumulator 618} 619 620register SINDEX { 621 address 0x065 622 access_mode RW 623 sindex 624} 625 626register DINDEX { 627 address 0x066 628 access_mode RW 629} 630 631register ALLONES { 632 address 0x069 633 access_mode RO 634 allones 635} 636 637register ALLZEROS { 638 address 0x06a 639 access_mode RO 640 allzeros 641} 642 643register NONE { 644 address 0x06a 645 access_mode WO 646 none 647} 648 649register FLAGS { 650 address 0x06b 651 access_mode RO 652 field ZERO 0x02 653 field CARRY 0x01 654} 655 656register SINDIR { 657 address 0x06c 658 access_mode RO 659} 660 661register DINDIR { 662 address 0x06d 663 access_mode WO 664} 665 666register FUNCTION1 { 667 address 0x06e 668 access_mode RW 669} 670 671register STACK { 672 address 0x06f 673 access_mode RO 674} 675 676/* 677 * Board Control (p. 3-43) 678 */ 679register BCTL { 680 address 0x084 681 access_mode RW 682 field ACE 0x08 683 field ENABLE 0x01 684} 685 686/* 687 * On the aic78X0 chips, Board Control is replaced by the DSCommand 688 * register (p. 4-64) 689 */ 690register DSCOMMAND0 { 691 address 0x084 692 access_mode RW 693 field CACHETHEN 0x80 /* Cache Threshold enable */ 694 field DPARCKEN 0x40 /* Data Parity Check Enable */ 695 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 696 field EXTREQLCK 0x10 /* External Request Lock */ 697 /* aic7890/91/96/97 only */ 698 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 699 field RAMPS 0x04 /* External SCB RAM Present */ 700 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 701 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 702} 703 704register DSCOMMAND1 { 705 address 0x085 706 access_mode RW 707 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 708 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 709 field HADDLDSEL0 0x01 710} 711 712/* 713 * Bus On/Off Time (p. 3-44) aic7770 only 714 */ 715register BUSTIME { 716 address 0x085 717 access_mode RW 718 mask BOFF 0xf0 719 mask BON 0x0f 720} 721 722/* 723 * Bus Speed (p. 3-45) aic7770 only 724 */ 725register BUSSPD { 726 address 0x086 727 access_mode RW 728 mask DFTHRSH 0xc0 729 mask STBOFF 0x38 730 mask STBON 0x07 731 mask DFTHRSH_100 0xc0 732 mask DFTHRSH_75 0x80 733} 734 735/* aic7850/55/60/70/80/95 only */ 736register DSPCISTATUS { 737 address 0x086 738 mask DFTHRSH_100 0xc0 739} 740 741/* aic7890/91/96/97 only */ 742register HS_MAILBOX { 743 address 0x086 744 mask HOST_MAILBOX 0xF0 745 mask SEQ_MAILBOX 0x0F 746 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 747} 748 749const HOST_MAILBOX_SHIFT 4 750const SEQ_MAILBOX_SHIFT 0 751 752/* 753 * Host Control (p. 3-47) R/W 754 * Overall host control of the device. 755 */ 756register HCNTRL { 757 address 0x087 758 access_mode RW 759 field POWRDN 0x40 760 field SWINT 0x10 761 field IRQMS 0x08 762 field PAUSE 0x04 763 field INTEN 0x02 764 field CHIPRST 0x01 765 field CHIPRSTACK 0x01 766} 767 768/* 769 * Host Address (p. 3-48) 770 * This register contains the address of the byte about 771 * to be transferred across the host bus. 772 */ 773register HADDR { 774 address 0x088 775 size 4 776 access_mode RW 777} 778 779register HCNT { 780 address 0x08c 781 size 3 782 access_mode RW 783} 784 785/* 786 * SCB Pointer (p. 3-49) 787 * Gate one of the SCBs into the SCBARRAY window. 788 */ 789register SCBPTR { 790 address 0x090 791 access_mode RW 792} 793 794/* 795 * Interrupt Status (p. 3-50) 796 * Status for system interrupts 797 */ 798register INTSTAT { 799 address 0x091 800 access_mode RW 801 field BRKADRINT 0x08 802 field SCSIINT 0x04 803 field CMDCMPLT 0x02 804 field SEQINT 0x01 805 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 806 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 807 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 808 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 809 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 810 mask PDATA_REINIT 0x50|SEQINT /* 811 * Returned to data phase 812 * that requires data 813 * transfer pointers to be 814 * recalculated from the 815 * transfer residual. 816 */ 817 mask HOST_MSG_LOOP 0x60|SEQINT /* 818 * The bus is ready for the 819 * host to perform another 820 * message transaction. This 821 * mechanism is used for things 822 * like sync/wide negotiation 823 * that require a kernel based 824 * message state engine. 825 */ 826 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 827 mask PERR_DETECTED 0x80|SEQINT /* 828 * Either the phase_lock 829 * or inb_next routine has 830 * noticed a parity error. 831 */ 832 mask DATA_OVERRUN 0x90|SEQINT /* 833 * Target attempted to write 834 * beyond the bounds of its 835 * command. 836 */ 837 mask MKMSG_FAILED 0xa0|SEQINT /* 838 * Target completed command 839 * without honoring our ATN 840 * request to issue a message. 841 */ 842 mask MISSED_BUSFREE 0xb0|SEQINT /* 843 * The sequencer never saw 844 * the bus go free after 845 * either a command complete 846 * or disconnect message. 847 */ 848 mask SCB_MISMATCH 0xc0|SEQINT /* 849 * Downloaded SCB's tag does 850 * not match the entry we 851 * intended to download. 852 */ 853 mask NO_FREE_SCB 0xd0|SEQINT /* 854 * get_free_or_disc_scb failed. 855 */ 856 mask OUT_OF_RANGE 0xe0|SEQINT 857 858 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 859 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 860} 861 862/* 863 * Hard Error (p. 3-53) 864 * Reporting of catastrophic errors. You usually cannot recover from 865 * these without a full board reset. 866 */ 867register ERROR { 868 address 0x092 869 access_mode RO 870 field CIOPARERR 0x80 /* Ultra2 only */ 871 field PCIERRSTAT 0x40 /* PCI only */ 872 field MPARERR 0x20 /* PCI only */ 873 field DPARERR 0x10 /* PCI only */ 874 field SQPARERR 0x08 875 field ILLOPCODE 0x04 876 field ILLSADDR 0x02 877 field ILLHADDR 0x01 878} 879 880/* 881 * Clear Interrupt Status (p. 3-52) 882 */ 883register CLRINT { 884 address 0x092 885 access_mode WO 886 field CLRPARERR 0x10 /* PCI only */ 887 field CLRBRKADRINT 0x08 888 field CLRSCSIINT 0x04 889 field CLRCMDINT 0x02 890 field CLRSEQINT 0x01 891} 892 893register DFCNTRL { 894 address 0x093 895 access_mode RW 896 field PRELOADEN 0x80 /* aic7890 only */ 897 field WIDEODD 0x40 898 field SCSIEN 0x20 899 field SDMAEN 0x10 900 field SDMAENACK 0x10 901 field HDMAEN 0x08 902 field HDMAENACK 0x08 903 field DIRECTION 0x04 904 field FIFOFLUSH 0x02 905 field FIFORESET 0x01 906} 907 908register DFSTATUS { 909 address 0x094 910 access_mode RO 911 field PRELOAD_AVAIL 0x80 912 field DFCACHETH 0x40 913 field FIFOQWDEMP 0x20 914 field MREQPEND 0x10 915 field HDONE 0x08 916 field DFTHRESH 0x04 917 field FIFOFULL 0x02 918 field FIFOEMP 0x01 919} 920 921register DFWADDR { 922 address 0x95 923 access_mode RW 924} 925 926register DFRADDR { 927 address 0x97 928 access_mode RW 929} 930 931register DFDAT { 932 address 0x099 933 access_mode RW 934} 935 936/* 937 * SCB Auto Increment (p. 3-59) 938 * Byte offset into the SCB Array and an optional bit to allow auto 939 * incrementing of the address during download and upload operations 940 */ 941register SCBCNT { 942 address 0x09a 943 access_mode RW 944 field SCBAUTO 0x80 945 mask SCBCNT_MASK 0x1f 946} 947 948/* 949 * Queue In FIFO (p. 3-60) 950 * Input queue for queued SCBs (commands that the seqencer has yet to start) 951 */ 952register QINFIFO { 953 address 0x09b 954 access_mode RW 955} 956 957/* 958 * Queue In Count (p. 3-60) 959 * Number of queued SCBs 960 */ 961register QINCNT { 962 address 0x09c 963 access_mode RO 964} 965 966/* 967 * Queue Out FIFO (p. 3-61) 968 * Queue of SCBs that have completed and await the host 969 */ 970register QOUTFIFO { 971 address 0x09d 972 access_mode WO 973} 974 975register CRCCONTROL1 { 976 address 0x09d 977 access_mode RW 978 field CRCONSEEN 0x80 979 field CRCVALCHKEN 0x40 980 field CRCENDCHKEN 0x20 981 field CRCREQCHKEN 0x10 982 field TARGCRCENDEN 0x08 983 field TARGCRCCNTEN 0x04 984} 985 986 987/* 988 * Queue Out Count (p. 3-61) 989 * Number of queued SCBs in the Out FIFO 990 */ 991register QOUTCNT { 992 address 0x09e 993 access_mode RO 994} 995 996register SCSIPHASE { 997 address 0x09e 998 access_mode RO 999 field STATUS_PHASE 0x20 1000 field COMMAND_PHASE 0x10 1001 field MSG_IN_PHASE 0x08 1002 field MSG_OUT_PHASE 0x04 1003 field DATA_IN_PHASE 0x02 1004 field DATA_OUT_PHASE 0x01 1005 mask DATA_PHASE_MASK 0x03 1006} 1007 1008/* 1009 * Special Function 1010 */ 1011register SFUNCT { 1012 address 0x09f 1013 access_mode RW 1014 field ALT_MODE 0x80 1015} 1016 1017/* 1018 * SCB Definition (p. 5-4) 1019 */ 1020scb { 1021 address 0x0a0 1022 size 64 1023 1024 SCB_CDB_PTR { 1025 size 4 1026 alias SCB_RESIDUAL_DATACNT 1027 alias SCB_CDB_STORE 1028 } 1029 SCB_RESIDUAL_SGPTR { 1030 size 4 1031 } 1032 SCB_SCSI_STATUS { 1033 size 1 1034 } 1035 SCB_TARGET_PHASES { 1036 size 1 1037 } 1038 SCB_TARGET_DATA_DIR { 1039 size 1 1040 } 1041 SCB_TARGET_ITAG { 1042 size 1 1043 } 1044 SCB_DATAPTR { 1045 size 4 1046 } 1047 SCB_DATACNT { 1048 /* 1049 * The last byte is really the high address bits for 1050 * the data address. 1051 */ 1052 size 4 1053 field SG_LAST_SEG 0x80 /* In the fourth byte */ 1054 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1055 } 1056 SCB_SGPTR { 1057 size 4 1058 field SG_RESID_VALID 0x04 /* In the first byte */ 1059 field SG_FULL_RESID 0x02 /* In the first byte */ 1060 field SG_LIST_NULL 0x01 /* In the first byte */ 1061 } 1062 SCB_CONTROL { 1063 size 1 1064 field TARGET_SCB 0x80 1065 field DISCENB 0x40 1066 field TAG_ENB 0x20 1067 field MK_MESSAGE 0x10 1068 field ULTRAENB 0x08 1069 field DISCONNECTED 0x04 1070 mask SCB_TAG_TYPE 0x03 1071 } 1072 SCB_SCSIID { 1073 size 1 1074 field TWIN_CHNLB 0x80 1075 mask TWIN_TID 0x70 1076 mask TID 0xf0 1077 mask OID 0x0f 1078 } 1079 SCB_LUN { 1080 mask LID 0xff 1081 size 1 1082 } 1083 SCB_TAG { 1084 size 1 1085 } 1086 SCB_CDB_LEN { 1087 size 1 1088 } 1089 SCB_SCSIRATE { 1090 size 1 1091 } 1092 SCB_SCSIOFFSET { 1093 size 1 1094 } 1095 SCB_NEXT { 1096 size 1 1097 } 1098 SCB_64_SPARE { 1099 size 16 1100 } 1101 SCB_64_BTT { 1102 size 16 1103 } 1104} 1105 1106const SCB_UPLOAD_SIZE 32 1107const SCB_DOWNLOAD_SIZE 32 1108const SCB_DOWNLOAD_SIZE_64 48 1109 1110const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1111 1112/* --------------------- AHA-2840-only definitions -------------------- */ 1113 1114register SEECTL_2840 { 1115 address 0x0c0 1116 access_mode RW 1117 field CS_2840 0x04 1118 field CK_2840 0x02 1119 field DO_2840 0x01 1120} 1121 1122register STATUS_2840 { 1123 address 0x0c1 1124 access_mode RW 1125 field EEPROM_TF 0x80 1126 mask BIOS_SEL 0x60 1127 mask ADSEL 0x1e 1128 field DI_2840 0x01 1129} 1130 1131/* --------------------- AIC-7870-only definitions -------------------- */ 1132 1133register CCHADDR { 1134 address 0x0E0 1135 size 8 1136} 1137 1138register CCHCNT { 1139 address 0x0E8 1140} 1141 1142register CCSGRAM { 1143 address 0x0E9 1144} 1145 1146register CCSGADDR { 1147 address 0x0EA 1148} 1149 1150register CCSGCTL { 1151 address 0x0EB 1152 field CCSGDONE 0x80 1153 field CCSGEN 0x08 1154 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1155 field CCSGRESET 0x01 1156} 1157 1158register CCSCBCNT { 1159 address 0xEF 1160} 1161 1162register CCSCBCTL { 1163 address 0x0EE 1164 field CCSCBDONE 0x80 1165 field ARRDONE 0x40 /* SCB Array prefetch done */ 1166 field CCARREN 0x10 1167 field CCSCBEN 0x08 1168 field CCSCBDIR 0x04 1169 field CCSCBRESET 0x01 1170} 1171 1172register CCSCBADDR { 1173 address 0x0ED 1174} 1175 1176register CCSCBRAM { 1177 address 0xEC 1178} 1179 1180/* 1181 * SCB bank address (7895/7896/97 only) 1182 */ 1183register SCBBADDR { 1184 address 0x0F0 1185 access_mode RW 1186} 1187 1188register CCSCBPTR { 1189 address 0x0F1 1190} 1191 1192register HNSCB_QOFF { 1193 address 0x0F4 1194} 1195 1196register SNSCB_QOFF { 1197 address 0x0F6 1198} 1199 1200register SDSCB_QOFF { 1201 address 0x0F8 1202} 1203 1204register QOFF_CTLSTA { 1205 address 0x0FA 1206 field SCB_AVAIL 0x40 1207 field SNSCB_ROLLOVER 0x20 1208 field SDSCB_ROLLOVER 0x10 1209 mask SCB_QSIZE 0x07 1210 mask SCB_QSIZE_256 0x06 1211} 1212 1213register DFF_THRSH { 1214 address 0x0FB 1215 mask WR_DFTHRSH 0x70 1216 mask RD_DFTHRSH 0x07 1217 mask RD_DFTHRSH_MIN 0x00 1218 mask RD_DFTHRSH_25 0x01 1219 mask RD_DFTHRSH_50 0x02 1220 mask RD_DFTHRSH_63 0x03 1221 mask RD_DFTHRSH_75 0x04 1222 mask RD_DFTHRSH_85 0x05 1223 mask RD_DFTHRSH_90 0x06 1224 mask RD_DFTHRSH_MAX 0x07 1225 mask WR_DFTHRSH_MIN 0x00 1226 mask WR_DFTHRSH_25 0x10 1227 mask WR_DFTHRSH_50 0x20 1228 mask WR_DFTHRSH_63 0x30 1229 mask WR_DFTHRSH_75 0x40 1230 mask WR_DFTHRSH_85 0x50 1231 mask WR_DFTHRSH_90 0x60 1232 mask WR_DFTHRSH_MAX 0x70 1233} 1234 1235register SG_CACHE_PRE { 1236 access_mode WO 1237 address 0x0fc 1238 mask SG_ADDR_MASK 0xf8 1239 field ODD_SEG 0x04 1240 field LAST_SEG 0x02 1241 field LAST_SEG_DONE 0x01 1242} 1243 1244register SG_CACHE_SHADOW { 1245 access_mode RO 1246 address 0x0fc 1247 mask SG_ADDR_MASK 0xf8 1248 field ODD_SEG 0x04 1249 field LAST_SEG 0x02 1250 field LAST_SEG_DONE 0x01 1251} 1252/* ---------------------- Scratch RAM Offsets ------------------------- */ 1253/* These offsets are either to values that are initialized by the board's 1254 * BIOS or are specified by the sequencer code. 1255 * 1256 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1257 * device information, 32-33 and 5a-5f as well. As it turns out, the 1258 * BIOS trashes 20-2f, writing the synchronous negotiation results 1259 * on top of the BIOS values, so we re-use those for our per-target 1260 * scratchspace (actually a value that can be copied directly into 1261 * SCSIRATE). The kernel driver will enable synchronous negotiation 1262 * for all targets that have a value other than 0 in the lower four 1263 * bits of the target scratch space. This should work regardless of 1264 * whether the bios has been installed. 1265 */ 1266 1267scratch_ram { 1268 address 0x020 1269 size 58 1270 1271 /* 1272 * 1 byte per target starting at this address for configuration values 1273 */ 1274 BUSY_TARGETS { 1275 alias TARG_SCSIRATE 1276 size 16 1277 } 1278 /* 1279 * Bit vector of targets that have ULTRA enabled as set by 1280 * the BIOS. The Sequencer relies on a per-SCB field to 1281 * control whether to enable Ultra transfers or not. During 1282 * initialization, we read this field and reuse it for 2 1283 * entries in the busy target table. 1284 */ 1285 ULTRA_ENB { 1286 alias CMDSIZE_TABLE 1287 size 2 1288 } 1289 /* 1290 * Bit vector of targets that have disconnection disabled as set by 1291 * the BIOS. The Sequencer relies in a per-SCB field to control the 1292 * disconnect priveldge. During initialization, we read this field 1293 * and reuse it for 2 entries in the busy target table. 1294 */ 1295 DISC_DSB { 1296 size 2 1297 } 1298 CMDSIZE_TABLE_TAIL { 1299 size 4 1300 } 1301 /* 1302 * Partial transfer past cacheline end to be 1303 * transferred using an extra S/G. 1304 */ 1305 MWI_RESIDUAL { 1306 size 1 1307 alias TARG_IMMEDIATE_SCB 1308 } 1309 /* 1310 * SCBID of the next SCB to be started by the controller. 1311 */ 1312 NEXT_QUEUED_SCB { 1313 size 1 1314 } 1315 /* 1316 * Single byte buffer used to designate the type or message 1317 * to send to a target. 1318 */ 1319 MSG_OUT { 1320 size 1 1321 } 1322 /* Parameters for DMA Logic */ 1323 DMAPARAMS { 1324 size 1 1325 field PRELOADEN 0x80 1326 field WIDEODD 0x40 1327 field SCSIEN 0x20 1328 field SDMAEN 0x10 1329 field SDMAENACK 0x10 1330 field HDMAEN 0x08 1331 field HDMAENACK 0x08 1332 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 1333 field FIFOFLUSH 0x02 1334 field FIFORESET 0x01 1335 } 1336 SEQ_FLAGS { 1337 size 1 1338 field IDENTIFY_SEEN 0x80 1339 field TARGET_CMD_IS_TAGGED 0x40 1340 field DPHASE 0x20 1341 /* Target flags */ 1342 field TARG_CMD_PENDING 0x10 1343 field CMDPHASE_PENDING 0x08 1344 field DPHASE_PENDING 0x04 1345 field SPHASE_PENDING 0x02 1346 field NO_DISCONNECT 0x01 1347 } 1348 /* 1349 * Temporary storage for the 1350 * target/channel/lun of a 1351 * reconnecting target 1352 */ 1353 SAVED_SCSIID { 1354 size 1 1355 } 1356 SAVED_LUN { 1357 size 1 1358 } 1359 /* 1360 * The last bus phase as seen by the sequencer. 1361 */ 1362 LASTPHASE { 1363 size 1 1364 field CDI 0x80 1365 field IOI 0x40 1366 field MSGI 0x20 1367 mask PHASE_MASK CDI|IOI|MSGI 1368 mask P_DATAOUT 0x00 1369 mask P_DATAIN IOI 1370 mask P_COMMAND CDI 1371 mask P_MESGOUT CDI|MSGI 1372 mask P_STATUS CDI|IOI 1373 mask P_MESGIN CDI|IOI|MSGI 1374 mask P_BUSFREE 0x01 1375 } 1376 /* 1377 * head of list of SCBs awaiting 1378 * selection 1379 */ 1380 WAITING_SCBH { 1381 size 1 1382 } 1383 /* 1384 * head of list of SCBs that are 1385 * disconnected. Used for SCB 1386 * paging. 1387 */ 1388 DISCONNECTED_SCBH { 1389 size 1 1390 } 1391 /* 1392 * head of list of SCBs that are 1393 * not in use. Used for SCB paging. 1394 */ 1395 FREE_SCBH { 1396 size 1 1397 } 1398 /* 1399 * head of list of SCBs that have 1400 * completed but have not been 1401 * put into the qoutfifo. 1402 */ 1403 COMPLETE_SCBH { 1404 size 1 1405 } 1406 /* 1407 * Address of the hardware scb array in the host. 1408 */ 1409 HSCB_ADDR { 1410 size 4 1411 } 1412 /* 1413 * Base address of our shared data with the kernel driver in host 1414 * memory. This includes the qoutfifo and target mode 1415 * incoming command queue. 1416 */ 1417 SHARED_DATA_ADDR { 1418 size 4 1419 } 1420 KERNEL_QINPOS { 1421 size 1 1422 } 1423 QINPOS { 1424 size 1 1425 } 1426 QOUTPOS { 1427 size 1 1428 } 1429 /* 1430 * Kernel and sequencer offsets into the queue of 1431 * incoming target mode command descriptors. The 1432 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1433 */ 1434 KERNEL_TQINPOS { 1435 size 1 1436 } 1437 TQINPOS { 1438 size 1 1439 } 1440 ARG_1 { 1441 size 1 1442 mask SEND_MSG 0x80 1443 mask SEND_SENSE 0x40 1444 mask SEND_REJ 0x20 1445 mask MSGOUT_PHASEMIS 0x10 1446 mask EXIT_MSG_LOOP 0x08 1447 mask CONT_MSG_LOOP 0x04 1448 mask CONT_TARG_SESSION 0x02 1449 alias RETURN_1 1450 } 1451 ARG_2 { 1452 size 1 1453 alias RETURN_2 1454 } 1455 1456 /* 1457 * Snapshot of MSG_OUT taken after each message is sent. 1458 */ 1459 LAST_MSG { 1460 size 1 1461 } 1462 1463 /* 1464 * Sequences the kernel driver has okayed for us. This allows 1465 * the driver to do things like prevent initiator or target 1466 * operations. 1467 */ 1468 SCSISEQ_TEMPLATE { 1469 size 1 1470 field ENSELO 0x40 1471 field ENSELI 0x20 1472 field ENRSELI 0x10 1473 field ENAUTOATNO 0x08 1474 field ENAUTOATNI 0x04 1475 field ENAUTOATNP 0x02 1476 } 1477 1478 /* 1479 * Track whether the transfer byte count for 1480 * the current data phase is odd. 1481 */ 1482 DATA_COUNT_ODD { 1483 size 1 1484 } 1485} 1486 1487scratch_ram { 1488 address 0x056 1489 size 4 1490 /* 1491 * These scratch ram locations are initialized by the 274X BIOS. 1492 * We reuse them after capturing the BIOS settings during 1493 * initialization. 1494 */ 1495 1496 /* 1497 * The initiator specified tag for this target mode transaction. 1498 */ 1499 HA_274_BIOSGLOBAL { 1500 size 1 1501 field HA_274_EXTENDED_TRANS 0x01 1502 alias INITIATOR_TAG 1503 } 1504 1505 SEQ_FLAGS2 { 1506 size 1 1507 field SCB_DMA 0x01 1508 field TARGET_MSG_PENDING 0x02 1509 } 1510} 1511 1512scratch_ram { 1513 address 0x05a 1514 size 6 1515 /* 1516 * These are reserved registers in the card's scratch ram on the 2742. 1517 * The EISA configuraiton chip is mapped here. On Rev E. of the 1518 * aic7770, the sequencer can use this area for scratch, but the 1519 * host cannot directly access these registers. On later chips, this 1520 * area can be read and written by both the host and the sequencer. 1521 * Even on later chips, many of these locations are initialized by 1522 * the BIOS. 1523 */ 1524 SCSICONF { 1525 size 1 1526 field TERM_ENB 0x80 1527 field RESET_SCSI 0x40 1528 field ENSPCHK 0x20 1529 mask HSCSIID 0x07 /* our SCSI ID */ 1530 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1531 } 1532 INTDEF { 1533 address 0x05c 1534 size 1 1535 field EDGE_TRIG 0x80 1536 mask VECTOR 0x0f 1537 } 1538 HOSTCONF { 1539 address 0x05d 1540 size 1 1541 } 1542 HA_274_BIOSCTRL { 1543 address 0x05f 1544 size 1 1545 mask BIOSMODE 0x30 1546 mask BIOSDISABLED 0x30 1547 field CHANNEL_B_PRIMARY 0x08 1548 } 1549} 1550 1551scratch_ram { 1552 address 0x070 1553 size 16 1554 1555 /* 1556 * Per target SCSI offset values for Ultra2 controllers. 1557 */ 1558 TARG_OFFSET { 1559 size 16 1560 } 1561} 1562 1563const TID_SHIFT 4 1564const SCB_LIST_NULL 0xff 1565const TARGET_CMD_CMPLT 0xfe 1566 1567const CCSGADDR_MAX 0x80 1568const CCSGRAM_MAXSEGS 16 1569 1570/* WDTR Message values */ 1571const BUS_8_BIT 0x00 1572const BUS_16_BIT 0x01 1573const BUS_32_BIT 0x02 1574 1575/* Offset maximums */ 1576const MAX_OFFSET_8BIT 0x0f 1577const MAX_OFFSET_16BIT 0x08 1578const MAX_OFFSET_ULTRA2 0x7f 1579const HOST_MSG 0xff 1580 1581/* Target mode command processing constants */ 1582const CMD_GROUP_CODE_SHIFT 0x05 1583 1584const STATUS_BUSY 0x08 1585const STATUS_QUEUE_FULL 0x28 1586const TARGET_DATA_IN 1 1587 1588/* 1589 * Downloaded (kernel inserted) constants 1590 */ 1591/* Offsets into the SCBID array where different data is stored */ 1592const QOUTFIFO_OFFSET download 1593const QINFIFO_OFFSET download 1594const CACHESIZE_MASK download 1595const INVERTED_CACHESIZE_MASK download 1596const SG_PREFETCH_CNT download 1597const SG_PREFETCH_ALIGN_MASK download 1598const SG_PREFETCH_ADDR_MASK download 1599