1/*- 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 */ 40VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $" 41 42/* 43 * This file is processed by the aic7xxx_asm utility for use in assembling 44 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 45 * a C header file for use in the kernel portion of the Aic7xxx driver. 46 * 47 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 48 * Adaptec's Technical Documents Department 1-800-934-2766 49 */ 50 51/* 52 * SCSI Sequence Control (p. 3-11). 53 * Each bit, when set starts a specific SCSI sequence on the bus 54 */ 55register SCSISEQ { 56 address 0x000 57 access_mode RW 58 field TEMODE 0x80 59 field ENSELO 0x40 60 field ENSELI 0x20 61 field ENRSELI 0x10 62 field ENAUTOATNO 0x08 63 field ENAUTOATNI 0x04 64 field ENAUTOATNP 0x02 65 field SCSIRSTO 0x01 66} 67 68/* 69 * SCSI Transfer Control 0 Register (pp. 3-13). 70 * Controls the SCSI module data path. 71 */ 72register SXFRCTL0 { 73 address 0x001 74 access_mode RW 75 field DFON 0x80 76 field DFPEXP 0x40 77 field FAST20 0x20 78 field CLRSTCNT 0x10 79 field SPIOEN 0x08 80 field SCAMEN 0x04 81 field CLRCHN 0x02 82} 83 84/* 85 * SCSI Transfer Control 1 Register (pp. 3-14,15). 86 * Controls the SCSI module data path. 87 */ 88register SXFRCTL1 { 89 address 0x002 90 access_mode RW 91 field BITBUCKET 0x80 92 field SWRAPEN 0x40 93 field ENSPCHK 0x20 94 mask STIMESEL 0x18 95 field ENSTIMER 0x04 96 field ACTNEGEN 0x02 97 field STPWEN 0x01 /* Powered Termination */ 98} 99 100/* 101 * SCSI Control Signal Read Register (p. 3-15). 102 * Reads the actual state of the SCSI bus pins 103 */ 104register SCSISIGI { 105 address 0x003 106 access_mode RO 107 field CDI 0x80 108 field IOI 0x40 109 field MSGI 0x20 110 field ATNI 0x10 111 field SELI 0x08 112 field BSYI 0x04 113 field REQI 0x02 114 field ACKI 0x01 115/* 116 * Possible phases in SCSISIGI 117 */ 118 mask PHASE_MASK CDI|IOI|MSGI 119 mask P_DATAOUT 0x00 120 mask P_DATAIN IOI 121 mask P_DATAOUT_DT P_DATAOUT|MSGI 122 mask P_DATAIN_DT P_DATAIN|MSGI 123 mask P_COMMAND CDI 124 mask P_MESGOUT CDI|MSGI 125 mask P_STATUS CDI|IOI 126 mask P_MESGIN CDI|IOI|MSGI 127} 128 129/* 130 * SCSI Control Signal Write Register (p. 3-16). 131 * Writing to this register modifies the control signals on the bus. Only 132 * those signals that are allowed in the current mode (Initiator/Target) are 133 * asserted. 134 */ 135register SCSISIGO { 136 address 0x003 137 access_mode WO 138 field CDO 0x80 139 field IOO 0x40 140 field MSGO 0x20 141 field ATNO 0x10 142 field SELO 0x08 143 field BSYO 0x04 144 field REQO 0x02 145 field ACKO 0x01 146/* 147 * Possible phases to write into SCSISIG0 148 */ 149 mask PHASE_MASK CDI|IOI|MSGI 150 mask P_DATAOUT 0x00 151 mask P_DATAIN IOI 152 mask P_COMMAND CDI 153 mask P_MESGOUT CDI|MSGI 154 mask P_STATUS CDI|IOI 155 mask P_MESGIN CDI|IOI|MSGI 156} 157 158/* 159 * SCSI Rate Control (p. 3-17). 160 * Contents of this register determine the Synchronous SCSI data transfer 161 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 162 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 163 * greater than 0 enables synchronous transfers. 164 */ 165register SCSIRATE { 166 address 0x004 167 access_mode RW 168 field WIDEXFER 0x80 /* Wide transfer control */ 169 field ENABLE_CRC 0x40 /* CRC for D-Phases */ 170 field SINGLE_EDGE 0x10 /* Disable DT Transfers */ 171 mask SXFR 0x70 /* Sync transfer rate */ 172 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 173 mask SOFS 0x0f /* Sync offset */ 174} 175 176/* 177 * SCSI ID (p. 3-18). 178 * Contains the ID of the board and the current target on the 179 * selected channel. 180 */ 181register SCSIID { 182 address 0x005 183 access_mode RW 184 mask TID 0xf0 /* Target ID mask */ 185 mask TWIN_TID 0x70 186 field TWIN_CHNLB 0x80 187 mask OID 0x0f /* Our ID mask */ 188 /* 189 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 190 * The aic7890/91 allow an offset of up to 127 transfers in both wide 191 * and narrow mode. 192 */ 193 alias SCSIOFFSET 194 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 195} 196 197/* 198 * SCSI Latched Data (p. 3-19). 199 * Read/Write latches used to transfer data on the SCSI bus during 200 * Automatic or Manual PIO mode. SCSIDATH can be used for the 201 * upper byte of a 16bit wide asynchronouse data phase transfer. 202 */ 203register SCSIDATL { 204 address 0x006 205 access_mode RW 206} 207 208register SCSIDATH { 209 address 0x007 210 access_mode RW 211} 212 213/* 214 * SCSI Transfer Count (pp. 3-19,20) 215 * These registers count down the number of bytes transferred 216 * across the SCSI bus. The counter is decremented only once 217 * the data has been safely transferred. SDONE in SSTAT0 is 218 * set when STCNT goes to 0 219 */ 220register STCNT { 221 address 0x008 222 size 3 223 access_mode RW 224} 225 226/* ALT_MODE registers (Ultra2 and Ultra160 chips) */ 227register SXFRCTL2 { 228 address 0x013 229 access_mode RW 230 field AUTORSTDIS 0x10 231 field CMDDMAEN 0x08 232 mask ASYNC_SETUP 0x07 233} 234 235/* ALT_MODE register on Ultra160 chips */ 236register OPTIONMODE { 237 address 0x008 238 access_mode RW 239 field AUTORATEEN 0x80 240 field AUTOACKEN 0x40 241 field ATNMGMNTEN 0x20 242 field BUSFREEREV 0x10 243 field EXPPHASEDIS 0x08 244 field SCSIDATL_IMGEN 0x04 245 field AUTO_MSGOUT_DE 0x02 246 field DIS_MSGIN_DUALEDGE 0x01 247 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 248} 249 250/* ALT_MODE register on Ultra160 chips */ 251register TARGCRCCNT { 252 address 0x00a 253 size 2 254 access_mode RW 255} 256 257/* 258 * Clear SCSI Interrupt 0 (p. 3-20) 259 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 260 */ 261register CLRSINT0 { 262 address 0x00b 263 access_mode WO 264 field CLRSELDO 0x40 265 field CLRSELDI 0x20 266 field CLRSELINGO 0x10 267 field CLRSWRAP 0x08 268 field CLRIOERR 0x08 /* Ultra2 Only */ 269 field CLRSPIORDY 0x02 270} 271 272/* 273 * SCSI Status 0 (p. 3-21) 274 * Contains one set of SCSI Interrupt codes 275 * These are most likely of interest to the sequencer 276 */ 277register SSTAT0 { 278 address 0x00b 279 access_mode RO 280 field TARGET 0x80 /* Board acting as target */ 281 field SELDO 0x40 /* Selection Done */ 282 field SELDI 0x20 /* Board has been selected */ 283 field SELINGO 0x10 /* Selection In Progress */ 284 field SWRAP 0x08 /* 24bit counter wrap */ 285 field IOERR 0x08 /* LVD Tranceiver mode changed */ 286 field SDONE 0x04 /* STCNT = 0x000000 */ 287 field SPIORDY 0x02 /* SCSI PIO Ready */ 288 field DMADONE 0x01 /* DMA transfer completed */ 289} 290 291/* 292 * Clear SCSI Interrupt 1 (p. 3-23) 293 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 294 */ 295register CLRSINT1 { 296 address 0x00c 297 access_mode WO 298 field CLRSELTIMEO 0x80 299 field CLRATNO 0x40 300 field CLRSCSIRSTI 0x20 301 field CLRBUSFREE 0x08 302 field CLRSCSIPERR 0x04 303 field CLRPHASECHG 0x02 304 field CLRREQINIT 0x01 305} 306 307/* 308 * SCSI Status 1 (p. 3-24) 309 */ 310register SSTAT1 { 311 address 0x00c 312 access_mode RO 313 field SELTO 0x80 314 field ATNTARG 0x40 315 field SCSIRSTI 0x20 316 field PHASEMIS 0x10 317 field BUSFREE 0x08 318 field SCSIPERR 0x04 319 field PHASECHG 0x02 320 field REQINIT 0x01 321} 322 323/* 324 * SCSI Status 2 (pp. 3-25,26) 325 */ 326register SSTAT2 { 327 address 0x00d 328 access_mode RO 329 field OVERRUN 0x80 330 field SHVALID 0x40 /* Shadow Layer non-zero */ 331 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 332 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 333 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 334 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 335 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 336 mask SFCNT 0x1f 337} 338 339/* 340 * SCSI Status 3 (p. 3-26) 341 */ 342register SSTAT3 { 343 address 0x00e 344 access_mode RO 345 mask SCSICNT 0xf0 346 mask OFFCNT 0x0f 347 mask U2OFFCNT 0x7f 348} 349 350/* 351 * SCSI ID for the aic7890/91 chips 352 */ 353register SCSIID_ULTRA2 { 354 address 0x00f 355 access_mode RW 356 mask TID 0xf0 /* Target ID mask */ 357 mask OID 0x0f /* Our ID mask */ 358} 359 360/* 361 * SCSI Interrupt Mode 1 (p. 3-28) 362 * Setting any bit will enable the corresponding function 363 * in SIMODE0 to interrupt via the IRQ pin. 364 */ 365register SIMODE0 { 366 address 0x010 367 access_mode RW 368 field ENSELDO 0x40 369 field ENSELDI 0x20 370 field ENSELINGO 0x10 371 field ENSWRAP 0x08 372 field ENIOERR 0x08 /* LVD Tranceiver mode changes */ 373 field ENSDONE 0x04 374 field ENSPIORDY 0x02 375 field ENDMADONE 0x01 376} 377 378/* 379 * SCSI Interrupt Mode 1 (pp. 3-28,29) 380 * Setting any bit will enable the corresponding function 381 * in SIMODE1 to interrupt via the IRQ pin. 382 */ 383register SIMODE1 { 384 address 0x011 385 access_mode RW 386 field ENSELTIMO 0x80 387 field ENATNTARG 0x40 388 field ENSCSIRST 0x20 389 field ENPHASEMIS 0x10 390 field ENBUSFREE 0x08 391 field ENSCSIPERR 0x04 392 field ENPHASECHG 0x02 393 field ENREQINIT 0x01 394} 395 396/* 397 * SCSI Data Bus (High) (p. 3-29) 398 * This register reads data on the SCSI Data bus directly. 399 */ 400register SCSIBUSL { 401 address 0x012 402 access_mode RW 403} 404 405register SCSIBUSH { 406 address 0x013 407 access_mode RW 408} 409 410/* 411 * SCSI/Host Address (p. 3-30) 412 * These registers hold the host address for the byte about to be 413 * transferred on the SCSI bus. They are counted up in the same 414 * manner as STCNT is counted down. SHADDR should always be used 415 * to determine the address of the last byte transferred since HADDR 416 * can be skewed by write ahead. 417 */ 418register SHADDR { 419 address 0x014 420 size 4 421 access_mode RO 422} 423 424/* 425 * Selection Timeout Timer (p. 3-30) 426 */ 427register SELTIMER { 428 address 0x018 429 access_mode RW 430 field STAGE6 0x20 431 field STAGE5 0x10 432 field STAGE4 0x08 433 field STAGE3 0x04 434 field STAGE2 0x02 435 field STAGE1 0x01 436 alias TARGIDIN 437} 438 439/* 440 * Selection/Reselection ID (p. 3-31) 441 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 442 * device did not set its own ID. 443 */ 444register SELID { 445 address 0x019 446 access_mode RW 447 mask SELID_MASK 0xf0 448 field ONEBIT 0x08 449} 450 451register SCAMCTL { 452 address 0x01a 453 access_mode RW 454 field ENSCAMSELO 0x80 455 field CLRSCAMSELID 0x40 456 field ALTSTIM 0x20 457 field DFLTTID 0x10 458 mask SCAMLVL 0x03 459} 460 461/* 462 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 463 */ 464register TARGID { 465 address 0x01b 466 size 2 467 access_mode RW 468} 469 470/* 471 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 472 * Indicates if external logic has been attached to the chip to 473 * perform the tasks of accessing a serial eeprom, testing termination 474 * strength, and performing cable detection. On the aic7860, most of 475 * these features are handled on chip, but on the aic7855 an attached 476 * aic3800 does the grunt work. 477 */ 478register SPIOCAP { 479 address 0x01b 480 access_mode RW 481 field SOFT1 0x80 482 field SOFT0 0x40 483 field SOFTCMDEN 0x20 484 field EXT_BRDCTL 0x10 /* External Board control */ 485 field SEEPROM 0x08 /* External serial eeprom logic */ 486 field EEPROM 0x04 /* Writable external BIOS ROM */ 487 field ROM 0x02 /* Logic for accessing external ROM */ 488 field SSPIOCPS 0x01 /* Termination and cable detection */ 489} 490 491register BRDCTL { 492 address 0x01d 493 field BRDDAT7 0x80 494 field BRDDAT6 0x40 495 field BRDDAT5 0x20 496 field BRDSTB 0x10 497 field BRDCS 0x08 498 field BRDRW 0x04 499 field BRDCTL1 0x02 500 field BRDCTL0 0x01 501 /* 7890 Definitions */ 502 field BRDDAT4 0x10 503 field BRDDAT3 0x08 504 field BRDDAT2 0x04 505 field BRDRW_ULTRA2 0x02 506 field BRDSTB_ULTRA2 0x01 507} 508 509/* 510 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 511 * Controls the reading and writing of an external serial 1-bit 512 * EEPROM Device. In order to access the serial EEPROM, you must 513 * first set the SEEMS bit that generates a request to the memory 514 * port for access to the serial EEPROM device. When the memory 515 * port is not busy servicing another request, it reconfigures 516 * to allow access to the serial EEPROM. When this happens, SEERDY 517 * gets set high to verify that the memory port access has been 518 * granted. 519 * 520 * After successful arbitration for the memory port, the SEECS bit of 521 * the SEECTL register is connected to the chip select. The SEECK, 522 * SEEDO, and SEEDI are connected to the clock, data out, and data in 523 * lines respectively. The SEERDY bit of SEECTL is useful in that it 524 * gives us an 800 nsec timer. After a write to the SEECTL register, 525 * the SEERDY goes high 800 nsec later. The one exception to this is 526 * when we first request access to the memory port. The SEERDY goes 527 * high to signify that access has been granted and, for this case, has 528 * no implied timing. 529 * 530 * See 93cx6.c for detailed information on the protocol necessary to 531 * read the serial EEPROM. 532 */ 533register SEECTL { 534 address 0x01e 535 field EXTARBACK 0x80 536 field EXTARBREQ 0x40 537 field SEEMS 0x20 538 field SEERDY 0x10 539 field SEECS 0x08 540 field SEECK 0x04 541 field SEEDO 0x02 542 field SEEDI 0x01 543} 544/* 545 * SCSI Block Control (p. 3-32) 546 * Controls Bus type and channel selection. In a twin channel configuration 547 * addresses 0x00-0x1e are gated to the appropriate channel based on this 548 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 549 * on a wide bus. 550 */ 551register SBLKCTL { 552 address 0x01f 553 access_mode RW 554 field DIAGLEDEN 0x80 /* Aic78X0 only */ 555 field DIAGLEDON 0x40 /* Aic78X0 only */ 556 field AUTOFLUSHDIS 0x20 557 field SELBUSB 0x08 558 field ENAB40 0x08 /* LVD transceiver active */ 559 field ENAB20 0x04 /* SE/HVD transceiver active */ 560 field SELWIDE 0x02 561 field XCVR 0x01 /* External transceiver active */ 562} 563 564/* 565 * Sequencer Control (p. 3-33) 566 * Error detection mode and speed configuration 567 */ 568register SEQCTL { 569 address 0x060 570 access_mode RW 571 field PERRORDIS 0x80 572 field PAUSEDIS 0x40 573 field FAILDIS 0x20 574 field FASTMODE 0x10 575 field BRKADRINTEN 0x08 576 field STEP 0x04 577 field SEQRESET 0x02 578 field LOADRAM 0x01 579} 580 581/* 582 * Sequencer RAM Data (p. 3-34) 583 * Single byte window into the Scratch Ram area starting at the address 584 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 585 * four bytes in succession. The SEQADDRs will increment after the most 586 * significant byte is written 587 */ 588register SEQRAM { 589 address 0x061 590 access_mode RW 591} 592 593/* 594 * Sequencer Address Registers (p. 3-35) 595 * Only the first bit of SEQADDR1 holds addressing information 596 */ 597register SEQADDR0 { 598 address 0x062 599 access_mode RW 600} 601 602register SEQADDR1 { 603 address 0x063 604 access_mode RW 605 mask SEQADDR1_MASK 0x01 606} 607 608/* 609 * Accumulator 610 * We cheat by passing arguments in the Accumulator up to the kernel driver 611 */ 612register ACCUM { 613 address 0x064 614 access_mode RW 615 accumulator 616} 617 618register SINDEX { 619 address 0x065 620 access_mode RW 621 sindex 622} 623 624register DINDEX { 625 address 0x066 626 access_mode RW 627} 628 629register ALLONES { 630 address 0x069 631 access_mode RO 632 allones 633} 634 635register ALLZEROS { 636 address 0x06a 637 access_mode RO 638 allzeros 639} 640 641register NONE { 642 address 0x06a 643 access_mode WO 644 none 645} 646 647register FLAGS { 648 address 0x06b 649 access_mode RO 650 field ZERO 0x02 651 field CARRY 0x01 652} 653 654register SINDIR { 655 address 0x06c 656 access_mode RO 657} 658 659register DINDIR { 660 address 0x06d 661 access_mode WO 662} 663 664register FUNCTION1 { 665 address 0x06e 666 access_mode RW 667} 668 669register STACK { 670 address 0x06f 671 access_mode RO 672} 673 674const STACK_SIZE 4 675 676/* 677 * Board Control (p. 3-43) 678 */ 679register BCTL { 680 address 0x084 681 access_mode RW 682 field ACE 0x08 683 field ENABLE 0x01 684} 685 686/* 687 * On the aic78X0 chips, Board Control is replaced by the DSCommand 688 * register (p. 4-64) 689 */ 690register DSCOMMAND0 { 691 address 0x084 692 access_mode RW 693 field CACHETHEN 0x80 /* Cache Threshold enable */ 694 field DPARCKEN 0x40 /* Data Parity Check Enable */ 695 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 696 field EXTREQLCK 0x10 /* External Request Lock */ 697 /* aic7890/91/96/97 only */ 698 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 699 field RAMPS 0x04 /* External SCB RAM Present */ 700 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 701 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 702} 703 704register DSCOMMAND1 { 705 address 0x085 706 access_mode RW 707 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 708 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 709 field HADDLDSEL0 0x01 710} 711 712/* 713 * Bus On/Off Time (p. 3-44) aic7770 only 714 */ 715register BUSTIME { 716 address 0x085 717 access_mode RW 718 mask BOFF 0xf0 719 mask BON 0x0f 720} 721 722/* 723 * Bus Speed (p. 3-45) aic7770 only 724 */ 725register BUSSPD { 726 address 0x086 727 access_mode RW 728 mask DFTHRSH 0xc0 729 mask STBOFF 0x38 730 mask STBON 0x07 731 mask DFTHRSH_100 0xc0 732 mask DFTHRSH_75 0x80 733} 734 735/* aic7850/55/60/70/80/95 only */ 736register DSPCISTATUS { 737 address 0x086 738 mask DFTHRSH_100 0xc0 739} 740 741/* aic7890/91/96/97 only */ 742register HS_MAILBOX { 743 address 0x086 744 mask HOST_MAILBOX 0xF0 745 mask SEQ_MAILBOX 0x0F 746 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 747} 748 749const HOST_MAILBOX_SHIFT 4 750const SEQ_MAILBOX_SHIFT 0 751 752/* 753 * Host Control (p. 3-47) R/W 754 * Overall host control of the device. 755 */ 756register HCNTRL { 757 address 0x087 758 access_mode RW 759 field POWRDN 0x40 760 field SWINT 0x10 761 field IRQMS 0x08 762 field PAUSE 0x04 763 field INTEN 0x02 764 field CHIPRST 0x01 765 field CHIPRSTACK 0x01 766} 767 768/* 769 * Host Address (p. 3-48) 770 * This register contains the address of the byte about 771 * to be transferred across the host bus. 772 */ 773register HADDR { 774 address 0x088 775 size 4 776 access_mode RW 777} 778 779register HCNT { 780 address 0x08c 781 size 3 782 access_mode RW 783} 784 785/* 786 * SCB Pointer (p. 3-49) 787 * Gate one of the SCBs into the SCBARRAY window. 788 */ 789register SCBPTR { 790 address 0x090 791 access_mode RW 792} 793 794/* 795 * Interrupt Status (p. 3-50) 796 * Status for system interrupts 797 */ 798register INTSTAT { 799 address 0x091 800 access_mode RW 801 field BRKADRINT 0x08 802 field SCSIINT 0x04 803 field CMDCMPLT 0x02 804 field SEQINT 0x01 805 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 806 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 807 mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ 808 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 809 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 810 mask PDATA_REINIT 0x50|SEQINT /* 811 * Returned to data phase 812 * that requires data 813 * transfer pointers to be 814 * recalculated from the 815 * transfer residual. 816 */ 817 mask HOST_MSG_LOOP 0x60|SEQINT /* 818 * The bus is ready for the 819 * host to perform another 820 * message transaction. This 821 * mechanism is used for things 822 * like sync/wide negotiation 823 * that require a kernel based 824 * message state engine. 825 */ 826 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 827 mask PERR_DETECTED 0x80|SEQINT /* 828 * Either the phase_lock 829 * or inb_next routine has 830 * noticed a parity error. 831 */ 832 mask DATA_OVERRUN 0x90|SEQINT /* 833 * Target attempted to write 834 * beyond the bounds of its 835 * command. 836 */ 837 mask MKMSG_FAILED 0xa0|SEQINT /* 838 * Target completed command 839 * without honoring our ATN 840 * request to issue a message. 841 */ 842 mask MISSED_BUSFREE 0xb0|SEQINT /* 843 * The sequencer never saw 844 * the bus go free after 845 * either a command complete 846 * or disconnect message. 847 */ 848 mask SCB_MISMATCH 0xc0|SEQINT /* 849 * Downloaded SCB's tag does 850 * not match the entry we 851 * intended to download. 852 */ 853 mask NO_FREE_SCB 0xd0|SEQINT /* 854 * get_free_or_disc_scb failed. 855 */ 856 mask OUT_OF_RANGE 0xe0|SEQINT 857 858 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 859 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 860} 861 862/* 863 * Hard Error (p. 3-53) 864 * Reporting of catastrophic errors. You usually cannot recover from 865 * these without a full board reset. 866 */ 867register ERROR { 868 address 0x092 869 access_mode RO 870 field CIOPARERR 0x80 /* Ultra2 only */ 871 field PCIERRSTAT 0x40 /* PCI only */ 872 field MPARERR 0x20 /* PCI only */ 873 field DPARERR 0x10 /* PCI only */ 874 field SQPARERR 0x08 875 field ILLOPCODE 0x04 876 field ILLSADDR 0x02 877 field ILLHADDR 0x01 878} 879 880/* 881 * Clear Interrupt Status (p. 3-52) 882 */ 883register CLRINT { 884 address 0x092 885 access_mode WO 886 field CLRPARERR 0x10 /* PCI only */ 887 field CLRBRKADRINT 0x08 888 field CLRSCSIINT 0x04 889 field CLRCMDINT 0x02 890 field CLRSEQINT 0x01 891} 892 893register DFCNTRL { 894 address 0x093 895 access_mode RW 896 field PRELOADEN 0x80 /* aic7890 only */ 897 field WIDEODD 0x40 898 field SCSIEN 0x20 899 field SDMAEN 0x10 900 field SDMAENACK 0x10 901 field HDMAEN 0x08 902 field HDMAENACK 0x08 903 field DIRECTION 0x04 904 field FIFOFLUSH 0x02 905 field FIFORESET 0x01 906} 907 908register DFSTATUS { 909 address 0x094 910 access_mode RO 911 field PRELOAD_AVAIL 0x80 912 field DFCACHETH 0x40 913 field FIFOQWDEMP 0x20 914 field MREQPEND 0x10 915 field HDONE 0x08 916 field DFTHRESH 0x04 917 field FIFOFULL 0x02 918 field FIFOEMP 0x01 919} 920 921register DFWADDR { 922 address 0x95 923 access_mode RW 924} 925 926register DFRADDR { 927 address 0x97 928 access_mode RW 929} 930 931register DFDAT { 932 address 0x099 933 access_mode RW 934} 935 936/* 937 * SCB Auto Increment (p. 3-59) 938 * Byte offset into the SCB Array and an optional bit to allow auto 939 * incrementing of the address during download and upload operations 940 */ 941register SCBCNT { 942 address 0x09a 943 access_mode RW 944 field SCBAUTO 0x80 945 mask SCBCNT_MASK 0x1f 946} 947 948/* 949 * Queue In FIFO (p. 3-60) 950 * Input queue for queued SCBs (commands that the seqencer has yet to start) 951 */ 952register QINFIFO { 953 address 0x09b 954 access_mode RW 955} 956 957/* 958 * Queue In Count (p. 3-60) 959 * Number of queued SCBs 960 */ 961register QINCNT { 962 address 0x09c 963 access_mode RO 964} 965 966/* 967 * Queue Out FIFO (p. 3-61) 968 * Queue of SCBs that have completed and await the host 969 */ 970register QOUTFIFO { 971 address 0x09d 972 access_mode WO 973} 974 975register CRCCONTROL1 { 976 address 0x09d 977 access_mode RW 978 field CRCONSEEN 0x80 979 field CRCVALCHKEN 0x40 980 field CRCENDCHKEN 0x20 981 field CRCREQCHKEN 0x10 982 field TARGCRCENDEN 0x08 983 field TARGCRCCNTEN 0x04 984} 985 986 987/* 988 * Queue Out Count (p. 3-61) 989 * Number of queued SCBs in the Out FIFO 990 */ 991register QOUTCNT { 992 address 0x09e 993 access_mode RO 994} 995 996register SCSIPHASE { 997 address 0x09e 998 access_mode RO 999 field STATUS_PHASE 0x20 1000 field COMMAND_PHASE 0x10 1001 field MSG_IN_PHASE 0x08 1002 field MSG_OUT_PHASE 0x04 1003 field DATA_IN_PHASE 0x02 1004 field DATA_OUT_PHASE 0x01 1005 mask DATA_PHASE_MASK 0x03 1006} 1007 1008/* 1009 * Special Function 1010 */ 1011register SFUNCT { 1012 address 0x09f 1013 access_mode RW 1014 field ALT_MODE 0x80 1015} 1016 1017/* 1018 * SCB Definition (p. 5-4) 1019 */ 1020scb { 1021 address 0x0a0 1022 size 64 1023 1024 SCB_CDB_PTR { 1025 size 4 1026 alias SCB_RESIDUAL_DATACNT 1027 alias SCB_CDB_STORE 1028 } 1029 SCB_RESIDUAL_SGPTR { 1030 size 4 1031 } 1032 SCB_SCSI_STATUS { 1033 size 1 1034 } 1035 SCB_TARGET_PHASES { 1036 size 1 1037 } 1038 SCB_TARGET_DATA_DIR { 1039 size 1 1040 } 1041 SCB_TARGET_ITAG { 1042 size 1 1043 } 1044 SCB_DATAPTR { 1045 size 4 1046 } 1047 SCB_DATACNT { 1048 /* 1049 * The last byte is really the high address bits for 1050 * the data address. 1051 */ 1052 size 4 1053 field SG_LAST_SEG 0x80 /* In the fourth byte */ 1054 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1055 } 1056 SCB_SGPTR { 1057 size 4 1058 field SG_RESID_VALID 0x04 /* In the first byte */ 1059 field SG_FULL_RESID 0x02 /* In the first byte */ 1060 field SG_LIST_NULL 0x01 /* In the first byte */ 1061 } 1062 SCB_CONTROL { 1063 size 1 1064 field TARGET_SCB 0x80 1065 field STATUS_RCVD 0x80 1066 field DISCENB 0x40 1067 field TAG_ENB 0x20 1068 field MK_MESSAGE 0x10 1069 field ULTRAENB 0x08 1070 field DISCONNECTED 0x04 1071 mask SCB_TAG_TYPE 0x03 1072 } 1073 SCB_SCSIID { 1074 size 1 1075 field TWIN_CHNLB 0x80 1076 mask TWIN_TID 0x70 1077 mask TID 0xf0 1078 mask OID 0x0f 1079 } 1080 SCB_LUN { 1081 field SCB_XFERLEN_ODD 0x80 1082 mask LID 0x3f 1083 size 1 1084 } 1085 SCB_TAG { 1086 size 1 1087 } 1088 SCB_CDB_LEN { 1089 size 1 1090 } 1091 SCB_SCSIRATE { 1092 size 1 1093 } 1094 SCB_SCSIOFFSET { 1095 size 1 1096 } 1097 SCB_NEXT { 1098 size 1 1099 } 1100 SCB_64_SPARE { 1101 size 16 1102 } 1103 SCB_64_BTT { 1104 size 16 1105 } 1106} 1107 1108const SCB_UPLOAD_SIZE 32 1109const SCB_DOWNLOAD_SIZE 32 1110const SCB_DOWNLOAD_SIZE_64 48 1111 1112const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1113 1114/* --------------------- AHA-2840-only definitions -------------------- */ 1115 1116register SEECTL_2840 { 1117 address 0x0c0 1118 access_mode RW 1119 field CS_2840 0x04 1120 field CK_2840 0x02 1121 field DO_2840 0x01 1122} 1123 1124register STATUS_2840 { 1125 address 0x0c1 1126 access_mode RW 1127 field EEPROM_TF 0x80 1128 mask BIOS_SEL 0x60 1129 mask ADSEL 0x1e 1130 field DI_2840 0x01 1131} 1132 1133/* --------------------- AIC-7870-only definitions -------------------- */ 1134 1135register CCHADDR { 1136 address 0x0E0 1137 size 8 1138} 1139 1140register CCHCNT { 1141 address 0x0E8 1142} 1143 1144register CCSGRAM { 1145 address 0x0E9 1146} 1147 1148register CCSGADDR { 1149 address 0x0EA 1150} 1151 1152register CCSGCTL { 1153 address 0x0EB 1154 field CCSGDONE 0x80 1155 field CCSGEN 0x08 1156 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1157 field CCSGRESET 0x01 1158} 1159 1160register CCSCBCNT { 1161 address 0xEF 1162} 1163 1164register CCSCBCTL { 1165 address 0x0EE 1166 field CCSCBDONE 0x80 1167 field ARRDONE 0x40 /* SCB Array prefetch done */ 1168 field CCARREN 0x10 1169 field CCSCBEN 0x08 1170 field CCSCBDIR 0x04 1171 field CCSCBRESET 0x01 1172} 1173 1174register CCSCBADDR { 1175 address 0x0ED 1176} 1177 1178register CCSCBRAM { 1179 address 0xEC 1180} 1181 1182/* 1183 * SCB bank address (7895/7896/97 only) 1184 */ 1185register SCBBADDR { 1186 address 0x0F0 1187 access_mode RW 1188} 1189 1190register CCSCBPTR { 1191 address 0x0F1 1192} 1193 1194register HNSCB_QOFF { 1195 address 0x0F4 1196} 1197 1198register SNSCB_QOFF { 1199 address 0x0F6 1200} 1201 1202register SDSCB_QOFF { 1203 address 0x0F8 1204} 1205 1206register QOFF_CTLSTA { 1207 address 0x0FA 1208 field SCB_AVAIL 0x40 1209 field SNSCB_ROLLOVER 0x20 1210 field SDSCB_ROLLOVER 0x10 1211 mask SCB_QSIZE 0x07 1212 mask SCB_QSIZE_256 0x06 1213} 1214 1215register DFF_THRSH { 1216 address 0x0FB 1217 mask WR_DFTHRSH 0x70 1218 mask RD_DFTHRSH 0x07 1219 mask RD_DFTHRSH_MIN 0x00 1220 mask RD_DFTHRSH_25 0x01 1221 mask RD_DFTHRSH_50 0x02 1222 mask RD_DFTHRSH_63 0x03 1223 mask RD_DFTHRSH_75 0x04 1224 mask RD_DFTHRSH_85 0x05 1225 mask RD_DFTHRSH_90 0x06 1226 mask RD_DFTHRSH_MAX 0x07 1227 mask WR_DFTHRSH_MIN 0x00 1228 mask WR_DFTHRSH_25 0x10 1229 mask WR_DFTHRSH_50 0x20 1230 mask WR_DFTHRSH_63 0x30 1231 mask WR_DFTHRSH_75 0x40 1232 mask WR_DFTHRSH_85 0x50 1233 mask WR_DFTHRSH_90 0x60 1234 mask WR_DFTHRSH_MAX 0x70 1235} 1236 1237register SG_CACHE_PRE { 1238 access_mode WO 1239 address 0x0fc 1240 mask SG_ADDR_MASK 0xf8 1241 field LAST_SEG 0x02 1242 field LAST_SEG_DONE 0x01 1243} 1244 1245register SG_CACHE_SHADOW { 1246 access_mode RO 1247 address 0x0fc 1248 mask SG_ADDR_MASK 0xf8 1249 field LAST_SEG 0x02 1250 field LAST_SEG_DONE 0x01 1251} 1252/* ---------------------- Scratch RAM Offsets ------------------------- */ 1253/* These offsets are either to values that are initialized by the board's 1254 * BIOS or are specified by the sequencer code. 1255 * 1256 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1257 * device information, 32-33 and 5a-5f as well. As it turns out, the 1258 * BIOS trashes 20-2f, writing the synchronous negotiation results 1259 * on top of the BIOS values, so we re-use those for our per-target 1260 * scratchspace (actually a value that can be copied directly into 1261 * SCSIRATE). The kernel driver will enable synchronous negotiation 1262 * for all targets that have a value other than 0 in the lower four 1263 * bits of the target scratch space. This should work regardless of 1264 * whether the bios has been installed. 1265 */ 1266 1267scratch_ram { 1268 address 0x020 1269 size 58 1270 1271 /* 1272 * 1 byte per target starting at this address for configuration values 1273 */ 1274 BUSY_TARGETS { 1275 alias TARG_SCSIRATE 1276 size 16 1277 } 1278 /* 1279 * Bit vector of targets that have ULTRA enabled as set by 1280 * the BIOS. The Sequencer relies on a per-SCB field to 1281 * control whether to enable Ultra transfers or not. During 1282 * initialization, we read this field and reuse it for 2 1283 * entries in the busy target table. 1284 */ 1285 ULTRA_ENB { 1286 alias CMDSIZE_TABLE 1287 size 2 1288 } 1289 /* 1290 * Bit vector of targets that have disconnection disabled as set by 1291 * the BIOS. The Sequencer relies in a per-SCB field to control the 1292 * disconnect priveldge. During initialization, we read this field 1293 * and reuse it for 2 entries in the busy target table. 1294 */ 1295 DISC_DSB { 1296 size 2 1297 } 1298 CMDSIZE_TABLE_TAIL { 1299 size 4 1300 } 1301 /* 1302 * Partial transfer past cacheline end to be 1303 * transferred using an extra S/G. 1304 */ 1305 MWI_RESIDUAL { 1306 size 1 1307 } 1308 /* 1309 * SCBID of the next SCB to be started by the controller. 1310 */ 1311 NEXT_QUEUED_SCB { 1312 size 1 1313 } 1314 /* 1315 * Single byte buffer used to designate the type or message 1316 * to send to a target. 1317 */ 1318 MSG_OUT { 1319 size 1 1320 } 1321 /* Parameters for DMA Logic */ 1322 DMAPARAMS { 1323 size 1 1324 field PRELOADEN 0x80 1325 field WIDEODD 0x40 1326 field SCSIEN 0x20 1327 field SDMAEN 0x10 1328 field SDMAENACK 0x10 1329 field HDMAEN 0x08 1330 field HDMAENACK 0x08 1331 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 1332 field FIFOFLUSH 0x02 1333 field FIFORESET 0x01 1334 } 1335 SEQ_FLAGS { 1336 size 1 1337 field NOT_IDENTIFIED 0x80 1338 field NO_CDB_SENT 0x40 1339 field TARGET_CMD_IS_TAGGED 0x40 1340 field DPHASE 0x20 1341 /* Target flags */ 1342 field TARG_CMD_PENDING 0x10 1343 field CMDPHASE_PENDING 0x08 1344 field DPHASE_PENDING 0x04 1345 field SPHASE_PENDING 0x02 1346 field NO_DISCONNECT 0x01 1347 } 1348 /* 1349 * Temporary storage for the 1350 * target/channel/lun of a 1351 * reconnecting target 1352 */ 1353 SAVED_SCSIID { 1354 size 1 1355 } 1356 SAVED_LUN { 1357 size 1 1358 } 1359 /* 1360 * The last bus phase as seen by the sequencer. 1361 */ 1362 LASTPHASE { 1363 size 1 1364 field CDI 0x80 1365 field IOI 0x40 1366 field MSGI 0x20 1367 mask PHASE_MASK CDI|IOI|MSGI 1368 mask P_DATAOUT 0x00 1369 mask P_DATAIN IOI 1370 mask P_COMMAND CDI 1371 mask P_MESGOUT CDI|MSGI 1372 mask P_STATUS CDI|IOI 1373 mask P_MESGIN CDI|IOI|MSGI 1374 mask P_BUSFREE 0x01 1375 } 1376 /* 1377 * head of list of SCBs awaiting 1378 * selection 1379 */ 1380 WAITING_SCBH { 1381 size 1 1382 } 1383 /* 1384 * head of list of SCBs that are 1385 * disconnected. Used for SCB 1386 * paging. 1387 */ 1388 DISCONNECTED_SCBH { 1389 size 1 1390 } 1391 /* 1392 * head of list of SCBs that are 1393 * not in use. Used for SCB paging. 1394 */ 1395 FREE_SCBH { 1396 size 1 1397 } 1398 /* 1399 * head of list of SCBs that have 1400 * completed but have not been 1401 * put into the qoutfifo. 1402 */ 1403 COMPLETE_SCBH { 1404 size 1 1405 } 1406 /* 1407 * Address of the hardware scb array in the host. 1408 */ 1409 HSCB_ADDR { 1410 size 4 1411 } 1412 /* 1413 * Base address of our shared data with the kernel driver in host 1414 * memory. This includes the qoutfifo and target mode 1415 * incoming command queue. 1416 */ 1417 SHARED_DATA_ADDR { 1418 size 4 1419 } 1420 KERNEL_QINPOS { 1421 size 1 1422 } 1423 QINPOS { 1424 size 1 1425 } 1426 QOUTPOS { 1427 size 1 1428 } 1429 /* 1430 * Kernel and sequencer offsets into the queue of 1431 * incoming target mode command descriptors. The 1432 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1433 */ 1434 KERNEL_TQINPOS { 1435 size 1 1436 } 1437 TQINPOS { 1438 size 1 1439 } 1440 ARG_1 { 1441 size 1 1442 mask SEND_MSG 0x80 1443 mask SEND_SENSE 0x40 1444 mask SEND_REJ 0x20 1445 mask MSGOUT_PHASEMIS 0x10 1446 mask EXIT_MSG_LOOP 0x08 1447 mask CONT_MSG_LOOP 0x04 1448 mask CONT_TARG_SESSION 0x02 1449 mask SPARE 0x01 1450 alias RETURN_1 1451 } 1452 ARG_2 { 1453 size 1 1454 alias RETURN_2 1455 } 1456 1457 /* 1458 * Snapshot of MSG_OUT taken after each message is sent. 1459 */ 1460 LAST_MSG { 1461 size 1 1462 alias TARG_IMMEDIATE_SCB 1463 } 1464 1465 /* 1466 * Sequences the kernel driver has okayed for us. This allows 1467 * the driver to do things like prevent initiator or target 1468 * operations. 1469 */ 1470 SCSISEQ_TEMPLATE { 1471 size 1 1472 field ENSELO 0x40 1473 field ENSELI 0x20 1474 field ENRSELI 0x10 1475 field ENAUTOATNO 0x08 1476 field ENAUTOATNI 0x04 1477 field ENAUTOATNP 0x02 1478 } 1479} 1480 1481scratch_ram { 1482 address 0x056 1483 size 4 1484 /* 1485 * These scratch ram locations are initialized by the 274X BIOS. 1486 * We reuse them after capturing the BIOS settings during 1487 * initialization. 1488 */ 1489 1490 /* 1491 * The initiator specified tag for this target mode transaction. 1492 */ 1493 HA_274_BIOSGLOBAL { 1494 size 1 1495 field HA_274_EXTENDED_TRANS 0x01 1496 alias INITIATOR_TAG 1497 } 1498 1499 SEQ_FLAGS2 { 1500 size 1 1501 field SCB_DMA 0x01 1502 field TARGET_MSG_PENDING 0x02 1503 } 1504} 1505 1506scratch_ram { 1507 address 0x05a 1508 size 6 1509 /* 1510 * These are reserved registers in the card's scratch ram on the 2742. 1511 * The EISA configuration chip is mapped here. On Rev E. of the 1512 * aic7770, the sequencer can use this area for scratch, but the 1513 * host cannot directly access these registers. On later chips, this 1514 * area can be read and written by both the host and the sequencer. 1515 * Even on later chips, many of these locations are initialized by 1516 * the BIOS. 1517 */ 1518 SCSICONF { 1519 size 1 1520 field TERM_ENB 0x80 1521 field RESET_SCSI 0x40 1522 field ENSPCHK 0x20 1523 mask HSCSIID 0x07 /* our SCSI ID */ 1524 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1525 } 1526 INTDEF { 1527 address 0x05c 1528 size 1 1529 field EDGE_TRIG 0x80 1530 mask VECTOR 0x0f 1531 } 1532 HOSTCONF { 1533 address 0x05d 1534 size 1 1535 } 1536 HA_274_BIOSCTRL { 1537 address 0x05f 1538 size 1 1539 mask BIOSMODE 0x30 1540 mask BIOSDISABLED 0x30 1541 field CHANNEL_B_PRIMARY 0x08 1542 } 1543} 1544 1545scratch_ram { 1546 address 0x070 1547 size 16 1548 1549 /* 1550 * Per target SCSI offset values for Ultra2 controllers. 1551 */ 1552 TARG_OFFSET { 1553 size 16 1554 } 1555} 1556 1557const TID_SHIFT 4 1558const SCB_LIST_NULL 0xff 1559const TARGET_CMD_CMPLT 0xfe 1560 1561const CCSGADDR_MAX 0x80 1562const CCSGRAM_MAXSEGS 16 1563 1564/* WDTR Message values */ 1565const BUS_8_BIT 0x00 1566const BUS_16_BIT 0x01 1567const BUS_32_BIT 0x02 1568 1569/* Offset maximums */ 1570const MAX_OFFSET_8BIT 0x0f 1571const MAX_OFFSET_16BIT 0x08 1572const MAX_OFFSET_ULTRA2 0x7f 1573const MAX_OFFSET 0x7f 1574const HOST_MSG 0xff 1575 1576/* Target mode command processing constants */ 1577const CMD_GROUP_CODE_SHIFT 0x05 1578 1579const STATUS_BUSY 0x08 1580const STATUS_QUEUE_FULL 0x28 1581const TARGET_DATA_IN 1 1582 1583/* 1584 * Downloaded (kernel inserted) constants 1585 */ 1586/* Offsets into the SCBID array where different data is stored */ 1587const QOUTFIFO_OFFSET download 1588const QINFIFO_OFFSET download 1589const CACHESIZE_MASK download 1590const INVERTED_CACHESIZE_MASK download 1591const SG_PREFETCH_CNT download 1592const SG_PREFETCH_ALIGN_MASK download 1593const SG_PREFETCH_ADDR_MASK download 1594