1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.reg#17 $ 32 * 33 * $FreeBSD$ 34 */ 35 36/* 37 * This file is processed by the aic7xxx_asm utility for use in assembling 38 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 39 * a C header file for use in the kernel portion of the Aic7xxx driver. 40 * 41 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 42 * Adaptec's Technical Documents Department 1-800-934-2766 43 */ 44 45/* 46 * SCSI Sequence Control (p. 3-11). 47 * Each bit, when set starts a specific SCSI sequence on the bus 48 */ 49register SCSISEQ { 50 address 0x000 51 access_mode RW 52 bit TEMODE 0x80 53 bit ENSELO 0x40 54 bit ENSELI 0x20 55 bit ENRSELI 0x10 56 bit ENAUTOATNO 0x08 57 bit ENAUTOATNI 0x04 58 bit ENAUTOATNP 0x02 59 bit SCSIRSTO 0x01 60} 61 62/* 63 * SCSI Transfer Control 0 Register (pp. 3-13). 64 * Controls the SCSI module data path. 65 */ 66register SXFRCTL0 { 67 address 0x001 68 access_mode RW 69 bit DFON 0x80 70 bit DFPEXP 0x40 71 bit FAST20 0x20 72 bit CLRSTCNT 0x10 73 bit SPIOEN 0x08 74 bit SCAMEN 0x04 75 bit CLRCHN 0x02 76} 77 78/* 79 * SCSI Transfer Control 1 Register (pp. 3-14,15). 80 * Controls the SCSI module data path. 81 */ 82register SXFRCTL1 { 83 address 0x002 84 access_mode RW 85 bit BITBUCKET 0x80 86 bit SWRAPEN 0x40 87 bit ENSPCHK 0x20 88 mask STIMESEL 0x18 89 bit ENSTIMER 0x04 90 bit ACTNEGEN 0x02 91 bit STPWEN 0x01 /* Powered Termination */ 92} 93 94/* 95 * SCSI Control Signal Read Register (p. 3-15). 96 * Reads the actual state of the SCSI bus pins 97 */ 98register SCSISIGI { 99 address 0x003 100 access_mode RO 101 bit CDI 0x80 102 bit IOI 0x40 103 bit MSGI 0x20 104 bit ATNI 0x10 105 bit SELI 0x08 106 bit BSYI 0x04 107 bit REQI 0x02 108 bit ACKI 0x01 109/* 110 * Possible phases in SCSISIGI 111 */ 112 mask PHASE_MASK CDI|IOI|MSGI 113 mask P_DATAOUT 0x00 114 mask P_DATAIN IOI 115 mask P_DATAOUT_DT P_DATAOUT|MSGI 116 mask P_DATAIN_DT P_DATAIN|MSGI 117 mask P_COMMAND CDI 118 mask P_MESGOUT CDI|MSGI 119 mask P_STATUS CDI|IOI 120 mask P_MESGIN CDI|IOI|MSGI 121} 122 123/* 124 * SCSI Control Signal Write Register (p. 3-16). 125 * Writing to this register modifies the control signals on the bus. Only 126 * those signals that are allowed in the current mode (Initiator/Target) are 127 * asserted. 128 */ 129register SCSISIGO { 130 address 0x003 131 access_mode WO 132 bit CDO 0x80 133 bit IOO 0x40 134 bit MSGO 0x20 135 bit ATNO 0x10 136 bit SELO 0x08 137 bit BSYO 0x04 138 bit REQO 0x02 139 bit ACKO 0x01 140/* 141 * Possible phases to write into SCSISIG0 142 */ 143 mask PHASE_MASK CDI|IOI|MSGI 144 mask P_DATAOUT 0x00 145 mask P_DATAIN IOI 146 mask P_COMMAND CDI 147 mask P_MESGOUT CDI|MSGI 148 mask P_STATUS CDI|IOI 149 mask P_MESGIN CDI|IOI|MSGI 150} 151 152/* 153 * SCSI Rate Control (p. 3-17). 154 * Contents of this register determine the Synchronous SCSI data transfer 155 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 156 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 157 * greater than 0 enables synchronous transfers. 158 */ 159register SCSIRATE { 160 address 0x004 161 access_mode RW 162 bit WIDEXFER 0x80 /* Wide transfer control */ 163 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 164 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 165 mask SXFR 0x70 /* Sync transfer rate */ 166 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 167 mask SOFS 0x0f /* Sync offset */ 168} 169 170/* 171 * SCSI ID (p. 3-18). 172 * Contains the ID of the board and the current target on the 173 * selected channel. 174 */ 175register SCSIID { 176 address 0x005 177 access_mode RW 178 mask TID 0xf0 /* Target ID mask */ 179 mask TWIN_TID 0x70 180 bit TWIN_CHNLB 0x80 181 mask OID 0x0f /* Our ID mask */ 182 /* 183 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 184 * The aic7890/91 allow an offset of up to 127 transfers in both wide 185 * and narrow mode. 186 */ 187 alias SCSIOFFSET 188 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 189} 190 191/* 192 * SCSI Latched Data (p. 3-19). 193 * Read/Write latches used to transfer data on the SCSI bus during 194 * Automatic or Manual PIO mode. SCSIDATH can be used for the 195 * upper byte of a 16bit wide asynchronouse data phase transfer. 196 */ 197register SCSIDATL { 198 address 0x006 199 access_mode RW 200} 201 202register SCSIDATH { 203 address 0x007 204 access_mode RW 205} 206 207/* 208 * SCSI Transfer Count (pp. 3-19,20) 209 * These registers count down the number of bytes transferred 210 * across the SCSI bus. The counter is decremented only once 211 * the data has been safely transferred. SDONE in SSTAT0 is 212 * set when STCNT goes to 0 213 */ 214register STCNT { 215 address 0x008 216 size 3 217 access_mode RW 218} 219 220/* ALT_MODE register on Ultra160 chips */ 221register OPTIONMODE { 222 address 0x008 223 access_mode RW 224 bit AUTORATEEN 0x80 225 bit AUTOACKEN 0x40 226 bit ATNMGMNTEN 0x20 227 bit BUSFREEREV 0x10 228 bit EXPPHASEDIS 0x08 229 bit SCSIDATL_IMGEN 0x04 230 bit AUTO_MSGOUT_DE 0x02 231 bit DIS_MSGIN_DUALEDGE 0x01 232 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 233} 234 235/* ALT_MODE register on Ultra160 chips */ 236register TARGCRCCNT { 237 address 0x00a 238 size 2 239 access_mode RW 240} 241 242/* 243 * Clear SCSI Interrupt 0 (p. 3-20) 244 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 245 */ 246register CLRSINT0 { 247 address 0x00b 248 access_mode WO 249 bit CLRSELDO 0x40 250 bit CLRSELDI 0x20 251 bit CLRSELINGO 0x10 252 bit CLRSWRAP 0x08 253 bit CLRIOERR 0x08 /* Ultra2 Only */ 254 bit CLRSPIORDY 0x02 255} 256 257/* 258 * SCSI Status 0 (p. 3-21) 259 * Contains one set of SCSI Interrupt codes 260 * These are most likely of interest to the sequencer 261 */ 262register SSTAT0 { 263 address 0x00b 264 access_mode RO 265 bit TARGET 0x80 /* Board acting as target */ 266 bit SELDO 0x40 /* Selection Done */ 267 bit SELDI 0x20 /* Board has been selected */ 268 bit SELINGO 0x10 /* Selection In Progress */ 269 bit SWRAP 0x08 /* 24bit counter wrap */ 270 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 271 bit SDONE 0x04 /* STCNT = 0x000000 */ 272 bit SPIORDY 0x02 /* SCSI PIO Ready */ 273 bit DMADONE 0x01 /* DMA transfer completed */ 274} 275 276/* 277 * Clear SCSI Interrupt 1 (p. 3-23) 278 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 279 */ 280register CLRSINT1 { 281 address 0x00c 282 access_mode WO 283 bit CLRSELTIMEO 0x80 284 bit CLRATNO 0x40 285 bit CLRSCSIRSTI 0x20 286 bit CLRBUSFREE 0x08 287 bit CLRSCSIPERR 0x04 288 bit CLRPHASECHG 0x02 289 bit CLRREQINIT 0x01 290} 291 292/* 293 * SCSI Status 1 (p. 3-24) 294 */ 295register SSTAT1 { 296 address 0x00c 297 access_mode RO 298 bit SELTO 0x80 299 bit ATNTARG 0x40 300 bit SCSIRSTI 0x20 301 bit PHASEMIS 0x10 302 bit BUSFREE 0x08 303 bit SCSIPERR 0x04 304 bit PHASECHG 0x02 305 bit REQINIT 0x01 306} 307 308/* 309 * SCSI Status 2 (pp. 3-25,26) 310 */ 311register SSTAT2 { 312 address 0x00d 313 access_mode RO 314 bit OVERRUN 0x80 315 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 316 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 317 bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 318 bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 319 bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 320 bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 321 mask SFCNT 0x1f 322} 323 324/* 325 * SCSI Status 3 (p. 3-26) 326 */ 327register SSTAT3 { 328 address 0x00e 329 access_mode RO 330 mask SCSICNT 0xf0 331 mask OFFCNT 0x0f 332} 333 334/* 335 * SCSI ID for the aic7890/91 chips 336 */ 337register SCSIID_ULTRA2 { 338 address 0x00f 339 access_mode RW 340 mask TID 0xf0 /* Target ID mask */ 341 mask OID 0x0f /* Our ID mask */ 342} 343 344/* 345 * SCSI Interrupt Mode 1 (p. 3-28) 346 * Setting any bit will enable the corresponding function 347 * in SIMODE0 to interrupt via the IRQ pin. 348 */ 349register SIMODE0 { 350 address 0x010 351 access_mode RW 352 bit ENSELDO 0x40 353 bit ENSELDI 0x20 354 bit ENSELINGO 0x10 355 bit ENSWRAP 0x08 356 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 357 bit ENSDONE 0x04 358 bit ENSPIORDY 0x02 359 bit ENDMADONE 0x01 360} 361 362/* 363 * SCSI Interrupt Mode 1 (pp. 3-28,29) 364 * Setting any bit will enable the corresponding function 365 * in SIMODE1 to interrupt via the IRQ pin. 366 */ 367register SIMODE1 { 368 address 0x011 369 access_mode RW 370 bit ENSELTIMO 0x80 371 bit ENATNTARG 0x40 372 bit ENSCSIRST 0x20 373 bit ENPHASEMIS 0x10 374 bit ENBUSFREE 0x08 375 bit ENSCSIPERR 0x04 376 bit ENPHASECHG 0x02 377 bit ENREQINIT 0x01 378} 379 380/* 381 * SCSI Data Bus (High) (p. 3-29) 382 * This register reads data on the SCSI Data bus directly. 383 */ 384register SCSIBUSL { 385 address 0x012 386 access_mode RW 387} 388 389register SCSIBUSH { 390 address 0x013 391 access_mode RW 392} 393 394/* 395 * SCSI/Host Address (p. 3-30) 396 * These registers hold the host address for the byte about to be 397 * transferred on the SCSI bus. They are counted up in the same 398 * manner as STCNT is counted down. SHADDR should always be used 399 * to determine the address of the last byte transferred since HADDR 400 * can be skewed by write ahead. 401 */ 402register SHADDR { 403 address 0x014 404 size 4 405 access_mode RO 406} 407 408/* 409 * Selection Timeout Timer (p. 3-30) 410 */ 411register SELTIMER { 412 address 0x018 413 access_mode RW 414 bit STAGE6 0x20 415 bit STAGE5 0x10 416 bit STAGE4 0x08 417 bit STAGE3 0x04 418 bit STAGE2 0x02 419 bit STAGE1 0x01 420 alias TARGIDIN 421} 422 423/* 424 * Selection/Reselection ID (p. 3-31) 425 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 426 * device did not set its own ID. 427 */ 428register SELID { 429 address 0x019 430 access_mode RW 431 mask SELID_MASK 0xf0 432 bit ONEBIT 0x08 433} 434 435register SCAMCTL { 436 address 0x01a 437 access_mode RW 438 bit ENSCAMSELO 0x80 439 bit CLRSCAMSELID 0x40 440 bit ALTSTIM 0x20 441 bit DFLTTID 0x10 442 mask SCAMLVL 0x03 443} 444 445/* 446 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 447 */ 448register TARGID { 449 address 0x01b 450 size 2 451 access_mode RW 452} 453 454/* 455 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 456 * Indicates if external logic has been attached to the chip to 457 * perform the tasks of accessing a serial eeprom, testing termination 458 * strength, and performing cable detection. On the aic7860, most of 459 * these features are handled on chip, but on the aic7855 an attached 460 * aic3800 does the grunt work. 461 */ 462register SPIOCAP { 463 address 0x01b 464 access_mode RW 465 bit SOFT1 0x80 466 bit SOFT0 0x40 467 bit SOFTCMDEN 0x20 468 bit HAS_BRDCTL 0x10 /* External Board control */ 469 bit SEEPROM 0x08 /* External serial eeprom logic */ 470 bit EEPROM 0x04 /* Writable external BIOS ROM */ 471 bit ROM 0x02 /* Logic for accessing external ROM */ 472 bit SSPIOCPS 0x01 /* Termination and cable detection */ 473} 474 475register BRDCTL { 476 address 0x01d 477 bit BRDDAT7 0x80 478 bit BRDDAT6 0x40 479 bit BRDDAT5 0x20 480 bit BRDSTB 0x10 481 bit BRDCS 0x08 482 bit BRDRW 0x04 483 bit BRDCTL1 0x02 484 bit BRDCTL0 0x01 485 /* 7890 Definitions */ 486 bit BRDDAT4 0x10 487 bit BRDDAT3 0x08 488 bit BRDDAT2 0x04 489 bit BRDRW_ULTRA2 0x02 490 bit BRDSTB_ULTRA2 0x01 491} 492 493/* 494 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 495 * Controls the reading and writing of an external serial 1-bit 496 * EEPROM Device. In order to access the serial EEPROM, you must 497 * first set the SEEMS bit that generates a request to the memory 498 * port for access to the serial EEPROM device. When the memory 499 * port is not busy servicing another request, it reconfigures 500 * to allow access to the serial EEPROM. When this happens, SEERDY 501 * gets set high to verify that the memory port access has been 502 * granted. 503 * 504 * After successful arbitration for the memory port, the SEECS bit of 505 * the SEECTL register is connected to the chip select. The SEECK, 506 * SEEDO, and SEEDI are connected to the clock, data out, and data in 507 * lines respectively. The SEERDY bit of SEECTL is useful in that it 508 * gives us an 800 nsec timer. After a write to the SEECTL register, 509 * the SEERDY goes high 800 nsec later. The one exception to this is 510 * when we first request access to the memory port. The SEERDY goes 511 * high to signify that access has been granted and, for this case, has 512 * no implied timing. 513 * 514 * See 93cx6.c for detailed information on the protocol necessary to 515 * read the serial EEPROM. 516 */ 517register SEECTL { 518 address 0x01e 519 bit EXTARBACK 0x80 520 bit EXTARBREQ 0x40 521 bit SEEMS 0x20 522 bit SEERDY 0x10 523 bit SEECS 0x08 524 bit SEECK 0x04 525 bit SEEDO 0x02 526 bit SEEDI 0x01 527} 528/* 529 * SCSI Block Control (p. 3-32) 530 * Controls Bus type and channel selection. In a twin channel configuration 531 * addresses 0x00-0x1e are gated to the appropriate channel based on this 532 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 533 * on a wide bus. 534 */ 535register SBLKCTL { 536 address 0x01f 537 access_mode RW 538 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 539 bit DIAGLEDON 0x40 /* Aic78X0 only */ 540 bit AUTOFLUSHDIS 0x20 541 bit SELBUSB 0x08 542 bit ENAB40 0x08 /* LVD transceiver active */ 543 bit ENAB20 0x04 /* SE/HVD transceiver active */ 544 bit SELWIDE 0x02 545 bit XCVR 0x01 /* External transceiver active */ 546} 547 548/* 549 * Sequencer Control (p. 3-33) 550 * Error detection mode and speed configuration 551 */ 552register SEQCTL { 553 address 0x060 554 access_mode RW 555 bit PERRORDIS 0x80 556 bit PAUSEDIS 0x40 557 bit FAILDIS 0x20 558 bit FASTMODE 0x10 559 bit BRKADRINTEN 0x08 560 bit STEP 0x04 561 bit SEQRESET 0x02 562 bit LOADRAM 0x01 563} 564 565/* 566 * Sequencer RAM Data (p. 3-34) 567 * Single byte window into the Scratch Ram area starting at the address 568 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 569 * four bytes in succession. The SEQADDRs will increment after the most 570 * significant byte is written 571 */ 572register SEQRAM { 573 address 0x061 574 access_mode RW 575} 576 577/* 578 * Sequencer Address Registers (p. 3-35) 579 * Only the first bit of SEQADDR1 holds addressing information 580 */ 581register SEQADDR0 { 582 address 0x062 583 access_mode RW 584} 585 586register SEQADDR1 { 587 address 0x063 588 access_mode RW 589 mask SEQADDR1_MASK 0x01 590} 591 592/* 593 * Accumulator 594 * We cheat by passing arguments in the Accumulator up to the kernel driver 595 */ 596register ACCUM { 597 address 0x064 598 access_mode RW 599 accumulator 600} 601 602register SINDEX { 603 address 0x065 604 access_mode RW 605 sindex 606} 607 608register DINDEX { 609 address 0x066 610 access_mode RW 611} 612 613register ALLONES { 614 address 0x069 615 access_mode RO 616 allones 617} 618 619register ALLZEROS { 620 address 0x06a 621 access_mode RO 622 allzeros 623} 624 625register NONE { 626 address 0x06a 627 access_mode WO 628 none 629} 630 631register FLAGS { 632 address 0x06b 633 access_mode RO 634 bit ZERO 0x02 635 bit CARRY 0x01 636} 637 638register SINDIR { 639 address 0x06c 640 access_mode RO 641} 642 643register DINDIR { 644 address 0x06d 645 access_mode WO 646} 647 648register FUNCTION1 { 649 address 0x06e 650 access_mode RW 651} 652 653register STACK { 654 address 0x06f 655 access_mode RO 656} 657 658/* 659 * Board Control (p. 3-43) 660 */ 661register BCTL { 662 address 0x084 663 access_mode RW 664 bit ACE 0x08 665 bit ENABLE 0x01 666} 667 668/* 669 * On the aic78X0 chips, Board Control is replaced by the DSCommand 670 * register (p. 4-64) 671 */ 672register DSCOMMAND0 { 673 address 0x084 674 access_mode RW 675 bit CACHETHEN 0x80 /* Cache Threshold enable */ 676 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 677 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 678 bit EXTREQLCK 0x10 /* External Request Lock */ 679 /* aic7890/91/96/97 only */ 680 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 681 bit RAMPS 0x04 /* External SCB RAM Present */ 682 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 683 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 684} 685 686/* 687 * Bus On/Off Time (p. 3-44) 688 */ 689register BUSTIME { 690 address 0x085 691 access_mode RW 692 mask BOFF 0xf0 693 mask BON 0x0f 694} 695 696/* 697 * Bus Speed (p. 3-45) aic7770 only 698 */ 699register BUSSPD { 700 address 0x086 701 access_mode RW 702 mask DFTHRSH 0xc0 703 mask STBOFF 0x38 704 mask STBON 0x07 705 mask DFTHRSH_100 0xc0 706 mask DFTHRSH_75 0x80 707} 708 709/* aic7850/55/60/70/80/95 only */ 710register DSPCISTATUS { 711 address 0x086 712 mask DFTHRSH_100 0xc0 713} 714 715/* aic7890/91/96/97 only */ 716register HS_MAILBOX { 717 address 0x086 718 mask HOST_MAILBOX 0xF0 719 mask SEQ_MAILBOX 0x0F 720 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 721} 722 723const HOST_MAILBOX_SHIFT 4 724const SEQ_MAILBOX_SHIFT 0 725 726/* 727 * Host Control (p. 3-47) R/W 728 * Overall host control of the device. 729 */ 730register HCNTRL { 731 address 0x087 732 access_mode RW 733 bit POWRDN 0x40 734 bit SWINT 0x10 735 bit IRQMS 0x08 736 bit PAUSE 0x04 737 bit INTEN 0x02 738 bit CHIPRST 0x01 739 bit CHIPRSTACK 0x01 740} 741 742/* 743 * Host Address (p. 3-48) 744 * This register contains the address of the byte about 745 * to be transferred across the host bus. 746 */ 747register HADDR { 748 address 0x088 749 size 4 750 access_mode RW 751} 752 753register HCNT { 754 address 0x08c 755 size 3 756 access_mode RW 757} 758 759/* 760 * SCB Pointer (p. 3-49) 761 * Gate one of the SCBs into the SCBARRAY window. 762 */ 763register SCBPTR { 764 address 0x090 765 access_mode RW 766} 767 768/* 769 * Interrupt Status (p. 3-50) 770 * Status for system interrupts 771 */ 772register INTSTAT { 773 address 0x091 774 access_mode RW 775 bit BRKADRINT 0x08 776 bit SCSIINT 0x04 777 bit CMDCMPLT 0x02 778 bit SEQINT 0x01 779 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 780 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 781 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 782 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 783 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 784 mask RESIDUAL 0x50|SEQINT /* Residual byte count != 0 */ 785 mask HOST_MSG_LOOP 0x60|SEQINT /* 786 * The bus is ready for the 787 * host to perform another 788 * message transaction. This 789 * mechanism is used for things 790 * like sync/wide negotiation 791 * that require a kernel based 792 * message state engine. 793 */ 794 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 795 mask PERR_DETECTED 0x80|SEQINT /* 796 * Either the phase_lock 797 * or inb_next routine has 798 * noticed a parity error. 799 */ 800 mask DATA_OVERRUN 0x90|SEQINT /* 801 * Target attempted to write 802 * beyond the bounds of its 803 * command. 804 */ 805 mask MKMSG_FAILED 0xa0|SEQINT /* 806 * Target completed command 807 * without honoring our ATN 808 * request to issue a message. 809 */ 810 mask MISSED_BUSFREE 0xb0|SEQINT /* 811 * The sequencer never saw 812 * the bus go free after 813 * either a command complete 814 * or disconnect message. 815 */ 816 mask SCB_MISMATCH 0xc0|SEQINT /* 817 * Downloaded SCB's tag does 818 * not match the entry we 819 * intended to download. 820 */ 821 mask NO_FREE_SCB 0xd0|SEQINT /* 822 * get_free_or_disc_scb failed. 823 */ 824 mask OUT_OF_RANGE 0xe0|SEQINT 825 826 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 827 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 828} 829 830/* 831 * Hard Error (p. 3-53) 832 * Reporting of catastrophic errors. You usually cannot recover from 833 * these without a full board reset. 834 */ 835register ERROR { 836 address 0x092 837 access_mode RO 838 bit CIOPARERR 0x80 /* Ultra2 only */ 839 bit PCIERRSTAT 0x40 /* PCI only */ 840 bit MPARERR 0x20 /* PCI only */ 841 bit DPARERR 0x10 /* PCI only */ 842 bit SQPARERR 0x08 843 bit ILLOPCODE 0x04 844 bit ILLSADDR 0x02 845 bit ILLHADDR 0x01 846} 847 848/* 849 * Clear Interrupt Status (p. 3-52) 850 */ 851register CLRINT { 852 address 0x092 853 access_mode WO 854 bit CLRPARERR 0x10 /* PCI only */ 855 bit CLRBRKADRINT 0x08 856 bit CLRSCSIINT 0x04 857 bit CLRCMDINT 0x02 858 bit CLRSEQINT 0x01 859} 860 861register DFCNTRL { 862 address 0x093 863 access_mode RW 864 bit PRELOADEN 0x80 /* aic7890 only */ 865 bit WIDEODD 0x40 866 bit SCSIEN 0x20 867 bit SDMAEN 0x10 868 bit SDMAENACK 0x10 869 bit HDMAEN 0x08 870 bit HDMAENACK 0x08 871 bit DIRECTION 0x04 872 bit FIFOFLUSH 0x02 873 bit FIFORESET 0x01 874} 875 876register DFSTATUS { 877 address 0x094 878 access_mode RO 879 bit PRELOAD_AVAIL 0x80 880 bit DFCACHETH 0x40 881 bit FIFOQWDEMP 0x20 882 bit MREQPEND 0x10 883 bit HDONE 0x08 884 bit DFTHRESH 0x04 885 bit FIFOFULL 0x02 886 bit FIFOEMP 0x01 887} 888 889register DFWADDR { 890 address 0x95 891 access_mode RW 892} 893 894register DFRADDR { 895 address 0x97 896 access_mode RW 897} 898 899register DFDAT { 900 address 0x099 901 access_mode RW 902} 903 904/* 905 * SCB Auto Increment (p. 3-59) 906 * Byte offset into the SCB Array and an optional bit to allow auto 907 * incrementing of the address during download and upload operations 908 */ 909register SCBCNT { 910 address 0x09a 911 access_mode RW 912 bit SCBAUTO 0x80 913 mask SCBCNT_MASK 0x1f 914} 915 916/* 917 * Queue In FIFO (p. 3-60) 918 * Input queue for queued SCBs (commands that the seqencer has yet to start) 919 */ 920register QINFIFO { 921 address 0x09b 922 access_mode RW 923} 924 925/* 926 * Queue In Count (p. 3-60) 927 * Number of queued SCBs 928 */ 929register QINCNT { 930 address 0x09c 931 access_mode RO 932} 933 934/* 935 * Queue Out FIFO (p. 3-61) 936 * Queue of SCBs that have completed and await the host 937 */ 938register QOUTFIFO { 939 address 0x09d 940 access_mode WO 941} 942 943register CRCCONTROL1 { 944 address 0x09d 945 access_mode RW 946 bit CRCONSEEN 0x80 947 bit CRCVALCHKEN 0x40 948 bit CRCENDCHKEN 0x20 949 bit CRCREQCHKEN 0x10 950 bit TARGCRCENDEN 0x08 951 bit TARGCRCCNTEN 0x04 952} 953 954 955/* 956 * Queue Out Count (p. 3-61) 957 * Number of queued SCBs in the Out FIFO 958 */ 959register QOUTCNT { 960 address 0x09e 961 access_mode RO 962} 963 964register SCSIPHASE { 965 address 0x09e 966 access_mode RO 967 bit STATUS_PHASE 0x20 968 bit COMMAND_PHASE 0x10 969 bit MSG_IN_PHASE 0x08 970 bit MSG_OUT_PHASE 0x04 971 bit DATA_IN_PHASE 0x02 972 bit DATA_OUT_PHASE 0x01 973 mask DATA_PHASE_MASK 0x03 974} 975 976/* 977 * Special Function 978 */ 979register SFUNCT { 980 address 0x09f 981 access_mode RW 982 bit ALT_MODE 0x80 983} 984 985/* 986 * SCB Definition (p. 5-4) 987 */ 988scb { 989 address 0x0a0 990 SCB_CDB_PTR { 991 size 4 992 alias SCB_RESIDUAL_DATACNT 993 alias SCB_CDB_STORE 994 alias SCB_TARGET_INFO 995 } 996 SCB_RESIDUAL_SGPTR { 997 size 4 998 } 999 SCB_SCSI_STATUS { 1000 size 1 1001 } 1002 SCB_CDB_STORE_PAD { 1003 size 3 1004 } 1005 SCB_DATAPTR { 1006 size 4 1007 } 1008 SCB_DATACNT { 1009 /* 1010 * The last byte is really the high address bits for 1011 * the data address. 1012 */ 1013 size 4 1014 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 1015 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1016 } 1017 SCB_SGPTR { 1018 size 4 1019 bit SG_RESID_VALID 0x04 /* In the first byte */ 1020 bit SG_FULL_RESID 0x02 /* In the first byte */ 1021 bit SG_LIST_NULL 0x01 /* In the first byte */ 1022 } 1023 SCB_CONTROL { 1024 size 1 1025 bit TARGET_SCB 0x80 1026 bit DISCENB 0x40 1027 bit TAG_ENB 0x20 1028 bit MK_MESSAGE 0x10 1029 bit ULTRAENB 0x08 1030 bit DISCONNECTED 0x04 1031 mask SCB_TAG_TYPE 0x03 1032 } 1033 SCB_SCSIID { 1034 size 1 1035 bit TWIN_CHNLB 0x80 1036 mask TWIN_TID 0x70 1037 mask TID 0xf0 1038 mask OID 0x0f 1039 } 1040 SCB_LUN { 1041 mask LID 0xff 1042 size 1 1043 } 1044 SCB_TAG { 1045 size 1 1046 } 1047 SCB_CDB_LEN { 1048 size 1 1049 } 1050 SCB_SCSIRATE { 1051 size 1 1052 } 1053 SCB_SCSIOFFSET { 1054 size 1 1055 } 1056 SCB_NEXT { 1057 size 1 1058 } 1059 SCB_64_SPARE { 1060 size 16 1061 } 1062 SCB_64_BTT { 1063 size 16 1064 } 1065} 1066 1067const SCB_UPLOAD_SIZE 32 1068const SCB_DOWNLOAD_SIZE 32 1069const SCB_DOWNLOAD_SIZE_64 48 1070 1071const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1072 1073/* --------------------- AHA-2840-only definitions -------------------- */ 1074 1075register SEECTL_2840 { 1076 address 0x0c0 1077 access_mode RW 1078 bit CS_2840 0x04 1079 bit CK_2840 0x02 1080 bit DO_2840 0x01 1081} 1082 1083register STATUS_2840 { 1084 address 0x0c1 1085 access_mode RW 1086 bit EEPROM_TF 0x80 1087 mask BIOS_SEL 0x60 1088 mask ADSEL 0x1e 1089 bit DI_2840 0x01 1090} 1091 1092/* --------------------- AIC-7870-only definitions -------------------- */ 1093 1094register CCHADDR { 1095 address 0x0E0 1096 size 8 1097} 1098 1099register CCHCNT { 1100 address 0x0E8 1101} 1102 1103register CCSGRAM { 1104 address 0x0E9 1105} 1106 1107register CCSGADDR { 1108 address 0x0EA 1109} 1110 1111register CCSGCTL { 1112 address 0x0EB 1113 bit CCSGDONE 0x80 1114 bit CCSGEN 0x08 1115 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1116 bit CCSGRESET 0x01 1117} 1118 1119register CCSCBCNT { 1120 address 0xEF 1121} 1122 1123register CCSCBCTL { 1124 address 0x0EE 1125 bit CCSCBDONE 0x80 1126 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1127 bit CCARREN 0x10 1128 bit CCSCBEN 0x08 1129 bit CCSCBDIR 0x04 1130 bit CCSCBRESET 0x01 1131} 1132 1133register CCSCBADDR { 1134 address 0x0ED 1135} 1136 1137register CCSCBRAM { 1138 address 0xEC 1139} 1140 1141/* 1142 * SCB bank address (7895/7896/97 only) 1143 */ 1144register SCBBADDR { 1145 address 0x0F0 1146 access_mode RW 1147} 1148 1149register CCSCBPTR { 1150 address 0x0F1 1151} 1152 1153register HNSCB_QOFF { 1154 address 0x0F4 1155} 1156 1157register SNSCB_QOFF { 1158 address 0x0F6 1159} 1160 1161register SDSCB_QOFF { 1162 address 0x0F8 1163} 1164 1165register QOFF_CTLSTA { 1166 address 0x0FA 1167 bit SCB_AVAIL 0x40 1168 bit SNSCB_ROLLOVER 0x20 1169 bit SDSCB_ROLLOVER 0x10 1170 mask SCB_QSIZE 0x07 1171 mask SCB_QSIZE_256 0x06 1172} 1173 1174register DFF_THRSH { 1175 address 0x0FB 1176 mask WR_DFTHRSH 0x70 1177 mask RD_DFTHRSH 0x07 1178 mask RD_DFTHRSH_MIN 0x00 1179 mask RD_DFTHRSH_25 0x01 1180 mask RD_DFTHRSH_50 0x02 1181 mask RD_DFTHRSH_63 0x03 1182 mask RD_DFTHRSH_75 0x04 1183 mask RD_DFTHRSH_85 0x05 1184 mask RD_DFTHRSH_90 0x06 1185 mask RD_DFTHRSH_MAX 0x07 1186 mask WR_DFTHRSH_MIN 0x00 1187 mask WR_DFTHRSH_25 0x10 1188 mask WR_DFTHRSH_50 0x20 1189 mask WR_DFTHRSH_63 0x30 1190 mask WR_DFTHRSH_75 0x40 1191 mask WR_DFTHRSH_85 0x50 1192 mask WR_DFTHRSH_90 0x60 1193 mask WR_DFTHRSH_MAX 0x70 1194} 1195 1196register SG_CACHE_PRE { 1197 access_mode WO 1198 address 0x0fc 1199 mask SG_ADDR_MASK 0xf8 1200 bit ODD_SEG 0x04 1201 bit LAST_SEG 0x02 1202 bit LAST_SEG_DONE 0x01 1203} 1204 1205register SG_CACHE_SHADOW { 1206 access_mode RO 1207 address 0x0fc 1208 mask SG_ADDR_MASK 0xf8 1209 bit ODD_SEG 0x04 1210 bit LAST_SEG 0x02 1211 bit LAST_SEG_DONE 0x01 1212} 1213/* ---------------------- Scratch RAM Offsets ------------------------- */ 1214/* These offsets are either to values that are initialized by the board's 1215 * BIOS or are specified by the sequencer code. 1216 * 1217 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1218 * device information, 32-33 and 5a-5f as well. As it turns out, the 1219 * BIOS trashes 20-2f, writing the synchronous negotiation results 1220 * on top of the BIOS values, so we re-use those for our per-target 1221 * scratchspace (actually a value that can be copied directly into 1222 * SCSIRATE). The kernel driver will enable synchronous negotiation 1223 * for all targets that have a value other than 0 in the lower four 1224 * bits of the target scratch space. This should work regardless of 1225 * whether the bios has been installed. 1226 */ 1227 1228scratch_ram { 1229 address 0x020 1230 1231 /* 1232 * 1 byte per target starting at this address for configuration values 1233 */ 1234 BUSY_TARGETS { 1235 alias TARG_SCSIRATE 1236 size 16 1237 } 1238 /* 1239 * Bit vector of targets that have ULTRA enabled as set by 1240 * the BIOS. The Sequencer relies on a per-SCB field to 1241 * control whether to enable Ultra transfers or not. During 1242 * initialization, we read this field and reuse it for 2 1243 * entries in the busy target table. 1244 */ 1245 ULTRA_ENB { 1246 alias CMDSIZE_TABLE 1247 size 2 1248 } 1249 /* 1250 * Bit vector of targets that have disconnection disabled as set by 1251 * the BIOS. The Sequencer relies in a per-SCB field to control the 1252 * disconnect priveldge. During initialization, we read this field 1253 * and reuse it for 2 entries in the busy target table. 1254 */ 1255 DISC_DSB { 1256 size 2 1257 } 1258 CMDSIZE_TABLE_TAIL { 1259 size 4 1260 } 1261 /* 1262 * Partial transfer past cacheline end to be 1263 * transferred using an extra S/G. 1264 */ 1265 MWI_RESIDUAL { 1266 size 1 1267 } 1268 /* 1269 * SCBID of the next SCB to be started by the controller. 1270 */ 1271 NEXT_QUEUED_SCB { 1272 size 1 1273 } 1274 /* 1275 * Single byte buffer used to designate the type or message 1276 * to send to a target. 1277 */ 1278 MSG_OUT { 1279 size 1 1280 } 1281 /* Parameters for DMA Logic */ 1282 DMAPARAMS { 1283 size 1 1284 bit PRELOADEN 0x80 1285 bit WIDEODD 0x40 1286 bit SCSIEN 0x20 1287 bit SDMAEN 0x10 1288 bit SDMAENACK 0x10 1289 bit HDMAEN 0x08 1290 bit HDMAENACK 0x08 1291 bit DIRECTION 0x04 1292 bit FIFOFLUSH 0x02 1293 bit FIFORESET 0x01 1294 } 1295 SEQ_FLAGS { 1296 size 1 1297 bit IDENTIFY_SEEN 0x80 1298 bit TARGET_CMD_IS_TAGGED 0x40 1299 bit DPHASE 0x20 1300 /* Target flags */ 1301 bit TARG_CMD_PENDING 0x10 1302 bit CMDPHASE_PENDING 0x08 1303 bit DPHASE_PENDING 0x04 1304 bit SPHASE_PENDING 0x02 1305 bit NO_DISCONNECT 0x01 1306 } 1307 /* 1308 * Temporary storage for the 1309 * target/channel/lun of a 1310 * reconnecting target 1311 */ 1312 SAVED_SCSIID { 1313 size 1 1314 } 1315 SAVED_LUN { 1316 size 1 1317 } 1318 /* 1319 * The last bus phase as seen by the sequencer. 1320 */ 1321 LASTPHASE { 1322 size 1 1323 bit CDI 0x80 1324 bit IOI 0x40 1325 bit MSGI 0x20 1326 mask PHASE_MASK CDI|IOI|MSGI 1327 mask P_DATAOUT 0x00 1328 mask P_DATAIN IOI 1329 mask P_COMMAND CDI 1330 mask P_MESGOUT CDI|MSGI 1331 mask P_STATUS CDI|IOI 1332 mask P_MESGIN CDI|IOI|MSGI 1333 mask P_BUSFREE 0x01 1334 } 1335 /* 1336 * head of list of SCBs awaiting 1337 * selection 1338 */ 1339 WAITING_SCBH { 1340 size 1 1341 } 1342 /* 1343 * head of list of SCBs that are 1344 * disconnected. Used for SCB 1345 * paging. 1346 */ 1347 DISCONNECTED_SCBH { 1348 size 1 1349 } 1350 /* 1351 * head of list of SCBs that are 1352 * not in use. Used for SCB paging. 1353 */ 1354 FREE_SCBH { 1355 size 1 1356 } 1357 /* 1358 * head of list of SCBs that have 1359 * completed but have not been 1360 * put into the qoutfifo. 1361 */ 1362 COMPLETE_SCBH { 1363 size 1 1364 } 1365 /* 1366 * Address of the hardware scb array in the host. 1367 */ 1368 HSCB_ADDR { 1369 size 4 1370 } 1371 /* 1372 * Base address of our shared data with the kernel driver in host 1373 * memory. This includes the qoutfifo and target mode 1374 * incoming command queue. 1375 */ 1376 SHARED_DATA_ADDR { 1377 size 4 1378 } 1379 KERNEL_QINPOS { 1380 size 1 1381 } 1382 QINPOS { 1383 size 1 1384 } 1385 QOUTPOS { 1386 size 1 1387 } 1388 /* 1389 * Kernel and sequencer offsets into the queue of 1390 * incoming target mode command descriptors. The 1391 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1392 */ 1393 KERNEL_TQINPOS { 1394 size 1 1395 } 1396 TQINPOS { 1397 size 1 1398 } 1399 ARG_1 { 1400 size 1 1401 mask SEND_MSG 0x80 1402 mask SEND_SENSE 0x40 1403 mask SEND_REJ 0x20 1404 mask MSGOUT_PHASEMIS 0x10 1405 mask EXIT_MSG_LOOP 0x08 1406 mask CONT_MSG_LOOP 0x04 1407 mask CONT_TARG_SESSION 0x02 1408 alias RETURN_1 1409 } 1410 ARG_2 { 1411 size 1 1412 alias RETURN_2 1413 } 1414 1415 /* 1416 * Snapshot of MSG_OUT taken after each message is sent. 1417 */ 1418 LAST_MSG { 1419 size 1 1420 } 1421 1422 /* 1423 * Sequences the kernel driver has okayed for us. This allows 1424 * the driver to do things like prevent initiator or target 1425 * operations. 1426 */ 1427 SCSISEQ_TEMPLATE { 1428 size 1 1429 bit ENSELO 0x40 1430 bit ENSELI 0x20 1431 bit ENRSELI 0x10 1432 bit ENAUTOATNO 0x08 1433 bit ENAUTOATNI 0x04 1434 bit ENAUTOATNP 0x02 1435 } 1436 1437 /* 1438 * Track whether the transfer byte count for 1439 * the current data phase is odd. 1440 */ 1441 DATA_COUNT_ODD { 1442 size 1 1443 } 1444 1445 /* 1446 * The initiator specified tag for this target mode transaction. 1447 */ 1448 INITIATOR_TAG { 1449 size 1 1450 } 1451 1452 SEQ_FLAGS2 { 1453 size 1 1454 bit SCB_DMA 0x01 1455 } 1456 /* 1457 * These are reserved registers in the card's scratch ram. Some of 1458 * the values are specified in the AHA2742 technical reference manual 1459 * and are initialized by the BIOS at boot time. 1460 */ 1461 SCSICONF { 1462 address 0x05a 1463 size 1 1464 bit TERM_ENB 0x80 1465 bit RESET_SCSI 0x40 1466 bit ENSPCHK 0x20 1467 mask HSCSIID 0x07 /* our SCSI ID */ 1468 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1469 } 1470 INTDEF { 1471 address 0x05c 1472 size 1 1473 bit EDGE_TRIG 0x80 1474 mask VECTOR 0x0f 1475 } 1476 HOSTCONF { 1477 address 0x05d 1478 size 1 1479 } 1480 HA_274_BIOSCTRL { 1481 address 0x05f 1482 size 1 1483 mask BIOSMODE 0x30 1484 mask BIOSDISABLED 0x30 1485 bit CHANNEL_B_PRIMARY 0x08 1486 } 1487 /* 1488 * Per target SCSI offset values for Ultra2 controllers. 1489 */ 1490 TARG_OFFSET { 1491 address 0x070 1492 size 16 1493 } 1494} 1495 1496const TID_SHIFT 4 1497const SCB_LIST_NULL 0xff 1498const TARGET_CMD_CMPLT 0xfe 1499 1500const CCSGADDR_MAX 0x80 1501const CCSGRAM_MAXSEGS 16 1502 1503/* WDTR Message values */ 1504const BUS_8_BIT 0x00 1505const BUS_16_BIT 0x01 1506const BUS_32_BIT 0x02 1507 1508/* Offset maximums */ 1509const MAX_OFFSET_8BIT 0x0f 1510const MAX_OFFSET_16BIT 0x08 1511const MAX_OFFSET_ULTRA2 0x7f 1512const HOST_MSG 0xff 1513 1514/* Target mode command processing constants */ 1515const CMD_GROUP_CODE_SHIFT 0x05 1516 1517const STATUS_BUSY 0x08 1518const STATUS_QUEUE_FULL 0x28 1519const SCB_TARGET_PHASES 0 1520const SCB_TARGET_DATA_DIR 1 1521const SCB_TARGET_STATUS 2 1522const SCB_INITIATOR_TAG 3 1523const TARGET_DATA_IN 1 1524 1525/* 1526 * Downloaded (kernel inserted) constants 1527 */ 1528/* Offsets into the SCBID array where different data is stored */ 1529const QOUTFIFO_OFFSET download 1530const QINFIFO_OFFSET download 1531const CACHESIZE_MASK download 1532const INVERTED_CACHESIZE_MASK download 1533const SG_PREFETCH_CNT download 1534const SG_PREFETCH_ALIGN_MASK download 1535const SG_PREFETCH_ADDR_MASK download 1536