1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-1999 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * the GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34/* 35 * This file is processed by the aic7xxx_asm utility for use in assembling 36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 37 * a C header file for use in the kernel portion of the Aic7xxx driver. 38 * 39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 40 * Adaptec's Technical Documents Department 1-800-934-2766 41 */ 42 43/* 44 * SCSI Sequence Control (p. 3-11). 45 * Each bit, when set starts a specific SCSI sequence on the bus 46 */ 47register SCSISEQ { 48 address 0x000 49 access_mode RW 50 bit TEMODE 0x80 51 bit ENSELO 0x40 52 bit ENSELI 0x20 53 bit ENRSELI 0x10 54 bit ENAUTOATNO 0x08 55 bit ENAUTOATNI 0x04 56 bit ENAUTOATNP 0x02 57 bit SCSIRSTO 0x01 58} 59 60/* 61 * SCSI Transfer Control 0 Register (pp. 3-13). 62 * Controls the SCSI module data path. 63 */ 64register SXFRCTL0 { 65 address 0x001 66 access_mode RW 67 bit DFON 0x80 68 bit DFPEXP 0x40 69 bit FAST20 0x20 70 bit CLRSTCNT 0x10 71 bit SPIOEN 0x08 72 bit SCAMEN 0x04 73 bit CLRCHN 0x02 74} 75 76/* 77 * SCSI Transfer Control 1 Register (pp. 3-14,15). 78 * Controls the SCSI module data path. 79 */ 80register SXFRCTL1 { 81 address 0x002 82 access_mode RW 83 bit BITBUCKET 0x80 84 bit SWRAPEN 0x40 85 bit ENSPCHK 0x20 86 mask STIMESEL 0x18 87 bit ENSTIMER 0x04 88 bit ACTNEGEN 0x02 89 bit STPWEN 0x01 /* Powered Termination */ 90} 91 92/* 93 * SCSI Control Signal Read Register (p. 3-15). 94 * Reads the actual state of the SCSI bus pins 95 */ 96register SCSISIGI { 97 address 0x003 98 access_mode RO 99 bit CDI 0x80 100 bit IOI 0x40 101 bit MSGI 0x20 102 bit ATNI 0x10 103 bit SELI 0x08 104 bit BSYI 0x04 105 bit REQI 0x02 106 bit ACKI 0x01 107/* 108 * Possible phases in SCSISIGI 109 */ 110 mask PHASE_MASK CDI|IOI|MSGI 111 mask P_DATAOUT 0x00 112 mask P_DATAIN IOI 113 mask P_COMMAND CDI 114 mask P_MESGOUT CDI|MSGI 115 mask P_STATUS CDI|IOI 116 mask P_MESGIN CDI|IOI|MSGI 117} 118 119/* 120 * SCSI Control Signal Write Register (p. 3-16). 121 * Writing to this register modifies the control signals on the bus. Only 122 * those signals that are allowed in the current mode (Initiator/Target) are 123 * asserted. 124 */ 125register SCSISIGO { 126 address 0x003 127 access_mode WO 128 bit CDO 0x80 129 bit IOO 0x40 130 bit MSGO 0x20 131 bit ATNO 0x10 132 bit SELO 0x08 133 bit BSYO 0x04 134 bit REQO 0x02 135 bit ACKO 0x01 136/* 137 * Possible phases to write into SCSISIG0 138 */ 139 mask PHASE_MASK CDI|IOI|MSGI 140 mask P_DATAOUT 0x00 141 mask P_DATAIN IOI 142 mask P_COMMAND CDI 143 mask P_MESGOUT CDI|MSGI 144 mask P_STATUS CDI|IOI 145 mask P_MESGIN CDI|IOI|MSGI 146} 147 148/* 149 * SCSI Rate Control (p. 3-17). 150 * Contents of this register determine the Synchronous SCSI data transfer 151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 153 * greater than 0 enables synchronous transfers. 154 */ 155register SCSIRATE { 156 address 0x004 157 access_mode RW 158 bit WIDEXFER 0x80 /* Wide transfer control */ 159 mask SXFR 0x70 /* Sync transfer rate */ 160 mask SXFR_ULTRA2 0x7f /* Sync transfer rate */ 161 mask SOFS 0x0f /* Sync offset */ 162} 163 164/* 165 * SCSI ID (p. 3-18). 166 * Contains the ID of the board and the current target on the 167 * selected channel. 168 */ 169register SCSIID { 170 address 0x005 171 access_mode RW 172 mask TID 0xf0 /* Target ID mask */ 173 mask OID 0x0f /* Our ID mask */ 174 /* 175 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 176 * The aic7890/91 allow an offset of up to 127 transfers in both wide 177 * and narrow mode. 178 */ 179 alias SCSIOFFSET 180 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 181} 182 183/* 184 * SCSI Latched Data (p. 3-19). 185 * Read/Write latches used to transfer data on the SCSI bus during 186 * Automatic or Manual PIO mode. SCSIDATH can be used for the 187 * upper byte of a 16bit wide asynchronouse data phase transfer. 188 */ 189register SCSIDATL { 190 address 0x006 191 access_mode RW 192} 193 194register SCSIDATH { 195 address 0x007 196 access_mode RW 197} 198 199/* 200 * SCSI Transfer Count (pp. 3-19,20) 201 * These registers count down the number of bytes transferred 202 * across the SCSI bus. The counter is decremented only once 203 * the data has been safely transferred. SDONE in SSTAT0 is 204 * set when STCNT goes to 0 205 */ 206register STCNT { 207 address 0x008 208 size 3 209 access_mode RW 210} 211 212/* 213 * Clear SCSI Interrupt 0 (p. 3-20) 214 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 215 */ 216register CLRSINT0 { 217 address 0x00b 218 access_mode WO 219 bit CLRSELDO 0x40 220 bit CLRSELDI 0x20 221 bit CLRSELINGO 0x10 222 bit CLRSWRAP 0x08 223 bit CLRSPIORDY 0x02 224} 225 226/* 227 * SCSI Status 0 (p. 3-21) 228 * Contains one set of SCSI Interrupt codes 229 * These are most likely of interest to the sequencer 230 */ 231register SSTAT0 { 232 address 0x00b 233 access_mode RO 234 bit TARGET 0x80 /* Board acting as target */ 235 bit SELDO 0x40 /* Selection Done */ 236 bit SELDI 0x20 /* Board has been selected */ 237 bit SELINGO 0x10 /* Selection In Progress */ 238 bit SWRAP 0x08 /* 24bit counter wrap */ 239 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 240 bit SDONE 0x04 /* STCNT = 0x000000 */ 241 bit SPIORDY 0x02 /* SCSI PIO Ready */ 242 bit DMADONE 0x01 /* DMA transfer completed */ 243} 244 245/* 246 * Clear SCSI Interrupt 1 (p. 3-23) 247 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 248 */ 249register CLRSINT1 { 250 address 0x00c 251 access_mode WO 252 bit CLRSELTIMEO 0x80 253 bit CLRATNO 0x40 254 bit CLRSCSIRSTI 0x20 255 bit CLRBUSFREE 0x08 256 bit CLRSCSIPERR 0x04 257 bit CLRPHASECHG 0x02 258 bit CLRREQINIT 0x01 259} 260 261/* 262 * SCSI Status 1 (p. 3-24) 263 */ 264register SSTAT1 { 265 address 0x00c 266 access_mode RO 267 bit SELTO 0x80 268 bit ATNTARG 0x40 269 bit SCSIRSTI 0x20 270 bit PHASEMIS 0x10 271 bit BUSFREE 0x08 272 bit SCSIPERR 0x04 273 bit PHASECHG 0x02 274 bit REQINIT 0x01 275} 276 277/* 278 * SCSI Status 2 (pp. 3-25,26) 279 */ 280register SSTAT2 { 281 address 0x00d 282 access_mode RO 283 bit OVERRUN 0x80 284 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 285 mask SFCNT 0x1f 286} 287 288/* 289 * SCSI Status 3 (p. 3-26) 290 */ 291register SSTAT3 { 292 address 0x00e 293 access_mode RO 294 mask SCSICNT 0xf0 295 mask OFFCNT 0x0f 296} 297 298/* 299 * SCSI ID for the aic7890/91 chips 300 */ 301register SCSIID_ULTRA2 { 302 address 0x00f 303 access_mode RW 304 mask TID 0xf0 /* Target ID mask */ 305 mask OID 0x0f /* Our ID mask */ 306} 307 308/* 309 * SCSI Interrupt Mode 1 (p. 3-28) 310 * Setting any bit will enable the corresponding function 311 * in SIMODE0 to interrupt via the IRQ pin. 312 */ 313register SIMODE0 { 314 address 0x010 315 access_mode RW 316 bit ENSELDO 0x40 317 bit ENSELDI 0x20 318 bit ENSELINGO 0x10 319 bit ENSWRAP 0x08 320 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 321 bit ENSDONE 0x04 322 bit ENSPIORDY 0x02 323 bit ENDMADONE 0x01 324} 325 326/* 327 * SCSI Interrupt Mode 1 (pp. 3-28,29) 328 * Setting any bit will enable the corresponding function 329 * in SIMODE1 to interrupt via the IRQ pin. 330 */ 331register SIMODE1 { 332 address 0x011 333 access_mode RW 334 bit ENSELTIMO 0x80 335 bit ENATNTARG 0x40 336 bit ENSCSIRST 0x20 337 bit ENPHASEMIS 0x10 338 bit ENBUSFREE 0x08 339 bit ENSCSIPERR 0x04 340 bit ENPHASECHG 0x02 341 bit ENREQINIT 0x01 342} 343 344/* 345 * SCSI Data Bus (High) (p. 3-29) 346 * This register reads data on the SCSI Data bus directly. 347 */ 348register SCSIBUSL { 349 address 0x012 350 access_mode RO 351} 352 353register SCSIBUSH { 354 address 0x013 355 access_mode RO 356} 357 358/* 359 * SCSI/Host Address (p. 3-30) 360 * These registers hold the host address for the byte about to be 361 * transferred on the SCSI bus. They are counted up in the same 362 * manner as STCNT is counted down. SHADDR should always be used 363 * to determine the address of the last byte transferred since HADDR 364 * can be skewed by write ahead. 365 */ 366register SHADDR { 367 address 0x014 368 size 4 369 access_mode RO 370} 371 372/* 373 * Selection Timeout Timer (p. 3-30) 374 */ 375register SELTIMER { 376 address 0x018 377 access_mode RW 378 bit STAGE6 0x20 379 bit STAGE5 0x10 380 bit STAGE4 0x08 381 bit STAGE3 0x04 382 bit STAGE2 0x02 383 bit STAGE1 0x01 384 alias TARGIDIN 385} 386 387/* 388 * Selection/Reselection ID (p. 3-31) 389 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 390 * device did not set its own ID. 391 */ 392register SELID { 393 address 0x019 394 access_mode RW 395 mask SELID_MASK 0xf0 396 bit ONEBIT 0x08 397} 398 399/* 400 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 401 */ 402register TARGID { 403 address 0x01b 404 size 2 405 access_mode RW 406} 407 408/* 409 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 410 * Indicates if external logic has been attached to the chip to 411 * perform the tasks of accessing a serial eeprom, testing termination 412 * strength, and performing cable detection. On the aic7860, most of 413 * these features are handled on chip, but on the aic7855 an attached 414 * aic3800 does the grunt work. 415 */ 416register SPIOCAP { 417 address 0x01b 418 access_mode RW 419 bit SOFT1 0x80 420 bit SOFT0 0x40 421 bit SOFTCMDEN 0x20 422 bit HAS_BRDCTL 0x10 /* External Board control */ 423 bit SEEPROM 0x08 /* External serial eeprom logic */ 424 bit EEPROM 0x04 /* Writable external BIOS ROM */ 425 bit ROM 0x02 /* Logic for accessing external ROM */ 426 bit SSPIOCPS 0x01 /* Termination and cable detection */ 427} 428 429register BRDCTL { 430 address 0x01d 431 bit BRDDAT7 0x80 432 bit BRDDAT6 0x40 433 bit BRDDAT5 0x20 434 bit BRDSTB 0x10 435 bit BRDCS 0x08 436 bit BRDRW 0x04 437 bit BRDCTL1 0x02 438 bit BRDCTL0 0x01 439 /* 7890 Definitions */ 440 bit BRDDAT4 0x10 441 bit BRDDAT3 0x08 442 bit BRDDAT2 0x04 443 bit BRDRW_ULTRA2 0x02 444 bit BRDSTB_ULTRA2 0x01 445} 446 447/* 448 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 449 * Controls the reading and writing of an external serial 1-bit 450 * EEPROM Device. In order to access the serial EEPROM, you must 451 * first set the SEEMS bit that generates a request to the memory 452 * port for access to the serial EEPROM device. When the memory 453 * port is not busy servicing another request, it reconfigures 454 * to allow access to the serial EEPROM. When this happens, SEERDY 455 * gets set high to verify that the memory port access has been 456 * granted. 457 * 458 * After successful arbitration for the memory port, the SEECS bit of 459 * the SEECTL register is connected to the chip select. The SEECK, 460 * SEEDO, and SEEDI are connected to the clock, data out, and data in 461 * lines respectively. The SEERDY bit of SEECTL is useful in that it 462 * gives us an 800 nsec timer. After a write to the SEECTL register, 463 * the SEERDY goes high 800 nsec later. The one exception to this is 464 * when we first request access to the memory port. The SEERDY goes 465 * high to signify that access has been granted and, for this case, has 466 * no implied timing. 467 * 468 * See 93cx6.c for detailed information on the protocol necessary to 469 * read the serial EEPROM. 470 */ 471register SEECTL { 472 address 0x01e 473 bit EXTARBACK 0x80 474 bit EXTARBREQ 0x40 475 bit SEEMS 0x20 476 bit SEERDY 0x10 477 bit SEECS 0x08 478 bit SEECK 0x04 479 bit SEEDO 0x02 480 bit SEEDI 0x01 481} 482/* 483 * SCSI Block Control (p. 3-32) 484 * Controls Bus type and channel selection. In a twin channel configuration 485 * addresses 0x00-0x1e are gated to the appropriate channel based on this 486 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 487 * on a wide bus. 488 */ 489register SBLKCTL { 490 address 0x01f 491 access_mode RW 492 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 493 bit DIAGLEDON 0x40 /* Aic78X0 only */ 494 bit AUTOFLUSHDIS 0x20 495 bit SELBUSB 0x08 496 bit ENAB40 0x08 /* LVD transceiver active */ 497 bit ENAB20 0x04 /* SE/HVD transceiver active */ 498 bit SELWIDE 0x02 499 bit XCVR 0x01 /* External transceiver active */ 500} 501 502/* 503 * Sequencer Control (p. 3-33) 504 * Error detection mode and speed configuration 505 */ 506register SEQCTL { 507 address 0x060 508 access_mode RW 509 bit PERRORDIS 0x80 510 bit PAUSEDIS 0x40 511 bit FAILDIS 0x20 512 bit FASTMODE 0x10 513 bit BRKADRINTEN 0x08 514 bit STEP 0x04 515 bit SEQRESET 0x02 516 bit LOADRAM 0x01 517} 518 519/* 520 * Sequencer RAM Data (p. 3-34) 521 * Single byte window into the Scratch Ram area starting at the address 522 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 523 * four bytes in succession. The SEQADDRs will increment after the most 524 * significant byte is written 525 */ 526register SEQRAM { 527 address 0x061 528 access_mode RW 529} 530 531/* 532 * Sequencer Address Registers (p. 3-35) 533 * Only the first bit of SEQADDR1 holds addressing information 534 */ 535register SEQADDR0 { 536 address 0x062 537 access_mode RW 538} 539 540register SEQADDR1 { 541 address 0x063 542 access_mode RW 543 mask SEQADDR1_MASK 0x01 544} 545 546/* 547 * Accumulator 548 * We cheat by passing arguments in the Accumulator up to the kernel driver 549 */ 550register ACCUM { 551 address 0x064 552 access_mode RW 553 accumulator 554} 555 556register SINDEX { 557 address 0x065 558 access_mode RW 559 sindex 560} 561 562register DINDEX { 563 address 0x066 564 access_mode RW 565} 566 567register ALLONES { 568 address 0x069 569 access_mode RO 570 allones 571} 572 573register ALLZEROS { 574 address 0x06a 575 access_mode RO 576 allzeros 577} 578 579register NONE { 580 address 0x06a 581 access_mode WO 582 none 583} 584 585register FLAGS { 586 address 0x06b 587 access_mode RO 588 bit ZERO 0x02 589 bit CARRY 0x01 590} 591 592register SINDIR { 593 address 0x06c 594 access_mode RO 595} 596 597register DINDIR { 598 address 0x06d 599 access_mode WO 600} 601 602register FUNCTION1 { 603 address 0x06e 604 access_mode RW 605} 606 607register STACK { 608 address 0x06f 609 access_mode RO 610} 611 612/* 613 * Board Control (p. 3-43) 614 */ 615register BCTL { 616 address 0x084 617 access_mode RW 618 bit ACE 0x08 619 bit ENABLE 0x01 620} 621 622/* 623 * On the aic78X0 chips, Board Control is replaced by the DSCommand 624 * register (p. 4-64) 625 */ 626register DSCOMMAND0 { 627 address 0x084 628 access_mode RW 629 bit CACHETHEN 0x80 /* Cache Threshold enable */ 630 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 631 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 632 bit EXTREQLCK 0x10 /* External Request Lock */ 633 /* aic7890/91/96/97 only */ 634 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 635 bit RAMPS 0x04 /* External SCB RAM Present */ 636 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 637 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 638} 639 640/* 641 * Bus On/Off Time (p. 3-44) 642 */ 643register BUSTIME { 644 address 0x085 645 access_mode RW 646 mask BOFF 0xf0 647 mask BON 0x0f 648} 649 650/* 651 * Bus Speed (p. 3-45) aic7770 only 652 */ 653register BUSSPD { 654 address 0x086 655 access_mode RW 656 mask DFTHRSH 0xc0 657 mask STBOFF 0x38 658 mask STBON 0x07 659 mask DFTHRSH_100 0xc0 660} 661 662/* aic7850/55/60/70/80/95 only */ 663register DSPCISTATUS { 664 address 0x086 665 mask DFTHRSH_100 0xc0 666} 667 668/* aic7890/91/96/97 only */ 669register HS_MAILBOX { 670 address 0x086 671 mask HOST_MAILBOX 0xF0 672 mask SEQ_MAILBOX 0x0F 673} 674 675const HOST_MAILBOX_SHIFT 4 676const SEQ_MAILBOX_SHIFT 0 677 678/* 679 * Host Control (p. 3-47) R/W 680 * Overall host control of the device. 681 */ 682register HCNTRL { 683 address 0x087 684 access_mode RW 685 bit POWRDN 0x40 686 bit SWINT 0x10 687 bit IRQMS 0x08 688 bit PAUSE 0x04 689 bit INTEN 0x02 690 bit CHIPRST 0x01 691 bit CHIPRSTACK 0x01 692} 693 694/* 695 * Host Address (p. 3-48) 696 * This register contains the address of the byte about 697 * to be transferred across the host bus. 698 */ 699register HADDR { 700 address 0x088 701 size 4 702 access_mode RW 703} 704 705register HCNT { 706 address 0x08c 707 size 3 708 access_mode RW 709} 710 711/* 712 * SCB Pointer (p. 3-49) 713 * Gate one of the four SCBs into the SCBARRAY window. 714 */ 715register SCBPTR { 716 address 0x090 717 access_mode RW 718} 719 720/* 721 * Interrupt Status (p. 3-50) 722 * Status for system interrupts 723 */ 724register INTSTAT { 725 address 0x091 726 access_mode RW 727 bit BRKADRINT 0x08 728 bit SCSIINT 0x04 729 bit CMDCMPLT 0x02 730 bit SEQINT 0x01 731 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 732 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 733 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 734 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 735 mask ABORT_REQUESTED 0x50|SEQINT /* Reconect of aborted SCB */ 736 mask UPDATE_TMSG_REQ 0x60|SEQINT /* Update TMSG_REQ values */ 737 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 738 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ 739 mask TRACE_POINT 0x90|SEQINT 740 mask HOST_MSG_LOOP 0xa0|SEQINT /* 741 * The bus is ready for the 742 * host to perform another 743 * message transaction. This 744 * mechanism is used for things 745 * like sync/wide negotiation 746 * that require a kernel based 747 * message state engine. 748 */ 749 mask TRACEPOINT 0xd0|SEQINT 750 mask MSGIN_PHASEMIS 0xe0|SEQINT /* 751 * Target changed phase on us 752 * when we were expecting 753 * another msgin byte. 754 */ 755 mask DATA_OVERRUN 0xf0|SEQINT /* 756 * Target attempted to write 757 * beyond the bounds of its 758 * command. 759 */ 760 761 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 762 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 763} 764 765/* 766 * Hard Error (p. 3-53) 767 * Reporting of catastrophic errors. You usually cannot recover from 768 * these without a full board reset. 769 */ 770register ERROR { 771 address 0x092 772 access_mode RO 773 bit CIOPARERR 0x80 /* Ultra2 only */ 774 bit PCIERRSTAT 0x40 /* PCI only */ 775 bit MPARERR 0x20 /* PCI only */ 776 bit DPARERR 0x10 /* PCI only */ 777 bit SQPARERR 0x08 778 bit ILLOPCODE 0x04 779 bit ILLSADDR 0x02 780 bit ILLHADDR 0x01 781} 782 783/* 784 * Clear Interrupt Status (p. 3-52) 785 */ 786register CLRINT { 787 address 0x092 788 access_mode WO 789 bit CLRPARERR 0x10 /* PCI only */ 790 bit CLRBRKADRINT 0x08 791 bit CLRSCSIINT 0x04 792 bit CLRCMDINT 0x02 793 bit CLRSEQINT 0x01 794} 795 796register DFCNTRL { 797 address 0x093 798 access_mode RW 799 bit PRELOADEN 0x80 /* aic7890 only */ 800 bit WIDEODD 0x40 801 bit SCSIEN 0x20 802 bit SDMAEN 0x10 803 bit SDMAENACK 0x10 804 bit HDMAEN 0x08 805 bit HDMAENACK 0x08 806 bit DIRECTION 0x04 807 bit FIFOFLUSH 0x02 808 bit FIFORESET 0x01 809} 810 811register DFSTATUS { 812 address 0x094 813 access_mode RO 814 bit PRELOAD_AVAIL 0x80 815 bit DWORDEMP 0x20 816 bit MREQPEND 0x10 817 bit HDONE 0x08 818 bit DFTHRESH 0x04 819 bit FIFOFULL 0x02 820 bit FIFOEMP 0x01 821} 822 823register DFWADDR { 824 address 0x95 825 access_mode RW 826} 827 828register DFRADDR { 829 address 0x97 830 access_mode RW 831} 832 833register DFDAT { 834 address 0x099 835 access_mode RW 836} 837 838/* 839 * SCB Auto Increment (p. 3-59) 840 * Byte offset into the SCB Array and an optional bit to allow auto 841 * incrementing of the address during download and upload operations 842 */ 843register SCBCNT { 844 address 0x09a 845 access_mode RW 846 bit SCBAUTO 0x80 847 mask SCBCNT_MASK 0x1f 848} 849 850/* 851 * Queue In FIFO (p. 3-60) 852 * Input queue for queued SCBs (commands that the seqencer has yet to start) 853 */ 854register QINFIFO { 855 address 0x09b 856 access_mode RW 857} 858 859/* 860 * Queue In Count (p. 3-60) 861 * Number of queued SCBs 862 */ 863register QINCNT { 864 address 0x09c 865 access_mode RO 866} 867 868/* 869 * Queue Out FIFO (p. 3-61) 870 * Queue of SCBs that have completed and await the host 871 */ 872register QOUTFIFO { 873 address 0x09d 874 access_mode WO 875} 876 877/* 878 * Queue Out Count (p. 3-61) 879 * Number of queued SCBs in the Out FIFO 880 */ 881register QOUTCNT { 882 address 0x09e 883 access_mode RO 884} 885 886/* 887 * Special Function 888 */ 889register SFUNCT { 890 address 0x09f 891 access_mode RW 892} 893 894/* 895 * SCB Definition (p. 5-4) 896 */ 897scb { 898 address 0x0a0 899 SCB_CONTROL { 900 size 1 901 bit TARGET_SCB 0x80 902 bit DISCENB 0x40 903 bit TAG_ENB 0x20 904 bit MK_MESSAGE 0x10 905 bit ULTRAENB 0x08 906 bit DISCONNECTED 0x04 907 mask SCB_TAG_TYPE 0x03 908 } 909 SCB_TCL { 910 size 1 911 bit SELBUSB 0x08 912 mask TID 0xf0 913 mask LID 0x07 914 } 915 SCB_TARGET_STATUS { 916 size 1 917 } 918 SCB_SGCOUNT { 919 size 1 920 } 921 SCB_SGPTR { 922 size 4 923 } 924 SCB_RESID_SGCNT { 925 size 1 926 } 927 SCB_RESID_DCNT { 928 size 3 929 } 930 SCB_DATAPTR { 931 size 4 932 } 933 SCB_DATACNT { 934 /* 935 * Really only 3 bytes, but padded to make 936 * the kernel's job easier. 937 */ 938 size 4 939 } 940 SCB_CMDPTR { 941 alias SCB_TARGET_PHASES 942 bit TARGET_DATA_IN 0x1 /* In the second byte */ 943 size 4 944 } 945 SCB_CMDLEN { 946 alias SCB_INITIATOR_TAG 947 size 1 948 } 949 SCB_TAG { 950 size 1 951 } 952 SCB_NEXT { 953 size 1 954 } 955 SCB_SCSIRATE { 956 size 1 957 } 958 SCB_SCSIOFFSET { 959 size 1 960 } 961 SCB_SPARE { 962 size 3 963 } 964 SCB_CMDSTORE { 965 size 16 966 } 967 SCB_CMDSTORE_BUSADDR { 968 size 4 969 } 970 SCB_64BYTE_SPARE { 971 size 12 972 } 973} 974 975const SCB_32BYTE_SIZE 28 976const SCB_64BYTE_SIZE 48 977 978const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 979 980/* --------------------- AHA-2840-only definitions -------------------- */ 981 982register SEECTL_2840 { 983 address 0x0c0 984 access_mode RW 985 bit CS_2840 0x04 986 bit CK_2840 0x02 987 bit DO_2840 0x01 988} 989 990register STATUS_2840 { 991 address 0x0c1 992 access_mode RW 993 bit EEPROM_TF 0x80 994 mask BIOS_SEL 0x60 995 mask ADSEL 0x1e 996 bit DI_2840 0x01 997} 998 999/* --------------------- AIC-7870-only definitions -------------------- */ 1000 1001register CCHADDR { 1002 address 0x0E0 1003 size 8 1004} 1005 1006register CCHCNT { 1007 address 0x0E8 1008} 1009 1010register CCSGRAM { 1011 address 0x0E9 1012} 1013 1014register CCSGADDR { 1015 address 0x0EA 1016} 1017 1018register CCSGCTL { 1019 address 0x0EB 1020 bit CCSGDONE 0x80 1021 bit CCSGEN 0x08 1022 bit FLAG 0x02 1023 bit CCSGRESET 0x01 1024} 1025 1026register CCSCBCNT { 1027 address 0xEF 1028} 1029 1030register CCSCBCTL { 1031 address 0x0EE 1032 bit CCSCBDONE 0x80 1033 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1034 bit CCARREN 0x10 1035 bit CCSCBEN 0x08 1036 bit CCSCBDIR 0x04 1037 bit CCSCBRESET 0x01 1038} 1039 1040register CCSCBADDR { 1041 address 0x0ED 1042} 1043 1044register CCSCBRAM { 1045 address 0xEC 1046} 1047 1048/* 1049 * SCB bank address (7895/7896/97 only) 1050 */ 1051register SCBBADDR { 1052 address 0x0F0 1053 access_mode RW 1054} 1055 1056register CCSCBPTR { 1057 address 0x0F1 1058} 1059 1060register HNSCB_QOFF { 1061 address 0x0F4 1062} 1063 1064register SNSCB_QOFF { 1065 address 0x0F6 1066} 1067 1068register SDSCB_QOFF { 1069 address 0x0F8 1070} 1071 1072register QOFF_CTLSTA { 1073 address 0x0FA 1074 bit SCB_AVAIL 0x40 1075 bit SNSCB_ROLLOVER 0x20 1076 bit SDSCB_ROLLOVER 0x10 1077 mask SCB_QSIZE 0x07 1078 mask SCB_QSIZE_256 0x06 1079} 1080 1081register DFF_THRSH { 1082 address 0x0FB 1083 mask WR_DFTHRSH 0x70 1084 mask RD_DFTHRSH 0x07 1085 mask RD_DFTHRSH_MIN 0x00 1086 mask RD_DFTHRSH_25 0x01 1087 mask RD_DFTHRSH_50 0x02 1088 mask RD_DFTHRSH_63 0x03 1089 mask RD_DFTHRSH_75 0x04 1090 mask RD_DFTHRSH_85 0x05 1091 mask RD_DFTHRSH_90 0x06 1092 mask RD_DFTHRSH_MAX 0x07 1093 mask WR_DFTHRSH_MIN 0x00 1094 mask WR_DFTHRSH_25 0x10 1095 mask WR_DFTHRSH_50 0x20 1096 mask WR_DFTHRSH_63 0x30 1097 mask WR_DFTHRSH_75 0x40 1098 mask WR_DFTHRSH_85 0x50 1099 mask WR_DFTHRSH_90 0x60 1100 mask WR_DFTHRSH_MAX 0x70 1101} 1102 1103register SG_CACHEPTR { 1104 access_mode RW 1105 address 0x0fc 1106 mask SG_USER_DATA 0xfc 1107 bit LAST_SEG 0x02 1108 bit LAST_SEG_DONE 0x01 1109} 1110 1111/* ---------------------- Scratch RAM Offsets ------------------------- */ 1112/* These offsets are either to values that are initialized by the board's 1113 * BIOS or are specified by the sequencer code. 1114 * 1115 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1116 * device information, 32-33 and 5a-5f as well. As it turns out, the 1117 * BIOS trashes 20-2f, writing the synchronous negotiation results 1118 * on top of the BIOS values, so we re-use those for our per-target 1119 * scratchspace (actually a value that can be copied directly into 1120 * SCSIRATE). The kernel driver will enable synchronous negotiation 1121 * for all targets that have a value other than 0 in the lower four 1122 * bits of the target scratch space. This should work regardless of 1123 * whether the bios has been installed. 1124 */ 1125 1126scratch_ram { 1127 address 0x020 1128 1129 /* 1130 * 1 byte per target starting at this address for configuration values 1131 */ 1132 TARG_SCSIRATE { 1133 alias CMDSIZE_TABLE 1134 size 16 1135 } 1136 /* 1137 * Bit vector of targets that have ULTRA enabled. 1138 */ 1139 ULTRA_ENB { 1140 size 2 1141 } 1142 /* 1143 * Bit vector of targets that have disconnection disabled. 1144 */ 1145 DISC_DSB { 1146 size 2 1147 } 1148 /* 1149 * Single byte buffer used to designate the type or message 1150 * to send to a target. 1151 */ 1152 MSG_OUT { 1153 size 1 1154 } 1155 /* Parameters for DMA Logic */ 1156 DMAPARAMS { 1157 size 1 1158 bit PRELOADEN 0x80 1159 bit WIDEODD 0x40 1160 bit SCSIEN 0x20 1161 bit SDMAEN 0x10 1162 bit SDMAENACK 0x10 1163 bit HDMAEN 0x08 1164 bit HDMAENACK 0x08 1165 bit DIRECTION 0x04 1166 bit FIFOFLUSH 0x02 1167 bit FIFORESET 0x01 1168 } 1169 SEQ_FLAGS { 1170 size 1 1171 bit IDENTIFY_SEEN 0x80 1172 bit SCBPTR_VALID 0x40 1173 bit DPHASE 0x20 1174 /* Target flags */ 1175 bit TARG_CMD_PENDING 0x10 1176 bit CMDPHASE_PENDING 0x08 1177 bit DPHASE_PENDING 0x04 1178 bit SPHASE_PENDING 0x02 1179 bit NO_DISCONNECT 0x01 1180 } 1181 /* 1182 * Temporary storage for the 1183 * target/channel/lun of a 1184 * reconnecting target 1185 */ 1186 SAVED_TCL { 1187 size 1 1188 } 1189 /* Working value of the number of SG segments left */ 1190 SG_COUNT { 1191 size 1 1192 } 1193 /* Working value of SG pointer */ 1194 SG_NEXT { 1195 size 4 1196 } 1197 /* 1198 * The last bus phase as seen by the sequencer. 1199 */ 1200 LASTPHASE { 1201 size 1 1202 bit CDI 0x80 1203 bit IOI 0x40 1204 bit MSGI 0x20 1205 mask PHASE_MASK CDI|IOI|MSGI 1206 mask P_DATAOUT 0x00 1207 mask P_DATAIN IOI 1208 mask P_COMMAND CDI 1209 mask P_MESGOUT CDI|MSGI 1210 mask P_STATUS CDI|IOI 1211 mask P_MESGIN CDI|IOI|MSGI 1212 mask P_BUSFREE 0x01 1213 } 1214 /* 1215 * head of list of SCBs awaiting 1216 * selection 1217 */ 1218 WAITING_SCBH { 1219 size 1 1220 } 1221 /* 1222 * head of list of SCBs that are 1223 * disconnected. Used for SCB 1224 * paging. 1225 */ 1226 DISCONNECTED_SCBH { 1227 size 1 1228 } 1229 /* 1230 * head of list of SCBs that are 1231 * not in use. Used for SCB paging. 1232 */ 1233 FREE_SCBH { 1234 size 1 1235 } 1236 /* 1237 * Address of the hardware scb array in the host. 1238 */ 1239 HSCB_ADDR { 1240 size 4 1241 } 1242 /* 1243 * Address of the 256 byte array storing the SCBID of outstanding 1244 * untagged SCBs indexed by TCL. 1245 */ 1246 SCBID_ADDR { 1247 size 4 1248 } 1249 /* 1250 * Address of the array of command descriptors used to store 1251 * information about incoming selections. 1252 */ 1253 TMODE_CMDADDR { 1254 size 4 1255 } 1256 KERNEL_QINPOS { 1257 size 1 1258 } 1259 QINPOS { 1260 size 1 1261 } 1262 QOUTPOS { 1263 size 1 1264 } 1265 /* 1266 * Kernel and sequencer offsets into the queue of 1267 * incoming target mode command descriptors. The 1268 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1269 */ 1270 KERNEL_TQINPOS { 1271 size 1 1272 } 1273 TQINPOS { 1274 size 1 1275 } 1276 ARG_1 { 1277 size 1 1278 mask SEND_MSG 0x80 1279 mask SEND_SENSE 0x40 1280 mask SEND_REJ 0x20 1281 mask MSGOUT_PHASEMIS 0x10 1282 mask EXIT_MSG_LOOP 0x08 1283 mask CONT_MSG_LOOP 0x04 1284 mask CONT_TARG_SESSION 0x02 1285 alias RETURN_1 1286 } 1287 ARG_2 { 1288 size 1 1289 alias RETURN_2 1290 } 1291 1292 /* 1293 * Snapshot of MSG_OUT taken after each message is sent. 1294 */ 1295 LAST_MSG { 1296 size 1 1297 } 1298 1299 /* 1300 * Number of times we have filled the CCSGRAM with prefetched 1301 * SG elements. 1302 */ 1303 PREFETCH_CNT { 1304 size 1 1305 } 1306 1307 /* 1308 * Interrupt kernel for a message to this target on 1309 * the next transaction. This is usually used for 1310 * negotiation requests. 1311 */ 1312 TARGET_MSG_REQUEST { 1313 size 2 1314 } 1315 1316 /* 1317 * Sequences the kernel driver has okayed for us. This allows 1318 * the driver to do things like prevent initiator or target 1319 * operations. 1320 */ 1321 SCSISEQ_TEMPLATE { 1322 size 1 1323 bit ENSELO 0x40 1324 bit ENSELI 0x20 1325 bit ENRSELI 0x10 1326 bit ENAUTOATNO 0x08 1327 bit ENAUTOATNI 0x04 1328 bit ENAUTOATNP 0x02 1329 } 1330 1331 /* 1332 * Track whether the transfer byte count for 1333 * the current data phase is odd. 1334 */ 1335 DATA_COUNT_ODD { 1336 size 1 1337 } 1338 1339 /* 1340 * The initiator specified tag for this target mode transaction. 1341 */ 1342 INITIATOR_TAG { 1343 size 1 1344 } 1345 1346 /* 1347 * These are reserved registers in the card's scratch ram. Some of 1348 * the values are specified in the AHA2742 technical reference manual 1349 * and are initialized by the BIOS at boot time. 1350 */ 1351 SCSICONF { 1352 address 0x05a 1353 size 1 1354 bit TERM_ENB 0x80 1355 bit RESET_SCSI 0x40 1356 bit ENSPCHK 0x20 1357 mask HSCSIID 0x07 /* our SCSI ID */ 1358 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1359 } 1360 HOSTCONF { 1361 address 0x05d 1362 size 1 1363 } 1364 HA_274_BIOSCTRL { 1365 address 0x05f 1366 size 1 1367 mask BIOSMODE 0x30 1368 mask BIOSDISABLED 0x30 1369 bit CHANNEL_B_PRIMARY 0x08 1370 } 1371 /* 1372 * Per target SCSI offset values for Ultra2 controllers. 1373 */ 1374 TARG_OFFSET { 1375 address 0x070 1376 size 16 1377 } 1378} 1379 1380const SCB_LIST_NULL 0xff 1381const TARGET_CMD_CMPLT 0xfe 1382 1383const CCSGADDR_MAX 0x80 1384const CCSGRAM_MAXSEGS 16 1385 1386/* Offsets into the SCBID array where different data is stored */ 1387const QOUTFIFO_OFFSET 0 1388const QINFIFO_OFFSET 1 1389const UNTAGGEDSCB_OFFSET 2 1390 1391/* WDTR Message values */ 1392const BUS_8_BIT 0x00 1393const BUS_16_BIT 0x01 1394const BUS_32_BIT 0x02 1395 1396/* Offset maximums */ 1397const MAX_OFFSET_8BIT 0x0f 1398const MAX_OFFSET_16BIT 0x08 1399const MAX_OFFSET_ULTRA2 0x7f 1400const HOST_MSG 0xff 1401 1402/* Target mode command processing constants */ 1403const CMD_GROUP_CODE_SHIFT 0x05 1404 1405const TCL_TARGET_SHIFT 4 1406/* The update interval must be a power of 2 */ 1407const TQINFIFO_UPDATE_CNT 32 1408 1409const STATUS_BUSY 0x08 1410const STATUS_QUEUE_FULL 0x28 1411 1412/* 1413 * Downloaded (kernel inserted) constants 1414 */ 1415 1416/* 1417 * Number of command descriptors in the command descriptor array. 1418 * No longer used, but left here as an example for how downloaded 1419 * constantants can be defined. 1420const TMODE_NUMCMDS download 1421 */ 1422