1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-1999 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Where this Software is combined with software released under the terms of 17 * the GNU Public License ("GPL") and the terms of the GPL would require the 18 * combined work to also be released under the terms of the GPL, the terms 19 * and conditions of this License will apply in addition to those of the 20 * GPL with the exception of any terms or conditions of this License that 21 * conflict with, or are expressly prohibited by, the GPL. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38/* 39 * This file is processed by the aic7xxx_asm utility for use in assembling 40 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 41 * a C header file for use in the kernel portion of the Aic7xxx driver. 42 * 43 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 44 * Adaptec's Technical Documents Department 1-800-934-2766 45 */ 46 47/* 48 * SCSI Sequence Control (p. 3-11). 49 * Each bit, when set starts a specific SCSI sequence on the bus 50 */ 51register SCSISEQ { 52 address 0x000 53 access_mode RW 54 bit TEMODE 0x80 55 bit ENSELO 0x40 56 bit ENSELI 0x20 57 bit ENRSELI 0x10 58 bit ENAUTOATNO 0x08 59 bit ENAUTOATNI 0x04 60 bit ENAUTOATNP 0x02 61 bit SCSIRSTO 0x01 62} 63 64/* 65 * SCSI Transfer Control 0 Register (pp. 3-13). 66 * Controls the SCSI module data path. 67 */ 68register SXFRCTL0 { 69 address 0x001 70 access_mode RW 71 bit DFON 0x80 72 bit DFPEXP 0x40 73 bit FAST20 0x20 74 bit CLRSTCNT 0x10 75 bit SPIOEN 0x08 76 bit SCAMEN 0x04 77 bit CLRCHN 0x02 78} 79 80/* 81 * SCSI Transfer Control 1 Register (pp. 3-14,15). 82 * Controls the SCSI module data path. 83 */ 84register SXFRCTL1 { 85 address 0x002 86 access_mode RW 87 bit BITBUCKET 0x80 88 bit SWRAPEN 0x40 89 bit ENSPCHK 0x20 90 mask STIMESEL 0x18 91 bit ENSTIMER 0x04 92 bit ACTNEGEN 0x02 93 bit STPWEN 0x01 /* Powered Termination */ 94} 95 96/* 97 * SCSI Control Signal Read Register (p. 3-15). 98 * Reads the actual state of the SCSI bus pins 99 */ 100register SCSISIGI { 101 address 0x003 102 access_mode RO 103 bit CDI 0x80 104 bit IOI 0x40 105 bit MSGI 0x20 106 bit ATNI 0x10 107 bit SELI 0x08 108 bit BSYI 0x04 109 bit REQI 0x02 110 bit ACKI 0x01 111/* 112 * Possible phases in SCSISIGI 113 */ 114 mask PHASE_MASK CDI|IOI|MSGI 115 mask P_DATAOUT 0x00 116 mask P_DATAIN IOI 117 mask P_COMMAND CDI 118 mask P_MESGOUT CDI|MSGI 119 mask P_STATUS CDI|IOI 120 mask P_MESGIN CDI|IOI|MSGI 121} 122 123/* 124 * SCSI Control Signal Write Register (p. 3-16). 125 * Writing to this register modifies the control signals on the bus. Only 126 * those signals that are allowed in the current mode (Initiator/Target) are 127 * asserted. 128 */ 129register SCSISIGO { 130 address 0x003 131 access_mode WO 132 bit CDO 0x80 133 bit IOO 0x40 134 bit MSGO 0x20 135 bit ATNO 0x10 136 bit SELO 0x08 137 bit BSYO 0x04 138 bit REQO 0x02 139 bit ACKO 0x01 140/* 141 * Possible phases to write into SCSISIG0 142 */ 143 mask PHASE_MASK CDI|IOI|MSGI 144 mask P_DATAOUT 0x00 145 mask P_DATAIN IOI 146 mask P_COMMAND CDI 147 mask P_MESGOUT CDI|MSGI 148 mask P_STATUS CDI|IOI 149 mask P_MESGIN CDI|IOI|MSGI 150} 151 152/* 153 * SCSI Rate Control (p. 3-17). 154 * Contents of this register determine the Synchronous SCSI data transfer 155 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 156 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 157 * greater than 0 enables synchronous transfers. 158 */ 159register SCSIRATE { 160 address 0x004 161 access_mode RW 162 bit WIDEXFER 0x80 /* Wide transfer control */ 163 mask SXFR 0x70 /* Sync transfer rate */ 164 mask SXFR_ULTRA2 0x7f /* Sync transfer rate */ 165 mask SOFS 0x0f /* Sync offset */ 166} 167 168/* 169 * SCSI ID (p. 3-18). 170 * Contains the ID of the board and the current target on the 171 * selected channel. 172 */ 173register SCSIID { 174 address 0x005 175 access_mode RW 176 mask TID 0xf0 /* Target ID mask */ 177 mask OID 0x0f /* Our ID mask */ 178 /* 179 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 180 * The aic7890/91 allow an offset of up to 127 transfers in both wide 181 * and narrow mode. 182 */ 183 alias SCSIOFFSET 184 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 185} 186 187/* 188 * SCSI Latched Data (p. 3-19). 189 * Read/Write latches used to transfer data on the SCSI bus during 190 * Automatic or Manual PIO mode. SCSIDATH can be used for the 191 * upper byte of a 16bit wide asynchronouse data phase transfer. 192 */ 193register SCSIDATL { 194 address 0x006 195 access_mode RW 196} 197 198register SCSIDATH { 199 address 0x007 200 access_mode RW 201} 202 203/* 204 * SCSI Transfer Count (pp. 3-19,20) 205 * These registers count down the number of bytes transferred 206 * across the SCSI bus. The counter is decremented only once 207 * the data has been safely transferred. SDONE in SSTAT0 is 208 * set when STCNT goes to 0 209 */ 210register STCNT { 211 address 0x008 212 size 3 213 access_mode RW 214} 215 216/* 217 * Clear SCSI Interrupt 0 (p. 3-20) 218 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 219 */ 220register CLRSINT0 { 221 address 0x00b 222 access_mode WO 223 bit CLRSELDO 0x40 224 bit CLRSELDI 0x20 225 bit CLRSELINGO 0x10 226 bit CLRSWRAP 0x08 227 bit CLRSPIORDY 0x02 228} 229 230/* 231 * SCSI Status 0 (p. 3-21) 232 * Contains one set of SCSI Interrupt codes 233 * These are most likely of interest to the sequencer 234 */ 235register SSTAT0 { 236 address 0x00b 237 access_mode RO 238 bit TARGET 0x80 /* Board acting as target */ 239 bit SELDO 0x40 /* Selection Done */ 240 bit SELDI 0x20 /* Board has been selected */ 241 bit SELINGO 0x10 /* Selection In Progress */ 242 bit SWRAP 0x08 /* 24bit counter wrap */ 243 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 244 bit SDONE 0x04 /* STCNT = 0x000000 */ 245 bit SPIORDY 0x02 /* SCSI PIO Ready */ 246 bit DMADONE 0x01 /* DMA transfer completed */ 247} 248 249/* 250 * Clear SCSI Interrupt 1 (p. 3-23) 251 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 252 */ 253register CLRSINT1 { 254 address 0x00c 255 access_mode WO 256 bit CLRSELTIMEO 0x80 257 bit CLRATNO 0x40 258 bit CLRSCSIRSTI 0x20 259 bit CLRBUSFREE 0x08 260 bit CLRSCSIPERR 0x04 261 bit CLRPHASECHG 0x02 262 bit CLRREQINIT 0x01 263} 264 265/* 266 * SCSI Status 1 (p. 3-24) 267 */ 268register SSTAT1 { 269 address 0x00c 270 access_mode RO 271 bit SELTO 0x80 272 bit ATNTARG 0x40 273 bit SCSIRSTI 0x20 274 bit PHASEMIS 0x10 275 bit BUSFREE 0x08 276 bit SCSIPERR 0x04 277 bit PHASECHG 0x02 278 bit REQINIT 0x01 279} 280 281/* 282 * SCSI Status 2 (pp. 3-25,26) 283 */ 284register SSTAT2 { 285 address 0x00d 286 access_mode RO 287 bit OVERRUN 0x80 288 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 289 mask SFCNT 0x1f 290} 291 292/* 293 * SCSI Status 3 (p. 3-26) 294 */ 295register SSTAT3 { 296 address 0x00e 297 access_mode RO 298 mask SCSICNT 0xf0 299 mask OFFCNT 0x0f 300} 301 302/* 303 * SCSI ID for the aic7890/91 chips 304 */ 305register SCSIID_ULTRA2 { 306 address 0x00f 307 access_mode RW 308 mask TID 0xf0 /* Target ID mask */ 309 mask OID 0x0f /* Our ID mask */ 310} 311 312/* 313 * SCSI Interrupt Mode 1 (p. 3-28) 314 * Setting any bit will enable the corresponding function 315 * in SIMODE0 to interrupt via the IRQ pin. 316 */ 317register SIMODE0 { 318 address 0x010 319 access_mode RW 320 bit ENSELDO 0x40 321 bit ENSELDI 0x20 322 bit ENSELINGO 0x10 323 bit ENSWRAP 0x08 324 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 325 bit ENSDONE 0x04 326 bit ENSPIORDY 0x02 327 bit ENDMADONE 0x01 328} 329 330/* 331 * SCSI Interrupt Mode 1 (pp. 3-28,29) 332 * Setting any bit will enable the corresponding function 333 * in SIMODE1 to interrupt via the IRQ pin. 334 */ 335register SIMODE1 { 336 address 0x011 337 access_mode RW 338 bit ENSELTIMO 0x80 339 bit ENATNTARG 0x40 340 bit ENSCSIRST 0x20 341 bit ENPHASEMIS 0x10 342 bit ENBUSFREE 0x08 343 bit ENSCSIPERR 0x04 344 bit ENPHASECHG 0x02 345 bit ENREQINIT 0x01 346} 347 348/* 349 * SCSI Data Bus (High) (p. 3-29) 350 * This register reads data on the SCSI Data bus directly. 351 */ 352register SCSIBUSL { 353 address 0x012 354 access_mode RO 355} 356 357register SCSIBUSH { 358 address 0x013 359 access_mode RO 360} 361 362/* 363 * SCSI/Host Address (p. 3-30) 364 * These registers hold the host address for the byte about to be 365 * transferred on the SCSI bus. They are counted up in the same 366 * manner as STCNT is counted down. SHADDR should always be used 367 * to determine the address of the last byte transferred since HADDR 368 * can be skewed by write ahead. 369 */ 370register SHADDR { 371 address 0x014 372 size 4 373 access_mode RO 374} 375 376/* 377 * Selection Timeout Timer (p. 3-30) 378 */ 379register SELTIMER { 380 address 0x018 381 access_mode RW 382 bit STAGE6 0x20 383 bit STAGE5 0x10 384 bit STAGE4 0x08 385 bit STAGE3 0x04 386 bit STAGE2 0x02 387 bit STAGE1 0x01 388 alias TARGIDIN 389} 390 391/* 392 * Selection/Reselection ID (p. 3-31) 393 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 394 * device did not set its own ID. 395 */ 396register SELID { 397 address 0x019 398 access_mode RW 399 mask SELID_MASK 0xf0 400 bit ONEBIT 0x08 401} 402 403/* 404 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 405 */ 406register TARGID { 407 address 0x01b 408 size 2 409 access_mode RW 410} 411 412/* 413 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 414 * Indicates if external logic has been attached to the chip to 415 * perform the tasks of accessing a serial eeprom, testing termination 416 * strength, and performing cable detection. On the aic7860, most of 417 * these features are handled on chip, but on the aic7855 an attached 418 * aic3800 does the grunt work. 419 */ 420register SPIOCAP { 421 address 0x01b 422 access_mode RW 423 bit SOFT1 0x80 424 bit SOFT0 0x40 425 bit SOFTCMDEN 0x20 426 bit HAS_BRDCTL 0x10 /* External Board control */ 427 bit SEEPROM 0x08 /* External serial eeprom logic */ 428 bit EEPROM 0x04 /* Writable external BIOS ROM */ 429 bit ROM 0x02 /* Logic for accessing external ROM */ 430 bit SSPIOCPS 0x01 /* Termination and cable detection */ 431} 432 433register BRDCTL { 434 address 0x01d 435 bit BRDDAT7 0x80 436 bit BRDDAT6 0x40 437 bit BRDDAT5 0x20 438 bit BRDSTB 0x10 439 bit BRDCS 0x08 440 bit BRDRW 0x04 441 bit BRDCTL1 0x02 442 bit BRDCTL0 0x01 443 /* 7890 Definitions */ 444 bit BRDDAT4 0x10 445 bit BRDDAT3 0x08 446 bit BRDDAT2 0x04 447 bit BRDRW_ULTRA2 0x02 448 bit BRDSTB_ULTRA2 0x01 449} 450 451/* 452 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 453 * Controls the reading and writing of an external serial 1-bit 454 * EEPROM Device. In order to access the serial EEPROM, you must 455 * first set the SEEMS bit that generates a request to the memory 456 * port for access to the serial EEPROM device. When the memory 457 * port is not busy servicing another request, it reconfigures 458 * to allow access to the serial EEPROM. When this happens, SEERDY 459 * gets set high to verify that the memory port access has been 460 * granted. 461 * 462 * After successful arbitration for the memory port, the SEECS bit of 463 * the SEECTL register is connected to the chip select. The SEECK, 464 * SEEDO, and SEEDI are connected to the clock, data out, and data in 465 * lines respectively. The SEERDY bit of SEECTL is useful in that it 466 * gives us an 800 nsec timer. After a write to the SEECTL register, 467 * the SEERDY goes high 800 nsec later. The one exception to this is 468 * when we first request access to the memory port. The SEERDY goes 469 * high to signify that access has been granted and, for this case, has 470 * no implied timing. 471 * 472 * See 93cx6.c for detailed information on the protocol necessary to 473 * read the serial EEPROM. 474 */ 475register SEECTL { 476 address 0x01e 477 bit EXTARBACK 0x80 478 bit EXTARBREQ 0x40 479 bit SEEMS 0x20 480 bit SEERDY 0x10 481 bit SEECS 0x08 482 bit SEECK 0x04 483 bit SEEDO 0x02 484 bit SEEDI 0x01 485} 486/* 487 * SCSI Block Control (p. 3-32) 488 * Controls Bus type and channel selection. In a twin channel configuration 489 * addresses 0x00-0x1e are gated to the appropriate channel based on this 490 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 491 * on a wide bus. 492 */ 493register SBLKCTL { 494 address 0x01f 495 access_mode RW 496 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 497 bit DIAGLEDON 0x40 /* Aic78X0 only */ 498 bit AUTOFLUSHDIS 0x20 499 bit SELBUSB 0x08 500 bit ENAB40 0x08 /* LVD transceiver active */ 501 bit ENAB20 0x04 /* SE/HVD transceiver active */ 502 bit SELWIDE 0x02 503 bit XCVR 0x01 /* External transceiver active */ 504} 505 506/* 507 * Sequencer Control (p. 3-33) 508 * Error detection mode and speed configuration 509 */ 510register SEQCTL { 511 address 0x060 512 access_mode RW 513 bit PERRORDIS 0x80 514 bit PAUSEDIS 0x40 515 bit FAILDIS 0x20 516 bit FASTMODE 0x10 517 bit BRKADRINTEN 0x08 518 bit STEP 0x04 519 bit SEQRESET 0x02 520 bit LOADRAM 0x01 521} 522 523/* 524 * Sequencer RAM Data (p. 3-34) 525 * Single byte window into the Scratch Ram area starting at the address 526 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 527 * four bytes in succession. The SEQADDRs will increment after the most 528 * significant byte is written 529 */ 530register SEQRAM { 531 address 0x061 532 access_mode RW 533} 534 535/* 536 * Sequencer Address Registers (p. 3-35) 537 * Only the first bit of SEQADDR1 holds addressing information 538 */ 539register SEQADDR0 { 540 address 0x062 541 access_mode RW 542} 543 544register SEQADDR1 { 545 address 0x063 546 access_mode RW 547 mask SEQADDR1_MASK 0x01 548} 549 550/* 551 * Accumulator 552 * We cheat by passing arguments in the Accumulator up to the kernel driver 553 */ 554register ACCUM { 555 address 0x064 556 access_mode RW 557 accumulator 558} 559 560register SINDEX { 561 address 0x065 562 access_mode RW 563 sindex 564} 565 566register DINDEX { 567 address 0x066 568 access_mode RW 569} 570 571register ALLONES { 572 address 0x069 573 access_mode RO 574 allones 575} 576 577register ALLZEROS { 578 address 0x06a 579 access_mode RO 580 allzeros 581} 582 583register NONE { 584 address 0x06a 585 access_mode WO 586 none 587} 588 589register FLAGS { 590 address 0x06b 591 access_mode RO 592 bit ZERO 0x02 593 bit CARRY 0x01 594} 595 596register SINDIR { 597 address 0x06c 598 access_mode RO 599} 600 601register DINDIR { 602 address 0x06d 603 access_mode WO 604} 605 606register FUNCTION1 { 607 address 0x06e 608 access_mode RW 609} 610 611register STACK { 612 address 0x06f 613 access_mode RO 614} 615 616/* 617 * Board Control (p. 3-43) 618 */ 619register BCTL { 620 address 0x084 621 access_mode RW 622 bit ACE 0x08 623 bit ENABLE 0x01 624} 625 626/* 627 * On the aic78X0 chips, Board Control is replaced by the DSCommand 628 * register (p. 4-64) 629 */ 630register DSCOMMAND0 { 631 address 0x084 632 access_mode RW 633 bit CACHETHEN 0x80 /* Cache Threshold enable */ 634 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 635 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 636 bit EXTREQLCK 0x10 /* External Request Lock */ 637 /* aic7890/91/96/97 only */ 638 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 639 bit RAMPS 0x04 /* External SCB RAM Present */ 640 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 641 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 642} 643 644/* 645 * Bus On/Off Time (p. 3-44) 646 */ 647register BUSTIME { 648 address 0x085 649 access_mode RW 650 mask BOFF 0xf0 651 mask BON 0x0f 652} 653 654/* 655 * Bus Speed (p. 3-45) aic7770 only 656 */ 657register BUSSPD { 658 address 0x086 659 access_mode RW 660 mask DFTHRSH 0xc0 661 mask STBOFF 0x38 662 mask STBON 0x07 663 mask DFTHRSH_100 0xc0 664} 665 666/* aic7850/55/60/70/80/95 only */ 667register DSPCISTATUS { 668 address 0x086 669 mask DFTHRSH_100 0xc0 670} 671 672/* aic7890/91/96/97 only */ 673register HS_MAILBOX { 674 address 0x086 675 mask HOST_MAILBOX 0xF0 676 mask SEQ_MAILBOX 0x0F 677} 678 679const HOST_MAILBOX_SHIFT 4 680const SEQ_MAILBOX_SHIFT 0 681 682/* 683 * Host Control (p. 3-47) R/W 684 * Overall host control of the device. 685 */ 686register HCNTRL { 687 address 0x087 688 access_mode RW 689 bit POWRDN 0x40 690 bit SWINT 0x10 691 bit IRQMS 0x08 692 bit PAUSE 0x04 693 bit INTEN 0x02 694 bit CHIPRST 0x01 695 bit CHIPRSTACK 0x01 696} 697 698/* 699 * Host Address (p. 3-48) 700 * This register contains the address of the byte about 701 * to be transferred across the host bus. 702 */ 703register HADDR { 704 address 0x088 705 size 4 706 access_mode RW 707} 708 709register HCNT { 710 address 0x08c 711 size 3 712 access_mode RW 713} 714 715/* 716 * SCB Pointer (p. 3-49) 717 * Gate one of the four SCBs into the SCBARRAY window. 718 */ 719register SCBPTR { 720 address 0x090 721 access_mode RW 722} 723 724/* 725 * Interrupt Status (p. 3-50) 726 * Status for system interrupts 727 */ 728register INTSTAT { 729 address 0x091 730 access_mode RW 731 bit BRKADRINT 0x08 732 bit SCSIINT 0x04 733 bit CMDCMPLT 0x02 734 bit SEQINT 0x01 735 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 736 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 737 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 738 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 739 mask ABORT_REQUESTED 0x50|SEQINT /* Reconect of aborted SCB */ 740 mask UPDATE_TMSG_REQ 0x60|SEQINT /* Update TMSG_REQ values */ 741 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 742 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ 743 mask TRACE_POINT 0x90|SEQINT 744 mask HOST_MSG_LOOP 0xa0|SEQINT /* 745 * The bus is ready for the 746 * host to perform another 747 * message transaction. This 748 * mechanism is used for things 749 * like sync/wide negotiation 750 * that require a kernel based 751 * message state engine. 752 */ 753 mask TRACEPOINT 0xd0|SEQINT 754 mask MSGIN_PHASEMIS 0xe0|SEQINT /* 755 * Target changed phase on us 756 * when we were expecting 757 * another msgin byte. 758 */ 759 mask DATA_OVERRUN 0xf0|SEQINT /* 760 * Target attempted to write 761 * beyond the bounds of its 762 * command. 763 */ 764 765 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 766 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 767} 768 769/* 770 * Hard Error (p. 3-53) 771 * Reporting of catastrophic errors. You usually cannot recover from 772 * these without a full board reset. 773 */ 774register ERROR { 775 address 0x092 776 access_mode RO 777 bit CIOPARERR 0x80 /* Ultra2 only */ 778 bit PCIERRSTAT 0x40 /* PCI only */ 779 bit MPARERR 0x20 /* PCI only */ 780 bit DPARERR 0x10 /* PCI only */ 781 bit SQPARERR 0x08 782 bit ILLOPCODE 0x04 783 bit ILLSADDR 0x02 784 bit ILLHADDR 0x01 785} 786 787/* 788 * Clear Interrupt Status (p. 3-52) 789 */ 790register CLRINT { 791 address 0x092 792 access_mode WO 793 bit CLRPARERR 0x10 /* PCI only */ 794 bit CLRBRKADRINT 0x08 795 bit CLRSCSIINT 0x04 796 bit CLRCMDINT 0x02 797 bit CLRSEQINT 0x01 798} 799 800register DFCNTRL { 801 address 0x093 802 access_mode RW 803 bit PRELOADEN 0x80 /* aic7890 only */ 804 bit WIDEODD 0x40 805 bit SCSIEN 0x20 806 bit SDMAEN 0x10 807 bit SDMAENACK 0x10 808 bit HDMAEN 0x08 809 bit HDMAENACK 0x08 810 bit DIRECTION 0x04 811 bit FIFOFLUSH 0x02 812 bit FIFORESET 0x01 813} 814 815register DFSTATUS { 816 address 0x094 817 access_mode RO 818 bit PRELOAD_AVAIL 0x80 819 bit DWORDEMP 0x20 820 bit MREQPEND 0x10 821 bit HDONE 0x08 822 bit DFTHRESH 0x04 823 bit FIFOFULL 0x02 824 bit FIFOEMP 0x01 825} 826 827register DFWADDR { 828 address 0x95 829 access_mode RW 830} 831 832register DFRADDR { 833 address 0x97 834 access_mode RW 835} 836 837register DFDAT { 838 address 0x099 839 access_mode RW 840} 841 842/* 843 * SCB Auto Increment (p. 3-59) 844 * Byte offset into the SCB Array and an optional bit to allow auto 845 * incrementing of the address during download and upload operations 846 */ 847register SCBCNT { 848 address 0x09a 849 access_mode RW 850 bit SCBAUTO 0x80 851 mask SCBCNT_MASK 0x1f 852} 853 854/* 855 * Queue In FIFO (p. 3-60) 856 * Input queue for queued SCBs (commands that the seqencer has yet to start) 857 */ 858register QINFIFO { 859 address 0x09b 860 access_mode RW 861} 862 863/* 864 * Queue In Count (p. 3-60) 865 * Number of queued SCBs 866 */ 867register QINCNT { 868 address 0x09c 869 access_mode RO 870} 871 872/* 873 * Queue Out FIFO (p. 3-61) 874 * Queue of SCBs that have completed and await the host 875 */ 876register QOUTFIFO { 877 address 0x09d 878 access_mode WO 879} 880 881/* 882 * Queue Out Count (p. 3-61) 883 * Number of queued SCBs in the Out FIFO 884 */ 885register QOUTCNT { 886 address 0x09e 887 access_mode RO 888} 889 890/* 891 * Special Function 892 */ 893register SFUNCT { 894 address 0x09f 895 access_mode RW 896} 897 898/* 899 * SCB Definition (p. 5-4) 900 */ 901scb { 902 address 0x0a0 903 SCB_CONTROL { 904 size 1 905 bit TARGET_SCB 0x80 906 bit DISCENB 0x40 907 bit TAG_ENB 0x20 908 bit MK_MESSAGE 0x10 909 bit ULTRAENB 0x08 910 bit DISCONNECTED 0x04 911 mask SCB_TAG_TYPE 0x03 912 } 913 SCB_TCL { 914 size 1 915 bit SELBUSB 0x08 916 mask TID 0xf0 917 mask LID 0x07 918 } 919 SCB_TARGET_STATUS { 920 size 1 921 } 922 SCB_SGCOUNT { 923 size 1 924 } 925 SCB_SGPTR { 926 size 4 927 } 928 SCB_RESID_SGCNT { 929 size 1 930 } 931 SCB_RESID_DCNT { 932 size 3 933 } 934 SCB_DATAPTR { 935 size 4 936 } 937 SCB_DATACNT { 938 /* 939 * Really only 3 bytes, but padded to make 940 * the kernel's job easier. 941 */ 942 size 4 943 } 944 SCB_CMDPTR { 945 alias SCB_TARGET_PHASES 946 bit TARGET_DATA_IN 0x1 /* In the second byte */ 947 size 4 948 } 949 SCB_CMDLEN { 950 alias SCB_INITIATOR_TAG 951 size 1 952 } 953 SCB_TAG { 954 size 1 955 } 956 SCB_NEXT { 957 size 1 958 } 959 SCB_SCSIRATE { 960 size 1 961 } 962 SCB_SCSIOFFSET { 963 size 1 964 } 965 SCB_SPARE { 966 size 3 967 } 968 SCB_CMDSTORE { 969 size 16 970 } 971 SCB_CMDSTORE_BUSADDR { 972 size 4 973 } 974 SCB_64BYTE_SPARE { 975 size 12 976 } 977} 978 979const SCB_32BYTE_SIZE 28 980const SCB_64BYTE_SIZE 48 981 982const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 983 984/* --------------------- AHA-2840-only definitions -------------------- */ 985 986register SEECTL_2840 { 987 address 0x0c0 988 access_mode RW 989 bit CS_2840 0x04 990 bit CK_2840 0x02 991 bit DO_2840 0x01 992} 993 994register STATUS_2840 { 995 address 0x0c1 996 access_mode RW 997 bit EEPROM_TF 0x80 998 mask BIOS_SEL 0x60 999 mask ADSEL 0x1e 1000 bit DI_2840 0x01 1001} 1002 1003/* --------------------- AIC-7870-only definitions -------------------- */ 1004 1005register CCHADDR { 1006 address 0x0E0 1007 size 8 1008} 1009 1010register CCHCNT { 1011 address 0x0E8 1012} 1013 1014register CCSGRAM { 1015 address 0x0E9 1016} 1017 1018register CCSGADDR { 1019 address 0x0EA 1020} 1021 1022register CCSGCTL { 1023 address 0x0EB 1024 bit CCSGDONE 0x80 1025 bit CCSGEN 0x08 1026 bit FLAG 0x02 1027 bit CCSGRESET 0x01 1028} 1029 1030register CCSCBCNT { 1031 address 0xEF 1032} 1033 1034register CCSCBCTL { 1035 address 0x0EE 1036 bit CCSCBDONE 0x80 1037 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1038 bit CCARREN 0x10 1039 bit CCSCBEN 0x08 1040 bit CCSCBDIR 0x04 1041 bit CCSCBRESET 0x01 1042} 1043 1044register CCSCBADDR { 1045 address 0x0ED 1046} 1047 1048register CCSCBRAM { 1049 address 0xEC 1050} 1051 1052/* 1053 * SCB bank address (7895/7896/97 only) 1054 */ 1055register SCBBADDR { 1056 address 0x0F0 1057 access_mode RW 1058} 1059 1060register CCSCBPTR { 1061 address 0x0F1 1062} 1063 1064register HNSCB_QOFF { 1065 address 0x0F4 1066} 1067 1068register SNSCB_QOFF { 1069 address 0x0F6 1070} 1071 1072register SDSCB_QOFF { 1073 address 0x0F8 1074} 1075 1076register QOFF_CTLSTA { 1077 address 0x0FA 1078 bit SCB_AVAIL 0x40 1079 bit SNSCB_ROLLOVER 0x20 1080 bit SDSCB_ROLLOVER 0x10 1081 mask SCB_QSIZE 0x07 1082 mask SCB_QSIZE_256 0x06 1083} 1084 1085register DFF_THRSH { 1086 address 0x0FB 1087 mask WR_DFTHRSH 0x70 1088 mask RD_DFTHRSH 0x07 1089 mask RD_DFTHRSH_MIN 0x00 1090 mask RD_DFTHRSH_25 0x01 1091 mask RD_DFTHRSH_50 0x02 1092 mask RD_DFTHRSH_63 0x03 1093 mask RD_DFTHRSH_75 0x04 1094 mask RD_DFTHRSH_85 0x05 1095 mask RD_DFTHRSH_90 0x06 1096 mask RD_DFTHRSH_MAX 0x07 1097 mask WR_DFTHRSH_MIN 0x00 1098 mask WR_DFTHRSH_25 0x10 1099 mask WR_DFTHRSH_50 0x20 1100 mask WR_DFTHRSH_63 0x30 1101 mask WR_DFTHRSH_75 0x40 1102 mask WR_DFTHRSH_85 0x50 1103 mask WR_DFTHRSH_90 0x60 1104 mask WR_DFTHRSH_MAX 0x70 1105} 1106 1107register SG_CACHEPTR { 1108 access_mode RW 1109 address 0x0fc 1110 mask SG_USER_DATA 0xfc 1111 bit LAST_SEG 0x02 1112 bit LAST_SEG_DONE 0x01 1113} 1114 1115/* ---------------------- Scratch RAM Offsets ------------------------- */ 1116/* These offsets are either to values that are initialized by the board's 1117 * BIOS or are specified by the sequencer code. 1118 * 1119 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1120 * device information, 32-33 and 5a-5f as well. As it turns out, the 1121 * BIOS trashes 20-2f, writing the synchronous negotiation results 1122 * on top of the BIOS values, so we re-use those for our per-target 1123 * scratchspace (actually a value that can be copied directly into 1124 * SCSIRATE). The kernel driver will enable synchronous negotiation 1125 * for all targets that have a value other than 0 in the lower four 1126 * bits of the target scratch space. This should work regardless of 1127 * whether the bios has been installed. 1128 */ 1129 1130scratch_ram { 1131 address 0x020 1132 1133 /* 1134 * 1 byte per target starting at this address for configuration values 1135 */ 1136 TARG_SCSIRATE { 1137 alias CMDSIZE_TABLE 1138 size 16 1139 } 1140 /* 1141 * Bit vector of targets that have ULTRA enabled. 1142 */ 1143 ULTRA_ENB { 1144 size 2 1145 } 1146 /* 1147 * Bit vector of targets that have disconnection disabled. 1148 */ 1149 DISC_DSB { 1150 size 2 1151 } 1152 /* 1153 * Single byte buffer used to designate the type or message 1154 * to send to a target. 1155 */ 1156 MSG_OUT { 1157 size 1 1158 } 1159 /* Parameters for DMA Logic */ 1160 DMAPARAMS { 1161 size 1 1162 bit PRELOADEN 0x80 1163 bit WIDEODD 0x40 1164 bit SCSIEN 0x20 1165 bit SDMAEN 0x10 1166 bit SDMAENACK 0x10 1167 bit HDMAEN 0x08 1168 bit HDMAENACK 0x08 1169 bit DIRECTION 0x04 1170 bit FIFOFLUSH 0x02 1171 bit FIFORESET 0x01 1172 } 1173 SEQ_FLAGS { 1174 size 1 1175 bit IDENTIFY_SEEN 0x80 1176 bit SCBPTR_VALID 0x40 1177 bit DPHASE 0x20 1178 /* Target flags */ 1179 bit TARG_CMD_PENDING 0x10 1180 bit CMDPHASE_PENDING 0x08 1181 bit DPHASE_PENDING 0x04 1182 bit SPHASE_PENDING 0x02 1183 bit NO_DISCONNECT 0x01 1184 } 1185 /* 1186 * Temporary storage for the 1187 * target/channel/lun of a 1188 * reconnecting target 1189 */ 1190 SAVED_TCL { 1191 size 1 1192 } 1193 /* Working value of the number of SG segments left */ 1194 SG_COUNT { 1195 size 1 1196 } 1197 /* Working value of SG pointer */ 1198 SG_NEXT { 1199 size 4 1200 } 1201 /* 1202 * The last bus phase as seen by the sequencer. 1203 */ 1204 LASTPHASE { 1205 size 1 1206 bit CDI 0x80 1207 bit IOI 0x40 1208 bit MSGI 0x20 1209 mask PHASE_MASK CDI|IOI|MSGI 1210 mask P_DATAOUT 0x00 1211 mask P_DATAIN IOI 1212 mask P_COMMAND CDI 1213 mask P_MESGOUT CDI|MSGI 1214 mask P_STATUS CDI|IOI 1215 mask P_MESGIN CDI|IOI|MSGI 1216 mask P_BUSFREE 0x01 1217 } 1218 /* 1219 * head of list of SCBs awaiting 1220 * selection 1221 */ 1222 WAITING_SCBH { 1223 size 1 1224 } 1225 /* 1226 * head of list of SCBs that are 1227 * disconnected. Used for SCB 1228 * paging. 1229 */ 1230 DISCONNECTED_SCBH { 1231 size 1 1232 } 1233 /* 1234 * head of list of SCBs that are 1235 * not in use. Used for SCB paging. 1236 */ 1237 FREE_SCBH { 1238 size 1 1239 } 1240 /* 1241 * Address of the hardware scb array in the host. 1242 */ 1243 HSCB_ADDR { 1244 size 4 1245 } 1246 /* 1247 * Address of the 256 byte array storing the SCBID of outstanding 1248 * untagged SCBs indexed by TCL. 1249 */ 1250 SCBID_ADDR { 1251 size 4 1252 } 1253 /* 1254 * Address of the array of command descriptors used to store 1255 * information about incoming selections. 1256 */ 1257 TMODE_CMDADDR { 1258 size 4 1259 } 1260 KERNEL_QINPOS { 1261 size 1 1262 } 1263 QINPOS { 1264 size 1 1265 } 1266 QOUTPOS { 1267 size 1 1268 } 1269 /* 1270 * Kernel and sequencer offsets into the queue of 1271 * incoming target mode command descriptors. The 1272 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1273 */ 1274 KERNEL_TQINPOS { 1275 size 1 1276 } 1277 TQINPOS { 1278 size 1 1279 } 1280 ARG_1 { 1281 size 1 1282 mask SEND_MSG 0x80 1283 mask SEND_SENSE 0x40 1284 mask SEND_REJ 0x20 1285 mask MSGOUT_PHASEMIS 0x10 1286 mask EXIT_MSG_LOOP 0x08 1287 mask CONT_MSG_LOOP 0x04 1288 mask CONT_TARG_SESSION 0x02 1289 alias RETURN_1 1290 } 1291 ARG_2 { 1292 size 1 1293 alias RETURN_2 1294 } 1295 1296 /* 1297 * Snapshot of MSG_OUT taken after each message is sent. 1298 */ 1299 LAST_MSG { 1300 size 1 1301 } 1302 1303 /* 1304 * Number of times we have filled the CCSGRAM with prefetched 1305 * SG elements. 1306 */ 1307 PREFETCH_CNT { 1308 size 1 1309 } 1310 1311 /* 1312 * Interrupt kernel for a message to this target on 1313 * the next transaction. This is usually used for 1314 * negotiation requests. 1315 */ 1316 TARGET_MSG_REQUEST { 1317 size 2 1318 } 1319 1320 /* 1321 * Sequences the kernel driver has okayed for us. This allows 1322 * the driver to do things like prevent initiator or target 1323 * operations. 1324 */ 1325 SCSISEQ_TEMPLATE { 1326 size 1 1327 bit ENSELO 0x40 1328 bit ENSELI 0x20 1329 bit ENRSELI 0x10 1330 bit ENAUTOATNO 0x08 1331 bit ENAUTOATNI 0x04 1332 bit ENAUTOATNP 0x02 1333 } 1334 1335 /* 1336 * Track whether the transfer byte count for 1337 * the current data phase is odd. 1338 */ 1339 DATA_COUNT_ODD { 1340 size 1 1341 } 1342 1343 /* 1344 * The initiator specified tag for this target mode transaction. 1345 */ 1346 INITIATOR_TAG { 1347 size 1 1348 } 1349 1350 /* 1351 * These are reserved registers in the card's scratch ram. Some of 1352 * the values are specified in the AHA2742 technical reference manual 1353 * and are initialized by the BIOS at boot time. 1354 */ 1355 SCSICONF { 1356 address 0x05a 1357 size 1 1358 bit TERM_ENB 0x80 1359 bit RESET_SCSI 0x40 1360 mask HSCSIID 0x07 /* our SCSI ID */ 1361 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1362 } 1363 HOSTCONF { 1364 address 0x05d 1365 size 1 1366 } 1367 HA_274_BIOSCTRL { 1368 address 0x05f 1369 size 1 1370 mask BIOSMODE 0x30 1371 mask BIOSDISABLED 0x30 1372 bit CHANNEL_B_PRIMARY 0x08 1373 } 1374 /* 1375 * Per target SCSI offset values for Ultra2 controllers. 1376 */ 1377 TARG_OFFSET { 1378 address 0x070 1379 size 16 1380 } 1381} 1382 1383const SCB_LIST_NULL 0xff 1384const TARGET_CMD_CMPLT 0xfe 1385 1386const CCSGADDR_MAX 0x80 1387const CCSGRAM_MAXSEGS 16 1388 1389/* Offsets into the SCBID array where different data is stored */ 1390const QOUTFIFO_OFFSET 0 1391const QINFIFO_OFFSET 1 1392const UNTAGGEDSCB_OFFSET 2 1393 1394/* WDTR Message values */ 1395const BUS_8_BIT 0x00 1396const BUS_16_BIT 0x01 1397const BUS_32_BIT 0x02 1398 1399/* Offset maximums */ 1400const MAX_OFFSET_8BIT 0x0f 1401const MAX_OFFSET_16BIT 0x08 1402const MAX_OFFSET_ULTRA2 0x7f 1403const HOST_MSG 0xff 1404 1405/* Target mode command processing constants */ 1406const CMD_GROUP_CODE_SHIFT 0x05 1407 1408const TCL_TARGET_SHIFT 4 1409/* The update interval must be a power of 2 */ 1410const TQINFIFO_UPDATE_CNT 32 1411 1412const STATUS_BUSY 0x08 1413const STATUS_QUEUE_FULL 0x28 1414 1415/* 1416 * Downloaded (kernel inserted) constants 1417 */ 1418 1419/* 1420 * Number of command descriptors in the command descriptor array. 1421 * No longer used, but left here as an example for how downloaded 1422 * constantants can be defined. 1423const TMODE_NUMCMDS download 1424 */ 1425