1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33VERSION = "$Id: //depot/src/aic7xxx/aic7xxx.reg#19 $" 34 35/* 36 * This file is processed by the aic7xxx_asm utility for use in assembling 37 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 38 * a C header file for use in the kernel portion of the Aic7xxx driver. 39 * 40 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 41 * Adaptec's Technical Documents Department 1-800-934-2766 42 */ 43 44/* 45 * SCSI Sequence Control (p. 3-11). 46 * Each bit, when set starts a specific SCSI sequence on the bus 47 */ 48register SCSISEQ { 49 address 0x000 50 access_mode RW 51 bit TEMODE 0x80 52 bit ENSELO 0x40 53 bit ENSELI 0x20 54 bit ENRSELI 0x10 55 bit ENAUTOATNO 0x08 56 bit ENAUTOATNI 0x04 57 bit ENAUTOATNP 0x02 58 bit SCSIRSTO 0x01 59} 60 61/* 62 * SCSI Transfer Control 0 Register (pp. 3-13). 63 * Controls the SCSI module data path. 64 */ 65register SXFRCTL0 { 66 address 0x001 67 access_mode RW 68 bit DFON 0x80 69 bit DFPEXP 0x40 70 bit FAST20 0x20 71 bit CLRSTCNT 0x10 72 bit SPIOEN 0x08 73 bit SCAMEN 0x04 74 bit CLRCHN 0x02 75} 76 77/* 78 * SCSI Transfer Control 1 Register (pp. 3-14,15). 79 * Controls the SCSI module data path. 80 */ 81register SXFRCTL1 { 82 address 0x002 83 access_mode RW 84 bit BITBUCKET 0x80 85 bit SWRAPEN 0x40 86 bit ENSPCHK 0x20 87 mask STIMESEL 0x18 88 bit ENSTIMER 0x04 89 bit ACTNEGEN 0x02 90 bit STPWEN 0x01 /* Powered Termination */ 91} 92 93/* 94 * SCSI Control Signal Read Register (p. 3-15). 95 * Reads the actual state of the SCSI bus pins 96 */ 97register SCSISIGI { 98 address 0x003 99 access_mode RO 100 bit CDI 0x80 101 bit IOI 0x40 102 bit MSGI 0x20 103 bit ATNI 0x10 104 bit SELI 0x08 105 bit BSYI 0x04 106 bit REQI 0x02 107 bit ACKI 0x01 108/* 109 * Possible phases in SCSISIGI 110 */ 111 mask PHASE_MASK CDI|IOI|MSGI 112 mask P_DATAOUT 0x00 113 mask P_DATAIN IOI 114 mask P_DATAOUT_DT P_DATAOUT|MSGI 115 mask P_DATAIN_DT P_DATAIN|MSGI 116 mask P_COMMAND CDI 117 mask P_MESGOUT CDI|MSGI 118 mask P_STATUS CDI|IOI 119 mask P_MESGIN CDI|IOI|MSGI 120} 121 122/* 123 * SCSI Control Signal Write Register (p. 3-16). 124 * Writing to this register modifies the control signals on the bus. Only 125 * those signals that are allowed in the current mode (Initiator/Target) are 126 * asserted. 127 */ 128register SCSISIGO { 129 address 0x003 130 access_mode WO 131 bit CDO 0x80 132 bit IOO 0x40 133 bit MSGO 0x20 134 bit ATNO 0x10 135 bit SELO 0x08 136 bit BSYO 0x04 137 bit REQO 0x02 138 bit ACKO 0x01 139/* 140 * Possible phases to write into SCSISIG0 141 */ 142 mask PHASE_MASK CDI|IOI|MSGI 143 mask P_DATAOUT 0x00 144 mask P_DATAIN IOI 145 mask P_COMMAND CDI 146 mask P_MESGOUT CDI|MSGI 147 mask P_STATUS CDI|IOI 148 mask P_MESGIN CDI|IOI|MSGI 149} 150 151/* 152 * SCSI Rate Control (p. 3-17). 153 * Contents of this register determine the Synchronous SCSI data transfer 154 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 155 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 156 * greater than 0 enables synchronous transfers. 157 */ 158register SCSIRATE { 159 address 0x004 160 access_mode RW 161 bit WIDEXFER 0x80 /* Wide transfer control */ 162 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 163 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 164 mask SXFR 0x70 /* Sync transfer rate */ 165 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 166 mask SOFS 0x0f /* Sync offset */ 167} 168 169/* 170 * SCSI ID (p. 3-18). 171 * Contains the ID of the board and the current target on the 172 * selected channel. 173 */ 174register SCSIID { 175 address 0x005 176 access_mode RW 177 mask TID 0xf0 /* Target ID mask */ 178 mask TWIN_TID 0x70 179 bit TWIN_CHNLB 0x80 180 mask OID 0x0f /* Our ID mask */ 181 /* 182 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 183 * The aic7890/91 allow an offset of up to 127 transfers in both wide 184 * and narrow mode. 185 */ 186 alias SCSIOFFSET 187 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 188} 189 190/* 191 * SCSI Latched Data (p. 3-19). 192 * Read/Write latches used to transfer data on the SCSI bus during 193 * Automatic or Manual PIO mode. SCSIDATH can be used for the 194 * upper byte of a 16bit wide asynchronouse data phase transfer. 195 */ 196register SCSIDATL { 197 address 0x006 198 access_mode RW 199} 200 201register SCSIDATH { 202 address 0x007 203 access_mode RW 204} 205 206/* 207 * SCSI Transfer Count (pp. 3-19,20) 208 * These registers count down the number of bytes transferred 209 * across the SCSI bus. The counter is decremented only once 210 * the data has been safely transferred. SDONE in SSTAT0 is 211 * set when STCNT goes to 0 212 */ 213register STCNT { 214 address 0x008 215 size 3 216 access_mode RW 217} 218 219/* ALT_MODE register on Ultra160 chips */ 220register OPTIONMODE { 221 address 0x008 222 access_mode RW 223 bit AUTORATEEN 0x80 224 bit AUTOACKEN 0x40 225 bit ATNMGMNTEN 0x20 226 bit BUSFREEREV 0x10 227 bit EXPPHASEDIS 0x08 228 bit SCSIDATL_IMGEN 0x04 229 bit AUTO_MSGOUT_DE 0x02 230 bit DIS_MSGIN_DUALEDGE 0x01 231 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 232} 233 234/* ALT_MODE register on Ultra160 chips */ 235register TARGCRCCNT { 236 address 0x00a 237 size 2 238 access_mode RW 239} 240 241/* 242 * Clear SCSI Interrupt 0 (p. 3-20) 243 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 244 */ 245register CLRSINT0 { 246 address 0x00b 247 access_mode WO 248 bit CLRSELDO 0x40 249 bit CLRSELDI 0x20 250 bit CLRSELINGO 0x10 251 bit CLRSWRAP 0x08 252 bit CLRIOERR 0x08 /* Ultra2 Only */ 253 bit CLRSPIORDY 0x02 254} 255 256/* 257 * SCSI Status 0 (p. 3-21) 258 * Contains one set of SCSI Interrupt codes 259 * These are most likely of interest to the sequencer 260 */ 261register SSTAT0 { 262 address 0x00b 263 access_mode RO 264 bit TARGET 0x80 /* Board acting as target */ 265 bit SELDO 0x40 /* Selection Done */ 266 bit SELDI 0x20 /* Board has been selected */ 267 bit SELINGO 0x10 /* Selection In Progress */ 268 bit SWRAP 0x08 /* 24bit counter wrap */ 269 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 270 bit SDONE 0x04 /* STCNT = 0x000000 */ 271 bit SPIORDY 0x02 /* SCSI PIO Ready */ 272 bit DMADONE 0x01 /* DMA transfer completed */ 273} 274 275/* 276 * Clear SCSI Interrupt 1 (p. 3-23) 277 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 278 */ 279register CLRSINT1 { 280 address 0x00c 281 access_mode WO 282 bit CLRSELTIMEO 0x80 283 bit CLRATNO 0x40 284 bit CLRSCSIRSTI 0x20 285 bit CLRBUSFREE 0x08 286 bit CLRSCSIPERR 0x04 287 bit CLRPHASECHG 0x02 288 bit CLRREQINIT 0x01 289} 290 291/* 292 * SCSI Status 1 (p. 3-24) 293 */ 294register SSTAT1 { 295 address 0x00c 296 access_mode RO 297 bit SELTO 0x80 298 bit ATNTARG 0x40 299 bit SCSIRSTI 0x20 300 bit PHASEMIS 0x10 301 bit BUSFREE 0x08 302 bit SCSIPERR 0x04 303 bit PHASECHG 0x02 304 bit REQINIT 0x01 305} 306 307/* 308 * SCSI Status 2 (pp. 3-25,26) 309 */ 310register SSTAT2 { 311 address 0x00d 312 access_mode RO 313 bit OVERRUN 0x80 314 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 315 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 316 bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 317 bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 318 bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 319 bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 320 mask SFCNT 0x1f 321} 322 323/* 324 * SCSI Status 3 (p. 3-26) 325 */ 326register SSTAT3 { 327 address 0x00e 328 access_mode RO 329 mask SCSICNT 0xf0 330 mask OFFCNT 0x0f 331} 332 333/* 334 * SCSI ID for the aic7890/91 chips 335 */ 336register SCSIID_ULTRA2 { 337 address 0x00f 338 access_mode RW 339 mask TID 0xf0 /* Target ID mask */ 340 mask OID 0x0f /* Our ID mask */ 341} 342 343/* 344 * SCSI Interrupt Mode 1 (p. 3-28) 345 * Setting any bit will enable the corresponding function 346 * in SIMODE0 to interrupt via the IRQ pin. 347 */ 348register SIMODE0 { 349 address 0x010 350 access_mode RW 351 bit ENSELDO 0x40 352 bit ENSELDI 0x20 353 bit ENSELINGO 0x10 354 bit ENSWRAP 0x08 355 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 356 bit ENSDONE 0x04 357 bit ENSPIORDY 0x02 358 bit ENDMADONE 0x01 359} 360 361/* 362 * SCSI Interrupt Mode 1 (pp. 3-28,29) 363 * Setting any bit will enable the corresponding function 364 * in SIMODE1 to interrupt via the IRQ pin. 365 */ 366register SIMODE1 { 367 address 0x011 368 access_mode RW 369 bit ENSELTIMO 0x80 370 bit ENATNTARG 0x40 371 bit ENSCSIRST 0x20 372 bit ENPHASEMIS 0x10 373 bit ENBUSFREE 0x08 374 bit ENSCSIPERR 0x04 375 bit ENPHASECHG 0x02 376 bit ENREQINIT 0x01 377} 378 379/* 380 * SCSI Data Bus (High) (p. 3-29) 381 * This register reads data on the SCSI Data bus directly. 382 */ 383register SCSIBUSL { 384 address 0x012 385 access_mode RW 386} 387 388register SCSIBUSH { 389 address 0x013 390 access_mode RW 391} 392 393/* 394 * SCSI/Host Address (p. 3-30) 395 * These registers hold the host address for the byte about to be 396 * transferred on the SCSI bus. They are counted up in the same 397 * manner as STCNT is counted down. SHADDR should always be used 398 * to determine the address of the last byte transferred since HADDR 399 * can be skewed by write ahead. 400 */ 401register SHADDR { 402 address 0x014 403 size 4 404 access_mode RO 405} 406 407/* 408 * Selection Timeout Timer (p. 3-30) 409 */ 410register SELTIMER { 411 address 0x018 412 access_mode RW 413 bit STAGE6 0x20 414 bit STAGE5 0x10 415 bit STAGE4 0x08 416 bit STAGE3 0x04 417 bit STAGE2 0x02 418 bit STAGE1 0x01 419 alias TARGIDIN 420} 421 422/* 423 * Selection/Reselection ID (p. 3-31) 424 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 425 * device did not set its own ID. 426 */ 427register SELID { 428 address 0x019 429 access_mode RW 430 mask SELID_MASK 0xf0 431 bit ONEBIT 0x08 432} 433 434register SCAMCTL { 435 address 0x01a 436 access_mode RW 437 bit ENSCAMSELO 0x80 438 bit CLRSCAMSELID 0x40 439 bit ALTSTIM 0x20 440 bit DFLTTID 0x10 441 mask SCAMLVL 0x03 442} 443 444/* 445 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 446 */ 447register TARGID { 448 address 0x01b 449 size 2 450 access_mode RW 451} 452 453/* 454 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 455 * Indicates if external logic has been attached to the chip to 456 * perform the tasks of accessing a serial eeprom, testing termination 457 * strength, and performing cable detection. On the aic7860, most of 458 * these features are handled on chip, but on the aic7855 an attached 459 * aic3800 does the grunt work. 460 */ 461register SPIOCAP { 462 address 0x01b 463 access_mode RW 464 bit SOFT1 0x80 465 bit SOFT0 0x40 466 bit SOFTCMDEN 0x20 467 bit HAS_BRDCTL 0x10 /* External Board control */ 468 bit SEEPROM 0x08 /* External serial eeprom logic */ 469 bit EEPROM 0x04 /* Writable external BIOS ROM */ 470 bit ROM 0x02 /* Logic for accessing external ROM */ 471 bit SSPIOCPS 0x01 /* Termination and cable detection */ 472} 473 474register BRDCTL { 475 address 0x01d 476 bit BRDDAT7 0x80 477 bit BRDDAT6 0x40 478 bit BRDDAT5 0x20 479 bit BRDSTB 0x10 480 bit BRDCS 0x08 481 bit BRDRW 0x04 482 bit BRDCTL1 0x02 483 bit BRDCTL0 0x01 484 /* 7890 Definitions */ 485 bit BRDDAT4 0x10 486 bit BRDDAT3 0x08 487 bit BRDDAT2 0x04 488 bit BRDRW_ULTRA2 0x02 489 bit BRDSTB_ULTRA2 0x01 490} 491 492/* 493 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 494 * Controls the reading and writing of an external serial 1-bit 495 * EEPROM Device. In order to access the serial EEPROM, you must 496 * first set the SEEMS bit that generates a request to the memory 497 * port for access to the serial EEPROM device. When the memory 498 * port is not busy servicing another request, it reconfigures 499 * to allow access to the serial EEPROM. When this happens, SEERDY 500 * gets set high to verify that the memory port access has been 501 * granted. 502 * 503 * After successful arbitration for the memory port, the SEECS bit of 504 * the SEECTL register is connected to the chip select. The SEECK, 505 * SEEDO, and SEEDI are connected to the clock, data out, and data in 506 * lines respectively. The SEERDY bit of SEECTL is useful in that it 507 * gives us an 800 nsec timer. After a write to the SEECTL register, 508 * the SEERDY goes high 800 nsec later. The one exception to this is 509 * when we first request access to the memory port. The SEERDY goes 510 * high to signify that access has been granted and, for this case, has 511 * no implied timing. 512 * 513 * See 93cx6.c for detailed information on the protocol necessary to 514 * read the serial EEPROM. 515 */ 516register SEECTL { 517 address 0x01e 518 bit EXTARBACK 0x80 519 bit EXTARBREQ 0x40 520 bit SEEMS 0x20 521 bit SEERDY 0x10 522 bit SEECS 0x08 523 bit SEECK 0x04 524 bit SEEDO 0x02 525 bit SEEDI 0x01 526} 527/* 528 * SCSI Block Control (p. 3-32) 529 * Controls Bus type and channel selection. In a twin channel configuration 530 * addresses 0x00-0x1e are gated to the appropriate channel based on this 531 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 532 * on a wide bus. 533 */ 534register SBLKCTL { 535 address 0x01f 536 access_mode RW 537 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 538 bit DIAGLEDON 0x40 /* Aic78X0 only */ 539 bit AUTOFLUSHDIS 0x20 540 bit SELBUSB 0x08 541 bit ENAB40 0x08 /* LVD transceiver active */ 542 bit ENAB20 0x04 /* SE/HVD transceiver active */ 543 bit SELWIDE 0x02 544 bit XCVR 0x01 /* External transceiver active */ 545} 546 547/* 548 * Sequencer Control (p. 3-33) 549 * Error detection mode and speed configuration 550 */ 551register SEQCTL { 552 address 0x060 553 access_mode RW 554 bit PERRORDIS 0x80 555 bit PAUSEDIS 0x40 556 bit FAILDIS 0x20 557 bit FASTMODE 0x10 558 bit BRKADRINTEN 0x08 559 bit STEP 0x04 560 bit SEQRESET 0x02 561 bit LOADRAM 0x01 562} 563 564/* 565 * Sequencer RAM Data (p. 3-34) 566 * Single byte window into the Scratch Ram area starting at the address 567 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 568 * four bytes in succession. The SEQADDRs will increment after the most 569 * significant byte is written 570 */ 571register SEQRAM { 572 address 0x061 573 access_mode RW 574} 575 576/* 577 * Sequencer Address Registers (p. 3-35) 578 * Only the first bit of SEQADDR1 holds addressing information 579 */ 580register SEQADDR0 { 581 address 0x062 582 access_mode RW 583} 584 585register SEQADDR1 { 586 address 0x063 587 access_mode RW 588 mask SEQADDR1_MASK 0x01 589} 590 591/* 592 * Accumulator 593 * We cheat by passing arguments in the Accumulator up to the kernel driver 594 */ 595register ACCUM { 596 address 0x064 597 access_mode RW 598 accumulator 599} 600 601register SINDEX { 602 address 0x065 603 access_mode RW 604 sindex 605} 606 607register DINDEX { 608 address 0x066 609 access_mode RW 610} 611 612register ALLONES { 613 address 0x069 614 access_mode RO 615 allones 616} 617 618register ALLZEROS { 619 address 0x06a 620 access_mode RO 621 allzeros 622} 623 624register NONE { 625 address 0x06a 626 access_mode WO 627 none 628} 629 630register FLAGS { 631 address 0x06b 632 access_mode RO 633 bit ZERO 0x02 634 bit CARRY 0x01 635} 636 637register SINDIR { 638 address 0x06c 639 access_mode RO 640} 641 642register DINDIR { 643 address 0x06d 644 access_mode WO 645} 646 647register FUNCTION1 { 648 address 0x06e 649 access_mode RW 650} 651 652register STACK { 653 address 0x06f 654 access_mode RO 655} 656 657/* 658 * Board Control (p. 3-43) 659 */ 660register BCTL { 661 address 0x084 662 access_mode RW 663 bit ACE 0x08 664 bit ENABLE 0x01 665} 666 667/* 668 * On the aic78X0 chips, Board Control is replaced by the DSCommand 669 * register (p. 4-64) 670 */ 671register DSCOMMAND0 { 672 address 0x084 673 access_mode RW 674 bit CACHETHEN 0x80 /* Cache Threshold enable */ 675 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 676 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 677 bit EXTREQLCK 0x10 /* External Request Lock */ 678 /* aic7890/91/96/97 only */ 679 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 680 bit RAMPS 0x04 /* External SCB RAM Present */ 681 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 682 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 683} 684 685register DSCOMMAND1 { 686 address 0x085 687 access_mode RW 688 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 689 bit HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 690 bit HADDLDSEL0 0x01 691} 692 693/* 694 * Bus On/Off Time (p. 3-44) aic7770 only 695 */ 696register BUSTIME { 697 address 0x085 698 access_mode RW 699 mask BOFF 0xf0 700 mask BON 0x0f 701} 702 703/* 704 * Bus Speed (p. 3-45) aic7770 only 705 */ 706register BUSSPD { 707 address 0x086 708 access_mode RW 709 mask DFTHRSH 0xc0 710 mask STBOFF 0x38 711 mask STBON 0x07 712 mask DFTHRSH_100 0xc0 713 mask DFTHRSH_75 0x80 714} 715 716/* aic7850/55/60/70/80/95 only */ 717register DSPCISTATUS { 718 address 0x086 719 mask DFTHRSH_100 0xc0 720} 721 722/* aic7890/91/96/97 only */ 723register HS_MAILBOX { 724 address 0x086 725 mask HOST_MAILBOX 0xF0 726 mask SEQ_MAILBOX 0x0F 727 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 728} 729 730const HOST_MAILBOX_SHIFT 4 731const SEQ_MAILBOX_SHIFT 0 732 733/* 734 * Host Control (p. 3-47) R/W 735 * Overall host control of the device. 736 */ 737register HCNTRL { 738 address 0x087 739 access_mode RW 740 bit POWRDN 0x40 741 bit SWINT 0x10 742 bit IRQMS 0x08 743 bit PAUSE 0x04 744 bit INTEN 0x02 745 bit CHIPRST 0x01 746 bit CHIPRSTACK 0x01 747} 748 749/* 750 * Host Address (p. 3-48) 751 * This register contains the address of the byte about 752 * to be transferred across the host bus. 753 */ 754register HADDR { 755 address 0x088 756 size 4 757 access_mode RW 758} 759 760register HCNT { 761 address 0x08c 762 size 3 763 access_mode RW 764} 765 766/* 767 * SCB Pointer (p. 3-49) 768 * Gate one of the SCBs into the SCBARRAY window. 769 */ 770register SCBPTR { 771 address 0x090 772 access_mode RW 773} 774 775/* 776 * Interrupt Status (p. 3-50) 777 * Status for system interrupts 778 */ 779register INTSTAT { 780 address 0x091 781 access_mode RW 782 bit BRKADRINT 0x08 783 bit SCSIINT 0x04 784 bit CMDCMPLT 0x02 785 bit SEQINT 0x01 786 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 787 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 788 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 789 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 790 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 791 mask PDATA_REINIT 0x50|SEQINT /* 792 * Returned to data phase 793 * that requires data 794 * transfer pointers to be 795 * recalculated from the 796 * transfer residual. 797 */ 798 mask HOST_MSG_LOOP 0x60|SEQINT /* 799 * The bus is ready for the 800 * host to perform another 801 * message transaction. This 802 * mechanism is used for things 803 * like sync/wide negotiation 804 * that require a kernel based 805 * message state engine. 806 */ 807 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 808 mask PERR_DETECTED 0x80|SEQINT /* 809 * Either the phase_lock 810 * or inb_next routine has 811 * noticed a parity error. 812 */ 813 mask DATA_OVERRUN 0x90|SEQINT /* 814 * Target attempted to write 815 * beyond the bounds of its 816 * command. 817 */ 818 mask MKMSG_FAILED 0xa0|SEQINT /* 819 * Target completed command 820 * without honoring our ATN 821 * request to issue a message. 822 */ 823 mask MISSED_BUSFREE 0xb0|SEQINT /* 824 * The sequencer never saw 825 * the bus go free after 826 * either a command complete 827 * or disconnect message. 828 */ 829 mask SCB_MISMATCH 0xc0|SEQINT /* 830 * Downloaded SCB's tag does 831 * not match the entry we 832 * intended to download. 833 */ 834 mask NO_FREE_SCB 0xd0|SEQINT /* 835 * get_free_or_disc_scb failed. 836 */ 837 mask OUT_OF_RANGE 0xe0|SEQINT 838 839 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 840 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 841} 842 843/* 844 * Hard Error (p. 3-53) 845 * Reporting of catastrophic errors. You usually cannot recover from 846 * these without a full board reset. 847 */ 848register ERROR { 849 address 0x092 850 access_mode RO 851 bit CIOPARERR 0x80 /* Ultra2 only */ 852 bit PCIERRSTAT 0x40 /* PCI only */ 853 bit MPARERR 0x20 /* PCI only */ 854 bit DPARERR 0x10 /* PCI only */ 855 bit SQPARERR 0x08 856 bit ILLOPCODE 0x04 857 bit ILLSADDR 0x02 858 bit ILLHADDR 0x01 859} 860 861/* 862 * Clear Interrupt Status (p. 3-52) 863 */ 864register CLRINT { 865 address 0x092 866 access_mode WO 867 bit CLRPARERR 0x10 /* PCI only */ 868 bit CLRBRKADRINT 0x08 869 bit CLRSCSIINT 0x04 870 bit CLRCMDINT 0x02 871 bit CLRSEQINT 0x01 872} 873 874register DFCNTRL { 875 address 0x093 876 access_mode RW 877 bit PRELOADEN 0x80 /* aic7890 only */ 878 bit WIDEODD 0x40 879 bit SCSIEN 0x20 880 bit SDMAEN 0x10 881 bit SDMAENACK 0x10 882 bit HDMAEN 0x08 883 bit HDMAENACK 0x08 884 bit DIRECTION 0x04 885 bit FIFOFLUSH 0x02 886 bit FIFORESET 0x01 887} 888 889register DFSTATUS { 890 address 0x094 891 access_mode RO 892 bit PRELOAD_AVAIL 0x80 893 bit DFCACHETH 0x40 894 bit FIFOQWDEMP 0x20 895 bit MREQPEND 0x10 896 bit HDONE 0x08 897 bit DFTHRESH 0x04 898 bit FIFOFULL 0x02 899 bit FIFOEMP 0x01 900} 901 902register DFWADDR { 903 address 0x95 904 access_mode RW 905} 906 907register DFRADDR { 908 address 0x97 909 access_mode RW 910} 911 912register DFDAT { 913 address 0x099 914 access_mode RW 915} 916 917/* 918 * SCB Auto Increment (p. 3-59) 919 * Byte offset into the SCB Array and an optional bit to allow auto 920 * incrementing of the address during download and upload operations 921 */ 922register SCBCNT { 923 address 0x09a 924 access_mode RW 925 bit SCBAUTO 0x80 926 mask SCBCNT_MASK 0x1f 927} 928 929/* 930 * Queue In FIFO (p. 3-60) 931 * Input queue for queued SCBs (commands that the seqencer has yet to start) 932 */ 933register QINFIFO { 934 address 0x09b 935 access_mode RW 936} 937 938/* 939 * Queue In Count (p. 3-60) 940 * Number of queued SCBs 941 */ 942register QINCNT { 943 address 0x09c 944 access_mode RO 945} 946 947/* 948 * Queue Out FIFO (p. 3-61) 949 * Queue of SCBs that have completed and await the host 950 */ 951register QOUTFIFO { 952 address 0x09d 953 access_mode WO 954} 955 956register CRCCONTROL1 { 957 address 0x09d 958 access_mode RW 959 bit CRCONSEEN 0x80 960 bit CRCVALCHKEN 0x40 961 bit CRCENDCHKEN 0x20 962 bit CRCREQCHKEN 0x10 963 bit TARGCRCENDEN 0x08 964 bit TARGCRCCNTEN 0x04 965} 966 967 968/* 969 * Queue Out Count (p. 3-61) 970 * Number of queued SCBs in the Out FIFO 971 */ 972register QOUTCNT { 973 address 0x09e 974 access_mode RO 975} 976 977register SCSIPHASE { 978 address 0x09e 979 access_mode RO 980 bit STATUS_PHASE 0x20 981 bit COMMAND_PHASE 0x10 982 bit MSG_IN_PHASE 0x08 983 bit MSG_OUT_PHASE 0x04 984 bit DATA_IN_PHASE 0x02 985 bit DATA_OUT_PHASE 0x01 986 mask DATA_PHASE_MASK 0x03 987} 988 989/* 990 * Special Function 991 */ 992register SFUNCT { 993 address 0x09f 994 access_mode RW 995 bit ALT_MODE 0x80 996} 997 998/* 999 * SCB Definition (p. 5-4) 1000 */ 1001scb { 1002 address 0x0a0 1003 SCB_CDB_PTR { 1004 size 4 1005 alias SCB_RESIDUAL_DATACNT 1006 alias SCB_CDB_STORE 1007 alias SCB_TARGET_INFO 1008 } 1009 SCB_RESIDUAL_SGPTR { 1010 size 4 1011 } 1012 SCB_SCSI_STATUS { 1013 size 1 1014 } 1015 SCB_CDB_STORE_PAD { 1016 size 3 1017 } 1018 SCB_DATAPTR { 1019 size 4 1020 } 1021 SCB_DATACNT { 1022 /* 1023 * The last byte is really the high address bits for 1024 * the data address. 1025 */ 1026 size 4 1027 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 1028 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1029 } 1030 SCB_SGPTR { 1031 size 4 1032 bit SG_RESID_VALID 0x04 /* In the first byte */ 1033 bit SG_FULL_RESID 0x02 /* In the first byte */ 1034 bit SG_LIST_NULL 0x01 /* In the first byte */ 1035 } 1036 SCB_CONTROL { 1037 size 1 1038 bit TARGET_SCB 0x80 1039 bit DISCENB 0x40 1040 bit TAG_ENB 0x20 1041 bit MK_MESSAGE 0x10 1042 bit ULTRAENB 0x08 1043 bit DISCONNECTED 0x04 1044 mask SCB_TAG_TYPE 0x03 1045 } 1046 SCB_SCSIID { 1047 size 1 1048 bit TWIN_CHNLB 0x80 1049 mask TWIN_TID 0x70 1050 mask TID 0xf0 1051 mask OID 0x0f 1052 } 1053 SCB_LUN { 1054 mask LID 0xff 1055 size 1 1056 } 1057 SCB_TAG { 1058 size 1 1059 } 1060 SCB_CDB_LEN { 1061 size 1 1062 } 1063 SCB_SCSIRATE { 1064 size 1 1065 } 1066 SCB_SCSIOFFSET { 1067 size 1 1068 } 1069 SCB_NEXT { 1070 size 1 1071 } 1072 SCB_64_SPARE { 1073 size 16 1074 } 1075 SCB_64_BTT { 1076 size 16 1077 } 1078} 1079 1080const SCB_UPLOAD_SIZE 32 1081const SCB_DOWNLOAD_SIZE 32 1082const SCB_DOWNLOAD_SIZE_64 48 1083 1084const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1085 1086/* --------------------- AHA-2840-only definitions -------------------- */ 1087 1088register SEECTL_2840 { 1089 address 0x0c0 1090 access_mode RW 1091 bit CS_2840 0x04 1092 bit CK_2840 0x02 1093 bit DO_2840 0x01 1094} 1095 1096register STATUS_2840 { 1097 address 0x0c1 1098 access_mode RW 1099 bit EEPROM_TF 0x80 1100 mask BIOS_SEL 0x60 1101 mask ADSEL 0x1e 1102 bit DI_2840 0x01 1103} 1104 1105/* --------------------- AIC-7870-only definitions -------------------- */ 1106 1107register CCHADDR { 1108 address 0x0E0 1109 size 8 1110} 1111 1112register CCHCNT { 1113 address 0x0E8 1114} 1115 1116register CCSGRAM { 1117 address 0x0E9 1118} 1119 1120register CCSGADDR { 1121 address 0x0EA 1122} 1123 1124register CCSGCTL { 1125 address 0x0EB 1126 bit CCSGDONE 0x80 1127 bit CCSGEN 0x08 1128 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1129 bit CCSGRESET 0x01 1130} 1131 1132register CCSCBCNT { 1133 address 0xEF 1134} 1135 1136register CCSCBCTL { 1137 address 0x0EE 1138 bit CCSCBDONE 0x80 1139 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1140 bit CCARREN 0x10 1141 bit CCSCBEN 0x08 1142 bit CCSCBDIR 0x04 1143 bit CCSCBRESET 0x01 1144} 1145 1146register CCSCBADDR { 1147 address 0x0ED 1148} 1149 1150register CCSCBRAM { 1151 address 0xEC 1152} 1153 1154/* 1155 * SCB bank address (7895/7896/97 only) 1156 */ 1157register SCBBADDR { 1158 address 0x0F0 1159 access_mode RW 1160} 1161 1162register CCSCBPTR { 1163 address 0x0F1 1164} 1165 1166register HNSCB_QOFF { 1167 address 0x0F4 1168} 1169 1170register SNSCB_QOFF { 1171 address 0x0F6 1172} 1173 1174register SDSCB_QOFF { 1175 address 0x0F8 1176} 1177 1178register QOFF_CTLSTA { 1179 address 0x0FA 1180 bit SCB_AVAIL 0x40 1181 bit SNSCB_ROLLOVER 0x20 1182 bit SDSCB_ROLLOVER 0x10 1183 mask SCB_QSIZE 0x07 1184 mask SCB_QSIZE_256 0x06 1185} 1186 1187register DFF_THRSH { 1188 address 0x0FB 1189 mask WR_DFTHRSH 0x70 1190 mask RD_DFTHRSH 0x07 1191 mask RD_DFTHRSH_MIN 0x00 1192 mask RD_DFTHRSH_25 0x01 1193 mask RD_DFTHRSH_50 0x02 1194 mask RD_DFTHRSH_63 0x03 1195 mask RD_DFTHRSH_75 0x04 1196 mask RD_DFTHRSH_85 0x05 1197 mask RD_DFTHRSH_90 0x06 1198 mask RD_DFTHRSH_MAX 0x07 1199 mask WR_DFTHRSH_MIN 0x00 1200 mask WR_DFTHRSH_25 0x10 1201 mask WR_DFTHRSH_50 0x20 1202 mask WR_DFTHRSH_63 0x30 1203 mask WR_DFTHRSH_75 0x40 1204 mask WR_DFTHRSH_85 0x50 1205 mask WR_DFTHRSH_90 0x60 1206 mask WR_DFTHRSH_MAX 0x70 1207} 1208 1209register SG_CACHE_PRE { 1210 access_mode WO 1211 address 0x0fc 1212 mask SG_ADDR_MASK 0xf8 1213 bit ODD_SEG 0x04 1214 bit LAST_SEG 0x02 1215 bit LAST_SEG_DONE 0x01 1216} 1217 1218register SG_CACHE_SHADOW { 1219 access_mode RO 1220 address 0x0fc 1221 mask SG_ADDR_MASK 0xf8 1222 bit ODD_SEG 0x04 1223 bit LAST_SEG 0x02 1224 bit LAST_SEG_DONE 0x01 1225} 1226/* ---------------------- Scratch RAM Offsets ------------------------- */ 1227/* These offsets are either to values that are initialized by the board's 1228 * BIOS or are specified by the sequencer code. 1229 * 1230 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1231 * device information, 32-33 and 5a-5f as well. As it turns out, the 1232 * BIOS trashes 20-2f, writing the synchronous negotiation results 1233 * on top of the BIOS values, so we re-use those for our per-target 1234 * scratchspace (actually a value that can be copied directly into 1235 * SCSIRATE). The kernel driver will enable synchronous negotiation 1236 * for all targets that have a value other than 0 in the lower four 1237 * bits of the target scratch space. This should work regardless of 1238 * whether the bios has been installed. 1239 */ 1240 1241scratch_ram { 1242 address 0x020 1243 1244 /* 1245 * 1 byte per target starting at this address for configuration values 1246 */ 1247 BUSY_TARGETS { 1248 alias TARG_SCSIRATE 1249 size 16 1250 } 1251 /* 1252 * Bit vector of targets that have ULTRA enabled as set by 1253 * the BIOS. The Sequencer relies on a per-SCB field to 1254 * control whether to enable Ultra transfers or not. During 1255 * initialization, we read this field and reuse it for 2 1256 * entries in the busy target table. 1257 */ 1258 ULTRA_ENB { 1259 alias CMDSIZE_TABLE 1260 size 2 1261 } 1262 /* 1263 * Bit vector of targets that have disconnection disabled as set by 1264 * the BIOS. The Sequencer relies in a per-SCB field to control the 1265 * disconnect priveldge. During initialization, we read this field 1266 * and reuse it for 2 entries in the busy target table. 1267 */ 1268 DISC_DSB { 1269 size 2 1270 } 1271 CMDSIZE_TABLE_TAIL { 1272 size 4 1273 } 1274 /* 1275 * Partial transfer past cacheline end to be 1276 * transferred using an extra S/G. 1277 */ 1278 MWI_RESIDUAL { 1279 size 1 1280 } 1281 /* 1282 * SCBID of the next SCB to be started by the controller. 1283 */ 1284 NEXT_QUEUED_SCB { 1285 size 1 1286 } 1287 /* 1288 * Single byte buffer used to designate the type or message 1289 * to send to a target. 1290 */ 1291 MSG_OUT { 1292 size 1 1293 } 1294 /* Parameters for DMA Logic */ 1295 DMAPARAMS { 1296 size 1 1297 bit PRELOADEN 0x80 1298 bit WIDEODD 0x40 1299 bit SCSIEN 0x20 1300 bit SDMAEN 0x10 1301 bit SDMAENACK 0x10 1302 bit HDMAEN 0x08 1303 bit HDMAENACK 0x08 1304 bit DIRECTION 0x04 1305 bit FIFOFLUSH 0x02 1306 bit FIFORESET 0x01 1307 } 1308 SEQ_FLAGS { 1309 size 1 1310 bit IDENTIFY_SEEN 0x80 1311 bit TARGET_CMD_IS_TAGGED 0x40 1312 bit DPHASE 0x20 1313 /* Target flags */ 1314 bit TARG_CMD_PENDING 0x10 1315 bit CMDPHASE_PENDING 0x08 1316 bit DPHASE_PENDING 0x04 1317 bit SPHASE_PENDING 0x02 1318 bit NO_DISCONNECT 0x01 1319 } 1320 /* 1321 * Temporary storage for the 1322 * target/channel/lun of a 1323 * reconnecting target 1324 */ 1325 SAVED_SCSIID { 1326 size 1 1327 } 1328 SAVED_LUN { 1329 size 1 1330 } 1331 /* 1332 * The last bus phase as seen by the sequencer. 1333 */ 1334 LASTPHASE { 1335 size 1 1336 bit CDI 0x80 1337 bit IOI 0x40 1338 bit MSGI 0x20 1339 mask PHASE_MASK CDI|IOI|MSGI 1340 mask P_DATAOUT 0x00 1341 mask P_DATAIN IOI 1342 mask P_COMMAND CDI 1343 mask P_MESGOUT CDI|MSGI 1344 mask P_STATUS CDI|IOI 1345 mask P_MESGIN CDI|IOI|MSGI 1346 mask P_BUSFREE 0x01 1347 } 1348 /* 1349 * head of list of SCBs awaiting 1350 * selection 1351 */ 1352 WAITING_SCBH { 1353 size 1 1354 } 1355 /* 1356 * head of list of SCBs that are 1357 * disconnected. Used for SCB 1358 * paging. 1359 */ 1360 DISCONNECTED_SCBH { 1361 size 1 1362 } 1363 /* 1364 * head of list of SCBs that are 1365 * not in use. Used for SCB paging. 1366 */ 1367 FREE_SCBH { 1368 size 1 1369 } 1370 /* 1371 * head of list of SCBs that have 1372 * completed but have not been 1373 * put into the qoutfifo. 1374 */ 1375 COMPLETE_SCBH { 1376 size 1 1377 } 1378 /* 1379 * Address of the hardware scb array in the host. 1380 */ 1381 HSCB_ADDR { 1382 size 4 1383 } 1384 /* 1385 * Base address of our shared data with the kernel driver in host 1386 * memory. This includes the qoutfifo and target mode 1387 * incoming command queue. 1388 */ 1389 SHARED_DATA_ADDR { 1390 size 4 1391 } 1392 KERNEL_QINPOS { 1393 size 1 1394 } 1395 QINPOS { 1396 size 1 1397 } 1398 QOUTPOS { 1399 size 1 1400 } 1401 /* 1402 * Kernel and sequencer offsets into the queue of 1403 * incoming target mode command descriptors. The 1404 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1405 */ 1406 KERNEL_TQINPOS { 1407 size 1 1408 } 1409 TQINPOS { 1410 size 1 1411 } 1412 ARG_1 { 1413 size 1 1414 mask SEND_MSG 0x80 1415 mask SEND_SENSE 0x40 1416 mask SEND_REJ 0x20 1417 mask MSGOUT_PHASEMIS 0x10 1418 mask EXIT_MSG_LOOP 0x08 1419 mask CONT_MSG_LOOP 0x04 1420 mask CONT_TARG_SESSION 0x02 1421 alias RETURN_1 1422 } 1423 ARG_2 { 1424 size 1 1425 alias RETURN_2 1426 } 1427 1428 /* 1429 * Snapshot of MSG_OUT taken after each message is sent. 1430 */ 1431 LAST_MSG { 1432 size 1 1433 } 1434 1435 /* 1436 * Sequences the kernel driver has okayed for us. This allows 1437 * the driver to do things like prevent initiator or target 1438 * operations. 1439 */ 1440 SCSISEQ_TEMPLATE { 1441 size 1 1442 bit ENSELO 0x40 1443 bit ENSELI 0x20 1444 bit ENRSELI 0x10 1445 bit ENAUTOATNO 0x08 1446 bit ENAUTOATNI 0x04 1447 bit ENAUTOATNP 0x02 1448 } 1449 1450 /* 1451 * Track whether the transfer byte count for 1452 * the current data phase is odd. 1453 */ 1454 DATA_COUNT_ODD { 1455 size 1 1456 } 1457 1458 /* 1459 * The initiator specified tag for this target mode transaction. 1460 */ 1461 INITIATOR_TAG { 1462 size 1 1463 } 1464 1465 SEQ_FLAGS2 { 1466 size 1 1467 bit SCB_DMA 0x01 1468 } 1469 /* 1470 * These are reserved registers in the card's scratch ram. Some of 1471 * the values are specified in the AHA2742 technical reference manual 1472 * and are initialized by the BIOS at boot time. 1473 */ 1474 SCSICONF { 1475 address 0x05a 1476 size 1 1477 bit TERM_ENB 0x80 1478 bit RESET_SCSI 0x40 1479 bit ENSPCHK 0x20 1480 mask HSCSIID 0x07 /* our SCSI ID */ 1481 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1482 } 1483 INTDEF { 1484 address 0x05c 1485 size 1 1486 bit EDGE_TRIG 0x80 1487 mask VECTOR 0x0f 1488 } 1489 HOSTCONF { 1490 address 0x05d 1491 size 1 1492 } 1493 HA_274_BIOSCTRL { 1494 address 0x05f 1495 size 1 1496 mask BIOSMODE 0x30 1497 mask BIOSDISABLED 0x30 1498 bit CHANNEL_B_PRIMARY 0x08 1499 } 1500 /* 1501 * Per target SCSI offset values for Ultra2 controllers. 1502 */ 1503 TARG_OFFSET { 1504 address 0x070 1505 size 16 1506 } 1507} 1508 1509const TID_SHIFT 4 1510const SCB_LIST_NULL 0xff 1511const TARGET_CMD_CMPLT 0xfe 1512 1513const CCSGADDR_MAX 0x80 1514const CCSGRAM_MAXSEGS 16 1515 1516/* WDTR Message values */ 1517const BUS_8_BIT 0x00 1518const BUS_16_BIT 0x01 1519const BUS_32_BIT 0x02 1520 1521/* Offset maximums */ 1522const MAX_OFFSET_8BIT 0x0f 1523const MAX_OFFSET_16BIT 0x08 1524const MAX_OFFSET_ULTRA2 0x7f 1525const HOST_MSG 0xff 1526 1527/* Target mode command processing constants */ 1528const CMD_GROUP_CODE_SHIFT 0x05 1529 1530const STATUS_BUSY 0x08 1531const STATUS_QUEUE_FULL 0x28 1532const SCB_TARGET_PHASES 0 1533const SCB_TARGET_DATA_DIR 1 1534const SCB_TARGET_STATUS 2 1535const SCB_INITIATOR_TAG 3 1536const TARGET_DATA_IN 1 1537 1538/* 1539 * Downloaded (kernel inserted) constants 1540 */ 1541/* Offsets into the SCBID array where different data is stored */ 1542const QOUTFIFO_OFFSET download 1543const QINFIFO_OFFSET download 1544const CACHESIZE_MASK download 1545const INVERTED_CACHESIZE_MASK download 1546const SG_PREFETCH_CNT download 1547const SG_PREFETCH_ALIGN_MASK download 1548const SG_PREFETCH_ADDR_MASK download 1549