1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifndef _AIC7XXX_H_ 46 #define _AIC7XXX_H_ 47 48 /* Register Definitions */ 49 #include "aic7xxx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahc_platform_data; 53 struct scb_platform_data; 54 struct seeprom_descriptor; 55 56 /****************************** Useful Macros *********************************/ 57 #ifndef MAX 58 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59 #endif 60 61 #ifndef MIN 62 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63 #endif 64 65 #ifndef TRUE 66 #define TRUE 1 67 #endif 68 #ifndef FALSE 69 #define FALSE 0 70 #endif 71 72 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74 #define ALL_CHANNELS '\0' 75 #define ALL_TARGETS_MASK 0xFFFF 76 #define INITIATOR_WILDCARD (~0) 77 78 #define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81 #define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83 #define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89 #define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91 #define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93 #define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95 #define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun & LID) 97 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99 #define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101 #ifdef AHC_DEBUG 102 #define SCB_IS_SILENT(scb) \ 103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105 #else 106 #define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108 #endif 109 #define TCL_TARGET_OFFSET(tcl) \ 110 ((((tcl) >> 4) & TID) >> 4) 111 #define TCL_LUN(tcl) \ 112 (tcl & (AHC_NUM_LUNS - 1)) 113 #define BUILD_TCL(scsiid, lun) \ 114 ((lun) | (((scsiid) & TID) << 4)) 115 116 #ifndef AHC_TARGET_MODE 117 #undef AHC_TMODE_ENABLE 118 #define AHC_TMODE_ENABLE 0 119 #endif 120 121 /**************************** Driver Constants ********************************/ 122 /* 123 * The maximum number of supported targets. 124 */ 125 #define AHC_NUM_TARGETS 16 126 127 /* 128 * The maximum number of supported luns. 129 * The identify message only supports 64 luns in SPI3. 130 * You can have 2^64 luns when information unit transfers are enabled, 131 * but it is doubtful this driver will ever support IUTs. 132 */ 133 #define AHC_NUM_LUNS 64 134 135 /* 136 * The maximum transfer per S/G segment. 137 */ 138 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 139 140 /* 141 * The maximum amount of SCB storage in hardware on a controller. 142 * This value represents an upper bound. Controllers vary in the number 143 * they actually support. 144 */ 145 #define AHC_SCB_MAX 255 146 147 /* 148 * The maximum number of concurrent transactions supported per driver instance. 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 150 * the space for SCBs on the host adapter varies by model, the driver will 151 * page the SCBs between host and controller memory as needed. We are limited 152 * to 253 because: 153 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 154 * 2) We reserve one value, 255, to represent the invalid element. 155 * 3) Our input queue scheme requires one SCB to always be reserved 156 * in advance of queuing any SCBs. This takes us down to 254. 157 * 4) To handle our output queue correctly on machines that only 158 * support 32bit stores, we must clear the array 4 bytes at a 159 * time. To avoid colliding with a DMA write from the sequencer, 160 * we must be sure that 4 slots are empty when we write to clear 161 * the queue. This reduces us to 253 SCBs: 1 that just completed 162 * and the known three additional empty slots in the queue that 163 * precede it. 164 */ 165 #define AHC_MAX_QUEUE 253 166 167 /* 168 * The maximum amount of SCB storage we allocate in host memory. This 169 * number should reflect the 1 additional SCB we require to handle our 170 * qinfifo mechanism. 171 */ 172 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 173 174 /* 175 * Ring Buffer of incoming target commands. 176 * We allocate 256 to simplify the logic in the sequencer 177 * by using the natural wrap point of an 8bit counter. 178 */ 179 #define AHC_TMODE_CMDS 256 180 181 /* Reset line assertion time in us */ 182 #define AHC_BUSRESET_DELAY 25 183 184 /******************* Chip Characteristics/Operating Settings *****************/ 185 /* 186 * Chip Type 187 * The chip order is from least sophisticated to most sophisticated. 188 */ 189 typedef enum { 190 AHC_NONE = 0x0000, 191 AHC_CHIPID_MASK = 0x00FF, 192 AHC_AIC7770 = 0x0001, 193 AHC_AIC7850 = 0x0002, 194 AHC_AIC7855 = 0x0003, 195 AHC_AIC7859 = 0x0004, 196 AHC_AIC7860 = 0x0005, 197 AHC_AIC7870 = 0x0006, 198 AHC_AIC7880 = 0x0007, 199 AHC_AIC7895 = 0x0008, 200 AHC_AIC7895C = 0x0009, 201 AHC_AIC7890 = 0x000a, 202 AHC_AIC7896 = 0x000b, 203 AHC_AIC7892 = 0x000c, 204 AHC_AIC7899 = 0x000d, 205 AHC_VL = 0x0100, /* Bus type VL */ 206 AHC_EISA = 0x0200, /* Bus type EISA */ 207 AHC_PCI = 0x0400, /* Bus type PCI */ 208 AHC_BUS_MASK = 0x0F00 209 } ahc_chip; 210 211 /* 212 * Features available in each chip type. 213 */ 214 typedef enum { 215 AHC_FENONE = 0x00000, 216 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 217 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 218 AHC_WIDE = 0x00004, /* Wide Channel */ 219 AHC_TWIN = 0x00008, /* Twin Channel */ 220 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 221 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 222 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 223 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 224 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 225 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 226 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 227 AHC_DT = 0x00800, /* Double Transition transfers */ 228 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 229 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 230 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 231 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 232 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 233 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 234 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 235 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 236 AHC_AIC7770_FE = AHC_FENONE, 237 /* 238 * The real 7850 does not support Ultra modes, but there are 239 * several cards that use the generic 7850 PCI ID even though 240 * they are using an Ultra capable chip (7859/7860). We start 241 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 242 * register to determine if the capability is really present. 243 */ 244 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 245 AHC_AIC7860_FE = AHC_AIC7850_FE, 246 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 247 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 248 /* 249 * Although we have space for both the initiator and 250 * target roles on ULTRA2 chips, we currently disable 251 * the initiator role to allow multi-scsi-id target mode 252 * configurations. We can only respond on the same SCSI 253 * ID as our initiator role if we allow initiator operation. 254 * At some point, we should add a configuration knob to 255 * allow both roles to be loaded. 256 */ 257 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 258 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 259 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 260 |AHC_TARGETMODE, 261 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 262 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 263 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 264 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 265 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 266 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 267 } ahc_feature; 268 269 /* 270 * Bugs in the silicon that we work around in software. 271 */ 272 typedef enum { 273 AHC_BUGNONE = 0x00, 274 /* 275 * On all chips prior to the U2 product line, 276 * the WIDEODD S/G segment feature does not 277 * work during scsi->HostBus transfers. 278 */ 279 AHC_TMODE_WIDEODD_BUG = 0x01, 280 /* 281 * On the aic7890/91 Rev 0 chips, the autoflush 282 * feature does not work. A manual flush of 283 * the DMA FIFO is required. 284 */ 285 AHC_AUTOFLUSH_BUG = 0x02, 286 /* 287 * On many chips, cacheline streaming does not work. 288 */ 289 AHC_CACHETHEN_BUG = 0x04, 290 /* 291 * On the aic7896/97 chips, cacheline 292 * streaming must be enabled. 293 */ 294 AHC_CACHETHEN_DIS_BUG = 0x08, 295 /* 296 * PCI 2.1 Retry failure on non-empty data fifo. 297 */ 298 AHC_PCI_2_1_RETRY_BUG = 0x10, 299 /* 300 * Controller does not handle cacheline residuals 301 * properly on S/G segments if PCI MWI instructions 302 * are allowed. 303 */ 304 AHC_PCI_MWI_BUG = 0x20, 305 /* 306 * An SCB upload using the SCB channel's 307 * auto array entry copy feature may 308 * corrupt data. This appears to only 309 * occur on 66MHz systems. 310 */ 311 AHC_SCBCHAN_UPLOAD_BUG = 0x40 312 } ahc_bug; 313 314 /* 315 * Configuration specific settings. 316 * The driver determines these settings by probing the 317 * chip/controller's configuration. 318 */ 319 typedef enum { 320 AHC_FNONE = 0x000, 321 AHC_PRIMARY_CHANNEL = 0x003, /* 322 * The channel that should 323 * be probed first. 324 */ 325 AHC_USEDEFAULTS = 0x004, /* 326 * For cards without an seeprom 327 * or a BIOS to initialize the chip's 328 * SRAM, we use the default target 329 * settings. 330 */ 331 AHC_SEQUENCER_DEBUG = 0x008, 332 AHC_SHARED_SRAM = 0x010, 333 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 334 AHC_RESET_BUS_A = 0x040, 335 AHC_RESET_BUS_B = 0x080, 336 AHC_EXTENDED_TRANS_A = 0x100, 337 AHC_EXTENDED_TRANS_B = 0x200, 338 AHC_TERM_ENB_A = 0x400, 339 AHC_TERM_ENB_B = 0x800, 340 AHC_INITIATORROLE = 0x1000, /* 341 * Allow initiator operations on 342 * this controller. 343 */ 344 AHC_TARGETROLE = 0x2000, /* 345 * Allow target operations on this 346 * controller. 347 */ 348 AHC_NEWEEPROM_FMT = 0x4000, 349 AHC_RESOURCE_SHORTAGE = 0x8000, 350 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 351 AHC_INT50_SPEEDFLEX = 0x20000, /* 352 * Internal 50pin connector 353 * sits behind an aic3860 354 */ 355 AHC_SCB_BTT = 0x40000, /* 356 * The busy targets table is 357 * stored in SCB space rather 358 * than SRAM. 359 */ 360 AHC_BIOS_ENABLED = 0x80000, 361 AHC_ALL_INTERRUPTS = 0x100000, 362 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 363 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 364 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 365 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 366 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 367 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 368 AHC_DISABLE_PCI_PERR = 0x10000000, 369 AHC_HAS_TERM_LOGIC = 0x20000000, 370 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 371 } ahc_flag; 372 373 /************************* Hardware SCB Definition ***************************/ 374 375 /* 376 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 377 * consists of a "hardware SCB" mirroring the fields available on the card 378 * and additional information the kernel stores for each transaction. 379 * 380 * To minimize space utilization, a portion of the hardware scb stores 381 * different data during different portions of a SCSI transaction. 382 * As initialized by the host driver for the initiator role, this area 383 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 384 * the cdb has been presented to the target, this area serves to store 385 * residual transfer information and the SCSI status byte. 386 * For the target role, the contents of this area do not change, but 387 * still serve a different purpose than for the initiator role. See 388 * struct target_data for details. 389 */ 390 391 /* 392 * Status information embedded in the shared poriton of 393 * an SCB after passing the cdb to the target. The kernel 394 * driver will only read this data for transactions that 395 * complete abnormally (non-zero status byte). 396 */ 397 struct status_pkt { 398 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 399 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 400 uint8_t scsi_status; /* Standard SCSI status byte */ 401 }; 402 403 /* 404 * Target mode version of the shared data SCB segment. 405 */ 406 struct target_data { 407 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 408 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 409 uint8_t scsi_status; /* SCSI status to give to initiator */ 410 uint8_t target_phases; /* Bitmap of phases to execute */ 411 uint8_t data_phase; /* Data-In or Data-Out */ 412 uint8_t initiator_tag; /* Initiator's transaction tag */ 413 }; 414 415 #define MAX_CDB_LEN 16 416 struct hardware_scb { 417 /*0*/ union { 418 /* 419 * If the cdb is 12 bytes or less, we embed it directly 420 * in the SCB. For longer cdbs, we embed the address 421 * of the cdb payload as seen by the chip and a DMA 422 * is used to pull it in. 423 */ 424 uint8_t cdb[12]; 425 uint32_t cdb_ptr; 426 struct status_pkt status; 427 struct target_data tdata; 428 } shared_data; 429 /* 430 * A word about residuals. 431 * The scb is presented to the sequencer with the dataptr and datacnt 432 * fields initialized to the contents of the first S/G element to 433 * transfer. The sgptr field is initialized to the bus address for 434 * the S/G element that follows the first in the in core S/G array 435 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 436 * S/G entry for this transfer (single S/G element transfer with the 437 * first elements address and length preloaded in the dataptr/datacnt 438 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 439 * The SG_FULL_RESID flag ensures that the residual will be correctly 440 * noted even if no data transfers occur. Once the data phase is entered, 441 * the residual sgptr and datacnt are loaded from the sgptr and the 442 * datacnt fields. After each S/G element's dataptr and length are 443 * loaded into the hardware, the residual sgptr is advanced. After 444 * each S/G element is expired, its datacnt field is checked to see 445 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 446 * residual sg ptr and the transfer is considered complete. If the 447 * sequencer determines that there is a residual in the tranfer, it 448 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 449 * host memory. To sumarize: 450 * 451 * Sequencer: 452 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 453 * or residual_sgptr does not have SG_LIST_NULL set. 454 * 455 * o We are transfering the last segment if residual_datacnt has 456 * the SG_LAST_SEG flag set. 457 * 458 * Host: 459 * o A residual has occurred if a completed scb has the 460 * SG_RESID_VALID flag set. 461 * 462 * o residual_sgptr and sgptr refer to the "next" sg entry 463 * and so may point beyond the last valid sg entry for the 464 * transfer. 465 */ 466 /*12*/ uint32_t dataptr; 467 /*16*/ uint32_t datacnt; /* 468 * Byte 3 (numbered from 0) of 469 * the datacnt is really the 470 * 4th byte in that data address. 471 */ 472 /*20*/ uint32_t sgptr; 473 #define SG_PTR_MASK 0xFFFFFFF8 474 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 475 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 476 /*26*/ uint8_t lun; 477 /*27*/ uint8_t tag; /* 478 * Index into our kernel SCB array. 479 * Also used as the tag for tagged I/O 480 */ 481 /*28*/ uint8_t cdb_len; 482 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 483 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 484 /*31*/ uint8_t next; /* 485 * Used for threading SCBs in the 486 * "Waiting for Selection" and 487 * "Disconnected SCB" lists down 488 * in the sequencer. 489 */ 490 /*32*/ uint8_t cdb32[32]; /* 491 * CDB storage for cdbs of size 492 * 13->32. We store them here 493 * because hardware scbs are 494 * allocated from DMA safe 495 * memory so we are guaranteed 496 * the controller can access 497 * this data. 498 */ 499 }; 500 501 /************************ Kernel SCB Definitions ******************************/ 502 /* 503 * Some fields of the SCB are OS dependent. Here we collect the 504 * definitions for elements that all OS platforms need to include 505 * in there SCB definition. 506 */ 507 508 /* 509 * Definition of a scatter/gather element as transfered to the controller. 510 * The aic7xxx chips only support a 24bit length. We use the top byte of 511 * the length to store additional address bits and a flag to indicate 512 * that a given segment terminates the transfer. This gives us an 513 * addressable range of 512GB on machines with 64bit PCI or with chips 514 * that can support dual address cycles on 32bit PCI busses. 515 */ 516 struct ahc_dma_seg { 517 uint32_t addr; 518 uint32_t len; 519 #define AHC_DMA_LAST_SEG 0x80000000 520 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 521 #define AHC_SG_LEN_MASK 0x00FFFFFF 522 }; 523 524 struct sg_map_node { 525 bus_dmamap_t sg_dmamap; 526 bus_addr_t sg_physaddr; 527 struct ahc_dma_seg* sg_vaddr; 528 SLIST_ENTRY(sg_map_node) links; 529 }; 530 531 /* 532 * The current state of this SCB. 533 */ 534 typedef enum { 535 SCB_FLAG_NONE = 0x0000, 536 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 537 * Another device was active 538 * during the first timeout for 539 * this SCB so we gave ourselves 540 * an additional timeout period 541 * in case it was hogging the 542 * bus. 543 */ 544 SCB_DEVICE_RESET = 0x0004, 545 SCB_SENSE = 0x0008, 546 SCB_CDB32_PTR = 0x0010, 547 SCB_RECOVERY_SCB = 0x0020, 548 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 549 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 550 SCB_ABORT = 0x0100, 551 SCB_UNTAGGEDQ = 0x0200, 552 SCB_ACTIVE = 0x0400, 553 SCB_TARGET_IMMEDIATE = 0x0800, 554 SCB_TRANSMISSION_ERROR = 0x1000,/* 555 * We detected a parity or CRC 556 * error that has effected the 557 * payload of the command. This 558 * flag is checked when normal 559 * status is returned to catch 560 * the case of a target not 561 * responding to our attempt 562 * to report the error. 563 */ 564 SCB_TARGET_SCB = 0x2000, 565 SCB_SILENT = 0x4000,/* 566 * Be quiet about transmission type 567 * errors. They are expected and we 568 * don't want to upset the user. This 569 * flag is typically used during DV. 570 */ 571 SCB_TIMEDOUT = 0x8000 /* 572 * SCB has timed out and is on the 573 * timedout list. 574 */ 575 } scb_flag; 576 577 struct scb { 578 struct hardware_scb *hscb; 579 union { 580 SLIST_ENTRY(scb) sle; 581 TAILQ_ENTRY(scb) tqe; 582 } links; 583 LIST_ENTRY(scb) pending_links; 584 LIST_ENTRY(scb) timedout_links; 585 aic_io_ctx_t io_ctx; 586 struct ahc_softc *ahc_softc; 587 scb_flag flags; 588 #ifndef __linux__ 589 bus_dmamap_t dmamap; 590 #endif 591 struct scb_platform_data *platform_data; 592 struct sg_map_node *sg_map; 593 struct ahc_dma_seg *sg_list; 594 bus_addr_t sg_list_phys; 595 u_int sg_count;/* How full ahc_dma_seg is */ 596 }; 597 598 struct scb_data { 599 SLIST_HEAD(, scb) free_scbs; /* 600 * Pool of SCBs ready to be assigned 601 * commands to execute. 602 */ 603 struct scb *scbindex[256]; /* 604 * Mapping from tag to SCB. 605 * As tag identifiers are an 606 * 8bit value, we provide space 607 * for all possible tag values. 608 * Any lookups to entries at or 609 * above AHC_SCB_MAX_ALLOC will 610 * always fail. 611 */ 612 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 613 struct scb *scbarray; /* Array of kernel SCBs */ 614 struct scsi_sense_data *sense; /* Per SCB sense data */ 615 616 /* 617 * "Bus" addresses of our data structures. 618 */ 619 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 620 bus_dmamap_t hscb_dmamap; 621 bus_addr_t hscb_busaddr; 622 bus_dma_tag_t sense_dmat; 623 bus_dmamap_t sense_dmamap; 624 bus_addr_t sense_busaddr; 625 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 626 SLIST_HEAD(, sg_map_node) sg_maps; 627 uint8_t numscbs; 628 uint8_t maxhscbs; /* Number of SCBs on the card */ 629 uint8_t init_level; /* 630 * How far we've initialized 631 * this structure. 632 */ 633 }; 634 635 /************************ Target Mode Definitions *****************************/ 636 637 /* 638 * Connection desciptor for select-in requests in target mode. 639 */ 640 struct target_cmd { 641 uint8_t scsiid; /* Our ID and the initiator's ID */ 642 uint8_t identify; /* Identify message */ 643 uint8_t bytes[22]; /* 644 * Bytes contains any additional message 645 * bytes terminated by 0xFF. The remainder 646 * is the cdb to execute. 647 */ 648 uint8_t cmd_valid; /* 649 * When a command is complete, the firmware 650 * will set cmd_valid to all bits set. 651 * After the host has seen the command, 652 * the bits are cleared. This allows us 653 * to just peek at host memory to determine 654 * if more work is complete. cmd_valid is on 655 * an 8 byte boundary to simplify setting 656 * it on aic7880 hardware which only has 657 * limited direct access to the DMA FIFO. 658 */ 659 uint8_t pad[7]; 660 }; 661 662 /* 663 * Number of events we can buffer up if we run out 664 * of immediate notify ccbs. 665 */ 666 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 667 struct ahc_tmode_event { 668 uint8_t initiator_id; 669 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 670 #define EVENT_TYPE_BUS_RESET 0xFF 671 uint8_t event_arg; 672 }; 673 674 /* 675 * Per enabled lun target mode state. 676 * As this state is directly influenced by the host OS'es target mode 677 * environment, we let the OS module define it. Forward declare the 678 * structure here so we can store arrays of them, etc. in OS neutral 679 * data structures. 680 */ 681 #ifdef AHC_TARGET_MODE 682 struct ahc_tmode_lstate { 683 struct cam_path *path; 684 struct ccb_hdr_slist accept_tios; 685 struct ccb_hdr_slist immed_notifies; 686 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 687 uint8_t event_r_idx; 688 uint8_t event_w_idx; 689 }; 690 #else 691 struct ahc_tmode_lstate; 692 #endif 693 694 /******************** Transfer Negotiation Datastructures *********************/ 695 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 696 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 697 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 698 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 699 700 #define AHC_WIDTH_UNKNOWN 0xFF 701 #define AHC_PERIOD_UNKNOWN 0xFF 702 #define AHC_OFFSET_UNKNOWN 0xFF 703 #define AHC_PPR_OPTS_UNKNOWN 0xFF 704 705 /* 706 * Transfer Negotiation Information. 707 */ 708 struct ahc_transinfo { 709 uint8_t protocol_version; /* SCSI Revision level */ 710 uint8_t transport_version; /* SPI Revision level */ 711 uint8_t width; /* Bus width */ 712 uint8_t period; /* Sync rate factor */ 713 uint8_t offset; /* Sync offset */ 714 uint8_t ppr_options; /* Parallel Protocol Request options */ 715 }; 716 717 /* 718 * Per-initiator current, goal and user transfer negotiation information. */ 719 struct ahc_initiator_tinfo { 720 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 721 struct ahc_transinfo curr; 722 struct ahc_transinfo goal; 723 struct ahc_transinfo user; 724 }; 725 726 /* 727 * Per enabled target ID state. 728 * Pointers to lun target state as well as sync/wide negotiation information 729 * for each initiator<->target mapping. For the initiator role we pretend 730 * that we are the target and the targets are the initiators since the 731 * negotiation is the same regardless of role. 732 */ 733 struct ahc_tmode_tstate { 734 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 735 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 736 737 /* 738 * Per initiator state bitmasks. 739 */ 740 uint16_t auto_negotiate;/* Auto Negotiation Required */ 741 uint16_t ultraenb; /* Using ultra sync rate */ 742 uint16_t discenable; /* Disconnection allowed */ 743 uint16_t tagenable; /* Tagged Queuing allowed */ 744 }; 745 746 /* 747 * Data structure for our table of allowed synchronous transfer rates. 748 */ 749 struct ahc_syncrate { 750 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 751 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 752 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 753 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 754 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 755 uint8_t period; /* Period to send to SCSI target */ 756 char *rate; 757 }; 758 759 /* Safe and valid period for async negotiations. */ 760 #define AHC_ASYNC_XFER_PERIOD 0x45 761 #define AHC_ULTRA2_XFER_PERIOD 0x0a 762 763 /* 764 * Indexes into our table of syncronous transfer rates. 765 */ 766 #define AHC_SYNCRATE_DT 0 767 #define AHC_SYNCRATE_ULTRA2 1 768 #define AHC_SYNCRATE_ULTRA 3 769 #define AHC_SYNCRATE_FAST 6 770 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 771 #define AHC_SYNCRATE_MIN 13 772 773 /***************************** Lookup Tables **********************************/ 774 /* 775 * Phase -> name and message out response 776 * to parity errors in each phase table. 777 */ 778 struct ahc_phase_table_entry { 779 uint8_t phase; 780 uint8_t mesg_out; /* Message response to parity errors */ 781 char *phasemsg; 782 }; 783 784 /************************** Serial EEPROM Format ******************************/ 785 786 struct seeprom_config { 787 /* 788 * Per SCSI ID Configuration Flags 789 */ 790 uint16_t device_flags[16]; /* words 0-15 */ 791 #define CFXFER 0x0007 /* synchronous transfer rate */ 792 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 793 #define CFDISC 0x0010 /* enable disconnection */ 794 #define CFWIDEB 0x0020 /* wide bus device */ 795 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 796 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 797 #define CFSTART 0x0100 /* send start unit SCSI command */ 798 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 799 #define CFRNFOUND 0x0400 /* report even if not found */ 800 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 801 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 802 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 803 804 /* 805 * BIOS Control Bits 806 */ 807 uint16_t bios_control; /* word 16 */ 808 #define CFSUPREM 0x0001 /* support all removeable drives */ 809 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 810 #define CFBIOSEN 0x0004 /* BIOS enabled */ 811 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 812 #define CFSM2DRV 0x0010 /* support more than two drives */ 813 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 814 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 815 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 816 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 817 #define CFEXTEND 0x0080 /* extended translation enabled */ 818 #define CFSCAMEN 0x0100 /* SCAM enable */ 819 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 820 #define CFMSG_VERBOSE 0x0000 821 #define CFMSG_SILENT 0x0200 822 #define CFMSG_DIAG 0x0400 823 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 824 /* UNUSED 0xff00 */ 825 826 /* 827 * Host Adapter Control Bits 828 */ 829 uint16_t adapter_control; /* word 17 */ 830 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 831 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 832 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 833 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 834 #define CFSTERM 0x0004 /* SCSI low byte termination */ 835 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 836 #define CFSPARITY 0x0010 /* SCSI parity */ 837 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 838 #define CFMULTILUN 0x0020 839 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 840 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 841 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 842 #define CFBOOTCHANSHIFT 8 843 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 844 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 845 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 846 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 847 848 /* 849 * Bus Release Time, Host Adapter ID 850 */ 851 uint16_t brtime_id; /* word 18 */ 852 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 853 /* UNUSED 0x00f0 */ 854 #define CFBRTIME 0xff00 /* bus release time */ 855 856 /* 857 * Maximum targets 858 */ 859 uint16_t max_targets; /* word 19 */ 860 #define CFMAXTARG 0x00ff /* maximum targets */ 861 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 862 #define CFBOOTID 0xf000 /* Target to boot from */ 863 uint16_t res_1[10]; /* words 20-29 */ 864 uint16_t signature; /* Signature == 0x250 */ 865 #define CFSIGNATURE 0x250 866 #define CFSIGNATURE2 0x300 867 uint16_t checksum; /* word 31 */ 868 }; 869 870 /**************************** Message Buffer *********************************/ 871 typedef enum { 872 MSG_TYPE_NONE = 0x00, 873 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 874 MSG_TYPE_INITIATOR_MSGIN = 0x02, 875 MSG_TYPE_TARGET_MSGOUT = 0x03, 876 MSG_TYPE_TARGET_MSGIN = 0x04 877 } ahc_msg_type; 878 879 typedef enum { 880 MSGLOOP_IN_PROG, 881 MSGLOOP_MSGCOMPLETE, 882 MSGLOOP_TERMINATED 883 } msg_loop_stat; 884 885 /*********************** Software Configuration Structure *********************/ 886 TAILQ_HEAD(scb_tailq, scb); 887 888 struct ahc_aic7770_softc { 889 /* 890 * Saved register state used for chip_init(). 891 */ 892 uint8_t busspd; 893 uint8_t bustime; 894 }; 895 896 struct ahc_pci_softc { 897 /* 898 * Saved register state used for chip_init(). 899 */ 900 uint32_t devconfig; 901 uint16_t targcrccnt; 902 uint8_t command; 903 uint8_t csize_lattime; 904 uint8_t optionmode; 905 uint8_t crccontrol1; 906 uint8_t dscommand0; 907 uint8_t dspcistatus; 908 uint8_t scbbaddr; 909 uint8_t dff_thrsh; 910 }; 911 912 union ahc_bus_softc { 913 struct ahc_aic7770_softc aic7770_softc; 914 struct ahc_pci_softc pci_softc; 915 }; 916 917 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 918 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 919 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 920 typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 921 typedef void ahc_callback_t (void *); 922 923 struct ahc_softc { 924 bus_space_tag_t tag; 925 bus_space_handle_t bsh; 926 #ifndef __linux__ 927 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 928 #endif 929 struct scb_data *scb_data; 930 931 struct scb *next_queued_scb; 932 933 /* 934 * SCBs that have been sent to the controller 935 */ 936 LIST_HEAD(, scb) pending_scbs; 937 938 /* 939 * SCBs whose timeout routine has been called. 940 */ 941 LIST_HEAD(, scb) timedout_scbs; 942 943 /* 944 * Counting lock for deferring the release of additional 945 * untagged transactions from the untagged_queues. When 946 * the lock is decremented to 0, all queues in the 947 * untagged_queues array are run. 948 */ 949 u_int untagged_queue_lock; 950 951 /* 952 * Per-target queue of untagged-transactions. The 953 * transaction at the head of the queue is the 954 * currently pending untagged transaction for the 955 * target. The driver only allows a single untagged 956 * transaction per target. 957 */ 958 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 959 960 /* 961 * Bus attachment specific data. 962 */ 963 union ahc_bus_softc bus_softc; 964 965 /* 966 * Platform specific data. 967 */ 968 struct ahc_platform_data *platform_data; 969 970 /* 971 * Platform specific device information. 972 */ 973 aic_dev_softc_t dev_softc; 974 975 /* 976 * Bus specific device information. 977 */ 978 ahc_bus_intr_t bus_intr; 979 980 /* 981 * Bus specific initialization required 982 * after a chip reset. 983 */ 984 ahc_bus_chip_init_t bus_chip_init; 985 986 /* 987 * Bus specific suspend routine. 988 */ 989 ahc_bus_suspend_t bus_suspend; 990 991 /* 992 * Bus specific resume routine. 993 */ 994 ahc_bus_resume_t bus_resume; 995 996 /* 997 * Target mode related state kept on a per enabled lun basis. 998 * Targets that are not enabled will have null entries. 999 * As an initiator, we keep one target entry for our initiator 1000 * ID to store our sync/wide transfer settings. 1001 */ 1002 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1003 1004 /* 1005 * The black hole device responsible for handling requests for 1006 * disabled luns on enabled targets. 1007 */ 1008 struct ahc_tmode_lstate *black_hole; 1009 1010 /* 1011 * Device instance currently on the bus awaiting a continue TIO 1012 * for a command that was not given the disconnect priveledge. 1013 */ 1014 struct ahc_tmode_lstate *pending_device; 1015 1016 /* 1017 * Card characteristics 1018 */ 1019 ahc_chip chip; 1020 ahc_feature features; 1021 ahc_bug bugs; 1022 ahc_flag flags; 1023 struct seeprom_config *seep_config; 1024 1025 /* Values to store in the SEQCTL register for pause and unpause */ 1026 uint8_t unpause; 1027 uint8_t pause; 1028 1029 /* Command Queues */ 1030 uint8_t qoutfifonext; 1031 uint8_t qinfifonext; 1032 uint8_t *qoutfifo; 1033 uint8_t *qinfifo; 1034 1035 /* Critical Section Data */ 1036 struct cs *critical_sections; 1037 u_int num_critical_sections; 1038 1039 /* Links for chaining softcs */ 1040 TAILQ_ENTRY(ahc_softc) links; 1041 1042 /* Channel Names ('A', 'B', etc.) */ 1043 char channel; 1044 char channel_b; 1045 1046 /* Initiator Bus ID */ 1047 uint8_t our_id; 1048 uint8_t our_id_b; 1049 1050 /* 1051 * PCI error detection. 1052 */ 1053 int unsolicited_ints; 1054 1055 /* 1056 * Target incoming command FIFO. 1057 */ 1058 struct target_cmd *targetcmds; 1059 uint8_t tqinfifonext; 1060 1061 /* 1062 * Cached copy of the sequencer control register. 1063 */ 1064 uint8_t seqctl; 1065 1066 /* 1067 * Incoming and outgoing message handling. 1068 */ 1069 uint8_t send_msg_perror; 1070 ahc_msg_type msg_type; 1071 uint8_t msgout_buf[12];/* Message we are sending */ 1072 uint8_t msgin_buf[12];/* Message we are receiving */ 1073 u_int msgout_len; /* Length of message to send */ 1074 u_int msgout_index; /* Current index in msgout */ 1075 u_int msgin_index; /* Current index in msgin */ 1076 1077 /* 1078 * Mapping information for data structures shared 1079 * between the sequencer and kernel. 1080 */ 1081 bus_dma_tag_t parent_dmat; 1082 bus_dma_tag_t shared_data_dmat; 1083 bus_dmamap_t shared_data_dmamap; 1084 bus_addr_t shared_data_busaddr; 1085 1086 /* 1087 * Bus address of the one byte buffer used to 1088 * work-around a DMA bug for chips <= aic7880 1089 * in target mode. 1090 */ 1091 bus_addr_t dma_bug_buf; 1092 1093 /* Number of enabled target mode device on this card */ 1094 u_int enabled_luns; 1095 1096 /* Initialization level of this data structure */ 1097 u_int init_level; 1098 1099 /* PCI cacheline size. */ 1100 u_int pci_cachesize; 1101 1102 /* 1103 * Count of parity errors we have seen as a target. 1104 * We auto-disable parity error checking after seeing 1105 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1106 */ 1107 u_int pci_target_perr_count; 1108 #define AHC_PCI_TARGET_PERR_THRESH 10 1109 1110 /* Maximum number of sequencer instructions supported. */ 1111 u_int instruction_ram_size; 1112 1113 /* Per-Unit descriptive information */ 1114 const char *description; 1115 char *name; 1116 int unit; 1117 1118 /* Selection Timer settings */ 1119 int seltime; 1120 int seltime_b; 1121 1122 uint16_t user_discenable;/* Disconnection allowed */ 1123 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1124 }; 1125 1126 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1127 extern struct ahc_softc_tailq ahc_tailq; 1128 1129 /************************ Active Device Information ***************************/ 1130 typedef enum { 1131 ROLE_UNKNOWN, 1132 ROLE_INITIATOR, 1133 ROLE_TARGET 1134 } role_t; 1135 1136 struct ahc_devinfo { 1137 int our_scsiid; 1138 int target_offset; 1139 uint16_t target_mask; 1140 u_int target; 1141 u_int lun; 1142 char channel; 1143 role_t role; /* 1144 * Only guaranteed to be correct if not 1145 * in the busfree state. 1146 */ 1147 }; 1148 1149 /****************************** PCI Structures ********************************/ 1150 #define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 1151 #define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 1152 1153 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1154 1155 struct ahc_pci_identity { 1156 uint64_t full_id; 1157 uint64_t id_mask; 1158 char *name; 1159 ahc_device_setup_t *setup; 1160 }; 1161 extern struct ahc_pci_identity ahc_pci_ident_table[]; 1162 extern const u_int ahc_num_pci_devs; 1163 1164 /***************************** VL/EISA Declarations ***************************/ 1165 struct aic7770_identity { 1166 uint32_t full_id; 1167 uint32_t id_mask; 1168 const char *name; 1169 ahc_device_setup_t *setup; 1170 }; 1171 extern struct aic7770_identity aic7770_ident_table[]; 1172 extern const int ahc_num_aic7770_devs; 1173 1174 #define AHC_EISA_SLOT_OFFSET 0xc00 1175 #define AHC_EISA_IOSIZE 0x100 1176 1177 /*************************** Function Declarations ****************************/ 1178 /******************************************************************************/ 1179 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1180 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1181 void ahc_busy_tcl(struct ahc_softc *ahc, 1182 u_int tcl, u_int busyid); 1183 1184 /***************************** PCI Front End *********************************/ 1185 struct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t); 1186 int ahc_pci_config(struct ahc_softc *, 1187 struct ahc_pci_identity *); 1188 int ahc_pci_test_register_access(struct ahc_softc *); 1189 1190 /*************************** EISA/VL Front End ********************************/ 1191 struct aic7770_identity *aic7770_find_device(uint32_t); 1192 int aic7770_config(struct ahc_softc *ahc, 1193 struct aic7770_identity *, 1194 u_int port); 1195 1196 /************************** SCB and SCB queue management **********************/ 1197 int ahc_probe_scbs(struct ahc_softc *); 1198 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1199 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1200 struct scb_tailq *queue); 1201 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1202 struct scb *scb); 1203 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1204 int target, char channel, int lun, 1205 u_int tag, role_t role); 1206 1207 /****************************** Initialization ********************************/ 1208 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1209 int ahc_softc_init(struct ahc_softc *); 1210 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1211 int ahc_chip_init(struct ahc_softc *ahc); 1212 int ahc_init(struct ahc_softc *ahc); 1213 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1214 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1215 int ahc_suspend(struct ahc_softc *ahc); 1216 int ahc_resume(struct ahc_softc *ahc); 1217 void ahc_softc_insert(struct ahc_softc *); 1218 struct ahc_softc *ahc_find_softc(struct ahc_softc *ahc); 1219 void ahc_set_unit(struct ahc_softc *, int); 1220 void ahc_set_name(struct ahc_softc *, char *); 1221 void ahc_alloc_scbs(struct ahc_softc *ahc); 1222 void ahc_free(struct ahc_softc *ahc); 1223 int ahc_reset(struct ahc_softc *ahc, int reinit); 1224 void ahc_shutdown(void *arg); 1225 1226 /*************************** Interrupt Services *******************************/ 1227 void ahc_clear_intstat(struct ahc_softc *ahc); 1228 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1229 #ifdef AHC_TARGET_MODE 1230 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1231 #endif 1232 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1233 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1234 void ahc_handle_scsiint(struct ahc_softc *ahc, 1235 u_int intstat); 1236 void ahc_clear_critical_section(struct ahc_softc *ahc); 1237 1238 /***************************** Error Recovery *********************************/ 1239 typedef enum { 1240 SEARCH_COMPLETE, 1241 SEARCH_COUNT, 1242 SEARCH_REMOVE 1243 } ahc_search_action; 1244 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1245 char channel, int lun, u_int tag, 1246 role_t role, uint32_t status, 1247 ahc_search_action action); 1248 int ahc_search_untagged_queues(struct ahc_softc *ahc, 1249 aic_io_ctx_t ctx, 1250 int target, char channel, 1251 int lun, uint32_t status, 1252 ahc_search_action action); 1253 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1254 char channel, int lun, u_int tag, 1255 int stop_on_first, int remove, 1256 int save_state); 1257 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1258 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1259 int initiate_reset); 1260 int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1261 char channel, int lun, u_int tag, 1262 role_t role, uint32_t status); 1263 void ahc_restart(struct ahc_softc *ahc); 1264 void ahc_calc_residual(struct ahc_softc *ahc, 1265 struct scb *scb); 1266 void ahc_timeout(struct scb *scb); 1267 void ahc_recover_commands(struct ahc_softc *ahc); 1268 /*************************** Utility Functions ********************************/ 1269 struct ahc_phase_table_entry* 1270 ahc_lookup_phase_entry(int phase); 1271 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1272 u_int our_id, u_int target, 1273 u_int lun, char channel, 1274 role_t role); 1275 /************************** Transfer Negotiation ******************************/ 1276 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1277 u_int *ppr_options, u_int maxsync); 1278 u_int ahc_find_period(struct ahc_softc *ahc, 1279 u_int scsirate, u_int maxsync); 1280 void ahc_validate_offset(struct ahc_softc *ahc, 1281 struct ahc_initiator_tinfo *tinfo, 1282 struct ahc_syncrate *syncrate, 1283 u_int *offset, int wide, 1284 role_t role); 1285 void ahc_validate_width(struct ahc_softc *ahc, 1286 struct ahc_initiator_tinfo *tinfo, 1287 u_int *bus_width, 1288 role_t role); 1289 /* 1290 * Negotiation types. These are used to qualify if we should renegotiate 1291 * even if our goal and current transport parameters are identical. 1292 */ 1293 typedef enum { 1294 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1295 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1296 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1297 } ahc_neg_type; 1298 int ahc_update_neg_request(struct ahc_softc*, 1299 struct ahc_devinfo*, 1300 struct ahc_tmode_tstate*, 1301 struct ahc_initiator_tinfo*, 1302 ahc_neg_type); 1303 void ahc_set_width(struct ahc_softc *ahc, 1304 struct ahc_devinfo *devinfo, 1305 u_int width, u_int type, int paused); 1306 void ahc_set_syncrate(struct ahc_softc *ahc, 1307 struct ahc_devinfo *devinfo, 1308 struct ahc_syncrate *syncrate, 1309 u_int period, u_int offset, 1310 u_int ppr_options, 1311 u_int type, int paused); 1312 typedef enum { 1313 AHC_QUEUE_NONE, 1314 AHC_QUEUE_BASIC, 1315 AHC_QUEUE_TAGGED 1316 } ahc_queue_alg; 1317 1318 void ahc_set_tags(struct ahc_softc *ahc, 1319 struct ahc_devinfo *devinfo, 1320 ahc_queue_alg alg); 1321 1322 /**************************** Target Mode *************************************/ 1323 #ifdef AHC_TARGET_MODE 1324 void ahc_send_lstate_events(struct ahc_softc *, 1325 struct ahc_tmode_lstate *); 1326 void ahc_handle_en_lun(struct ahc_softc *ahc, 1327 struct cam_sim *sim, union ccb *ccb); 1328 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1329 struct cam_sim *sim, union ccb *ccb, 1330 struct ahc_tmode_tstate **tstate, 1331 struct ahc_tmode_lstate **lstate, 1332 int notfound_failure); 1333 #ifndef AHC_TMODE_ENABLE 1334 #define AHC_TMODE_ENABLE 0 1335 #endif 1336 #endif 1337 /******************************* Debug ***************************************/ 1338 #ifdef AHC_DEBUG 1339 extern uint32_t ahc_debug; 1340 #define AHC_SHOW_MISC 0x0001 1341 #define AHC_SHOW_SENSE 0x0002 1342 #define AHC_DUMP_SEEPROM 0x0004 1343 #define AHC_SHOW_TERMCTL 0x0008 1344 #define AHC_SHOW_MEMORY 0x0010 1345 #define AHC_SHOW_MESSAGES 0x0020 1346 #define AHC_SHOW_DV 0x0040 1347 #define AHC_SHOW_SELTO 0x0080 1348 #define AHC_SHOW_QFULL 0x0200 1349 #define AHC_SHOW_QUEUE 0x0400 1350 #define AHC_SHOW_TQIN 0x0800 1351 #define AHC_SHOW_MASKED_ERRORS 0x1000 1352 #define AHC_DEBUG_SEQUENCER 0x2000 1353 #endif 1354 void ahc_print_scb(struct scb *scb); 1355 void ahc_print_devinfo(struct ahc_softc *ahc, 1356 struct ahc_devinfo *dev); 1357 void ahc_dump_card_state(struct ahc_softc *ahc); 1358 int ahc_print_register(ahc_reg_parse_entry_t *table, 1359 u_int num_entries, 1360 const char *name, 1361 u_int address, 1362 u_int value, 1363 u_int *cur_column, 1364 u_int wrap_point); 1365 /******************************* SEEPROM *************************************/ 1366 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1367 struct seeprom_descriptor *sd); 1368 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1369 #endif /* _AIC7XXX_H_ */ 1370