1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #include "opt_aic7xxx.h" /* for config options */ 40 #include "aic7xxx_reg.h" 41 42 #include <sys/bus.h> /* For device_t */ 43 44 #ifndef MAX 45 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 46 #endif 47 48 #ifndef MIN 49 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 50 #endif 51 52 /* 53 * The maximum number of supported targets. 54 */ 55 #define AHC_NUM_TARGETS 16 56 57 /* 58 * The maximum number of supported luns. 59 * Although the identify message only supports 64 luns in SPI3, you 60 * can have 2^64 luns when information unit transfers are enabled. 61 * The max we can do sanely given the 8bit nature of the RISC engine 62 * on these chips is 256. 63 */ 64 #define AHC_NUM_LUNS 256 65 66 /* 67 * The maximum transfer per S/G segment. 68 */ 69 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 70 71 /* 72 * The number of dma segments supported. The sequencer can handle any number 73 * of physically contiguous S/G entrys. To reduce the driver's memory 74 * consumption, we limit the number supported to be sufficient to handle 75 * the largest mapping supported by the kernel, MAXPHYS. Assuming the 76 * transfer is as fragmented as possible and unaligned, this turns out to 77 * be the number of paged sized transfers in MAXPHYS plus an extra element 78 * to handle any unaligned residual. The sequencer fetches SG elements 79 * in 128 byte chucks, so make the number per-transaction a nice multiple 80 * of 16 (8 byte S/G elements). 81 */ 82 /* XXX Worth the space??? */ 83 #define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) 84 85 #define AHC_SCB_MAX 255 /* 86 * Up to 255 SCBs on some types of aic7xxx 87 * based boards. The aic7870 have 16 internal 88 * SCBs, but external SRAM bumps this to 255. 89 * The aic7770 family have only 4, and the 90 * aic7850 has only 3. 91 */ 92 93 #define AHC_TMODE_CMDS 256 /* 94 * Ring Buffer of incoming target commands. 95 * We allocate 256 to simplify the logic 96 * in the sequencer by using the natural 97 * wrap point of an 8bit counter. 98 */ 99 100 /* 101 * The aic7xxx chips only support a 24bit length. We use the top 102 * byte of the length to store additional address bits as well 103 * as an indicator if this is the last SG segment in a transfer. 104 * This gives us an addressable range of 512GB on machines with 105 * 64bit PCI or with chips that can support dual address cycles 106 * on 32bit PCI busses. 107 */ 108 struct ahc_dma_seg { 109 uint32_t addr; 110 uint32_t len; 111 #define AHC_DMA_LAST_SEG 0x80000000 112 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 113 #define AHC_SG_LEN_MASK 0x00FFFFFF 114 }; 115 116 /* The chip order is from least sophisticated to most sophisticated */ 117 typedef enum { 118 AHC_NONE = 0x0000, 119 AHC_CHIPID_MASK = 0x00FF, 120 AHC_AIC7770 = 0x0001, 121 AHC_AIC7850 = 0x0002, 122 AHC_AIC7855 = 0x0003, 123 AHC_AIC7859 = 0x0004, 124 AHC_AIC7860 = 0x0005, 125 AHC_AIC7870 = 0x0006, 126 AHC_AIC7880 = 0x0007, 127 AHC_AIC7895 = 0x0008, 128 AHC_AIC7890 = 0x0009, 129 AHC_AIC7896 = 0x000a, 130 AHC_AIC7892 = 0x000b, 131 AHC_AIC7899 = 0x000c, 132 AHC_VL = 0x0100, /* Bus type VL */ 133 AHC_EISA = 0x0200, /* Bus type EISA */ 134 AHC_PCI = 0x0400, /* Bus type PCI */ 135 AHC_BUS_MASK = 0x0F00 136 } ahc_chip; 137 138 extern char *ahc_chip_names[]; 139 140 typedef enum { 141 AHC_FENONE = 0x0000, 142 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 143 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 144 AHC_WIDE = 0x0004, /* Wide Channel */ 145 AHC_TWIN = 0x0008, /* Twin Channel */ 146 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 147 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 148 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 149 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 150 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 151 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 152 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 153 AHC_DT = 0x0800, /* Double Transition transfers */ 154 AHC_NEW_TERMCTL = 0x1000, 155 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 156 AHC_LARGE_SCBS = 0x4000, /* 64byte SCBs */ 157 AHC_AIC7770_FE = AHC_FENONE, 158 AHC_AIC7850_FE = AHC_SPIOCAP, 159 AHC_AIC7855_FE = AHC_AIC7850_FE, 160 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 161 AHC_AIC7860_FE = AHC_AIC7859_FE, 162 AHC_AIC7870_FE = AHC_FENONE, 163 AHC_AIC7880_FE = AHC_ULTRA, 164 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 165 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 166 |AHC_NEW_TERMCTL|AHC_LARGE_SCBS, 167 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 168 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 169 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 170 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 171 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 172 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 173 } ahc_feature; 174 175 typedef enum { 176 AHC_BUGNONE = 0x00, 177 /* 178 * On all chips prior to the U2 product line, 179 * the WIDEODD S/G segment feature does not 180 * work during scsi->HostBus transfers. 181 */ 182 AHC_TMODE_WIDEODD_BUG = 0x01, 183 /* 184 * On the aic7890/91 Rev 0 chips, the autoflush 185 * feature does not work. A manual flush of 186 * the DMA FIFO is required. 187 */ 188 AHC_AUTOFLUSH_BUG = 0x02 189 } ahc_bug; 190 191 typedef enum { 192 AHC_FNONE = 0x000, 193 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 194 AHC_CHANNEL_B_PRIMARY = 0x002,/* 195 * On twin channel adapters, probe 196 * channel B first since it is the 197 * primary bus. 198 */ 199 AHC_USEDEFAULTS = 0x004,/* 200 * For cards without an seeprom 201 * or a BIOS to initialize the chip's 202 * SRAM, we use the default target 203 * settings. 204 */ 205 AHC_SHARED_SRAM = 0x010, 206 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 207 AHC_RESET_BUS_A = 0x040, 208 AHC_RESET_BUS_B = 0x080, 209 AHC_EXTENDED_TRANS_A = 0x100, 210 AHC_EXTENDED_TRANS_B = 0x200, 211 AHC_TERM_ENB_A = 0x400, 212 AHC_TERM_ENB_B = 0x800, 213 AHC_INITIATORMODE = 0x1000,/* 214 * Allow initiator operations on 215 * this controller. 216 */ 217 AHC_TARGETMODE = 0x2000,/* 218 * Allow target operations on this 219 * controller. 220 */ 221 AHC_NEWEEPROM_FMT = 0x4000, 222 AHC_RESOURCE_SHORTAGE = 0x8000, 223 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 224 AHC_INT50_SPEEDFLEX = 0x20000,/* 225 * Internal 50pin connector 226 * sits behind an aic3860 227 */ 228 AHC_SCB_BTT = 0x40000 /* 229 * The busy targets table is 230 * stored in SCB space rather 231 * than SRAM. 232 */ 233 } ahc_flag; 234 235 struct ahc_probe_config { 236 const char *description; 237 char channel; 238 char channel_b; 239 ahc_chip chip; 240 ahc_feature features; 241 ahc_bug bugs; 242 ahc_flag flags; 243 }; 244 245 typedef enum { 246 SCB_FREE = 0x0000, 247 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 248 * Another device was active 249 * during the first timeout for 250 * this SCB so we gave ourselves 251 * an additional timeout period 252 * in case it was hogging the 253 * bus. 254 */ 255 SCB_DEVICE_RESET = 0x0004, 256 SCB_SENSE = 0x0008, 257 SCB_RECOVERY_SCB = 0x0040, 258 SCB_NEGOTIATE = 0x0080, 259 SCB_ABORT = 0x1000, 260 SCB_QUEUED_MSG = 0x2000, 261 SCB_ACTIVE = 0x4000, 262 SCB_TARGET_IMMEDIATE = 0x8000 263 } scb_flag; 264 265 /* 266 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 267 * consists of a "hardware SCB" mirroring the fields availible on the card 268 * and additional information the kernel stores for each transaction. 269 * 270 * To minimize space utilization, a portion of the hardware scb stores 271 * different data during different portions of a SCSI transaction. 272 * As initialized by the host driver for the initiator role, this area 273 * contains the SCSI cdb (or pointer to the cdb) to be executed. After 274 * the cdb has been presented to the target, this area serves to store 275 * residual transfer information and the SCSI status byte. 276 * For the target role, the contents of this area do not change, but 277 * still serve a different purpose than for the initiator role. See 278 * struct target_data for details. 279 */ 280 281 struct status_pkt { 282 uint32_t residual_datacnt; 283 uint32_t residual_sg_ptr; 284 uint8_t scsi_status; 285 }; 286 287 struct target_data { 288 uint8_t target_phases; 289 uint8_t data_phase; 290 uint8_t scsi_status; 291 uint8_t initiator_tag; 292 }; 293 294 struct hardware_scb { 295 /*0*/ uint8_t control; 296 /*1*/ uint8_t scsiid; /* what to load in the SCSIID register */ 297 /*2*/ uint8_t lun; 298 /*3*/ uint8_t cdb_len; 299 /*4*/ union { 300 /* 301 * 12 bytes of cdb information only 302 * used on chips with 32byte SCBs. 303 */ 304 uint8_t cdb[12]; 305 uint32_t cdb_ptr; 306 struct status_pkt status; 307 struct target_data tdata; 308 } shared_data; 309 /* 310 * A word about residuals. The scb is presented to the sequencer with 311 * the dataptr and datacnt fields initialized to the contents of the 312 * first S/G element to transfer. The sgptr field is initialized to 313 * the bus address for the S/G element that follows the first in the 314 * in core S/G array or'ed with the SG_FULL_RESID flag. Sgptr may point 315 * to an invalid S/G entry for this transfer. If no transfer is to occur, 316 * sgptr is set to SG_LIST_NULL. The SG_FULL_RESID flag insures that 317 * the residual will be correctly noted even if no data transfers occur. 318 * Once the data phase is entered, the residual sgptr and datacnt are 319 * loaded from the sgptr and the datacnt fields. After each S/G element's 320 * dataptr and length are loaded into the hardware, the residual sgptr 321 * is advanced. After each S/G element is expired, its datacnt field 322 * is checked to see if the LAST_SEG flag is set. If so, SG_LIST_NULL 323 * is set in the residual sg ptr and the transfer is considered complete. 324 * If the sequencer determines that three is a residual in the tranfer, 325 * it will set the SG_RESID_VALID flag in sgptr and dma the scb back into 326 * host memory. To sumarize: 327 * 328 * Sequencer: 329 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 330 * or residual_sgptr does not have SG_LIST_NULL set. 331 * 332 * o We are transfering the last segment if residual_datacnt has 333 * the SG_LAST_SEG flag set. 334 * 335 * Host: 336 * o A residual has occurred if a completed scb has the 337 * SG_RESID_VALID flag set. 338 * 339 * o residual_sgptr and sgptr refer to the "next" sg entry 340 * and so may point beyond the last valid sg entry for the 341 * transfer. 342 */ 343 /*16*/ uint32_t dataptr; 344 /*20*/ uint32_t datacnt; /* 345 * The highest address byte is 346 * really the 5th. byte in the 347 * dataptr. 348 */ 349 /*24*/ uint32_t sgptr; 350 #define SG_PTR_MASK 0xFFFFFFF8 351 /*28*/ uint8_t tag; /* Index into our kernel SCB array. 352 * Also used as the tag for tagged I/O 353 */ 354 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 355 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 356 /*31*/ uint8_t next; /* Used for threading SCBs in the 357 * "Waiting for Selection" and 358 * "Disconnected SCB" lists down 359 * in the sequencer. 360 */ 361 /*32*/ uint8_t cdb32[32]; /* 362 * CDB storage for controllers 363 * supporting 64 byte SCBs. 364 */ 365 }; 366 367 struct scb { 368 struct hardware_scb *hscb; 369 union { 370 SLIST_ENTRY(scb) sle; 371 TAILQ_ENTRY(scb) tqe; 372 } links; 373 union ccb *ccb; /* the ccb for this cmd */ 374 scb_flag flags; 375 bus_dmamap_t dmamap; 376 struct ahc_dma_seg *sg_list; 377 bus_addr_t sg_list_phys; 378 bus_addr_t cdb32_busaddr; 379 u_int sg_count;/* How full ahc_dma_seg is */ 380 }; 381 382 /* 383 * Connection desciptor for select-in requests in target mode. 384 * The first byte is the connecting target, followed by identify 385 * message and optional tag information, terminated by 0xFF. The 386 * remainder is the command to execute. The cmd_valid byte is on 387 * an 8 byte boundary to simplify setting it on aic7880 hardware 388 * which only has limited direct access to the DMA FIFO. 389 */ 390 struct target_cmd { 391 uint8_t scsiid; 392 uint8_t identify; /* Identify message */ 393 uint8_t bytes[22]; 394 uint8_t cmd_valid; 395 uint8_t pad[7]; 396 }; 397 398 /* 399 * Number of events we can buffer up if we run out 400 * of immediate notify ccbs. 401 */ 402 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 403 struct ahc_tmode_event { 404 uint8_t initiator_id; 405 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 406 #define EVENT_TYPE_BUS_RESET 0xFF 407 uint8_t event_arg; 408 }; 409 410 /* 411 * Per lun target mode state including accept TIO CCB 412 * and immediate notify CCB pools. 413 */ 414 struct tmode_lstate { 415 struct cam_path *path; 416 struct ccb_hdr_slist accept_tios; 417 struct ccb_hdr_slist immed_notifies; 418 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 419 uint8_t event_r_idx; 420 uint8_t event_w_idx; 421 }; 422 423 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 424 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 425 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 426 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 427 428 struct ahc_transinfo { 429 uint8_t protocol_version; 430 uint8_t transport_version; 431 uint8_t width; 432 uint8_t period; 433 uint8_t offset; 434 uint8_t ppr_options; 435 }; 436 437 struct ahc_initiator_tinfo { 438 uint8_t scsirate; 439 struct ahc_transinfo current; 440 struct ahc_transinfo goal; 441 struct ahc_transinfo user; 442 }; 443 444 /* 445 * Per target mode enabled target state. Esentially just an array of 446 * pointers to lun target state as well as sync/wide negotiation information 447 * for each initiator<->target mapping (including the mapping for when we 448 * are the initiator). 449 */ 450 struct tmode_tstate { 451 struct tmode_lstate* enabled_luns[64]; 452 struct ahc_initiator_tinfo transinfo[16]; 453 454 /* 455 * Per initiator state bitmasks. 456 */ 457 uint16_t ultraenb; /* Using ultra sync rate */ 458 uint16_t discenable; /* Disconnection allowed */ 459 uint16_t tagenable; /* Tagged Queuing allowed */ 460 }; 461 462 /* 463 * Define the format of the aic7XXX SEEPROM registers (16 bits). 464 */ 465 466 struct seeprom_config { 467 /* 468 * SCSI ID Configuration Flags 469 */ 470 uint16_t device_flags[16]; /* words 0-15 */ 471 #define CFXFER 0x0007 /* synchronous transfer rate */ 472 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 473 #define CFDISC 0x0010 /* enable disconnection */ 474 #define CFWIDEB 0x0020 /* wide bus device */ 475 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 476 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 477 #define CFSTART 0x0100 /* send start unit SCSI command */ 478 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 479 #define CFRNFOUND 0x0400 /* report even if not found */ 480 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 481 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 482 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 483 484 /* 485 * BIOS Control Bits 486 */ 487 uint16_t bios_control; /* word 16 */ 488 #define CFSUPREM 0x0001 /* support all removeable drives */ 489 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 490 #define CFBIOSEN 0x0004 /* BIOS enabled */ 491 /* UNUSED 0x0008 */ 492 #define CFSM2DRV 0x0010 /* support more than two drives */ 493 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 494 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 495 #define CFEXTEND 0x0080 /* extended translation enabled */ 496 #define CFSCAMEN 0x0100 /* SCAM enable */ 497 /* UNUSED 0xff00 */ 498 499 /* 500 * Host Adapter Control Bits 501 */ 502 uint16_t adapter_control; /* word 17 */ 503 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 504 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 505 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 506 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 507 #define CFSTERM 0x0004 /* SCSI low byte termination */ 508 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 509 #define CFSPARITY 0x0010 /* SCSI parity */ 510 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 511 #define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */ 512 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 513 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 514 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 515 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 516 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 517 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 518 #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 519 520 /* 521 * Bus Release, Host Adapter ID 522 */ 523 uint16_t brtime_id; /* word 18 */ 524 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 525 /* UNUSED 0x00f0 */ 526 #define CFBRTIME 0xff00 /* bus release time */ 527 528 /* 529 * Maximum targets 530 */ 531 uint16_t max_targets; /* word 19 */ 532 #define CFMAXTARG 0x00ff /* maximum targets */ 533 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 534 #define CFBOOTID 0xf000 /* Target to boot from */ 535 uint16_t res_1[10]; /* words 20-29 */ 536 uint16_t signature; /* Signature == 0x250 */ 537 #define CFSIGNATURE 0x250 538 uint16_t checksum; /* word 31 */ 539 }; 540 541 struct ahc_syncrate { 542 u_int sxfr_u2; 543 u_int sxfr; 544 /* Rates in Ultra mode have bit 8 of sxfr set */ 545 #define ULTRA_SXFR 0x100 546 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 547 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 548 uint8_t period; /* Period to send to SCSI target */ 549 char *rate; 550 }; 551 552 typedef enum { 553 MSG_TYPE_NONE = 0x00, 554 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 555 MSG_TYPE_INITIATOR_MSGIN = 0x02, 556 MSG_TYPE_TARGET_MSGOUT = 0x03, 557 MSG_TYPE_TARGET_MSGIN = 0x04 558 } ahc_msg_type; 559 560 struct sg_map_node { 561 bus_dmamap_t sg_dmamap; 562 bus_addr_t sg_physaddr; 563 struct ahc_dma_seg* sg_vaddr; 564 SLIST_ENTRY(sg_map_node) links; 565 }; 566 567 struct scb_data { 568 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 569 struct scb *scbarray; /* Array of kernel SCBs */ 570 SLIST_HEAD(, scb) free_scbs; /* 571 * Pool of SCBs ready to be assigned 572 * commands to execute. 573 */ 574 struct scsi_sense_data *sense; /* Per SCB sense data */ 575 576 /* 577 * "Bus" addresses of our data structures. 578 */ 579 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 580 bus_dmamap_t hscb_dmamap; 581 bus_addr_t hscb_busaddr; 582 bus_dma_tag_t sense_dmat; 583 bus_dmamap_t sense_dmamap; 584 bus_addr_t sense_busaddr; 585 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 586 SLIST_HEAD(, sg_map_node) sg_maps; 587 uint8_t numscbs; 588 uint8_t maxhscbs; /* Number of SCBs on the card */ 589 uint8_t init_level; /* 590 * How far we've initialized 591 * this structure. 592 */ 593 }; 594 595 TAILQ_HEAD(scb_tailq, scb); 596 597 struct ahc_softc { 598 bus_space_tag_t tag; 599 bus_space_handle_t bsh; 600 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 601 struct scb_data *scb_data; 602 603 /* 604 * CCBs that have been send to the controller 605 */ 606 LIST_HEAD(, ccb_hdr) pending_ccbs; 607 608 /* 609 * Counting lock for deferring the release of additional 610 * untagged transactions from the untagged_queues. When 611 * the lock is decremented to 0, all queues in the 612 * untagged_queues array are run. 613 */ 614 u_int untagged_queue_lock; 615 616 /* 617 * Per-target queue of untagged-transactions. The 618 * transaction at the head of the queue is the 619 * currently pending untagged transaction for the 620 * target. The driver only allows a single untagged 621 * transaction per target. 622 */ 623 struct scb_tailq untagged_queues[16]; 624 625 /* 626 * Target mode related state kept on a per enabled lun basis. 627 * Targets that are not enabled will have null entries. 628 * As an initiator, we keep one target entry for our initiator 629 * ID to store our sync/wide transfer settings. 630 */ 631 struct tmode_tstate* enabled_targets[16]; 632 633 /* 634 * The black hole device responsible for handling requests for 635 * disabled luns on enabled targets. 636 */ 637 struct tmode_lstate* black_hole; 638 639 /* 640 * Device instance currently on the bus awaiting a continue TIO 641 * for a command that was not given the disconnect priveledge. 642 */ 643 struct tmode_lstate* pending_device; 644 645 /* 646 * Card characteristics 647 */ 648 ahc_chip chip; 649 ahc_feature features; 650 ahc_bug bugs; 651 ahc_flag flags; 652 653 /* Values to store in the SEQCTL register for pause and unpause */ 654 uint8_t unpause; 655 uint8_t pause; 656 657 /* Command Queues */ 658 uint8_t qoutfifonext; 659 uint8_t qinfifonext; 660 uint8_t *qoutfifo; 661 uint8_t *qinfifo; 662 663 /* 664 * Hooks into the XPT. 665 */ 666 struct cam_sim *sim; 667 struct cam_sim *sim_b; 668 struct cam_path *path; 669 struct cam_path *path_b; 670 671 int unit; 672 673 /* Channel Names ('A', 'B', etc.) */ 674 char channel; 675 char channel_b; 676 677 /* Initiator Bus ID */ 678 uint8_t our_id; 679 uint8_t our_id_b; 680 681 /* Targets that need negotiation messages */ 682 uint16_t targ_msg_req; 683 684 /* 685 * PCI error detection and data for running the 686 * PCI error interrupt handler. 687 */ 688 int unsolicited_ints; 689 device_t device; 690 691 /* 692 * Target incoming command FIFO. 693 */ 694 struct target_cmd *targetcmds; 695 uint8_t tqinfifonext; 696 697 /* 698 * Incoming and outgoing message handling. 699 */ 700 uint8_t send_msg_perror; 701 ahc_msg_type msg_type; 702 uint8_t msgout_buf[8]; /* Message we are sending */ 703 uint8_t msgin_buf[8]; /* Message we are receiving */ 704 u_int msgout_len; /* Length of message to send */ 705 u_int msgout_index; /* Current index in msgout */ 706 u_int msgin_index; /* Current index in msgin */ 707 708 int regs_res_type; 709 int regs_res_id; 710 int irq_res_type; 711 struct resource *regs; 712 struct resource *irq; 713 void *ih; 714 bus_dma_tag_t parent_dmat; 715 bus_dma_tag_t shared_data_dmat; 716 bus_dmamap_t shared_data_dmamap; 717 bus_addr_t shared_data_busaddr; 718 bus_addr_t dma_bug_buf; 719 720 /* Number of enabled target mode device on this card */ 721 u_int enabled_luns; 722 723 /* Initialization level of this data structure */ 724 u_int init_level; 725 726 uint16_t user_discenable;/* Disconnection allowed */ 727 uint16_t user_tagenable;/* Tagged Queuing allowed */ 728 }; 729 730 struct full_ahc_softc { 731 struct ahc_softc softc; 732 struct scb_data scb_data_storage; 733 }; 734 735 /* #define AHC_DEBUG */ 736 #ifdef AHC_DEBUG 737 /* Different debugging levels used when AHC_DEBUG is defined */ 738 #define AHC_SHOWMISC 0x0001 739 #define AHC_SHOWCMDS 0x0002 740 #define AHC_SHOWSCBS 0x0004 741 #define AHC_SHOWABORTS 0x0008 742 #define AHC_SHOWSENSE 0x0010 743 #define AHC_SHOWSCBCNT 0x0020 744 745 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 746 #endif 747 748 #define ahc_inb(ahc, port) \ 749 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 750 751 #define ahc_outb(ahc, port, value) \ 752 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 753 754 #define ahc_outsb(ahc, port, valp, count) \ 755 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 756 757 #define ahc_insb(ahc, port, valp, count) \ 758 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 759 760 char *ahc_name(struct ahc_softc *ahc); 761 762 void ahc_init_probe_config(struct ahc_probe_config *config); 763 struct ahc_softc* 764 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 765 int regs_id, bus_dma_tag_t parent_dmat, 766 struct ahc_probe_config *config, struct scb_data *scb_data); 767 int ahc_reset(struct ahc_softc *ahc); 768 void ahc_free(struct ahc_softc *); 769 int ahc_probe_scbs(struct ahc_softc *); 770 int ahc_init(struct ahc_softc *); 771 int ahc_attach(struct ahc_softc *); 772 void ahc_intr(void *arg); 773 static __inline int sequencer_paused(struct ahc_softc *ahc); 774 static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); 775 static __inline void pause_sequencer(struct ahc_softc *ahc); 776 static __inline void unpause_sequencer(struct ahc_softc *ahc); 777 778 static __inline void 779 ahc_pause_bug_fix(struct ahc_softc *ahc) 780 { 781 /* 782 * Clear the CIOBUS stretch signal by reading a register that will 783 * set this signal and deassert it. Without this workaround, if 784 * the chip is paused, by an interrupt or manual pause, while 785 * accessing scb ram, then accesses to certain registers will hang 786 * the system (infinite pci retries). 787 */ 788 if ((ahc->features & AHC_ULTRA2) != 0) 789 (void)ahc_inb(ahc, CCSCBCTL); 790 } 791 792 static __inline int 793 sequencer_paused(struct ahc_softc *ahc) 794 { 795 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 796 } 797 798 static __inline void 799 pause_sequencer(struct ahc_softc *ahc) 800 { 801 ahc_outb(ahc, HCNTRL, ahc->pause); 802 803 /* 804 * Since the sequencer can disable pausing in a critical section, we 805 * must loop until it actually stops. 806 */ 807 while (sequencer_paused(ahc) == 0) 808 ; 809 810 ahc_pause_bug_fix(ahc); 811 } 812 813 static __inline void 814 unpause_sequencer(struct ahc_softc *ahc) 815 { 816 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 817 ahc_outb(ahc, HCNTRL, ahc->unpause); 818 } 819 820 #endif /* _AIC7XXX_H_ */ 821