1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#40 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifndef _AIC7XXX_H_ 46 #define _AIC7XXX_H_ 47 48 /* Register Definitions */ 49 #include "aic7xxx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahc_platform_data; 53 struct scb_platform_data; 54 struct seeprom_descriptor; 55 56 /****************************** Useful Macros *********************************/ 57 #ifndef MAX 58 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59 #endif 60 61 #ifndef MIN 62 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63 #endif 64 65 #ifndef TRUE 66 #define TRUE 1 67 #endif 68 #ifndef FALSE 69 #define FALSE 0 70 #endif 71 72 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74 #define ALL_CHANNELS '\0' 75 #define ALL_TARGETS_MASK 0xFFFF 76 #define INITIATOR_WILDCARD (~0) 77 78 #define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81 #define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83 #define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89 #define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91 #define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93 #define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95 #define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun) 97 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99 #define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101 #define TCL_TARGET_OFFSET(tcl) \ 102 ((((tcl) >> 4) & TID) >> 4) 103 #define TCL_LUN(tcl) \ 104 (tcl & (AHC_NUM_LUNS - 1)) 105 #define BUILD_TCL(scsiid, lun) \ 106 ((lun) | (((scsiid) & TID) << 4)) 107 108 #ifndef AHC_TARGET_MODE 109 #undef AHC_TMODE_ENABLE 110 #define AHC_TMODE_ENABLE 0 111 #endif 112 113 /**************************** Driver Constants ********************************/ 114 /* 115 * The maximum number of supported targets. 116 */ 117 #define AHC_NUM_TARGETS 16 118 119 /* 120 * The maximum number of supported luns. 121 * The identify message only supports 64 luns in SPI3. 122 * You can have 2^64 luns when information unit transfers are enabled, 123 * but it is doubtful this driver will ever support IUTs. 124 */ 125 #define AHC_NUM_LUNS 64 126 127 /* 128 * The maximum transfer per S/G segment. 129 */ 130 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 131 132 /* 133 * The maximum amount of SCB storage in hardware on a controller. 134 * This value represents an upper bound. Controllers vary in the number 135 * they actually support. 136 */ 137 #define AHC_SCB_MAX 255 138 139 /* 140 * The maximum number of concurrent transactions supported per driver instance. 141 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 142 * the space for SCBs on the host adapter varies by model, the driver will 143 * page the SCBs between host and controller memory as needed. We are limited 144 * to 253 because: 145 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 146 * 2) We reserve one value, 255, to represent the invalid element. 147 * 3) Our input queue scheme requires one SCB to always be reserved 148 * in advance of queuing any SCBs. This takes us down to 254. 149 * 4) To handle our output queue correctly on machines that only 150 * support 32bit stores, we must clear the array 4 bytes at a 151 * time. To avoid colliding with a DMA write from the sequencer, 152 * we must be sure that 4 slots are empty when we write to clear 153 * the queue. This reduces us to 253 SCBs: 1 that just completed 154 * and the known three additional empty slots in the queue that 155 * precede it. 156 */ 157 #define AHC_MAX_QUEUE 253 158 159 /* 160 * The maximum amount of SCB storage we allocate in host memory. This 161 * number should reflect the 1 additional SCB we require to handle our 162 * qinfifo mechanism. 163 */ 164 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 165 166 /* 167 * Ring Buffer of incoming target commands. 168 * We allocate 256 to simplify the logic in the sequencer 169 * by using the natural wrap point of an 8bit counter. 170 */ 171 #define AHC_TMODE_CMDS 256 172 173 /* Reset line assertion time in us */ 174 #define AHC_BUSRESET_DELAY 250 175 176 /******************* Chip Characteristics/Operating Settings *****************/ 177 /* 178 * Chip Type 179 * The chip order is from least sophisticated to most sophisticated. 180 */ 181 typedef enum { 182 AHC_NONE = 0x0000, 183 AHC_CHIPID_MASK = 0x00FF, 184 AHC_AIC7770 = 0x0001, 185 AHC_AIC7850 = 0x0002, 186 AHC_AIC7855 = 0x0003, 187 AHC_AIC7859 = 0x0004, 188 AHC_AIC7860 = 0x0005, 189 AHC_AIC7870 = 0x0006, 190 AHC_AIC7880 = 0x0007, 191 AHC_AIC7895 = 0x0008, 192 AHC_AIC7895C = 0x0009, 193 AHC_AIC7890 = 0x000a, 194 AHC_AIC7896 = 0x000b, 195 AHC_AIC7892 = 0x000c, 196 AHC_AIC7899 = 0x000d, 197 AHC_VL = 0x0100, /* Bus type VL */ 198 AHC_EISA = 0x0200, /* Bus type EISA */ 199 AHC_PCI = 0x0400, /* Bus type PCI */ 200 AHC_BUS_MASK = 0x0F00 201 } ahc_chip; 202 203 /* 204 * Features available in each chip type. 205 */ 206 typedef enum { 207 AHC_FENONE = 0x00000, 208 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 209 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 210 AHC_WIDE = 0x00004, /* Wide Channel */ 211 AHC_TWIN = 0x00008, /* Twin Channel */ 212 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 213 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 214 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 215 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 216 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 217 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 218 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 219 AHC_DT = 0x00800, /* Double Transition transfers */ 220 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 221 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 222 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 223 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 224 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 225 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 226 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 227 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 228 AHC_AIC7770_FE = AHC_FENONE, 229 /* 230 * The real 7850 does not support Ultra modes, but there are 231 * several cards that use the generic 7850 PCI ID even though 232 * they are using an Ultra capable chip (7859/7860). We start 233 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 234 * register to determine if the capability is really present. 235 */ 236 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 237 AHC_AIC7860_FE = AHC_AIC7850_FE, 238 AHC_AIC7870_FE = AHC_TARGETMODE, 239 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 240 /* 241 * Although we have space for both the initiator and 242 * target roles on ULTRA2 chips, we currently disable 243 * the initiator role to allow multi-scsi-id target mode 244 * configurations. We can only respond on the same SCSI 245 * ID as our initiator role if we allow initiator operation. 246 * At some point, we should add a configuration knob to 247 * allow both roles to be loaded. 248 */ 249 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 250 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 251 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 252 |AHC_TARGETMODE, 253 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 254 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 255 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 256 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 257 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 258 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 259 } ahc_feature; 260 261 /* 262 * Bugs in the silicon that we work around in software. 263 */ 264 typedef enum { 265 AHC_BUGNONE = 0x00, 266 /* 267 * On all chips prior to the U2 product line, 268 * the WIDEODD S/G segment feature does not 269 * work during scsi->HostBus transfers. 270 */ 271 AHC_TMODE_WIDEODD_BUG = 0x01, 272 /* 273 * On the aic7890/91 Rev 0 chips, the autoflush 274 * feature does not work. A manual flush of 275 * the DMA FIFO is required. 276 */ 277 AHC_AUTOFLUSH_BUG = 0x02, 278 /* 279 * On many chips, cacheline streaming does not work. 280 */ 281 AHC_CACHETHEN_BUG = 0x04, 282 /* 283 * On the aic7896/97 chips, cacheline 284 * streaming must be enabled. 285 */ 286 AHC_CACHETHEN_DIS_BUG = 0x08, 287 /* 288 * PCI 2.1 Retry failure on non-empty data fifo. 289 */ 290 AHC_PCI_2_1_RETRY_BUG = 0x10, 291 /* 292 * Controller does not handle cacheline residuals 293 * properly on S/G segments if PCI MWI instructions 294 * are allowed. 295 */ 296 AHC_PCI_MWI_BUG = 0x20, 297 /* 298 * An SCB upload using the SCB channel's 299 * auto array entry copy feature may 300 * corrupt data. This appears to only 301 * occur on 66MHz systems. 302 */ 303 AHC_SCBCHAN_UPLOAD_BUG = 0x40 304 } ahc_bug; 305 306 /* 307 * Configuration specific settings. 308 * The driver determines these settings by probing the 309 * chip/controller's configuration. 310 */ 311 typedef enum { 312 AHC_FNONE = 0x000, 313 AHC_PRIMARY_CHANNEL = 0x003,/* 314 * The channel that should 315 * be probed first. 316 */ 317 AHC_USEDEFAULTS = 0x004,/* 318 * For cards without an seeprom 319 * or a BIOS to initialize the chip's 320 * SRAM, we use the default target 321 * settings. 322 */ 323 AHC_SEQUENCER_DEBUG = 0x008, 324 AHC_SHARED_SRAM = 0x010, 325 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 326 AHC_RESET_BUS_A = 0x040, 327 AHC_RESET_BUS_B = 0x080, 328 AHC_EXTENDED_TRANS_A = 0x100, 329 AHC_EXTENDED_TRANS_B = 0x200, 330 AHC_TERM_ENB_A = 0x400, 331 AHC_TERM_ENB_B = 0x800, 332 AHC_INITIATORROLE = 0x1000,/* 333 * Allow initiator operations on 334 * this controller. 335 */ 336 AHC_TARGETROLE = 0x2000,/* 337 * Allow target operations on this 338 * controller. 339 */ 340 AHC_NEWEEPROM_FMT = 0x4000, 341 AHC_RESOURCE_SHORTAGE = 0x8000, 342 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 343 AHC_INT50_SPEEDFLEX = 0x20000,/* 344 * Internal 50pin connector 345 * sits behind an aic3860 346 */ 347 AHC_SCB_BTT = 0x40000,/* 348 * The busy targets table is 349 * stored in SCB space rather 350 * than SRAM. 351 */ 352 AHC_BIOS_ENABLED = 0x80000, 353 AHC_ALL_INTERRUPTS = 0x100000, 354 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 355 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 356 AHC_39BIT_ADDRESSING = 0x1000000 /* Use 39 bit addressing scheme. */ 357 } ahc_flag; 358 359 /************************* Hardware SCB Definition ***************************/ 360 361 /* 362 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 363 * consists of a "hardware SCB" mirroring the fields availible on the card 364 * and additional information the kernel stores for each transaction. 365 * 366 * To minimize space utilization, a portion of the hardware scb stores 367 * different data during different portions of a SCSI transaction. 368 * As initialized by the host driver for the initiator role, this area 369 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 370 * the cdb has been presented to the target, this area serves to store 371 * residual transfer information and the SCSI status byte. 372 * For the target role, the contents of this area do not change, but 373 * still serve a different purpose than for the initiator role. See 374 * struct target_data for details. 375 */ 376 377 /* 378 * Status information embedded in the shared poriton of 379 * an SCB after passing the cdb to the target. The kernel 380 * driver will only read this data for transactions that 381 * complete abnormally (non-zero status byte). 382 */ 383 struct status_pkt { 384 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 385 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 386 uint8_t scsi_status; /* Standard SCSI status byte */ 387 }; 388 389 /* 390 * Target mode version of the shared data SCB segment. 391 */ 392 struct target_data { 393 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 394 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 395 uint8_t scsi_status; /* SCSI status to give to initiator */ 396 uint8_t target_phases; /* Bitmap of phases to execute */ 397 uint8_t data_phase; /* Data-In or Data-Out */ 398 uint8_t initiator_tag; /* Initiator's transaction tag */ 399 }; 400 401 struct hardware_scb { 402 /*0*/ union { 403 /* 404 * If the cdb is 12 bytes or less, we embed it directly 405 * in the SCB. For longer cdbs, we embed the address 406 * of the cdb payload as seen by the chip and a DMA 407 * is used to pull it in. 408 */ 409 uint8_t cdb[12]; 410 uint32_t cdb_ptr; 411 struct status_pkt status; 412 struct target_data tdata; 413 } shared_data; 414 /* 415 * A word about residuals. 416 * The scb is presented to the sequencer with the dataptr and datacnt 417 * fields initialized to the contents of the first S/G element to 418 * transfer. The sgptr field is initialized to the bus address for 419 * the S/G element that follows the first in the in core S/G array 420 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 421 * S/G entry for this transfer (single S/G element transfer with the 422 * first elements address and length preloaded in the dataptr/datacnt 423 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 424 * The SG_FULL_RESID flag ensures that the residual will be correctly 425 * noted even if no data transfers occur. Once the data phase is entered, 426 * the residual sgptr and datacnt are loaded from the sgptr and the 427 * datacnt fields. After each S/G element's dataptr and length are 428 * loaded into the hardware, the residual sgptr is advanced. After 429 * each S/G element is expired, its datacnt field is checked to see 430 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 431 * residual sg ptr and the transfer is considered complete. If the 432 * sequencer determines that there is a residual in the tranfer, it 433 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 434 * host memory. To sumarize: 435 * 436 * Sequencer: 437 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 438 * or residual_sgptr does not have SG_LIST_NULL set. 439 * 440 * o We are transfering the last segment if residual_datacnt has 441 * the SG_LAST_SEG flag set. 442 * 443 * Host: 444 * o A residual has occurred if a completed scb has the 445 * SG_RESID_VALID flag set. 446 * 447 * o residual_sgptr and sgptr refer to the "next" sg entry 448 * and so may point beyond the last valid sg entry for the 449 * transfer. 450 */ 451 /*12*/ uint32_t dataptr; 452 /*16*/ uint32_t datacnt; /* 453 * Byte 3 (numbered from 0) of 454 * the datacnt is really the 455 * 4th byte in that data address. 456 */ 457 /*20*/ uint32_t sgptr; 458 #define SG_PTR_MASK 0xFFFFFFF8 459 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 460 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 461 /*26*/ uint8_t lun; 462 /*27*/ uint8_t tag; /* 463 * Index into our kernel SCB array. 464 * Also used as the tag for tagged I/O 465 */ 466 /*28*/ uint8_t cdb_len; 467 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 468 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 469 /*31*/ uint8_t next; /* 470 * Used for threading SCBs in the 471 * "Waiting for Selection" and 472 * "Disconnected SCB" lists down 473 * in the sequencer. 474 */ 475 /*32*/ uint8_t cdb32[32]; /* 476 * CDB storage for cdbs of size 477 * 13->32. We store them here 478 * because hardware scbs are 479 * allocated from DMA safe 480 * memory so we are guaranteed 481 * the controller can access 482 * this data. 483 */ 484 }; 485 486 /************************ Kernel SCB Definitions ******************************/ 487 /* 488 * Some fields of the SCB are OS dependent. Here we collect the 489 * definitions for elements that all OS platforms need to include 490 * in there SCB definition. 491 */ 492 493 /* 494 * Definition of a scatter/gather element as transfered to the controller. 495 * The aic7xxx chips only support a 24bit length. We use the top byte of 496 * the length to store additional address bits and a flag to indicate 497 * that a given segment terminates the transfer. This gives us an 498 * addressable range of 512GB on machines with 64bit PCI or with chips 499 * that can support dual address cycles on 32bit PCI busses. 500 */ 501 struct ahc_dma_seg { 502 uint32_t addr; 503 uint32_t len; 504 #define AHC_DMA_LAST_SEG 0x80000000 505 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 506 #define AHC_SG_LEN_MASK 0x00FFFFFF 507 }; 508 509 struct sg_map_node { 510 bus_dmamap_t sg_dmamap; 511 bus_addr_t sg_physaddr; 512 struct ahc_dma_seg* sg_vaddr; 513 SLIST_ENTRY(sg_map_node) links; 514 }; 515 516 /* 517 * The current state of this SCB. 518 */ 519 typedef enum { 520 SCB_FREE = 0x0000, 521 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 522 * Another device was active 523 * during the first timeout for 524 * this SCB so we gave ourselves 525 * an additional timeout period 526 * in case it was hogging the 527 * bus. 528 */ 529 SCB_DEVICE_RESET = 0x0004, 530 SCB_SENSE = 0x0008, 531 SCB_CDB32_PTR = 0x0010, 532 SCB_RECOVERY_SCB = 0x0020, 533 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 534 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 535 SCB_ABORT = 0x1000, 536 SCB_UNTAGGEDQ = 0x2000, 537 SCB_ACTIVE = 0x4000, 538 SCB_TARGET_IMMEDIATE = 0x8000 539 } scb_flag; 540 541 struct scb { 542 struct hardware_scb *hscb; 543 union { 544 SLIST_ENTRY(scb) sle; 545 TAILQ_ENTRY(scb) tqe; 546 } links; 547 LIST_ENTRY(scb) pending_links; 548 ahc_io_ctx_t io_ctx; 549 struct ahc_softc *ahc_softc; 550 scb_flag flags; 551 #ifndef __linux__ 552 bus_dmamap_t dmamap; 553 #endif 554 struct scb_platform_data *platform_data; 555 struct sg_map_node *sg_map; 556 struct ahc_dma_seg *sg_list; 557 bus_addr_t sg_list_phys; 558 u_int sg_count;/* How full ahc_dma_seg is */ 559 }; 560 561 struct scb_data { 562 SLIST_HEAD(, scb) free_scbs; /* 563 * Pool of SCBs ready to be assigned 564 * commands to execute. 565 */ 566 struct scb *scbindex[256]; /* 567 * Mapping from tag to SCB. 568 * As tag identifiers are an 569 * 8bit value, we provide space 570 * for all possible tag values. 571 * Any lookups to entries at or 572 * above AHC_SCB_MAX_ALLOC will 573 * always fail. 574 */ 575 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 576 struct scb *scbarray; /* Array of kernel SCBs */ 577 struct scsi_sense_data *sense; /* Per SCB sense data */ 578 579 /* 580 * "Bus" addresses of our data structures. 581 */ 582 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 583 bus_dmamap_t hscb_dmamap; 584 bus_addr_t hscb_busaddr; 585 bus_dma_tag_t sense_dmat; 586 bus_dmamap_t sense_dmamap; 587 bus_addr_t sense_busaddr; 588 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 589 SLIST_HEAD(, sg_map_node) sg_maps; 590 uint8_t numscbs; 591 uint8_t maxhscbs; /* Number of SCBs on the card */ 592 uint8_t init_level; /* 593 * How far we've initialized 594 * this structure. 595 */ 596 }; 597 598 /************************ Target Mode Definitions *****************************/ 599 600 /* 601 * Connection desciptor for select-in requests in target mode. 602 */ 603 struct target_cmd { 604 uint8_t scsiid; /* Our ID and the initiator's ID */ 605 uint8_t identify; /* Identify message */ 606 uint8_t bytes[22]; /* 607 * Bytes contains any additional message 608 * bytes terminated by 0xFF. The remainder 609 * is the cdb to execute. 610 */ 611 uint8_t cmd_valid; /* 612 * When a command is complete, the firmware 613 * will set cmd_valid to all bits set. 614 * After the host has seen the command, 615 * the bits are cleared. This allows us 616 * to just peek at host memory to determine 617 * if more work is complete. cmd_valid is on 618 * an 8 byte boundary to simplify setting 619 * it on aic7880 hardware which only has 620 * limited direct access to the DMA FIFO. 621 */ 622 uint8_t pad[7]; 623 }; 624 625 /* 626 * Number of events we can buffer up if we run out 627 * of immediate notify ccbs. 628 */ 629 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 630 struct ahc_tmode_event { 631 uint8_t initiator_id; 632 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 633 #define EVENT_TYPE_BUS_RESET 0xFF 634 uint8_t event_arg; 635 }; 636 637 /* 638 * Per enabled lun target mode state. 639 * As this state is directly influenced by the host OS'es target mode 640 * environment, we let the OS module define it. Forward declare the 641 * structure here so we can store arrays of them, etc. in OS neutral 642 * data structures. 643 */ 644 #ifdef AHC_TARGET_MODE 645 struct ahc_tmode_lstate { 646 struct cam_path *path; 647 struct ccb_hdr_slist accept_tios; 648 struct ccb_hdr_slist immed_notifies; 649 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 650 uint8_t event_r_idx; 651 uint8_t event_w_idx; 652 }; 653 #else 654 struct ahc_tmode_lstate; 655 #endif 656 657 /******************** Transfer Negotiation Datastructures *********************/ 658 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 659 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 660 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 661 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 662 663 /* 664 * Transfer Negotiation Information. 665 */ 666 struct ahc_transinfo { 667 uint8_t protocol_version; /* SCSI Revision level */ 668 uint8_t transport_version; /* SPI Revision level */ 669 uint8_t width; /* Bus width */ 670 uint8_t period; /* Sync rate factor */ 671 uint8_t offset; /* Sync offset */ 672 uint8_t ppr_options; /* Parallel Protocol Request options */ 673 }; 674 675 /* 676 * Per-initiator current, goal and user transfer negotiation information. */ 677 struct ahc_initiator_tinfo { 678 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 679 struct ahc_transinfo curr; 680 struct ahc_transinfo goal; 681 struct ahc_transinfo user; 682 }; 683 684 /* 685 * Per enabled target ID state. 686 * Pointers to lun target state as well as sync/wide negotiation information 687 * for each initiator<->target mapping. For the initiator role we pretend 688 * that we are the target and the targets are the initiators since the 689 * negotiation is the same regardless of role. 690 */ 691 struct ahc_tmode_tstate { 692 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 693 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 694 695 /* 696 * Per initiator state bitmasks. 697 */ 698 uint16_t auto_negotiate;/* Auto Negotiation Required */ 699 uint16_t ultraenb; /* Using ultra sync rate */ 700 uint16_t discenable; /* Disconnection allowed */ 701 uint16_t tagenable; /* Tagged Queuing allowed */ 702 }; 703 704 /* 705 * Data structure for our table of allowed synchronous transfer rates. 706 */ 707 struct ahc_syncrate { 708 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 709 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 710 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 711 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 712 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 713 uint8_t period; /* Period to send to SCSI target */ 714 char *rate; 715 }; 716 717 /* 718 * The synchronouse transfer rate table. 719 */ 720 extern struct ahc_syncrate ahc_syncrates[]; 721 722 /* 723 * Indexes into our table of syncronous transfer rates. 724 */ 725 #define AHC_SYNCRATE_DT 0 726 #define AHC_SYNCRATE_ULTRA2 1 727 #define AHC_SYNCRATE_ULTRA 3 728 #define AHC_SYNCRATE_FAST 6 729 730 /***************************** Lookup Tables **********************************/ 731 /* 732 * Phase -> name and message out response 733 * to parity errors in each phase table. 734 */ 735 struct ahc_phase_table_entry { 736 uint8_t phase; 737 uint8_t mesg_out; /* Message response to parity errors */ 738 char *phasemsg; 739 }; 740 741 /************************** Serial EEPROM Format ******************************/ 742 743 struct seeprom_config { 744 /* 745 * Per SCSI ID Configuration Flags 746 */ 747 uint16_t device_flags[16]; /* words 0-15 */ 748 #define CFXFER 0x0007 /* synchronous transfer rate */ 749 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 750 #define CFDISC 0x0010 /* enable disconnection */ 751 #define CFWIDEB 0x0020 /* wide bus device */ 752 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 753 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 754 #define CFSTART 0x0100 /* send start unit SCSI command */ 755 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 756 #define CFRNFOUND 0x0400 /* report even if not found */ 757 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 758 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 759 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 760 761 /* 762 * BIOS Control Bits 763 */ 764 uint16_t bios_control; /* word 16 */ 765 #define CFSUPREM 0x0001 /* support all removeable drives */ 766 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 767 #define CFBIOSEN 0x0004 /* BIOS enabled */ 768 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 769 #define CFSM2DRV 0x0010 /* support more than two drives */ 770 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 771 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 772 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 773 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 774 #define CFEXTEND 0x0080 /* extended translation enabled */ 775 #define CFSCAMEN 0x0100 /* SCAM enable */ 776 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 777 #define CFMSG_VERBOSE 0x0000 778 #define CFMSG_SILENT 0x0200 779 #define CFMSG_DIAG 0x0400 780 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 781 /* UNUSED 0xff00 */ 782 783 /* 784 * Host Adapter Control Bits 785 */ 786 uint16_t adapter_control; /* word 17 */ 787 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 788 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 789 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 790 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 791 #define CFSTERM 0x0004 /* SCSI low byte termination */ 792 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 793 #define CFSPARITY 0x0010 /* SCSI parity */ 794 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 795 #define CFMULTILUN 0x0020 796 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 797 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 798 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 799 #define CFBOOTCHANSHIFT 8 800 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 801 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 802 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 803 #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 804 805 /* 806 * Bus Release Time, Host Adapter ID 807 */ 808 uint16_t brtime_id; /* word 18 */ 809 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 810 /* UNUSED 0x00f0 */ 811 #define CFBRTIME 0xff00 /* bus release time */ 812 813 /* 814 * Maximum targets 815 */ 816 uint16_t max_targets; /* word 19 */ 817 #define CFMAXTARG 0x00ff /* maximum targets */ 818 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 819 #define CFBOOTID 0xf000 /* Target to boot from */ 820 uint16_t res_1[10]; /* words 20-29 */ 821 uint16_t signature; /* Signature == 0x250 */ 822 #define CFSIGNATURE 0x250 823 #define CFSIGNATURE2 0x300 824 uint16_t checksum; /* word 31 */ 825 }; 826 827 /**************************** Message Buffer *********************************/ 828 typedef enum { 829 MSG_TYPE_NONE = 0x00, 830 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 831 MSG_TYPE_INITIATOR_MSGIN = 0x02, 832 MSG_TYPE_TARGET_MSGOUT = 0x03, 833 MSG_TYPE_TARGET_MSGIN = 0x04 834 } ahc_msg_type; 835 836 typedef enum { 837 MSGLOOP_IN_PROG, 838 MSGLOOP_MSGCOMPLETE, 839 MSGLOOP_TERMINATED 840 } msg_loop_stat; 841 842 /*********************** Software Configuration Structure *********************/ 843 TAILQ_HEAD(scb_tailq, scb); 844 845 struct ahc_suspend_channel_state { 846 uint8_t scsiseq; 847 uint8_t sxfrctl0; 848 uint8_t sxfrctl1; 849 uint8_t simode0; 850 uint8_t simode1; 851 uint8_t seltimer; 852 uint8_t seqctl; 853 }; 854 855 struct ahc_suspend_state { 856 struct ahc_suspend_channel_state channel[2]; 857 uint8_t optionmode; 858 uint8_t dscommand0; 859 uint8_t dspcistatus; 860 /* hsmailbox */ 861 uint8_t crccontrol1; 862 uint8_t scbbaddr; 863 /* Host and sequencer SCB counts */ 864 uint8_t dff_thrsh; 865 uint8_t *scratch_ram; 866 uint8_t *btt; 867 }; 868 869 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 870 871 struct ahc_softc { 872 bus_space_tag_t tag; 873 bus_space_handle_t bsh; 874 #ifndef __linux__ 875 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 876 #endif 877 struct scb_data *scb_data; 878 879 struct scb *next_queued_scb; 880 881 /* 882 * SCBs that have been sent to the controller 883 */ 884 LIST_HEAD(, scb) pending_scbs; 885 886 /* 887 * Counting lock for deferring the release of additional 888 * untagged transactions from the untagged_queues. When 889 * the lock is decremented to 0, all queues in the 890 * untagged_queues array are run. 891 */ 892 u_int untagged_queue_lock; 893 894 /* 895 * Per-target queue of untagged-transactions. The 896 * transaction at the head of the queue is the 897 * currently pending untagged transaction for the 898 * target. The driver only allows a single untagged 899 * transaction per target. 900 */ 901 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 902 903 /* 904 * Platform specific data. 905 */ 906 struct ahc_platform_data *platform_data; 907 908 /* 909 * Platform specific device information. 910 */ 911 ahc_dev_softc_t dev_softc; 912 913 /* 914 * Bus specific device information. 915 */ 916 ahc_bus_intr_t bus_intr; 917 918 /* 919 * Target mode related state kept on a per enabled lun basis. 920 * Targets that are not enabled will have null entries. 921 * As an initiator, we keep one target entry for our initiator 922 * ID to store our sync/wide transfer settings. 923 */ 924 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 925 926 /* 927 * The black hole device responsible for handling requests for 928 * disabled luns on enabled targets. 929 */ 930 struct ahc_tmode_lstate *black_hole; 931 932 /* 933 * Device instance currently on the bus awaiting a continue TIO 934 * for a command that was not given the disconnect priveledge. 935 */ 936 struct ahc_tmode_lstate *pending_device; 937 938 /* 939 * Card characteristics 940 */ 941 ahc_chip chip; 942 ahc_feature features; 943 ahc_bug bugs; 944 ahc_flag flags; 945 946 /* Values to store in the SEQCTL register for pause and unpause */ 947 uint8_t unpause; 948 uint8_t pause; 949 950 /* Command Queues */ 951 uint8_t qoutfifonext; 952 uint8_t qinfifonext; 953 uint8_t *qoutfifo; 954 uint8_t *qinfifo; 955 956 /* Critical Section Data */ 957 struct cs *critical_sections; 958 u_int num_critical_sections; 959 960 /* Links for chaining softcs */ 961 TAILQ_ENTRY(ahc_softc) links; 962 963 /* Channel Names ('A', 'B', etc.) */ 964 char channel; 965 char channel_b; 966 967 /* Initiator Bus ID */ 968 uint8_t our_id; 969 uint8_t our_id_b; 970 971 /* 972 * PCI error detection. 973 */ 974 int unsolicited_ints; 975 976 /* 977 * Target incoming command FIFO. 978 */ 979 struct target_cmd *targetcmds; 980 uint8_t tqinfifonext; 981 982 /* 983 * Incoming and outgoing message handling. 984 */ 985 uint8_t send_msg_perror; 986 ahc_msg_type msg_type; 987 uint8_t msgout_buf[12];/* Message we are sending */ 988 uint8_t msgin_buf[12];/* Message we are receiving */ 989 u_int msgout_len; /* Length of message to send */ 990 u_int msgout_index; /* Current index in msgout */ 991 u_int msgin_index; /* Current index in msgin */ 992 993 /* 994 * Mapping information for data structures shared 995 * between the sequencer and kernel. 996 */ 997 bus_dma_tag_t parent_dmat; 998 bus_dma_tag_t shared_data_dmat; 999 bus_dmamap_t shared_data_dmamap; 1000 bus_addr_t shared_data_busaddr; 1001 1002 /* 1003 * Bus address of the one byte buffer used to 1004 * work-around a DMA bug for chips <= aic7880 1005 * in target mode. 1006 */ 1007 bus_addr_t dma_bug_buf; 1008 1009 /* Information saved through suspend/resume cycles */ 1010 struct ahc_suspend_state suspend_state; 1011 1012 /* Number of enabled target mode device on this card */ 1013 u_int enabled_luns; 1014 1015 /* Initialization level of this data structure */ 1016 u_int init_level; 1017 1018 /* PCI cacheline size. */ 1019 u_int pci_cachesize; 1020 1021 /* Per-Unit descriptive information */ 1022 const char *description; 1023 char *name; 1024 int unit; 1025 1026 /* Selection Timer settings */ 1027 int seltime; 1028 int seltime_b; 1029 1030 uint16_t user_discenable;/* Disconnection allowed */ 1031 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1032 }; 1033 1034 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1035 extern struct ahc_softc_tailq ahc_tailq; 1036 1037 /************************ Active Device Information ***************************/ 1038 typedef enum { 1039 ROLE_UNKNOWN, 1040 ROLE_INITIATOR, 1041 ROLE_TARGET 1042 } role_t; 1043 1044 struct ahc_devinfo { 1045 int our_scsiid; 1046 int target_offset; 1047 uint16_t target_mask; 1048 u_int target; 1049 u_int lun; 1050 char channel; 1051 role_t role; /* 1052 * Only guaranteed to be correct if not 1053 * in the busfree state. 1054 */ 1055 }; 1056 1057 /****************************** PCI Structures ********************************/ 1058 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1059 1060 struct ahc_pci_identity { 1061 uint64_t full_id; 1062 uint64_t id_mask; 1063 char *name; 1064 ahc_device_setup_t *setup; 1065 }; 1066 extern struct ahc_pci_identity ahc_pci_ident_table []; 1067 extern const u_int ahc_num_pci_devs; 1068 1069 /***************************** VL/EISA Declarations ***************************/ 1070 struct aic7770_identity { 1071 uint32_t full_id; 1072 uint32_t id_mask; 1073 char *name; 1074 ahc_device_setup_t *setup; 1075 }; 1076 extern struct aic7770_identity aic7770_ident_table []; 1077 extern const int ahc_num_aic7770_devs; 1078 1079 #define AHC_EISA_SLOT_OFFSET 0xc00 1080 #define AHC_EISA_IOSIZE 0x100 1081 1082 /*************************** Function Declarations ****************************/ 1083 /******************************************************************************/ 1084 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1085 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1086 void ahc_busy_tcl(struct ahc_softc *ahc, 1087 u_int tcl, u_int busyid); 1088 1089 /***************************** PCI Front End *********************************/ 1090 struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1091 int ahc_pci_config(struct ahc_softc *, 1092 struct ahc_pci_identity *); 1093 1094 /*************************** EISA/VL Front End ********************************/ 1095 struct aic7770_identity *aic7770_find_device(uint32_t); 1096 int aic7770_config(struct ahc_softc *ahc, 1097 struct aic7770_identity *, 1098 u_int port); 1099 1100 /************************** SCB and SCB queue management **********************/ 1101 int ahc_probe_scbs(struct ahc_softc *); 1102 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1103 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1104 struct scb_tailq *queue); 1105 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1106 struct scb *scb); 1107 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1108 int target, char channel, int lun, 1109 u_int tag, role_t role); 1110 1111 /****************************** Initialization ********************************/ 1112 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1113 int ahc_softc_init(struct ahc_softc *); 1114 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1115 int ahc_init(struct ahc_softc *ahc); 1116 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1117 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1118 int ahc_suspend(struct ahc_softc *ahc); 1119 int ahc_resume(struct ahc_softc *ahc); 1120 void ahc_softc_insert(struct ahc_softc *); 1121 struct ahc_softc *ahc_find_softc(struct ahc_softc *ahc); 1122 void ahc_set_unit(struct ahc_softc *, int); 1123 void ahc_set_name(struct ahc_softc *, char *); 1124 void ahc_alloc_scbs(struct ahc_softc *ahc); 1125 void ahc_free(struct ahc_softc *ahc); 1126 int ahc_reset(struct ahc_softc *ahc); 1127 void ahc_shutdown(void *arg); 1128 1129 /*************************** Interrupt Services *******************************/ 1130 void ahc_pci_intr(struct ahc_softc *ahc); 1131 void ahc_clear_intstat(struct ahc_softc *ahc); 1132 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1133 #ifdef AHC_TARGET_MODE 1134 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1135 #endif 1136 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1137 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1138 void ahc_handle_scsiint(struct ahc_softc *ahc, 1139 u_int intstat); 1140 void ahc_clear_critical_section(struct ahc_softc *ahc); 1141 1142 /***************************** Error Recovery *********************************/ 1143 typedef enum { 1144 SEARCH_COMPLETE, 1145 SEARCH_COUNT, 1146 SEARCH_REMOVE 1147 } ahc_search_action; 1148 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1149 char channel, int lun, u_int tag, 1150 role_t role, uint32_t status, 1151 ahc_search_action action); 1152 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1153 char channel, int lun, u_int tag, 1154 int stop_on_first, int remove, 1155 int save_state); 1156 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1157 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1158 int initiate_reset); 1159 int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1160 char channel, int lun, u_int tag, 1161 role_t role, uint32_t status); 1162 void ahc_restart(struct ahc_softc *ahc); 1163 void ahc_calc_residual(struct ahc_softc *ahc, 1164 struct scb *scb); 1165 /*************************** Utility Functions ********************************/ 1166 struct ahc_phase_table_entry* 1167 ahc_lookup_phase_entry(int phase); 1168 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1169 u_int our_id, u_int target, 1170 u_int lun, char channel, 1171 role_t role); 1172 /************************** Transfer Negotiation ******************************/ 1173 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1174 u_int *ppr_options, u_int maxsync); 1175 u_int ahc_find_period(struct ahc_softc *ahc, 1176 u_int scsirate, u_int maxsync); 1177 void ahc_validate_offset(struct ahc_softc *ahc, 1178 struct ahc_initiator_tinfo *tinfo, 1179 struct ahc_syncrate *syncrate, 1180 u_int *offset, int wide, 1181 role_t role); 1182 void ahc_validate_width(struct ahc_softc *ahc, 1183 struct ahc_initiator_tinfo *tinfo, 1184 u_int *bus_width, 1185 role_t role); 1186 int ahc_update_neg_request(struct ahc_softc*, 1187 struct ahc_devinfo*, 1188 struct ahc_tmode_tstate*, 1189 struct ahc_initiator_tinfo*, 1190 int /*force*/); 1191 void ahc_set_width(struct ahc_softc *ahc, 1192 struct ahc_devinfo *devinfo, 1193 u_int width, u_int type, int paused); 1194 void ahc_set_syncrate(struct ahc_softc *ahc, 1195 struct ahc_devinfo *devinfo, 1196 struct ahc_syncrate *syncrate, 1197 u_int period, u_int offset, 1198 u_int ppr_options, 1199 u_int type, int paused); 1200 typedef enum { 1201 AHC_QUEUE_NONE, 1202 AHC_QUEUE_BASIC, 1203 AHC_QUEUE_TAGGED 1204 } ahc_queue_alg; 1205 1206 void ahc_set_tags(struct ahc_softc *ahc, 1207 struct ahc_devinfo *devinfo, 1208 ahc_queue_alg alg); 1209 1210 /**************************** Target Mode *************************************/ 1211 #ifdef AHC_TARGET_MODE 1212 void ahc_send_lstate_events(struct ahc_softc *, 1213 struct ahc_tmode_lstate *); 1214 void ahc_handle_en_lun(struct ahc_softc *ahc, 1215 struct cam_sim *sim, union ccb *ccb); 1216 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1217 struct cam_sim *sim, union ccb *ccb, 1218 struct ahc_tmode_tstate **tstate, 1219 struct ahc_tmode_lstate **lstate, 1220 int notfound_failure); 1221 #ifndef AHC_TMODE_ENABLE 1222 #define AHC_TMODE_ENABLE 0 1223 #endif 1224 #endif 1225 /******************************* Debug ***************************************/ 1226 #ifdef AHC_DEBUG 1227 extern int ahc_debug; 1228 #define AHC_SHOWMISC 0x1 1229 #define AHC_SHOWSENSE 0x2 1230 #endif 1231 void ahc_print_scb(struct scb *scb); 1232 void ahc_dump_card_state(struct ahc_softc *ahc); 1233 /******************************* SEEPROM *************************************/ 1234 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1235 struct seeprom_descriptor *sd); 1236 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1237 #endif /* _AIC7XXX_H_ */ 1238