1 /*- 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $ 43 */ 44 45 #ifndef _AIC7XXX_H_ 46 #define _AIC7XXX_H_ 47 48 /* Register Definitions */ 49 #include "aic7xxx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahc_platform_data; 53 struct scb_platform_data; 54 struct seeprom_descriptor; 55 56 /****************************** Useful Macros *********************************/ 57 #ifndef MAX 58 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59 #endif 60 61 #ifndef MIN 62 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63 #endif 64 65 #ifndef TRUE 66 #define TRUE 1 67 #endif 68 #ifndef FALSE 69 #define FALSE 0 70 #endif 71 72 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74 #define ALL_CHANNELS '\0' 75 #define ALL_TARGETS_MASK 0xFFFF 76 #define INITIATOR_WILDCARD (~0) 77 78 #define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81 #define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83 #define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89 #define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91 #define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93 #define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95 #define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun & LID) 97 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99 #define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101 #ifdef AHC_DEBUG 102 #define SCB_IS_SILENT(scb) \ 103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105 #else 106 #define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108 #endif 109 #define TCL_TARGET_OFFSET(tcl) \ 110 ((((tcl) >> 4) & TID) >> 4) 111 #define TCL_LUN(tcl) \ 112 (tcl & (AHC_NUM_LUNS - 1)) 113 #define BUILD_TCL(scsiid, lun) \ 114 ((lun) | (((scsiid) & TID) << 4)) 115 116 #ifndef AHC_TARGET_MODE 117 #undef AHC_TMODE_ENABLE 118 #define AHC_TMODE_ENABLE 0 119 #endif 120 121 /**************************** Driver Constants ********************************/ 122 /* 123 * The maximum number of supported targets. 124 */ 125 #define AHC_NUM_TARGETS 16 126 127 /* 128 * The maximum number of supported luns. 129 * The identify message only supports 64 luns in SPI3. 130 * You can have 2^64 luns when information unit transfers are enabled, 131 * but it is doubtful this driver will ever support IUTs. 132 */ 133 #define AHC_NUM_LUNS 64 134 135 /* 136 * The maximum transfer per S/G segment. 137 */ 138 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 139 140 /* 141 * The maximum amount of SCB storage in hardware on a controller. 142 * This value represents an upper bound. Controllers vary in the number 143 * they actually support. 144 */ 145 #define AHC_SCB_MAX 255 146 147 /* 148 * The maximum number of concurrent transactions supported per driver instance. 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 150 * the space for SCBs on the host adapter varies by model, the driver will 151 * page the SCBs between host and controller memory as needed. We are limited 152 * to 253 because: 153 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 154 * 2) We reserve one value, 255, to represent the invalid element. 155 * 3) Our input queue scheme requires one SCB to always be reserved 156 * in advance of queuing any SCBs. This takes us down to 254. 157 * 4) To handle our output queue correctly on machines that only 158 * support 32bit stores, we must clear the array 4 bytes at a 159 * time. To avoid colliding with a DMA write from the sequencer, 160 * we must be sure that 4 slots are empty when we write to clear 161 * the queue. This reduces us to 253 SCBs: 1 that just completed 162 * and the known three additional empty slots in the queue that 163 * precede it. 164 */ 165 #define AHC_MAX_QUEUE 253 166 167 /* 168 * The maximum amount of SCB storage we allocate in host memory. This 169 * number should reflect the 1 additional SCB we require to handle our 170 * qinfifo mechanism. 171 */ 172 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 173 174 /* 175 * Ring Buffer of incoming target commands. 176 * We allocate 256 to simplify the logic in the sequencer 177 * by using the natural wrap point of an 8bit counter. 178 */ 179 #define AHC_TMODE_CMDS 256 180 181 /* Reset line assertion time in us */ 182 #define AHC_BUSRESET_DELAY 25 183 184 /* Phase change constants used in target mode. */ 185 #define AHC_BUSSETTLE_DELAY 400 186 #define AHC_DATARELEASE_DELAY 400 187 188 /******************* Chip Characteristics/Operating Settings *****************/ 189 /* 190 * Chip Type 191 * The chip order is from least sophisticated to most sophisticated. 192 */ 193 typedef enum { 194 AHC_NONE = 0x0000, 195 AHC_CHIPID_MASK = 0x00FF, 196 AHC_AIC7770 = 0x0001, 197 AHC_AIC7850 = 0x0002, 198 AHC_AIC7855 = 0x0003, 199 AHC_AIC7859 = 0x0004, 200 AHC_AIC7860 = 0x0005, 201 AHC_AIC7870 = 0x0006, 202 AHC_AIC7880 = 0x0007, 203 AHC_AIC7895 = 0x0008, 204 AHC_AIC7895C = 0x0009, 205 AHC_AIC7890 = 0x000a, 206 AHC_AIC7896 = 0x000b, 207 AHC_AIC7892 = 0x000c, 208 AHC_AIC7899 = 0x000d, 209 AHC_VL = 0x0100, /* Bus type VL */ 210 AHC_EISA = 0x0200, /* Bus type EISA/ISA */ 211 AHC_PCI = 0x0400, /* Bus type PCI */ 212 AHC_BUS_MASK = 0x0F00 213 } ahc_chip; 214 215 /* 216 * Features available in each chip type. 217 */ 218 typedef enum { 219 AHC_FENONE = 0x00000, 220 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 221 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 222 AHC_WIDE = 0x00004, /* Wide Channel */ 223 AHC_TWIN = 0x00008, /* Twin Channel */ 224 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 225 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 226 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 227 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 228 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 229 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 230 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 231 AHC_DT = 0x00800, /* Double Transition transfers */ 232 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 233 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 234 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 235 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 236 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 237 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 238 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 239 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 240 AHC_AIC7770_FE = AHC_FENONE, 241 /* 242 * The real 7850 does not support Ultra modes, but there are 243 * several cards that use the generic 7850 PCI ID even though 244 * they are using an Ultra capable chip (7859/7860). We start 245 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 246 * register to determine if the capability is really present. 247 */ 248 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 249 AHC_AIC7860_FE = AHC_AIC7850_FE, 250 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 251 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 252 /* 253 * Although we have space for both the initiator and 254 * target roles on ULTRA2 chips, we currently disable 255 * the initiator role to allow multi-scsi-id target mode 256 * configurations. We can only respond on the same SCSI 257 * ID as our initiator role if we allow initiator operation. 258 * At some point, we should add a configuration knob to 259 * allow both roles to be loaded. 260 */ 261 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 262 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 263 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 264 |AHC_TARGETMODE, 265 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 266 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 267 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 268 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 269 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 270 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 271 } ahc_feature; 272 273 /* 274 * Bugs in the silicon that we work around in software. 275 */ 276 typedef enum { 277 AHC_BUGNONE = 0x00, 278 /* 279 * On all chips prior to the U2 product line, 280 * the WIDEODD S/G segment feature does not 281 * work during scsi->HostBus transfers. 282 */ 283 AHC_TMODE_WIDEODD_BUG = 0x01, 284 /* 285 * On the aic7890/91 Rev 0 chips, the autoflush 286 * feature does not work. A manual flush of 287 * the DMA FIFO is required. 288 */ 289 AHC_AUTOFLUSH_BUG = 0x02, 290 /* 291 * On many chips, cacheline streaming does not work. 292 */ 293 AHC_CACHETHEN_BUG = 0x04, 294 /* 295 * On the aic7896/97 chips, cacheline 296 * streaming must be enabled. 297 */ 298 AHC_CACHETHEN_DIS_BUG = 0x08, 299 /* 300 * PCI 2.1 Retry failure on non-empty data fifo. 301 */ 302 AHC_PCI_2_1_RETRY_BUG = 0x10, 303 /* 304 * Controller does not handle cacheline residuals 305 * properly on S/G segments if PCI MWI instructions 306 * are allowed. 307 */ 308 AHC_PCI_MWI_BUG = 0x20, 309 /* 310 * An SCB upload using the SCB channel's 311 * auto array entry copy feature may 312 * corrupt data. This appears to only 313 * occur on 66MHz systems. 314 */ 315 AHC_SCBCHAN_UPLOAD_BUG = 0x40 316 } ahc_bug; 317 318 /* 319 * Configuration specific settings. 320 * The driver determines these settings by probing the 321 * chip/controller's configuration. 322 */ 323 typedef enum { 324 AHC_FNONE = 0x000, 325 AHC_PRIMARY_CHANNEL = 0x003, /* 326 * The channel that should 327 * be probed first. 328 */ 329 AHC_USEDEFAULTS = 0x004, /* 330 * For cards without an seeprom 331 * or a BIOS to initialize the chip's 332 * SRAM, we use the default target 333 * settings. 334 */ 335 AHC_SEQUENCER_DEBUG = 0x008, 336 AHC_SHARED_SRAM = 0x010, 337 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 338 AHC_RESET_BUS_A = 0x040, 339 AHC_RESET_BUS_B = 0x080, 340 AHC_EXTENDED_TRANS_A = 0x100, 341 AHC_EXTENDED_TRANS_B = 0x200, 342 AHC_TERM_ENB_A = 0x400, 343 AHC_TERM_ENB_B = 0x800, 344 AHC_INITIATORROLE = 0x1000, /* 345 * Allow initiator operations on 346 * this controller. 347 */ 348 AHC_TARGETROLE = 0x2000, /* 349 * Allow target operations on this 350 * controller. 351 */ 352 AHC_NEWEEPROM_FMT = 0x4000, 353 AHC_RESOURCE_SHORTAGE = 0x8000, 354 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 355 AHC_INT50_SPEEDFLEX = 0x20000, /* 356 * Internal 50pin connector 357 * sits behind an aic3860 358 */ 359 AHC_SCB_BTT = 0x40000, /* 360 * The busy targets table is 361 * stored in SCB space rather 362 * than SRAM. 363 */ 364 AHC_BIOS_ENABLED = 0x80000, 365 AHC_ALL_INTERRUPTS = 0x100000, 366 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 367 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 368 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 369 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 370 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 371 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 372 AHC_DISABLE_PCI_PERR = 0x10000000, 373 AHC_HAS_TERM_LOGIC = 0x20000000, 374 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 375 } ahc_flag; 376 377 /************************* Hardware SCB Definition ***************************/ 378 379 /* 380 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 381 * consists of a "hardware SCB" mirroring the fields available on the card 382 * and additional information the kernel stores for each transaction. 383 * 384 * To minimize space utilization, a portion of the hardware scb stores 385 * different data during different portions of a SCSI transaction. 386 * As initialized by the host driver for the initiator role, this area 387 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 388 * the cdb has been presented to the target, this area serves to store 389 * residual transfer information and the SCSI status byte. 390 * For the target role, the contents of this area do not change, but 391 * still serve a different purpose than for the initiator role. See 392 * struct target_data for details. 393 */ 394 395 /* 396 * Status information embedded in the shared poriton of 397 * an SCB after passing the cdb to the target. The kernel 398 * driver will only read this data for transactions that 399 * complete abnormally (non-zero status byte). 400 */ 401 struct status_pkt { 402 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 403 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 404 uint8_t scsi_status; /* Standard SCSI status byte */ 405 }; 406 407 /* 408 * Target mode version of the shared data SCB segment. 409 */ 410 struct target_data { 411 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 412 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 413 uint8_t scsi_status; /* SCSI status to give to initiator */ 414 uint8_t target_phases; /* Bitmap of phases to execute */ 415 uint8_t data_phase; /* Data-In or Data-Out */ 416 uint8_t initiator_tag; /* Initiator's transaction tag */ 417 }; 418 419 #define MAX_CDB_LEN 16 420 struct hardware_scb { 421 /*0*/ union { 422 /* 423 * If the cdb is 12 bytes or less, we embed it directly 424 * in the SCB. For longer cdbs, we embed the address 425 * of the cdb payload as seen by the chip and a DMA 426 * is used to pull it in. 427 */ 428 uint8_t cdb[12]; 429 uint32_t cdb_ptr; 430 struct status_pkt status; 431 struct target_data tdata; 432 } shared_data; 433 /* 434 * A word about residuals. 435 * The scb is presented to the sequencer with the dataptr and datacnt 436 * fields initialized to the contents of the first S/G element to 437 * transfer. The sgptr field is initialized to the bus address for 438 * the S/G element that follows the first in the in core S/G array 439 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 440 * S/G entry for this transfer (single S/G element transfer with the 441 * first elements address and length preloaded in the dataptr/datacnt 442 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 443 * The SG_FULL_RESID flag ensures that the residual will be correctly 444 * noted even if no data transfers occur. Once the data phase is entered, 445 * the residual sgptr and datacnt are loaded from the sgptr and the 446 * datacnt fields. After each S/G element's dataptr and length are 447 * loaded into the hardware, the residual sgptr is advanced. After 448 * each S/G element is expired, its datacnt field is checked to see 449 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 450 * residual sg ptr and the transfer is considered complete. If the 451 * sequencer determines that there is a residual in the transfer, it 452 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 453 * host memory. To sumarize: 454 * 455 * Sequencer: 456 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 457 * or residual_sgptr does not have SG_LIST_NULL set. 458 * 459 * o We are transferring the last segment if residual_datacnt has 460 * the SG_LAST_SEG flag set. 461 * 462 * Host: 463 * o A residual has occurred if a completed scb has the 464 * SG_RESID_VALID flag set. 465 * 466 * o residual_sgptr and sgptr refer to the "next" sg entry 467 * and so may point beyond the last valid sg entry for the 468 * transfer. 469 */ 470 /*12*/ uint32_t dataptr; 471 /*16*/ uint32_t datacnt; /* 472 * Byte 3 (numbered from 0) of 473 * the datacnt is really the 474 * 4th byte in that data address. 475 */ 476 /*20*/ uint32_t sgptr; 477 #define SG_PTR_MASK 0xFFFFFFF8 478 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 479 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 480 /*26*/ uint8_t lun; 481 /*27*/ uint8_t tag; /* 482 * Index into our kernel SCB array. 483 * Also used as the tag for tagged I/O 484 */ 485 /*28*/ uint8_t cdb_len; 486 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 487 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 488 /*31*/ uint8_t next; /* 489 * Used for threading SCBs in the 490 * "Waiting for Selection" and 491 * "Disconnected SCB" lists down 492 * in the sequencer. 493 */ 494 /*32*/ uint8_t cdb32[32]; /* 495 * CDB storage for cdbs of size 496 * 13->32. We store them here 497 * because hardware scbs are 498 * allocated from DMA safe 499 * memory so we are guaranteed 500 * the controller can access 501 * this data. 502 */ 503 }; 504 505 /************************ Kernel SCB Definitions ******************************/ 506 /* 507 * Some fields of the SCB are OS dependent. Here we collect the 508 * definitions for elements that all OS platforms need to include 509 * in there SCB definition. 510 */ 511 512 /* 513 * Definition of a scatter/gather element as transferred to the controller. 514 * The aic7xxx chips only support a 24bit length. We use the top byte of 515 * the length to store additional address bits and a flag to indicate 516 * that a given segment terminates the transfer. This gives us an 517 * addressable range of 512GB on machines with 64bit PCI or with chips 518 * that can support dual address cycles on 32bit PCI busses. 519 */ 520 struct ahc_dma_seg { 521 uint32_t addr; 522 uint32_t len; 523 #define AHC_DMA_LAST_SEG 0x80000000 524 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 525 #define AHC_SG_LEN_MASK 0x00FFFFFF 526 }; 527 528 struct sg_map_node { 529 bus_dmamap_t sg_dmamap; 530 bus_addr_t sg_physaddr; 531 struct ahc_dma_seg* sg_vaddr; 532 SLIST_ENTRY(sg_map_node) links; 533 }; 534 535 /* 536 * The current state of this SCB. 537 */ 538 typedef enum { 539 SCB_FLAG_NONE = 0x0000, 540 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 541 * Another device was active 542 * during the first timeout for 543 * this SCB so we gave ourselves 544 * an additional timeout period 545 * in case it was hogging the 546 * bus. 547 */ 548 SCB_DEVICE_RESET = 0x0004, 549 SCB_SENSE = 0x0008, 550 SCB_CDB32_PTR = 0x0010, 551 SCB_RECOVERY_SCB = 0x0020, 552 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 553 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 554 SCB_ABORT = 0x0100, 555 SCB_UNTAGGEDQ = 0x0200, 556 SCB_ACTIVE = 0x0400, 557 SCB_TARGET_IMMEDIATE = 0x0800, 558 SCB_TRANSMISSION_ERROR = 0x1000,/* 559 * We detected a parity or CRC 560 * error that has effected the 561 * payload of the command. This 562 * flag is checked when normal 563 * status is returned to catch 564 * the case of a target not 565 * responding to our attempt 566 * to report the error. 567 */ 568 SCB_TARGET_SCB = 0x2000, 569 SCB_SILENT = 0x4000,/* 570 * Be quiet about transmission type 571 * errors. They are expected and we 572 * don't want to upset the user. This 573 * flag is typically used during DV. 574 */ 575 SCB_TIMEDOUT = 0x8000 /* 576 * SCB has timed out and is on the 577 * timedout list. 578 */ 579 } scb_flag; 580 581 struct scb { 582 struct hardware_scb *hscb; 583 union { 584 SLIST_ENTRY(scb) sle; 585 TAILQ_ENTRY(scb) tqe; 586 } links; 587 LIST_ENTRY(scb) pending_links; 588 LIST_ENTRY(scb) timedout_links; 589 aic_io_ctx_t io_ctx; 590 struct ahc_softc *ahc_softc; 591 scb_flag flags; 592 bus_dmamap_t dmamap; 593 struct scb_platform_data *platform_data; 594 struct sg_map_node *sg_map; 595 struct ahc_dma_seg *sg_list; 596 bus_addr_t sg_list_phys; 597 u_int sg_count;/* How full ahc_dma_seg is */ 598 aic_timer_t io_timer; 599 }; 600 601 struct scb_data { 602 SLIST_HEAD(, scb) free_scbs; /* 603 * Pool of SCBs ready to be assigned 604 * commands to execute. 605 */ 606 struct scb *scbindex[256]; /* 607 * Mapping from tag to SCB. 608 * As tag identifiers are an 609 * 8bit value, we provide space 610 * for all possible tag values. 611 * Any lookups to entries at or 612 * above AHC_SCB_MAX_ALLOC will 613 * always fail. 614 */ 615 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 616 struct scb *scbarray; /* Array of kernel SCBs */ 617 struct scsi_sense_data *sense; /* Per SCB sense data */ 618 619 u_int recovery_scbs; /* Transactions currently in recovery */ 620 621 /* 622 * "Bus" addresses of our data structures. 623 */ 624 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 625 bus_dmamap_t hscb_dmamap; 626 bus_addr_t hscb_busaddr; 627 bus_dma_tag_t sense_dmat; 628 bus_dmamap_t sense_dmamap; 629 bus_addr_t sense_busaddr; 630 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 631 SLIST_HEAD(, sg_map_node) sg_maps; 632 uint8_t numscbs; 633 uint8_t maxhscbs; /* Number of SCBs on the card */ 634 uint8_t init_level; /* 635 * How far we've initialized 636 * this structure. 637 */ 638 }; 639 640 /************************ Target Mode Definitions *****************************/ 641 642 /* 643 * Connection descriptor for select-in requests in target mode. 644 */ 645 struct target_cmd { 646 uint8_t scsiid; /* Our ID and the initiator's ID */ 647 uint8_t identify; /* Identify message */ 648 uint8_t bytes[22]; /* 649 * Bytes contains any additional message 650 * bytes terminated by 0xFF. The remainder 651 * is the cdb to execute. 652 */ 653 uint8_t cmd_valid; /* 654 * When a command is complete, the firmware 655 * will set cmd_valid to all bits set. 656 * After the host has seen the command, 657 * the bits are cleared. This allows us 658 * to just peek at host memory to determine 659 * if more work is complete. cmd_valid is on 660 * an 8 byte boundary to simplify setting 661 * it on aic7880 hardware which only has 662 * limited direct access to the DMA FIFO. 663 */ 664 uint8_t pad[7]; 665 }; 666 667 /* 668 * Number of events we can buffer up if we run out 669 * of immediate notify ccbs. 670 */ 671 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 672 struct ahc_tmode_event { 673 uint8_t initiator_id; 674 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 675 #define EVENT_TYPE_BUS_RESET 0xFF 676 uint8_t event_arg; 677 }; 678 679 /* 680 * Per enabled lun target mode state. 681 * As this state is directly influenced by the host OS'es target mode 682 * environment, we let the OS module define it. Forward declare the 683 * structure here so we can store arrays of them, etc. in OS neutral 684 * data structures. 685 */ 686 #ifdef AHC_TARGET_MODE 687 struct ahc_tmode_lstate { 688 struct cam_path *path; 689 struct ccb_hdr_slist accept_tios; 690 struct ccb_hdr_slist immed_notifies; 691 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 692 uint8_t event_r_idx; 693 uint8_t event_w_idx; 694 }; 695 #else 696 struct ahc_tmode_lstate; 697 #endif 698 699 /******************** Transfer Negotiation Datastructures *********************/ 700 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 701 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 702 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 703 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 704 705 #define AHC_WIDTH_UNKNOWN 0xFF 706 #define AHC_PERIOD_UNKNOWN 0xFF 707 #define AHC_OFFSET_UNKNOWN 0xFF 708 #define AHC_PPR_OPTS_UNKNOWN 0xFF 709 710 /* 711 * Transfer Negotiation Information. 712 */ 713 struct ahc_transinfo { 714 uint8_t protocol_version; /* SCSI Revision level */ 715 uint8_t transport_version; /* SPI Revision level */ 716 uint8_t width; /* Bus width */ 717 uint8_t period; /* Sync rate factor */ 718 uint8_t offset; /* Sync offset */ 719 uint8_t ppr_options; /* Parallel Protocol Request options */ 720 }; 721 722 /* 723 * Per-initiator current, goal and user transfer negotiation information. */ 724 struct ahc_initiator_tinfo { 725 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 726 struct ahc_transinfo curr; 727 struct ahc_transinfo goal; 728 struct ahc_transinfo user; 729 }; 730 731 /* 732 * Per enabled target ID state. 733 * Pointers to lun target state as well as sync/wide negotiation information 734 * for each initiator<->target mapping. For the initiator role we pretend 735 * that we are the target and the targets are the initiators since the 736 * negotiation is the same regardless of role. 737 */ 738 struct ahc_tmode_tstate { 739 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 740 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 741 742 /* 743 * Per initiator state bitmasks. 744 */ 745 uint16_t auto_negotiate;/* Auto Negotiation Required */ 746 uint16_t ultraenb; /* Using ultra sync rate */ 747 uint16_t discenable; /* Disconnection allowed */ 748 uint16_t tagenable; /* Tagged Queuing allowed */ 749 }; 750 751 /* 752 * Data structure for our table of allowed synchronous transfer rates. 753 */ 754 struct ahc_syncrate { 755 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 756 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 757 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 758 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 759 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 760 uint8_t period; /* Period to send to SCSI target */ 761 char *rate; 762 }; 763 764 /* Safe and valid period for async negotiations. */ 765 #define AHC_ASYNC_XFER_PERIOD 0x45 766 #define AHC_ULTRA2_XFER_PERIOD 0x0a 767 768 /* 769 * Indexes into our table of synchronous transfer rates. 770 */ 771 #define AHC_SYNCRATE_DT 0 772 #define AHC_SYNCRATE_ULTRA2 1 773 #define AHC_SYNCRATE_ULTRA 3 774 #define AHC_SYNCRATE_FAST 6 775 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 776 #define AHC_SYNCRATE_MIN 13 777 778 /***************************** Lookup Tables **********************************/ 779 /* 780 * Phase -> name and message out response 781 * to parity errors in each phase table. 782 */ 783 struct ahc_phase_table_entry { 784 uint8_t phase; 785 uint8_t mesg_out; /* Message response to parity errors */ 786 char *phasemsg; 787 }; 788 789 /************************** Serial EEPROM Format ******************************/ 790 791 struct seeprom_config { 792 /* 793 * Per SCSI ID Configuration Flags 794 */ 795 uint16_t device_flags[16]; /* words 0-15 */ 796 #define CFXFER 0x0007 /* synchronous transfer rate */ 797 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 798 #define CFDISC 0x0010 /* enable disconnection */ 799 #define CFWIDEB 0x0020 /* wide bus device */ 800 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 801 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 802 #define CFSTART 0x0100 /* send start unit SCSI command */ 803 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 804 #define CFRNFOUND 0x0400 /* report even if not found */ 805 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 806 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 807 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 808 809 /* 810 * BIOS Control Bits 811 */ 812 uint16_t bios_control; /* word 16 */ 813 #define CFSUPREM 0x0001 /* support all removeable drives */ 814 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 815 #define CFBIOSEN 0x0004 /* BIOS enabled */ 816 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 817 #define CFSM2DRV 0x0010 /* support more than two drives */ 818 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 819 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 820 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 821 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 822 #define CFEXTEND 0x0080 /* extended translation enabled */ 823 #define CFSCAMEN 0x0100 /* SCAM enable */ 824 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 825 #define CFMSG_VERBOSE 0x0000 826 #define CFMSG_SILENT 0x0200 827 #define CFMSG_DIAG 0x0400 828 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 829 /* UNUSED 0xff00 */ 830 831 /* 832 * Host Adapter Control Bits 833 */ 834 uint16_t adapter_control; /* word 17 */ 835 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 836 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 837 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 838 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 839 #define CFSTERM 0x0004 /* SCSI low byte termination */ 840 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 841 #define CFSPARITY 0x0010 /* SCSI parity */ 842 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 843 #define CFMULTILUN 0x0020 844 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 845 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 846 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 847 #define CFBOOTCHANSHIFT 8 848 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 849 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 850 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 851 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 852 853 /* 854 * Bus Release Time, Host Adapter ID 855 */ 856 uint16_t brtime_id; /* word 18 */ 857 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 858 /* UNUSED 0x00f0 */ 859 #define CFBRTIME 0xff00 /* bus release time */ 860 861 /* 862 * Maximum targets 863 */ 864 uint16_t max_targets; /* word 19 */ 865 #define CFMAXTARG 0x00ff /* maximum targets */ 866 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 867 #define CFBOOTID 0xf000 /* Target to boot from */ 868 uint16_t res_1[10]; /* words 20-29 */ 869 uint16_t signature; /* Signature == 0x250 */ 870 #define CFSIGNATURE 0x250 871 #define CFSIGNATURE2 0x300 872 uint16_t checksum; /* word 31 */ 873 }; 874 875 /**************************** Message Buffer *********************************/ 876 typedef enum { 877 MSG_TYPE_NONE = 0x00, 878 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 879 MSG_TYPE_INITIATOR_MSGIN = 0x02, 880 MSG_TYPE_TARGET_MSGOUT = 0x03, 881 MSG_TYPE_TARGET_MSGIN = 0x04 882 } ahc_msg_type; 883 884 typedef enum { 885 MSGLOOP_IN_PROG, 886 MSGLOOP_MSGCOMPLETE, 887 MSGLOOP_TERMINATED 888 } msg_loop_stat; 889 890 /*********************** Software Configuration Structure *********************/ 891 TAILQ_HEAD(scb_tailq, scb); 892 893 struct ahc_aic7770_softc { 894 /* 895 * Saved register state used for chip_init(). 896 */ 897 uint8_t busspd; 898 uint8_t bustime; 899 }; 900 901 struct ahc_pci_softc { 902 /* 903 * Saved register state used for chip_init(). 904 */ 905 uint32_t devconfig; 906 uint16_t targcrccnt; 907 uint8_t command; 908 uint8_t csize_lattime; 909 uint8_t optionmode; 910 uint8_t crccontrol1; 911 uint8_t dscommand0; 912 uint8_t dspcistatus; 913 uint8_t scbbaddr; 914 uint8_t dff_thrsh; 915 }; 916 917 union ahc_bus_softc { 918 struct ahc_aic7770_softc aic7770_softc; 919 struct ahc_pci_softc pci_softc; 920 }; 921 922 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 923 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 924 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 925 typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 926 typedef void ahc_callback_t (void *); 927 928 #define AIC_SCB_DATA(softc) ((softc)->scb_data) 929 930 struct ahc_softc { 931 bus_space_tag_t tag; 932 bus_space_handle_t bsh; 933 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 934 struct scb_data *scb_data; 935 936 struct scb *next_queued_scb; 937 938 /* 939 * SCBs that have been sent to the controller 940 */ 941 LIST_HEAD(, scb) pending_scbs; 942 943 /* 944 * SCBs whose timeout routine has been called. 945 */ 946 LIST_HEAD(, scb) timedout_scbs; 947 948 /* 949 * Counting lock for deferring the release of additional 950 * untagged transactions from the untagged_queues. When 951 * the lock is decremented to 0, all queues in the 952 * untagged_queues array are run. 953 */ 954 u_int untagged_queue_lock; 955 956 /* 957 * Per-target queue of untagged-transactions. The 958 * transaction at the head of the queue is the 959 * currently pending untagged transaction for the 960 * target. The driver only allows a single untagged 961 * transaction per target. 962 */ 963 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 964 965 /* 966 * Bus attachment specific data. 967 */ 968 union ahc_bus_softc bus_softc; 969 970 /* 971 * Platform specific data. 972 */ 973 struct ahc_platform_data *platform_data; 974 975 /* 976 * Platform specific device information. 977 */ 978 aic_dev_softc_t dev_softc; 979 980 /* 981 * Bus specific device information. 982 */ 983 ahc_bus_intr_t bus_intr; 984 985 /* 986 * Bus specific initialization required 987 * after a chip reset. 988 */ 989 ahc_bus_chip_init_t bus_chip_init; 990 991 /* 992 * Bus specific suspend routine. 993 */ 994 ahc_bus_suspend_t bus_suspend; 995 996 /* 997 * Bus specific resume routine. 998 */ 999 ahc_bus_resume_t bus_resume; 1000 1001 /* 1002 * Target mode related state kept on a per enabled lun basis. 1003 * Targets that are not enabled will have null entries. 1004 * As an initiator, we keep one target entry for our initiator 1005 * ID to store our sync/wide transfer settings. 1006 */ 1007 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1008 1009 /* 1010 * The black hole device responsible for handling requests for 1011 * disabled luns on enabled targets. 1012 */ 1013 struct ahc_tmode_lstate *black_hole; 1014 1015 /* 1016 * Device instance currently on the bus awaiting a continue TIO 1017 * for a command that was not given the disconnect priveledge. 1018 */ 1019 struct ahc_tmode_lstate *pending_device; 1020 1021 /* 1022 * Card characteristics 1023 */ 1024 ahc_chip chip; 1025 ahc_feature features; 1026 ahc_bug bugs; 1027 ahc_flag flags; 1028 struct seeprom_config *seep_config; 1029 1030 /* Values to store in the SEQCTL register for pause and unpause */ 1031 uint8_t unpause; 1032 uint8_t pause; 1033 1034 /* Command Queues */ 1035 uint8_t qoutfifonext; 1036 uint8_t qinfifonext; 1037 uint8_t *qoutfifo; 1038 uint8_t *qinfifo; 1039 1040 /* Critical Section Data */ 1041 struct cs *critical_sections; 1042 u_int num_critical_sections; 1043 1044 /* Links for chaining softcs */ 1045 TAILQ_ENTRY(ahc_softc) links; 1046 1047 /* Channel Names ('A', 'B', etc.) */ 1048 char channel; 1049 char channel_b; 1050 1051 /* Initiator Bus ID */ 1052 uint8_t our_id; 1053 uint8_t our_id_b; 1054 1055 /* 1056 * PCI error detection. 1057 */ 1058 int unsolicited_ints; 1059 1060 /* 1061 * Target incoming command FIFO. 1062 */ 1063 struct target_cmd *targetcmds; 1064 uint8_t tqinfifonext; 1065 1066 /* 1067 * Cached copy of the sequencer control register. 1068 */ 1069 uint8_t seqctl; 1070 1071 /* 1072 * Incoming and outgoing message handling. 1073 */ 1074 uint8_t send_msg_perror; 1075 ahc_msg_type msg_type; 1076 uint8_t msgout_buf[12];/* Message we are sending */ 1077 uint8_t msgin_buf[12];/* Message we are receiving */ 1078 u_int msgout_len; /* Length of message to send */ 1079 u_int msgout_index; /* Current index in msgout */ 1080 u_int msgin_index; /* Current index in msgin */ 1081 1082 /* 1083 * Mapping information for data structures shared 1084 * between the sequencer and kernel. 1085 */ 1086 bus_dma_tag_t parent_dmat; 1087 bus_dma_tag_t shared_data_dmat; 1088 bus_dmamap_t shared_data_dmamap; 1089 bus_addr_t shared_data_busaddr; 1090 1091 /* 1092 * Bus address of the one byte buffer used to 1093 * work-around a DMA bug for chips <= aic7880 1094 * in target mode. 1095 */ 1096 bus_addr_t dma_bug_buf; 1097 1098 /* Number of enabled target mode device on this card */ 1099 u_int enabled_luns; 1100 1101 /* Initialization level of this data structure */ 1102 u_int init_level; 1103 1104 /* PCI cacheline size. */ 1105 u_int pci_cachesize; 1106 1107 /* 1108 * Count of parity errors we have seen as a target. 1109 * We auto-disable parity error checking after seeing 1110 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1111 */ 1112 u_int pci_target_perr_count; 1113 #define AHC_PCI_TARGET_PERR_THRESH 10 1114 1115 /* Maximum number of sequencer instructions supported. */ 1116 u_int instruction_ram_size; 1117 1118 /* Per-Unit descriptive information */ 1119 const char *description; 1120 char *name; 1121 int unit; 1122 1123 /* Selection Timer settings */ 1124 int seltime; 1125 int seltime_b; 1126 1127 uint16_t user_discenable;/* Disconnection allowed */ 1128 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1129 }; 1130 1131 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1132 extern struct ahc_softc_tailq ahc_tailq; 1133 1134 /************************ Active Device Information ***************************/ 1135 typedef enum { 1136 ROLE_UNKNOWN, 1137 ROLE_INITIATOR, 1138 ROLE_TARGET 1139 } role_t; 1140 1141 struct ahc_devinfo { 1142 int our_scsiid; 1143 int target_offset; 1144 uint16_t target_mask; 1145 u_int target; 1146 u_int lun; 1147 char channel; 1148 role_t role; /* 1149 * Only guaranteed to be correct if not 1150 * in the busfree state. 1151 */ 1152 }; 1153 1154 /****************************** PCI Structures ********************************/ 1155 #define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 1156 #define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 1157 1158 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1159 1160 struct ahc_pci_identity { 1161 uint64_t full_id; 1162 uint64_t id_mask; 1163 char *name; 1164 ahc_device_setup_t *setup; 1165 }; 1166 extern struct ahc_pci_identity ahc_pci_ident_table[]; 1167 extern const u_int ahc_num_pci_devs; 1168 1169 /*************************** VL/EISA/ISA Declarations *************************/ 1170 struct aic7770_identity { 1171 uint32_t full_id; 1172 uint32_t id_mask; 1173 const char *name; 1174 ahc_device_setup_t *setup; 1175 }; 1176 extern struct aic7770_identity aic7770_ident_table[]; 1177 extern const int ahc_num_aic7770_devs; 1178 1179 #define AHC_EISA_SLOT_SIZE 0x1000 1180 #define AHC_EISA_SLOT_OFFSET 0xc00 1181 #define AHC_EISA_IOSIZE 0x100 1182 1183 /*************************** Function Declarations ****************************/ 1184 /******************************************************************************/ 1185 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1186 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1187 void ahc_busy_tcl(struct ahc_softc *ahc, 1188 u_int tcl, u_int busyid); 1189 1190 /***************************** PCI Front End *********************************/ 1191 struct ahc_pci_identity *ahc_find_pci_device(aic_dev_softc_t); 1192 int ahc_pci_config(struct ahc_softc *, 1193 struct ahc_pci_identity *); 1194 int ahc_pci_test_register_access(struct ahc_softc *); 1195 1196 /*************************** ISA/EISA/VL Front End ****************************/ 1197 struct aic7770_identity *aic7770_find_device(uint32_t); 1198 int aic7770_config(struct ahc_softc *ahc, 1199 struct aic7770_identity *, 1200 u_int port); 1201 1202 /************************** SCB and SCB queue management **********************/ 1203 int ahc_probe_scbs(struct ahc_softc *); 1204 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1205 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1206 struct scb_tailq *queue); 1207 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1208 struct scb *scb); 1209 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1210 int target, char channel, int lun, 1211 u_int tag, role_t role); 1212 1213 /****************************** Initialization ********************************/ 1214 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1215 int ahc_softc_init(struct ahc_softc *); 1216 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1217 int ahc_chip_init(struct ahc_softc *ahc); 1218 int ahc_init(struct ahc_softc *ahc); 1219 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1220 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1221 int ahc_suspend(struct ahc_softc *ahc); 1222 int ahc_resume(struct ahc_softc *ahc); 1223 void ahc_softc_insert(struct ahc_softc *); 1224 void ahc_set_unit(struct ahc_softc *, int); 1225 void ahc_set_name(struct ahc_softc *, char *); 1226 int ahc_alloc_scbs(struct ahc_softc *ahc); 1227 void ahc_free(struct ahc_softc *ahc); 1228 int ahc_reset(struct ahc_softc *ahc, int reinit); 1229 void ahc_shutdown(void *arg); 1230 1231 /*************************** Interrupt Services *******************************/ 1232 void ahc_clear_intstat(struct ahc_softc *ahc); 1233 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1234 #ifdef AHC_TARGET_MODE 1235 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1236 #endif 1237 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1238 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1239 void ahc_handle_scsiint(struct ahc_softc *ahc, 1240 u_int intstat); 1241 void ahc_clear_critical_section(struct ahc_softc *ahc); 1242 1243 /***************************** Error Recovery *********************************/ 1244 typedef enum { 1245 SEARCH_COMPLETE, 1246 SEARCH_COUNT, 1247 SEARCH_REMOVE 1248 } ahc_search_action; 1249 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1250 char channel, int lun, u_int tag, 1251 role_t role, uint32_t status, 1252 ahc_search_action action); 1253 int ahc_search_untagged_queues(struct ahc_softc *ahc, 1254 aic_io_ctx_t ctx, 1255 int target, char channel, 1256 int lun, uint32_t status, 1257 ahc_search_action action); 1258 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1259 char channel, int lun, u_int tag, 1260 int stop_on_first, int remove, 1261 int save_state); 1262 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1263 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1264 int initiate_reset); 1265 int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1266 char channel, int lun, u_int tag, 1267 role_t role, uint32_t status); 1268 void ahc_restart(struct ahc_softc *ahc); 1269 void ahc_calc_residual(struct ahc_softc *ahc, 1270 struct scb *scb); 1271 void ahc_timeout(struct scb *scb); 1272 void ahc_recover_commands(struct ahc_softc *ahc); 1273 /*************************** Utility Functions ********************************/ 1274 struct ahc_phase_table_entry* 1275 ahc_lookup_phase_entry(int phase); 1276 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1277 u_int our_id, u_int target, 1278 u_int lun, char channel, 1279 role_t role); 1280 /************************** Transfer Negotiation ******************************/ 1281 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1282 u_int *ppr_options, u_int maxsync); 1283 u_int ahc_find_period(struct ahc_softc *ahc, 1284 u_int scsirate, u_int maxsync); 1285 void ahc_validate_offset(struct ahc_softc *ahc, 1286 struct ahc_initiator_tinfo *tinfo, 1287 struct ahc_syncrate *syncrate, 1288 u_int *offset, int wide, 1289 role_t role); 1290 void ahc_validate_width(struct ahc_softc *ahc, 1291 struct ahc_initiator_tinfo *tinfo, 1292 u_int *bus_width, 1293 role_t role); 1294 /* 1295 * Negotiation types. These are used to qualify if we should renegotiate 1296 * even if our goal and current transport parameters are identical. 1297 */ 1298 typedef enum { 1299 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1300 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1301 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1302 } ahc_neg_type; 1303 int ahc_update_neg_request(struct ahc_softc*, 1304 struct ahc_devinfo*, 1305 struct ahc_tmode_tstate*, 1306 struct ahc_initiator_tinfo*, 1307 ahc_neg_type); 1308 void ahc_set_width(struct ahc_softc *ahc, 1309 struct ahc_devinfo *devinfo, 1310 u_int width, u_int type, int paused); 1311 void ahc_set_syncrate(struct ahc_softc *ahc, 1312 struct ahc_devinfo *devinfo, 1313 struct ahc_syncrate *syncrate, 1314 u_int period, u_int offset, 1315 u_int ppr_options, 1316 u_int type, int paused); 1317 typedef enum { 1318 AHC_QUEUE_NONE, 1319 AHC_QUEUE_BASIC, 1320 AHC_QUEUE_TAGGED 1321 } ahc_queue_alg; 1322 1323 void ahc_set_tags(struct ahc_softc *ahc, 1324 struct ahc_devinfo *devinfo, 1325 ahc_queue_alg alg); 1326 1327 /**************************** Target Mode *************************************/ 1328 #ifdef AHC_TARGET_MODE 1329 void ahc_send_lstate_events(struct ahc_softc *, 1330 struct ahc_tmode_lstate *); 1331 void ahc_handle_en_lun(struct ahc_softc *ahc, 1332 struct cam_sim *sim, union ccb *ccb); 1333 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1334 struct cam_sim *sim, union ccb *ccb, 1335 struct ahc_tmode_tstate **tstate, 1336 struct ahc_tmode_lstate **lstate, 1337 int notfound_failure); 1338 #ifndef AHC_TMODE_ENABLE 1339 #define AHC_TMODE_ENABLE 0 1340 #endif 1341 #endif 1342 /******************************* Debug ***************************************/ 1343 #ifdef AHC_DEBUG 1344 extern uint32_t ahc_debug; 1345 #define AHC_SHOW_MISC 0x0001 1346 #define AHC_SHOW_SENSE 0x0002 1347 #define AHC_DUMP_SEEPROM 0x0004 1348 #define AHC_SHOW_TERMCTL 0x0008 1349 #define AHC_SHOW_MEMORY 0x0010 1350 #define AHC_SHOW_MESSAGES 0x0020 1351 #define AHC_SHOW_DV 0x0040 1352 #define AHC_SHOW_SELTO 0x0080 1353 #define AHC_SHOW_QFULL 0x0200 1354 #define AHC_SHOW_QUEUE 0x0400 1355 #define AHC_SHOW_TQIN 0x0800 1356 #define AHC_SHOW_MASKED_ERRORS 0x1000 1357 #define AHC_DEBUG_SEQUENCER 0x2000 1358 #endif 1359 void ahc_print_scb(struct scb *scb); 1360 void ahc_print_devinfo(struct ahc_softc *ahc, 1361 struct ahc_devinfo *dev); 1362 void ahc_dump_card_state(struct ahc_softc *ahc); 1363 int ahc_print_register(ahc_reg_parse_entry_t *table, 1364 u_int num_entries, 1365 const char *name, 1366 u_int address, 1367 u_int value, 1368 u_int *cur_column, 1369 u_int wrap_point); 1370 /******************************* SEEPROM *************************************/ 1371 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1372 struct seeprom_descriptor *sd); 1373 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1374 #endif /* _AIC7XXX_H_ */ 1375