1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: aic7xxx.h,v 1.40 1997/02/25 03:05:35 gibbs Exp $ 38 */ 39 40 #ifndef _AIC7XXX_H_ 41 #define _AIC7XXX_H_ 42 43 #include "ahc.h" /* for NAHC from config */ 44 #include "opt_aic7xxx.h" /* for config options */ 45 46 #include <pci/pcivar.h> /* for pcici_t */ 47 48 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 49 #define AHC_NSEG 32 /* The number of dma segments supported. 50 * AHC_NSEG can be maxed out at 256 entries, 51 * but the kernel will never need to transfer 52 * such a large (1MB) request. To reduce the 53 * driver's memory consumption, we reduce the 54 * max to 32. 16 would work if all transfers 55 * are paged alined since the kernel will only 56 * generate at most a 64k transfer, but to 57 * handle non-page aligned transfers, you need 58 * 17, so we round to the next power of two 59 * to make allocating SG space easy and 60 * efficient. 61 */ 62 63 #define AHC_SCB_MAX 255 /* 64 * Up to 255 SCBs on some types of aic7xxx 65 * based boards. The aic7870 have 16 internal 66 * SCBs, but external SRAM bumps this to 255. 67 * The aic7770 family have only 4, and the 68 * aic7850 has only 3. 69 */ 70 71 72 #if defined(__FreeBSD__) 73 extern u_long ahc_unit; 74 #endif 75 76 struct ahc_dma_seg { 77 u_int32_t addr; 78 u_int32_t len; 79 }; 80 81 typedef enum { 82 AHC_NONE = 0x0000, 83 AHC_CHIPID_MASK = 0x00FF, 84 AHC_AIC7770 = 0x0001, 85 AHC_AIC7850 = 0x0002, 86 AHC_AIC7860 = 0x0003, 87 AHC_AIC7870 = 0x0004, 88 AHC_AIC7880 = 0x0005, 89 AHC_AIC7890 = 0x0006, 90 AHC_AIC7895 = 0x0007, 91 AHC_AIC7896 = 0x0008, 92 AHC_VL = 0x0100, /* Bus type VL */ 93 AHC_EISA = 0x0200, /* Bus type EISA */ 94 AHC_PCI = 0x0400, /* Bus type PCI */ 95 } ahc_chip; 96 97 typedef enum { 98 AHC_FENONE = 0x0000, 99 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 100 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 101 AHC_WIDE = 0x0004, /* Wide Channel */ 102 AHC_TWIN = 0x0008, /* Twin Channel */ 103 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 104 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 105 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 106 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 107 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 108 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 109 AHC_AIC7770_FE = AHC_FENONE, 110 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 111 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 112 AHC_AIC7870_FE = AHC_FENONE, 113 AHC_AIC7880_FE = AHC_ULTRA, 114 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID, 115 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 116 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID, 117 } ahc_feature; 118 119 typedef enum { 120 AHC_FNONE = 0x000, 121 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 122 AHC_CHANNEL_B_PRIMARY = 0x002,/* 123 * On twin channel adapters, probe 124 * channel B first since it is the 125 * primary bus. 126 */ 127 AHC_USEDEFAULTS = 0x004,/* 128 * For cards without an seeprom 129 * or a BIOS to initialize the chip's 130 * SRAM, we use the default target 131 * settings. 132 */ 133 AHC_INDIRECT_PAGING = 0x008, 134 AHC_SHARED_SRAM = 0x010, 135 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 136 AHC_EXTENDED_TRANS_A = 0x100, 137 AHC_EXTENDED_TRANS_B = 0x200, 138 AHC_TERM_ENB_A = 0x400, 139 AHC_TERM_ENB_B = 0x800, 140 AHC_HANDLING_REQINITS = 0x1000, 141 AHC_TARGETMODE = 0x2000,/* 142 * Allow target operations on this 143 * controller. 144 */ 145 AHC_NEWEEPROM_FMT = 0x4000, 146 AHC_RESOURCE_SHORTAGE = 0x8000 147 } ahc_flag; 148 149 typedef enum { 150 SCB_FREE = 0x0000, 151 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 152 * Another device was active 153 * during the first timeout for 154 * this SCB so we gave ourselves 155 * an additional timeout period 156 * in case it was hogging the 157 * bus. 158 */ 159 SCB_DEVICE_RESET = 0x0004, 160 SCB_SENSE = 0x0008, 161 SCB_RECOVERY_SCB = 0x0040, 162 SCB_MSGOUT_SENT = 0x0200, 163 SCB_MSGOUT_SDTR = 0x0400, 164 SCB_MSGOUT_WDTR = 0x0800, 165 SCB_MSGOUT_BITS = (SCB_MSGOUT_SDTR|SCB_MSGOUT_WDTR 166 |SCB_MSGOUT_SENT), 167 SCB_ABORT = 0x1000, 168 SCB_QUEUED_MSG = 0x2000, 169 SCB_ACTIVE = 0x4000, 170 SCB_TARGET_IMMEDIATE = 0x8000 171 } scb_flag; 172 173 /* 174 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 175 * consists of a "hardware SCB" mirroring the fields availible on the card 176 * and additional information the kernel stores for each transaction. 177 */ 178 struct hardware_scb { 179 /*0*/ u_int8_t control; 180 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 181 /*2*/ u_int8_t status; 182 /*3*/ u_int8_t SG_count; 183 /*4*/ u_int32_t SG_pointer; 184 /*8*/ u_int8_t residual_SG_count; 185 /*9*/ u_int8_t residual_data_count[3]; 186 /*12*/ u_int32_t data; 187 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 188 * faster to treat it as a long on 189 * a quad boundary. 190 */ 191 /*20*/ u_int32_t cmdpointer; 192 /*24*/ u_int8_t cmdlen; 193 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 194 * Also used as the tag for tagged I/O 195 */ 196 /*26*/ u_int8_t next; /* Used for threading SCBs in the 197 * "Waiting for Selection" and 198 * "Disconnected SCB" lists down 199 * in the sequencer. 200 */ 201 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 202 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 203 /*29*/ u_int8_t spare[3]; /* 204 * Spare space available on 205 * all controller types. 206 */ 207 /*32*/ u_int8_t cmdstore[16]; /* 208 * CDB storage for controllers 209 * supporting 64 byte SCBs. 210 */ 211 /*48*/ u_int32_t cmdstore_busaddr; /* 212 * Address of command store for 213 * 32byte SCB adapters 214 */ 215 /*48*/ u_int8_t spare_64[12]; /* 216 * Pad to 64 bytes. 217 */ 218 }; 219 220 struct scb { 221 struct hardware_scb *hscb; 222 STAILQ_ENTRY(scb) links; /* for chaining */ 223 union ccb *ccb; /* the ccb for this cmd */ 224 scb_flag flags; 225 bus_dmamap_t dmamap; 226 struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */ 227 u_int32_t ahc_dmaphys;/* Phsical address of SG list */ 228 u_int sg_count;/* How full ahc_dma_seg is */ 229 }; 230 231 struct scb_data { 232 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 233 struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */ 234 STAILQ_HEAD(, scb) free_scbs; /* 235 * Pool of SCBs ready to be assigned 236 * commands to execute. 237 */ 238 u_int8_t numscbs; 239 u_int8_t maxhscbs; /* Number of SCBs on the card */ 240 u_int8_t maxscbs; /* 241 * Max SCBs we allocate total including 242 * any that will force us to page SCBs 243 */ 244 }; 245 246 /* 247 * Connection desciptor for select-in requests in target mode. 248 * The first byte is the connecting target, followed by identify 249 * message and optional tag information, terminated by 0xFF. The 250 * remainder is the command to execute. 251 */ 252 struct target_cmd { 253 u_int8_t icl; /* Really only holds Initiator ID */ 254 u_int8_t targ_id; /* Target ID we were selected at */ 255 u_int8_t identify; /* Identify message */ 256 u_int8_t bytes[29]; 257 }; 258 259 /* 260 * Per lun target mode state including accept TIO CCB 261 * and immediate notify CCB pools. 262 */ 263 struct tmode_lstate { 264 SLIST_HEAD(, ccb_hdr) accept_tios; 265 SLIST_HEAD(, ccb_hdr) immed_notifies; 266 }; 267 268 /* 269 * Per target mode enabled target state. Esentially just an array of 270 * pointers to lun target state. 271 */ 272 struct tmode_tstate { 273 struct tmode_lstate* enabled_luns[8]; 274 }; 275 276 /* 277 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 278 */ 279 280 struct seeprom_config { 281 /* 282 * SCSI ID Configuration Flags 283 */ 284 u_int16_t device_flags[16]; /* words 0-15 */ 285 #define CFXFER 0x0007 /* synchronous transfer rate */ 286 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 287 #define CFDISC 0x0010 /* enable disconnection */ 288 #define CFWIDEB 0x0020 /* wide bus device */ 289 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 290 /* UNUSED 0x0080 */ 291 #define CFSTART 0x0100 /* send start unit SCSI command */ 292 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 293 #define CFRNFOUND 0x0400 /* report even if not found */ 294 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 295 /* UNUSED 0xf000 */ 296 297 /* 298 * BIOS Control Bits 299 */ 300 u_int16_t bios_control; /* word 16 */ 301 #define CFSUPREM 0x0001 /* support all removeable drives */ 302 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 303 #define CFBIOSEN 0x0004 /* BIOS enabled */ 304 /* UNUSED 0x0008 */ 305 #define CFSM2DRV 0x0010 /* support more than two drives */ 306 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 307 /* UNUSED 0x0060 */ 308 #define CFEXTEND 0x0080 /* extended translation enabled */ 309 /* UNUSED 0xff00 */ 310 311 /* 312 * Host Adapter Control Bits 313 */ 314 u_int16_t adapter_control; /* word 17 */ 315 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 316 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 317 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 318 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 319 #define CFSTERM 0x0004 /* SCSI low byte termination */ 320 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 321 #define CFSPARITY 0x0010 /* SCSI parity */ 322 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 323 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 324 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 325 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 326 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 327 /* UNUSED 0xf080 */ 328 329 /* 330 * Bus Release, Host Adapter ID 331 */ 332 u_int16_t brtime_id; /* word 18 */ 333 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 334 /* UNUSED 0x00f0 */ 335 #define CFBRTIME 0xff00 /* bus release time */ 336 337 /* 338 * Maximum targets 339 */ 340 u_int16_t max_targets; /* word 19 */ 341 #define CFMAXTARG 0x00ff /* maximum targets */ 342 /* UNUSED 0xff00 */ 343 u_int16_t res_1[11]; /* words 20-30 */ 344 u_int16_t checksum; /* word 31 */ 345 }; 346 347 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 348 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 349 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 350 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 351 352 struct ahc_transinfo { 353 u_int8_t width; 354 u_int8_t period; 355 u_int8_t offset; 356 }; 357 358 struct ahc_target_tinfo { 359 u_int8_t scsirate; 360 struct ahc_transinfo current; 361 struct ahc_transinfo goal; 362 struct ahc_transinfo user; 363 }; 364 365 struct ahc_syncrate { 366 int sxfr_ultra2; 367 int sxfr; 368 /* Rates in Ultra mode have bit 8 of sxfr set */ 369 #define ULTRA_SXFR 0x100 370 u_int8_t period; /* Period to send to SCSI target */ 371 char *rate; 372 }; 373 374 typedef enum { 375 MSG_TYPE_NONE = 0x00, 376 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 377 MSG_TYPE_INITIATOR_MSGIN = 0x02 378 } ahc_msg_type; 379 380 struct ahc_softc { 381 bus_space_tag_t tag; 382 bus_space_handle_t bsh; 383 bus_dma_tag_t dmat; 384 struct scb_data *scb_data; 385 386 /* 387 * CCBs that have been send to the controller 388 */ 389 LIST_HEAD(, ccb_hdr) pending_ccbs; 390 391 /* 392 * Target mode related state kept on a per enabled lun basis. 393 * Targets that are not enabled will have null entries. 394 */ 395 struct tmode_tstate* enabled_targets[16]; 396 397 /* 398 * Device instance currently on the bus awaiting a continue TIO 399 * for a command that was not given the disconnect priveledge. 400 */ 401 struct tmode_lstate* pending_device; 402 403 /* 404 * Card characteristics 405 */ 406 ahc_chip chip; 407 ahc_feature features; 408 ahc_flag flags; 409 410 /* Values to store in the SEQCTL register for pause and unpause */ 411 u_int8_t unpause; 412 u_int8_t pause; 413 414 /* Command Queues */ 415 u_int8_t qoutfifonext; 416 u_int8_t qinfifonext; 417 u_int8_t qoutfifo[256]; 418 u_int8_t qinfifo[256]; 419 420 /* 421 * 256 byte array storing the SCBID of outstanding 422 * untagged SCBs indexed by TCL. 423 */ 424 u_int8_t untagged_scbs[256]; 425 426 /* 427 * User/Current/Active Negotiation settings 428 */ 429 struct ahc_target_tinfo transinfo[16]; 430 431 /* 432 * Per target state bitmasks. 433 */ 434 u_int16_t ultraenb; /* Using ultra sync rate */ 435 u_int16_t sdtrpending; /* Pending SDTR request */ 436 u_int16_t wdtrpending; /* Pending WDTR request */ 437 u_int16_t discenable; /* Disconnection allowed */ 438 u_int16_t tagenable; /* Tagged Queuing allowed */ 439 440 /* 441 * Hooks into the XPT. 442 */ 443 struct cam_sim *sim; 444 struct cam_sim *sim_b; 445 struct cam_path *path; 446 struct cam_path *path_b; 447 448 int unit; 449 450 /* Channel Names ('A', 'B', etc.) */ 451 char channel; 452 char channel_b; 453 454 /* Initiator Bus ID */ 455 u_int8_t our_id; 456 u_int8_t our_id_b; 457 458 /* 459 * PCI error detection and data for running the 460 * PCI error interrupt handler. 461 */ 462 int unsolicited_ints; 463 pcici_t pci_config_id; 464 465 /* Hmmm. */ 466 struct target_cmd *targetcmds; 467 int next_targetcmd; 468 int num_targetcmds; 469 470 /* 471 * Incoming and outgoing message handling. 472 */ 473 ahc_msg_type msg_type; 474 u_int8_t msg_buf[8]; /* Message we are sending */ 475 u_int msg_len; /* Length of message to send */ 476 u_int msg_index; /* Current index in message */ 477 478 /* 479 * "Bus" addresses of our data structures. 480 */ 481 u_int32_t hscb_busaddr; 482 }; 483 484 struct full_ahc_softc { 485 struct ahc_softc softc; 486 struct scb_data scb_data_storage; 487 }; 488 489 /* #define AHC_DEBUG */ 490 #ifdef AHC_DEBUG 491 /* Different debugging levels used when AHC_DEBUG is defined */ 492 #define AHC_SHOWMISC 0x0001 493 #define AHC_SHOWCMDS 0x0002 494 #define AHC_SHOWSCBS 0x0004 495 #define AHC_SHOWABORTS 0x0008 496 #define AHC_SHOWSENSE 0x0010 497 #define AHC_SHOWSCBCNT 0x0020 498 499 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 500 #endif 501 502 char *ahc_name(struct ahc_softc *ahc); 503 504 struct ahc_softc *ahc_alloc(int unit, u_int32_t io_base, 505 vm_offset_t maddr, ahc_chip chip, 506 ahc_feature features, ahc_flag flags, 507 struct scb_data *scb_data); 508 int ahc_reset(struct ahc_softc *ahc); 509 void ahc_free(struct ahc_softc *); 510 int ahc_probe_scbs(struct ahc_softc *); 511 int ahc_init(struct ahc_softc *); 512 int ahc_attach(struct ahc_softc *); 513 void ahc_intr(void *arg); 514 515 #define ahc_inb(ahc, port) \ 516 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 517 518 #define ahc_outb(ahc, port, value) \ 519 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 520 521 #define ahc_outsb(ahc, port, valp, count) \ 522 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 523 524 #endif /* _AIC7XXX_H_ */ 525