1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * the GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #include "opt_aic7xxx.h" /* for config options */ 40 41 #include <sys/bus.h> /* For device_t */ 42 43 #ifndef MAX 44 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 45 #endif 46 47 #ifndef MIN 48 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 49 #endif 50 51 /* 52 * The maximum transfer per S/G segment. 53 */ 54 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 55 56 /* 57 * The number of dma segments supported. The current implementation limits 58 * us to 255 S/G entries (this may change to be unlimited at some point). 59 * To reduce the driver's memory consumption, we further limit the number 60 * supported to be sufficient to handle the largest mapping supported by 61 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 62 * and unaligned, this turns out to be the number of paged sized transfers 63 * in MAXPHYS plus an extra element to handle any unaligned residual. 64 */ 65 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 66 67 #define AHC_SCB_MAX 255 /* 68 * Up to 255 SCBs on some types of aic7xxx 69 * based boards. The aic7870 have 16 internal 70 * SCBs, but external SRAM bumps this to 255. 71 * The aic7770 family have only 4, and the 72 * aic7850 has only 3. 73 */ 74 75 #define AHC_TMODE_CMDS 256 /* 76 * Ring Buffer of incoming target commands. 77 * We allocate 256 to simplify the logic 78 * in the sequencer by using the natural 79 * wrap point of an 8bit counter. 80 */ 81 82 struct ahc_dma_seg { 83 u_int32_t addr; 84 u_int32_t len; 85 }; 86 87 typedef enum { 88 AHC_NONE = 0x0000, 89 AHC_CHIPID_MASK = 0x00FF, 90 AHC_AIC7770 = 0x0001, 91 AHC_AIC7850 = 0x0002, 92 AHC_AIC7855 = 0x0003, 93 AHC_AIC7859 = 0x0004, 94 AHC_AIC7860 = 0x0005, 95 AHC_AIC7870 = 0x0006, 96 AHC_AIC7880 = 0x0007, 97 AHC_AIC7890 = 0x0008, 98 AHC_AIC7892 = 0x0009, 99 AHC_AIC7895 = 0x000a, 100 AHC_AIC7896 = 0x000b, 101 AHC_AIC7899 = 0x000c, 102 AHC_VL = 0x0100, /* Bus type VL */ 103 AHC_EISA = 0x0200, /* Bus type EISA */ 104 AHC_PCI = 0x0400, /* Bus type PCI */ 105 AHC_BUS_MASK = 0x0F00 106 } ahc_chip; 107 108 extern char *ahc_chip_names[]; 109 110 typedef enum { 111 AHC_FENONE = 0x0000, 112 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 113 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 114 AHC_WIDE = 0x0004, /* Wide Channel */ 115 AHC_TWIN = 0x0008, /* Twin Channel */ 116 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 117 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 118 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 119 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 120 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 121 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 122 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 123 AHC_DT = 0x0800, /* Double Transition transfers */ 124 AHC_NEW_TERMCTL = 0x1000, 125 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 126 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 127 AHC_AIC7770_FE = AHC_TARG_DMABUG, 128 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 129 AHC_AIC7855_FE = AHC_AIC7850_FE, 130 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 131 AHC_AIC7860_FE = AHC_AIC7859_FE, 132 AHC_AIC7870_FE = AHC_TARG_DMABUG, 133 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 134 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 135 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 136 |AHC_NEW_TERMCTL, 137 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 138 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 139 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 140 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 141 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 142 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 143 } ahc_feature; 144 145 typedef enum { 146 AHC_FNONE = 0x000, 147 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 148 AHC_CHANNEL_B_PRIMARY = 0x002,/* 149 * On twin channel adapters, probe 150 * channel B first since it is the 151 * primary bus. 152 */ 153 AHC_USEDEFAULTS = 0x004,/* 154 * For cards without an seeprom 155 * or a BIOS to initialize the chip's 156 * SRAM, we use the default target 157 * settings. 158 */ 159 AHC_SHARED_SRAM = 0x010, 160 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 161 AHC_RESET_BUS_A = 0x040, 162 AHC_RESET_BUS_B = 0x080, 163 AHC_EXTENDED_TRANS_A = 0x100, 164 AHC_EXTENDED_TRANS_B = 0x200, 165 AHC_TERM_ENB_A = 0x400, 166 AHC_TERM_ENB_B = 0x800, 167 AHC_INITIATORMODE = 0x1000,/* 168 * Allow initiator operations on 169 * this controller. 170 */ 171 AHC_TARGETMODE = 0x2000,/* 172 * Allow target operations on this 173 * controller. 174 */ 175 AHC_NEWEEPROM_FMT = 0x4000, 176 AHC_RESOURCE_SHORTAGE = 0x8000, 177 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 178 AHC_INT50_SPEEDFLEX = 0x20000,/* 179 * Internal 50pin connector 180 * sits behind an aic3860 181 */ 182 } ahc_flag; 183 184 typedef enum { 185 SCB_FREE = 0x0000, 186 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 187 * Another device was active 188 * during the first timeout for 189 * this SCB so we gave ourselves 190 * an additional timeout period 191 * in case it was hogging the 192 * bus. 193 */ 194 SCB_DEVICE_RESET = 0x0004, 195 SCB_SENSE = 0x0008, 196 SCB_RECOVERY_SCB = 0x0040, 197 SCB_ABORT = 0x1000, 198 SCB_QUEUED_MSG = 0x2000, 199 SCB_ACTIVE = 0x4000, 200 SCB_TARGET_IMMEDIATE = 0x8000 201 } scb_flag; 202 203 /* 204 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 205 * consists of a "hardware SCB" mirroring the fields availible on the card 206 * and additional information the kernel stores for each transaction. 207 */ 208 struct hardware_scb { 209 /*0*/ u_int8_t control; 210 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 211 /*2*/ u_int8_t status; 212 /*3*/ u_int8_t SG_count; 213 /*4*/ u_int32_t SG_pointer; 214 /*8*/ u_int8_t residual_SG_count; 215 /*9*/ u_int8_t residual_data_count[3]; 216 /*12*/ u_int32_t data; 217 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 218 * faster to treat it as a long on 219 * a quad boundary. 220 */ 221 /*20*/ u_int32_t cmdpointer; 222 /*24*/ u_int8_t cmdlen; 223 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 224 * Also used as the tag for tagged I/O 225 */ 226 /*26*/ u_int8_t next; /* Used for threading SCBs in the 227 * "Waiting for Selection" and 228 * "Disconnected SCB" lists down 229 * in the sequencer. 230 */ 231 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 232 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 233 /*29*/ u_int8_t spare[3]; /* 234 * Spare space available on 235 * all controller types. 236 */ 237 /*32*/ u_int8_t cmdstore[16]; /* 238 * CDB storage for controllers 239 * supporting 64 byte SCBs. 240 */ 241 /*48*/ u_int32_t cmdstore_busaddr; /* 242 * Address of command store for 243 * 32byte SCB adapters 244 */ 245 /*48*/ u_int8_t spare_64[12]; /* 246 * Pad to 64 bytes. 247 */ 248 }; 249 250 struct scb { 251 struct hardware_scb *hscb; 252 SLIST_ENTRY(scb) links; /* for chaining */ 253 union ccb *ccb; /* the ccb for this cmd */ 254 scb_flag flags; 255 bus_dmamap_t dmamap; 256 struct ahc_dma_seg *sg_list; 257 bus_addr_t sg_list_phys; 258 u_int sg_count;/* How full ahc_dma_seg is */ 259 }; 260 261 /* 262 * Connection desciptor for select-in requests in target mode. 263 * The first byte is the connecting target, followed by identify 264 * message and optional tag information, terminated by 0xFF. The 265 * remainder is the command to execute. The cmd_valid byte is on 266 * an 8 byte boundary to simplify setting it on aic7880 hardware 267 * which only has limited direct access to the DMA FIFO. 268 */ 269 struct target_cmd { 270 u_int8_t initiator_channel; 271 u_int8_t targ_id; /* Target ID we were selected at */ 272 u_int8_t identify; /* Identify message */ 273 u_int8_t bytes[21]; 274 u_int8_t cmd_valid; 275 u_int8_t pad[7]; 276 }; 277 278 /* 279 * Number of events we can buffer up if we run out 280 * of immediate notify ccbs. 281 */ 282 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 283 struct ahc_tmode_event { 284 u_int8_t initiator_id; 285 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 286 #define EVENT_TYPE_BUS_RESET 0xFF 287 u_int8_t event_arg; 288 }; 289 290 /* 291 * Per lun target mode state including accept TIO CCB 292 * and immediate notify CCB pools. 293 */ 294 struct tmode_lstate { 295 struct cam_path *path; 296 struct ccb_hdr_slist accept_tios; 297 struct ccb_hdr_slist immed_notifies; 298 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 299 u_int8_t event_r_idx; 300 u_int8_t event_w_idx; 301 }; 302 303 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 304 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 305 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 306 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 307 308 struct ahc_transinfo { 309 u_int8_t width; 310 u_int8_t period; 311 u_int8_t offset; 312 u_int8_t ppr_flags; 313 }; 314 315 struct ahc_initiator_tinfo { 316 u_int8_t scsirate; 317 struct ahc_transinfo current; 318 struct ahc_transinfo goal; 319 struct ahc_transinfo user; 320 }; 321 322 /* 323 * Per target mode enabled target state. Esentially just an array of 324 * pointers to lun target state as well as sync/wide negotiation information 325 * for each initiator<->target mapping (including the mapping for when we 326 * are the initiator). 327 */ 328 struct tmode_tstate { 329 struct tmode_lstate* enabled_luns[8]; 330 struct ahc_initiator_tinfo transinfo[16]; 331 332 /* 333 * Per initiator state bitmasks. 334 */ 335 u_int16_t ultraenb; /* Using ultra sync rate */ 336 u_int16_t discenable; /* Disconnection allowed */ 337 u_int16_t tagenable; /* Tagged Queuing allowed */ 338 }; 339 340 /* 341 * Define the format of the aic7XXX SEEPROM registers (16 bits). 342 */ 343 344 struct seeprom_config { 345 /* 346 * SCSI ID Configuration Flags 347 */ 348 u_int16_t device_flags[16]; /* words 0-15 */ 349 #define CFXFER 0x0007 /* synchronous transfer rate */ 350 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 351 #define CFDISC 0x0010 /* enable disconnection */ 352 #define CFWIDEB 0x0020 /* wide bus device */ 353 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 354 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 355 #define CFSTART 0x0100 /* send start unit SCSI command */ 356 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 357 #define CFRNFOUND 0x0400 /* report even if not found */ 358 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 359 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 360 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 361 362 /* 363 * BIOS Control Bits 364 */ 365 u_int16_t bios_control; /* word 16 */ 366 #define CFSUPREM 0x0001 /* support all removeable drives */ 367 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 368 #define CFBIOSEN 0x0004 /* BIOS enabled */ 369 /* UNUSED 0x0008 */ 370 #define CFSM2DRV 0x0010 /* support more than two drives */ 371 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 372 /* UNUSED 0x0040 */ 373 #define CFEXTEND 0x0080 /* extended translation enabled */ 374 /* UNUSED 0xff00 */ 375 376 /* 377 * Host Adapter Control Bits 378 */ 379 u_int16_t adapter_control; /* word 17 */ 380 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 381 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 382 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 383 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 384 #define CFSTERM 0x0004 /* SCSI low byte termination */ 385 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 386 #define CFSPARITY 0x0010 /* SCSI parity */ 387 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 388 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 389 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 390 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 391 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 392 /* UNUSED 0xf280 */ 393 394 /* 395 * Bus Release, Host Adapter ID 396 */ 397 u_int16_t brtime_id; /* word 18 */ 398 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 399 /* UNUSED 0x00f0 */ 400 #define CFBRTIME 0xff00 /* bus release time */ 401 402 /* 403 * Maximum targets 404 */ 405 u_int16_t max_targets; /* word 19 */ 406 #define CFMAXTARG 0x00ff /* maximum targets */ 407 /* UNUSED 0xff00 */ 408 u_int16_t res_1[11]; /* words 20-30 */ 409 u_int16_t checksum; /* word 31 */ 410 }; 411 412 struct ahc_syncrate { 413 int sxfr_u2; 414 int sxfr; 415 /* Rates in Ultra mode have bit 8 of sxfr set */ 416 #define ULTRA_SXFR 0x100 417 #define ST_SXFR 0x010 418 u_int8_t period; /* Period to send to SCSI target */ 419 char *rate; 420 }; 421 422 typedef enum { 423 MSG_TYPE_NONE = 0x00, 424 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 425 MSG_TYPE_INITIATOR_MSGIN = 0x02, 426 MSG_TYPE_TARGET_MSGOUT = 0x03, 427 MSG_TYPE_TARGET_MSGIN = 0x04 428 } ahc_msg_type; 429 430 struct sg_map_node { 431 bus_dmamap_t sg_dmamap; 432 bus_addr_t sg_physaddr; 433 struct ahc_dma_seg* sg_vaddr; 434 SLIST_ENTRY(sg_map_node) links; 435 }; 436 437 struct scb_data { 438 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 439 struct scb *scbarray; /* Array of kernel SCBs */ 440 SLIST_HEAD(, scb) free_scbs; /* 441 * Pool of SCBs ready to be assigned 442 * commands to execute. 443 */ 444 struct scsi_sense_data *sense; /* Per SCB sense data */ 445 446 /* 447 * "Bus" addresses of our data structures. 448 */ 449 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 450 bus_dmamap_t hscb_dmamap; 451 bus_addr_t hscb_busaddr; 452 bus_dma_tag_t sense_dmat; 453 bus_dmamap_t sense_dmamap; 454 bus_addr_t sense_busaddr; 455 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 456 SLIST_HEAD(, sg_map_node) sg_maps; 457 u_int8_t numscbs; 458 u_int8_t maxhscbs; /* Number of SCBs on the card */ 459 u_int8_t init_level; /* 460 * How far we've initialized 461 * this structure. 462 */ 463 }; 464 465 struct ahc_softc { 466 bus_space_tag_t tag; 467 bus_space_handle_t bsh; 468 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 469 struct scb_data *scb_data; 470 471 /* 472 * CCBs that have been send to the controller 473 */ 474 LIST_HEAD(, ccb_hdr) pending_ccbs; 475 476 /* 477 * Target mode related state kept on a per enabled lun basis. 478 * Targets that are not enabled will have null entries. 479 * As an initiator, we keep one target entry for our initiator 480 * ID to store our sync/wide transfer settings. 481 */ 482 struct tmode_tstate* enabled_targets[16]; 483 484 /* 485 * The black hole device responsible for handling requests for 486 * disabled luns on enabled targets. 487 */ 488 struct tmode_lstate* black_hole; 489 490 /* 491 * Device instance currently on the bus awaiting a continue TIO 492 * for a command that was not given the disconnect priveledge. 493 */ 494 struct tmode_lstate* pending_device; 495 496 /* 497 * Card characteristics 498 */ 499 ahc_chip chip; 500 ahc_feature features; 501 ahc_flag flags; 502 503 /* Values to store in the SEQCTL register for pause and unpause */ 504 u_int8_t unpause; 505 u_int8_t pause; 506 507 /* Command Queues */ 508 u_int8_t qoutfifonext; 509 u_int8_t qinfifonext; 510 u_int8_t *qoutfifo; 511 u_int8_t *qinfifo; 512 513 /* 514 * 256 byte array storing the SCBID of outstanding 515 * untagged SCBs indexed by TCL. 516 */ 517 u_int8_t *untagged_scbs; 518 519 /* 520 * Hooks into the XPT. 521 */ 522 struct cam_sim *sim; 523 struct cam_sim *sim_b; 524 struct cam_path *path; 525 struct cam_path *path_b; 526 527 int unit; 528 529 /* Channel Names ('A', 'B', etc.) */ 530 char channel; 531 char channel_b; 532 533 /* Initiator Bus ID */ 534 u_int8_t our_id; 535 u_int8_t our_id_b; 536 537 /* Targets that need negotiation messages */ 538 u_int16_t targ_msg_req; 539 540 /* 541 * PCI error detection and data for running the 542 * PCI error interrupt handler. 543 */ 544 int unsolicited_ints; 545 device_t device; 546 547 /* 548 * Target incoming command FIFO. 549 */ 550 struct target_cmd *targetcmds; 551 u_int8_t tqinfifonext; 552 553 /* 554 * Incoming and outgoing message handling. 555 */ 556 u_int8_t send_msg_perror; 557 ahc_msg_type msg_type; 558 u_int8_t msgout_buf[8]; /* Message we are sending */ 559 u_int8_t msgin_buf[8]; /* Message we are receiving */ 560 u_int msgout_len; /* Length of message to send */ 561 u_int msgout_index; /* Current index in msgout */ 562 u_int msgin_index; /* Current index in msgin */ 563 564 int regs_res_type; 565 int regs_res_id; 566 int irq_res_type; 567 struct resource *regs; 568 struct resource *irq; 569 void *ih; 570 bus_dma_tag_t parent_dmat; 571 bus_dma_tag_t shared_data_dmat; 572 bus_dmamap_t shared_data_dmamap; 573 bus_addr_t shared_data_busaddr; 574 bus_addr_t dma_bug_buf; 575 576 /* Number of enabled target mode device on this card */ 577 u_int enabled_luns; 578 579 /* Initialization level of this data structure */ 580 u_int init_level; 581 582 u_int16_t user_discenable;/* Disconnection allowed */ 583 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 584 }; 585 586 struct full_ahc_softc { 587 struct ahc_softc softc; 588 struct scb_data scb_data_storage; 589 }; 590 591 /* #define AHC_DEBUG */ 592 #ifdef AHC_DEBUG 593 /* Different debugging levels used when AHC_DEBUG is defined */ 594 #define AHC_SHOWMISC 0x0001 595 #define AHC_SHOWCMDS 0x0002 596 #define AHC_SHOWSCBS 0x0004 597 #define AHC_SHOWABORTS 0x0008 598 #define AHC_SHOWSENSE 0x0010 599 #define AHC_SHOWSCBCNT 0x0020 600 601 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 602 #endif 603 604 char *ahc_name(struct ahc_softc *ahc); 605 606 struct ahc_softc* 607 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 608 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 609 ahc_feature features, ahc_flag flags, 610 struct scb_data *scb_data); 611 int ahc_reset(struct ahc_softc *ahc); 612 void ahc_free(struct ahc_softc *); 613 int ahc_probe_scbs(struct ahc_softc *); 614 int ahc_init(struct ahc_softc *); 615 int ahc_attach(struct ahc_softc *); 616 void ahc_intr(void *arg); 617 618 #define ahc_inb(ahc, port) \ 619 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 620 621 #define ahc_outb(ahc, port, value) \ 622 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 623 624 #define ahc_outsb(ahc, port, valp, count) \ 625 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 626 627 #define ahc_insb(ahc, port, valp, count) \ 628 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 629 630 #endif /* _AIC7XXX_H_ */ 631