1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#13 $ 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 /* Register Definitions */ 40 #include "aic7xxx_reg.h" 41 42 /************************* Forward Declarations *******************************/ 43 struct ahc_platform_data; 44 struct scb_platform_data; 45 46 /****************************** Useful Macros *********************************/ 47 #ifndef MAX 48 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 49 #endif 50 51 #ifndef MIN 52 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 53 #endif 54 55 #ifndef TRUE 56 #define TRUE 1 57 #endif 58 #ifndef FALSE 59 #define FALSE 0 60 #endif 61 62 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 63 64 #define ALL_CHANNELS '\0' 65 #define ALL_TARGETS_MASK 0xFFFF 66 #define INITIATOR_WILDCARD (~0) 67 68 #define SCSIID_TARGET(ahc, scsiid) \ 69 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 70 >> TID_SHIFT) 71 #define SCSIID_OUR_ID(scsiid) \ 72 ((scsiid) & OID) 73 #define SCSIID_CHANNEL(ahc, scsiid) \ 74 ((((ahc)->features & AHC_TWIN) != 0) \ 75 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 76 : 'A') 77 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 78 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 79 #define SCB_GET_OUR_ID(scb) \ 80 SCSIID_OUR_ID((scb)->hscb->scsiid) 81 #define SCB_GET_TARGET(ahc, scb) \ 82 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 83 #define SCB_GET_CHANNEL(ahc, scb) \ 84 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 85 #define SCB_GET_LUN(scb) \ 86 ((scb)->hscb->lun) 87 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 88 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 89 #define SCB_GET_TARGET_MASK(ahc, scb) \ 90 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 91 #define TCL_TARGET_OFFSET(tcl) \ 92 ((((tcl) >> 4) & TID) >> 4) 93 #define TCL_LUN(tcl) \ 94 (tcl & (AHC_NUM_LUNS - 1)) 95 #define BUILD_TCL(scsiid, lun) \ 96 ((lun) | (((scsiid) & TID) << 4)) 97 98 #ifndef AHC_TARGET_MODE 99 #undef AHC_TMODE_ENABLE 100 #define AHC_TMODE_ENABLE 0 101 #endif 102 103 /**************************** Driver Constants ********************************/ 104 /* 105 * The maximum number of supported targets. 106 */ 107 #define AHC_NUM_TARGETS 16 108 109 /* 110 * The maximum number of supported luns. 111 * Although the identify message only supports 64 luns in SPI3, you 112 * can have 2^64 luns when information unit transfers are enabled. 113 * The max we can do sanely given the 8bit nature of the RISC engine 114 * on these chips is 256. 115 */ 116 #define AHC_NUM_LUNS 256 117 118 /* 119 * The maximum transfer per S/G segment. 120 */ 121 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 122 123 /* 124 * The maximum number of concurrent transactions supported per driver instance. 125 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 126 * the space for SCBs on the host adapter varies by model, the driver will 127 * page the SCBs between host and controller memory as needed. We are limited 128 * to 255 because of the 8bit nature of the RISC engine and the need to 129 * reserve the value of 255 as a "No Transaction" value. 130 */ 131 #define AHC_SCB_MAX 255 132 133 /* 134 * Ring Buffer of incoming target commands. 135 * We allocate 256 to simplify the logic in the sequencer 136 * by using the natural wrap point of an 8bit counter. 137 */ 138 #define AHC_TMODE_CMDS 256 139 140 /* Reset line assertion time in us */ 141 #define AHC_BUSRESET_DELAY 250 142 143 /******************* Chip Characteristics/Operating Settings *****************/ 144 /* 145 * Chip Type 146 * The chip order is from least sophisticated to most sophisticated. 147 */ 148 typedef enum { 149 AHC_NONE = 0x0000, 150 AHC_CHIPID_MASK = 0x00FF, 151 AHC_AIC7770 = 0x0001, 152 AHC_AIC7850 = 0x0002, 153 AHC_AIC7855 = 0x0003, 154 AHC_AIC7859 = 0x0004, 155 AHC_AIC7860 = 0x0005, 156 AHC_AIC7870 = 0x0006, 157 AHC_AIC7880 = 0x0007, 158 AHC_AIC7895 = 0x0008, 159 AHC_AIC7895C = 0x0009, 160 AHC_AIC7890 = 0x000a, 161 AHC_AIC7896 = 0x000b, 162 AHC_AIC7892 = 0x000c, 163 AHC_AIC7899 = 0x000d, 164 AHC_VL = 0x0100, /* Bus type VL */ 165 AHC_EISA = 0x0200, /* Bus type EISA */ 166 AHC_PCI = 0x0400, /* Bus type PCI */ 167 AHC_BUS_MASK = 0x0F00 168 } ahc_chip; 169 170 /* 171 * Features available in each chip type. 172 */ 173 typedef enum { 174 AHC_FENONE = 0x00000, 175 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 176 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 177 AHC_WIDE = 0x00004, /* Wide Channel */ 178 AHC_TWIN = 0x00008, /* Twin Channel */ 179 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 180 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 181 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 182 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 183 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 184 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 185 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 186 AHC_DT = 0x00800, /* Double Transition transfers */ 187 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 188 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 189 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 190 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 191 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 192 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 193 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 194 AHC_AIC7770_FE = AHC_FENONE, 195 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE, 196 AHC_AIC7855_FE = AHC_AIC7850_FE, 197 AHC_AIC7860_FE = AHC_AIC7850_FE|AHC_ULTRA, 198 AHC_AIC7870_FE = AHC_TARGETMODE, 199 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 200 /* 201 * Although we have space for both the initiator and 202 * target roles on ULTRA2 chips, we currently disable 203 * the initiator role to allow multi-scsi-id target mode 204 * configurations. We can only respond on the same SCSI 205 * ID as our initiator role if we allow initiator operation. 206 * At some point, we should add a configuration knob to 207 * allow both roles to be loaded. 208 */ 209 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 210 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 211 |AHC_HS_MAILBOX |AHC_NEW_TERMCTL|AHC_LARGE_SCBS 212 |AHC_TARGETMODE, 213 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 214 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 215 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 216 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 217 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 218 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 219 } ahc_feature; 220 221 /* 222 * Bugs in the silicon that we work around in software. 223 */ 224 typedef enum { 225 AHC_BUGNONE = 0x00, 226 /* 227 * On all chips prior to the U2 product line, 228 * the WIDEODD S/G segment feature does not 229 * work during scsi->HostBus transfers. 230 */ 231 AHC_TMODE_WIDEODD_BUG = 0x01, 232 /* 233 * On the aic7890/91 Rev 0 chips, the autoflush 234 * feature does not work. A manual flush of 235 * the DMA FIFO is required. 236 */ 237 AHC_AUTOFLUSH_BUG = 0x02, 238 /* 239 * On many chips, cacheline streaming does not work. 240 */ 241 AHC_CACHETHEN_BUG = 0x04, 242 /* 243 * On the aic7896/97 chips, cacheline 244 * streaming must be enabled. 245 */ 246 AHC_CACHETHEN_DIS_BUG = 0x08, 247 /* 248 * PCI 2.1 Retry failure on non-empty data fifo. 249 */ 250 AHC_PCI_2_1_RETRY_BUG = 0x10, 251 /* 252 * Controller does not handle cacheline residuals 253 * properly on S/G segments if PCI MWI instructions 254 * are allowed. 255 */ 256 AHC_PCI_MWI_BUG = 0x20, 257 /* 258 * An SCB upload using the SCB channel's 259 * auto array entry copy feature may 260 * corrupt data. This appears to only 261 * occur on 66MHz systems. 262 */ 263 AHC_SCBCHAN_UPLOAD_BUG = 0x40 264 } ahc_bug; 265 266 /* 267 * Configuration specific settings. 268 * The driver determines these settings by probing the 269 * chip/controller's configuration. 270 */ 271 typedef enum { 272 AHC_FNONE = 0x000, 273 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 274 AHC_CHANNEL_B_PRIMARY = 0x002,/* 275 * On twin channel adapters, probe 276 * channel B first since it is the 277 * primary bus. 278 */ 279 AHC_USEDEFAULTS = 0x004,/* 280 * For cards without an seeprom 281 * or a BIOS to initialize the chip's 282 * SRAM, we use the default target 283 * settings. 284 */ 285 AHC_SEQUENCER_DEBUG = 0x008, 286 AHC_SHARED_SRAM = 0x010, 287 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 288 AHC_RESET_BUS_A = 0x040, 289 AHC_RESET_BUS_B = 0x080, 290 AHC_EXTENDED_TRANS_A = 0x100, 291 AHC_EXTENDED_TRANS_B = 0x200, 292 AHC_TERM_ENB_A = 0x400, 293 AHC_TERM_ENB_B = 0x800, 294 AHC_INITIATORROLE = 0x1000,/* 295 * Allow initiator operations on 296 * this controller. 297 */ 298 AHC_TARGETROLE = 0x2000,/* 299 * Allow target operations on this 300 * controller. 301 */ 302 AHC_NEWEEPROM_FMT = 0x4000, 303 AHC_RESOURCE_SHORTAGE = 0x8000, 304 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 305 AHC_INT50_SPEEDFLEX = 0x20000,/* 306 * Internal 50pin connector 307 * sits behind an aic3860 308 */ 309 AHC_SCB_BTT = 0x40000,/* 310 * The busy targets table is 311 * stored in SCB space rather 312 * than SRAM. 313 */ 314 AHC_BIOS_ENABLED = 0x80000 315 } ahc_flag; 316 317 /* 318 * Controller Information composed at probe time. 319 */ 320 struct ahc_probe_config { 321 const char *description; 322 char channel; 323 char channel_b; 324 ahc_chip chip; 325 ahc_feature features; 326 ahc_bug bugs; 327 ahc_flag flags; 328 }; 329 330 /************************* Hardware SCB Definition ***************************/ 331 332 /* 333 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 334 * consists of a "hardware SCB" mirroring the fields availible on the card 335 * and additional information the kernel stores for each transaction. 336 * 337 * To minimize space utilization, a portion of the hardware scb stores 338 * different data during different portions of a SCSI transaction. 339 * As initialized by the host driver for the initiator role, this area 340 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 341 * the cdb has been presented to the target, this area serves to store 342 * residual transfer information and the SCSI status byte. 343 * For the target role, the contents of this area do not change, but 344 * still serve a different purpose than for the initiator role. See 345 * struct target_data for details. 346 */ 347 348 /* 349 * Status information embedded in the shared poriton of 350 * an SCB after passing the cdb to the target. The kernel 351 * driver will only read this data for transactions that 352 * complete abnormally (non-zero status byte). 353 */ 354 struct status_pkt { 355 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 356 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 357 uint8_t scsi_status; /* Standard SCSI status byte */ 358 }; 359 360 /* 361 * Target mode version of the shared data SCB segment. 362 */ 363 struct target_data { 364 uint8_t target_phases; /* Bitmap of phases to execute */ 365 uint8_t data_phase; /* Data-In or Data-Out */ 366 uint8_t scsi_status; /* SCSI status to give to initiator */ 367 uint8_t initiator_tag; /* Initiator's transaction tag */ 368 }; 369 370 struct hardware_scb { 371 /*0*/ union { 372 /* 373 * If the cdb is 12 bytes or less, we embed it directly 374 * in the SCB. For longer cdbs, we embed the address 375 * of the cdb payload as seen by the chip and a DMA 376 * is used to pull it in. 377 */ 378 uint8_t cdb[12]; 379 uint32_t cdb_ptr; 380 struct status_pkt status; 381 struct target_data tdata; 382 } shared_data; 383 /* 384 * A word about residuals. 385 * The scb is presented to the sequencer with the dataptr and datacnt 386 * fields initialized to the contents of the first S/G element to 387 * transfer. The sgptr field is initialized to the bus address for 388 * the S/G element that follows the first in the in core S/G array 389 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 390 * S/G entry for this transfer (single S/G element transfer with the 391 * first elements address and length preloaded in the dataptr/datacnt 392 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 393 * The SG_FULL_RESID flag ensures that the residual will be correctly 394 * noted even if no data transfers occur. Once the data phase is entered, 395 * the residual sgptr and datacnt are loaded from the sgptr and the 396 * datacnt fields. After each S/G element's dataptr and length are 397 * loaded into the hardware, the residual sgptr is advanced. After 398 * each S/G element is expired, its datacnt field is checked to see 399 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 400 * residual sg ptr and the transfer is considered complete. If the 401 * sequencer determines that there is a residual in the tranfer, it 402 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 403 * host memory. To sumarize: 404 * 405 * Sequencer: 406 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 407 * or residual_sgptr does not have SG_LIST_NULL set. 408 * 409 * o We are transfering the last segment if residual_datacnt has 410 * the SG_LAST_SEG flag set. 411 * 412 * Host: 413 * o A residual has occurred if a completed scb has the 414 * SG_RESID_VALID flag set. 415 * 416 * o residual_sgptr and sgptr refer to the "next" sg entry 417 * and so may point beyond the last valid sg entry for the 418 * transfer. 419 */ 420 /*12*/ uint32_t dataptr; 421 /*16*/ uint32_t datacnt; /* 422 * Byte 3 (numbered from 0) of 423 * the datacnt is really the 424 * 4th byte in that data address. 425 */ 426 /*20*/ uint32_t sgptr; 427 #define SG_PTR_MASK 0xFFFFFFF8 428 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 429 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 430 /*26*/ uint8_t lun; 431 /*27*/ uint8_t tag; /* 432 * Index into our kernel SCB array. 433 * Also used as the tag for tagged I/O 434 */ 435 /*28*/ uint8_t cdb_len; 436 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 437 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 438 /*31*/ uint8_t next; /* 439 * Used for threading SCBs in the 440 * "Waiting for Selection" and 441 * "Disconnected SCB" lists down 442 * in the sequencer. 443 */ 444 /*32*/ uint8_t cdb32[32]; /* 445 * CDB storage for cdbs of size 446 * 13->32. We store them here 447 * because hardware scbs are 448 * allocated from DMA safe 449 * memory so we are guaranteed 450 * the controller can access 451 * this data. 452 */ 453 }; 454 455 /************************ Kernel SCB Definitions ******************************/ 456 /* 457 * Some fields of the SCB are OS dependent. Here we collect the 458 * definitions for elements that all OS platforms need to include 459 * in there SCB definition. 460 */ 461 462 /* 463 * Definition of a scatter/gather element as transfered to the controller. 464 * The aic7xxx chips only support a 24bit length. We use the top byte of 465 * the length to store additional address bits and a flag to indicate 466 * that a given segment terminates the transfer. This gives us an 467 * addressable range of 512GB on machines with 64bit PCI or with chips 468 * that can support dual address cycles on 32bit PCI busses. 469 */ 470 struct ahc_dma_seg { 471 uint32_t addr; 472 uint32_t len; 473 #define AHC_DMA_LAST_SEG 0x80000000 474 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 475 #define AHC_SG_LEN_MASK 0x00FFFFFF 476 }; 477 478 /* 479 * The current state of this SCB. 480 */ 481 typedef enum { 482 SCB_FREE = 0x0000, 483 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 484 * Another device was active 485 * during the first timeout for 486 * this SCB so we gave ourselves 487 * an additional timeout period 488 * in case it was hogging the 489 * bus. 490 */ 491 SCB_DEVICE_RESET = 0x0004, 492 SCB_SENSE = 0x0008, 493 SCB_CDB32_PTR = 0x0010, 494 SCB_RECOVERY_SCB = 0x0040, 495 SCB_NEGOTIATE = 0x0080, 496 SCB_ABORT = 0x1000, 497 SCB_UNTAGGEDQ = 0x2000, 498 SCB_ACTIVE = 0x4000, 499 SCB_TARGET_IMMEDIATE = 0x8000 500 } scb_flag; 501 502 struct scb { 503 struct hardware_scb *hscb; 504 union { 505 SLIST_ENTRY(scb) sle; 506 TAILQ_ENTRY(scb) tqe; 507 } links; 508 LIST_ENTRY(scb) pending_links; 509 ahc_io_ctx_t io_ctx; 510 struct ahc_softc *ahc_softc; 511 scb_flag flags; 512 #ifndef __linux__ 513 bus_dmamap_t dmamap; 514 #endif 515 struct scb_platform_data *platform_data; 516 struct ahc_dma_seg *sg_list; 517 bus_addr_t sg_list_phys; 518 u_int sg_count;/* How full ahc_dma_seg is */ 519 }; 520 521 struct sg_map_node { 522 bus_dmamap_t sg_dmamap; 523 bus_addr_t sg_physaddr; 524 struct ahc_dma_seg* sg_vaddr; 525 SLIST_ENTRY(sg_map_node) links; 526 }; 527 528 struct scb_data { 529 SLIST_HEAD(, scb) free_scbs; /* 530 * Pool of SCBs ready to be assigned 531 * commands to execute. 532 */ 533 struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */ 534 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 535 struct scb *scbarray; /* Array of kernel SCBs */ 536 struct scsi_sense_data *sense; /* Per SCB sense data */ 537 538 /* 539 * "Bus" addresses of our data structures. 540 */ 541 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 542 bus_dmamap_t hscb_dmamap; 543 bus_addr_t hscb_busaddr; 544 bus_dma_tag_t sense_dmat; 545 bus_dmamap_t sense_dmamap; 546 bus_addr_t sense_busaddr; 547 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 548 SLIST_HEAD(, sg_map_node) sg_maps; 549 uint8_t numscbs; 550 uint8_t maxhscbs; /* Number of SCBs on the card */ 551 uint8_t init_level; /* 552 * How far we've initialized 553 * this structure. 554 */ 555 }; 556 557 /************************ Target Mode Definitions *****************************/ 558 559 /* 560 * Connection desciptor for select-in requests in target mode. 561 */ 562 struct target_cmd { 563 uint8_t scsiid; /* Our ID and the initiator's ID */ 564 uint8_t identify; /* Identify message */ 565 uint8_t bytes[22]; /* 566 * Bytes contains any additional message 567 * bytes terminated by 0xFF. The remainder 568 * is the cdb to execute. 569 */ 570 uint8_t cmd_valid; /* 571 * When a command is complete, the firmware 572 * will set cmd_valid to all bits set. 573 * After the host has seen the command, 574 * the bits are cleared. This allows us 575 * to just peek at host memory to determine 576 * if more work is complete. cmd_valid is on 577 * an 8 byte boundary to simplify setting 578 * it on aic7880 hardware which only has 579 * limited direct access to the DMA FIFO. 580 */ 581 uint8_t pad[7]; 582 }; 583 584 /* 585 * Number of events we can buffer up if we run out 586 * of immediate notify ccbs. 587 */ 588 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 589 struct ahc_tmode_event { 590 uint8_t initiator_id; 591 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 592 #define EVENT_TYPE_BUS_RESET 0xFF 593 uint8_t event_arg; 594 }; 595 596 /* 597 * Per enabled lun target mode state. 598 * As this state is directly influenced by the host OS'es target mode 599 * environment, we let the OS module define it. Forward declare the 600 * structure here so we can store arrays of them, etc. in OS neutral 601 * data structures. 602 */ 603 #ifdef AHC_TARGET_MODE 604 struct tmode_lstate { 605 struct cam_path *path; 606 struct ccb_hdr_slist accept_tios; 607 struct ccb_hdr_slist immed_notifies; 608 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 609 uint8_t event_r_idx; 610 uint8_t event_w_idx; 611 }; 612 #else 613 struct tmode_lstate; 614 #endif 615 616 /******************** Transfer Negotiation Datastructures *********************/ 617 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 618 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 619 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 620 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 621 622 /* 623 * Transfer Negotiation Information. 624 */ 625 struct ahc_transinfo { 626 uint8_t protocol_version; /* SCSI Revision level */ 627 uint8_t transport_version; /* SPI Revision level */ 628 uint8_t width; /* Bus width */ 629 uint8_t period; /* Sync rate factor */ 630 uint8_t offset; /* Sync offset */ 631 uint8_t ppr_options; /* Parallel Protocol Request options */ 632 }; 633 634 /* 635 * Per-initiator current, goal and user transfer negotiation information. */ 636 struct ahc_initiator_tinfo { 637 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 638 struct ahc_transinfo current; 639 struct ahc_transinfo goal; 640 struct ahc_transinfo user; 641 }; 642 643 /* 644 * Per enabled target ID state. 645 * Pointers to lun target state as well as sync/wide negotiation information 646 * for each initiator<->target mapping. For the initiator role we pretend 647 * that we are the target and the targets are the initiators since the 648 * negotiation is the same regardless of role. 649 */ 650 struct tmode_tstate { 651 struct tmode_lstate* enabled_luns[64]; /* NULL == disabled */ 652 struct ahc_initiator_tinfo transinfo[16]; 653 654 /* 655 * Per initiator state bitmasks. 656 */ 657 uint16_t ultraenb; /* Using ultra sync rate */ 658 uint16_t discenable; /* Disconnection allowed */ 659 uint16_t tagenable; /* Tagged Queuing allowed */ 660 }; 661 662 /* 663 * Data structure for our table of allowed synchronous transfer rates. 664 */ 665 struct ahc_syncrate { 666 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 667 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 668 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 669 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 670 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 671 uint8_t period; /* Period to send to SCSI target */ 672 char *rate; 673 }; 674 675 /* 676 * The synchronouse transfer rate table. 677 */ 678 extern struct ahc_syncrate ahc_syncrates[]; 679 680 /* 681 * Indexes into our table of syncronous transfer rates. 682 */ 683 #define AHC_SYNCRATE_DT 0 684 #define AHC_SYNCRATE_ULTRA2 1 685 #define AHC_SYNCRATE_ULTRA 3 686 #define AHC_SYNCRATE_FAST 6 687 688 /***************************** Lookup Tables **********************************/ 689 /* 690 * Textual descriptions of the different chips indexed by chip type. 691 */ 692 extern char *ahc_chip_names[]; 693 extern const u_int num_chip_names; 694 695 /* 696 * Hardware error codes. 697 */ 698 struct hard_error_entry { 699 uint8_t errno; 700 char *errmesg; 701 }; 702 extern struct hard_error_entry hard_error[]; 703 extern const u_int num_errors; 704 705 /* 706 * Phase -> name and message out response 707 * to parity errors in each phase table. 708 */ 709 struct phase_table_entry { 710 uint8_t phase; 711 uint8_t mesg_out; /* Message response to parity errors */ 712 char *phasemsg; 713 }; 714 extern struct phase_table_entry phase_table[]; 715 extern const u_int num_phases; 716 717 /************************** Serial EEPROM Format ******************************/ 718 719 struct seeprom_config { 720 /* 721 * Per SCSI ID Configuration Flags 722 */ 723 uint16_t device_flags[16]; /* words 0-15 */ 724 #define CFXFER 0x0007 /* synchronous transfer rate */ 725 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 726 #define CFDISC 0x0010 /* enable disconnection */ 727 #define CFWIDEB 0x0020 /* wide bus device */ 728 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 729 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 730 #define CFSTART 0x0100 /* send start unit SCSI command */ 731 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 732 #define CFRNFOUND 0x0400 /* report even if not found */ 733 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 734 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 735 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 736 737 /* 738 * BIOS Control Bits 739 */ 740 uint16_t bios_control; /* word 16 */ 741 #define CFSUPREM 0x0001 /* support all removeable drives */ 742 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 743 #define CFBIOSEN 0x0004 /* BIOS enabled */ 744 /* UNUSED 0x0008 */ 745 #define CFSM2DRV 0x0010 /* support more than two drives */ 746 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 747 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 748 #define CFEXTEND 0x0080 /* extended translation enabled */ 749 #define CFSCAMEN 0x0100 /* SCAM enable */ 750 /* UNUSED 0xff00 */ 751 752 /* 753 * Host Adapter Control Bits 754 */ 755 uint16_t adapter_control; /* word 17 */ 756 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 757 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 758 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 759 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 760 #define CFSTERM 0x0004 /* SCSI low byte termination */ 761 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 762 #define CFSPARITY 0x0010 /* SCSI parity */ 763 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 764 #define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */ 765 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 766 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 767 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 768 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 769 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 770 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 771 #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 772 773 /* 774 * Bus Release Time, Host Adapter ID 775 */ 776 uint16_t brtime_id; /* word 18 */ 777 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 778 /* UNUSED 0x00f0 */ 779 #define CFBRTIME 0xff00 /* bus release time */ 780 781 /* 782 * Maximum targets 783 */ 784 uint16_t max_targets; /* word 19 */ 785 #define CFMAXTARG 0x00ff /* maximum targets */ 786 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 787 #define CFBOOTID 0xf000 /* Target to boot from */ 788 uint16_t res_1[10]; /* words 20-29 */ 789 uint16_t signature; /* Signature == 0x250 */ 790 #define CFSIGNATURE 0x250 791 uint16_t checksum; /* word 31 */ 792 }; 793 794 /**************************** Message Buffer *********************************/ 795 typedef enum { 796 MSG_TYPE_NONE = 0x00, 797 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 798 MSG_TYPE_INITIATOR_MSGIN = 0x02, 799 MSG_TYPE_TARGET_MSGOUT = 0x03, 800 MSG_TYPE_TARGET_MSGIN = 0x04 801 } ahc_msg_type; 802 803 typedef enum { 804 MSGLOOP_IN_PROG, 805 MSGLOOP_MSGCOMPLETE, 806 MSGLOOP_TERMINATED 807 } msg_loop_stat; 808 809 /*********************** Software Configuration Structure *********************/ 810 TAILQ_HEAD(scb_tailq, scb); 811 812 struct ahc_softc { 813 bus_space_tag_t tag; 814 bus_space_handle_t bsh; 815 #ifndef __linux__ 816 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 817 #endif 818 struct scb_data *scb_data; 819 820 struct scb *next_queued_scb; 821 822 /* 823 * SCBs that have been sent to the controller 824 */ 825 LIST_HEAD(, scb) pending_scbs; 826 827 /* 828 * Counting lock for deferring the release of additional 829 * untagged transactions from the untagged_queues. When 830 * the lock is decremented to 0, all queues in the 831 * untagged_queues array are run. 832 */ 833 u_int untagged_queue_lock; 834 835 /* 836 * Per-target queue of untagged-transactions. The 837 * transaction at the head of the queue is the 838 * currently pending untagged transaction for the 839 * target. The driver only allows a single untagged 840 * transaction per target. 841 */ 842 struct scb_tailq untagged_queues[16]; 843 844 /* 845 * Platform specific data. 846 */ 847 struct ahc_platform_data *platform_data; 848 849 /* 850 * Platform specific device information. 851 */ 852 ahc_dev_softc_t dev_softc; 853 854 /* 855 * Target mode related state kept on a per enabled lun basis. 856 * Targets that are not enabled will have null entries. 857 * As an initiator, we keep one target entry for our initiator 858 * ID to store our sync/wide transfer settings. 859 */ 860 struct tmode_tstate* enabled_targets[16]; 861 862 /* 863 * The black hole device responsible for handling requests for 864 * disabled luns on enabled targets. 865 */ 866 struct tmode_lstate* black_hole; 867 868 /* 869 * Device instance currently on the bus awaiting a continue TIO 870 * for a command that was not given the disconnect priveledge. 871 */ 872 struct tmode_lstate* pending_device; 873 874 /* 875 * Card characteristics 876 */ 877 ahc_chip chip; 878 ahc_feature features; 879 ahc_bug bugs; 880 ahc_flag flags; 881 882 /* Values to store in the SEQCTL register for pause and unpause */ 883 uint8_t unpause; 884 uint8_t pause; 885 886 /* Command Queues */ 887 uint8_t qoutfifonext; 888 uint8_t qinfifonext; 889 uint8_t *qoutfifo; 890 uint8_t *qinfifo; 891 892 /* Critical Section Data */ 893 struct cs *critical_sections; 894 u_int num_critical_sections; 895 896 /* Links for chaining softcs */ 897 TAILQ_ENTRY(ahc_softc) links; 898 899 /* Channel Names ('A', 'B', etc.) */ 900 char channel; 901 char channel_b; 902 903 /* Initiator Bus ID */ 904 uint8_t our_id; 905 uint8_t our_id_b; 906 907 /* Targets that need negotiation messages */ 908 uint16_t targ_msg_req; 909 910 /* 911 * PCI error detection. 912 */ 913 int unsolicited_ints; 914 915 /* 916 * Target incoming command FIFO. 917 */ 918 struct target_cmd *targetcmds; 919 uint8_t tqinfifonext; 920 921 /* 922 * Incoming and outgoing message handling. 923 */ 924 uint8_t send_msg_perror; 925 ahc_msg_type msg_type; 926 uint8_t msgout_buf[12];/* Message we are sending */ 927 uint8_t msgin_buf[12];/* Message we are receiving */ 928 u_int msgout_len; /* Length of message to send */ 929 u_int msgout_index; /* Current index in msgout */ 930 u_int msgin_index; /* Current index in msgin */ 931 932 /* 933 * Mapping information for data structures shared 934 * between the sequencer and kernel. 935 */ 936 bus_dma_tag_t parent_dmat; 937 bus_dma_tag_t shared_data_dmat; 938 bus_dmamap_t shared_data_dmamap; 939 bus_addr_t shared_data_busaddr; 940 941 /* 942 * Bus address of the one byte buffer used to 943 * work-around a DMA bug for chips <= aic7880 944 * in target mode. 945 */ 946 bus_addr_t dma_bug_buf; 947 948 /* Number of enabled target mode device on this card */ 949 u_int enabled_luns; 950 951 /* Initialization level of this data structure */ 952 u_int init_level; 953 954 /* PCI cacheline size. */ 955 u_int pci_cachesize; 956 957 /* Per-Unit descriptive information */ 958 const char *description; 959 char *name; 960 int unit; 961 962 uint16_t user_discenable;/* Disconnection allowed */ 963 uint16_t user_tagenable;/* Tagged Queuing allowed */ 964 }; 965 966 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 967 extern struct ahc_softc_tailq ahc_tailq; 968 969 /************************ Active Device Information ***************************/ 970 typedef enum { 971 ROLE_UNKNOWN, 972 ROLE_INITIATOR, 973 ROLE_TARGET 974 } role_t; 975 976 struct ahc_devinfo { 977 int our_scsiid; 978 int target_offset; 979 uint16_t target_mask; 980 u_int target; 981 u_int lun; 982 char channel; 983 role_t role; /* 984 * Only guaranteed to be correct if not 985 * in the busfree state. 986 */ 987 }; 988 989 /****************************** PCI Structures ********************************/ 990 typedef int (ahc_device_setup_t)(ahc_dev_softc_t, 991 struct ahc_probe_config *); 992 993 struct ahc_pci_identity { 994 uint64_t full_id; 995 uint64_t id_mask; 996 char *name; 997 ahc_device_setup_t *setup; 998 }; 999 extern struct ahc_pci_identity ahc_pci_ident_table []; 1000 extern const int ahc_num_pci_devs; 1001 1002 /***************************** VL/EISA Declarations ***************************/ 1003 struct aic7770_identity { 1004 uint32_t full_id; 1005 uint32_t id_mask; 1006 char *name; 1007 ahc_device_setup_t *setup; 1008 }; 1009 extern struct aic7770_identity aic7770_ident_table []; 1010 extern const int ahc_num_aic7770_devs; 1011 1012 #define AHC_EISA_SLOT_OFFSET 0xc00 1013 #define AHC_EISA_IOSIZE 0x100 1014 1015 /*************************** Function Declarations ****************************/ 1016 /******************************************************************************/ 1017 1018 /***************************** PCI Front End *********************************/ 1019 struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1020 int ahc_pci_config(struct ahc_softc *, 1021 struct ahc_pci_identity *); 1022 1023 /*************************** EISA/VL Front End ********************************/ 1024 struct aic7770_identity *aic7770_find_device(uint32_t); 1025 int aic7770_config(struct ahc_softc *ahc, 1026 struct aic7770_identity *); 1027 1028 /************************** SCB and SCB queue management **********************/ 1029 int ahc_probe_scbs(struct ahc_softc *); 1030 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1031 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1032 struct scb_tailq *queue); 1033 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1034 struct scb *scb); 1035 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1036 int target, char channel, int lun, 1037 u_int tag, role_t role); 1038 1039 /****************************** Initialization ********************************/ 1040 void ahc_init_probe_config(struct ahc_probe_config *); 1041 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1042 int ahc_softc_init(struct ahc_softc *, 1043 struct ahc_probe_config*); 1044 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1045 int ahc_init(struct ahc_softc *ahc); 1046 void ahc_softc_insert(struct ahc_softc *); 1047 void ahc_set_unit(struct ahc_softc *, int); 1048 void ahc_set_name(struct ahc_softc *, char *); 1049 void ahc_alloc_scbs(struct ahc_softc *ahc); 1050 void ahc_free(struct ahc_softc *ahc); 1051 int ahc_reset(struct ahc_softc *ahc); 1052 void ahc_shutdown(void *arg); 1053 1054 /*************************** Interrupt Services *******************************/ 1055 void ahc_pci_intr(struct ahc_softc *ahc); 1056 void ahc_clear_intstat(struct ahc_softc *ahc); 1057 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1058 #ifdef AHC_TARGET_MODE 1059 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1060 #endif 1061 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1062 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1063 void ahc_handle_scsiint(struct ahc_softc *ahc, 1064 u_int intstat); 1065 void ahc_clear_critical_section(struct ahc_softc *ahc); 1066 1067 /***************************** Error Recovery *********************************/ 1068 typedef enum { 1069 SEARCH_COMPLETE, 1070 SEARCH_COUNT, 1071 SEARCH_REMOVE 1072 } ahc_search_action; 1073 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1074 char channel, int lun, u_int tag, 1075 role_t role, uint32_t status, 1076 ahc_search_action action); 1077 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1078 char channel, int lun, u_int tag, 1079 int stop_on_first, int remove, 1080 int save_state); 1081 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1082 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1083 int initiate_reset); 1084 void restart_sequencer(struct ahc_softc *ahc); 1085 /*************************** Utility Functions ********************************/ 1086 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1087 u_int our_id, u_int target, 1088 u_int lun, char channel, 1089 role_t role); 1090 /************************** Transfer Negotiation ******************************/ 1091 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1092 u_int *ppr_options, u_int maxsync); 1093 u_int ahc_find_period(struct ahc_softc *ahc, 1094 u_int scsirate, u_int maxsync); 1095 void ahc_validate_offset(struct ahc_softc *ahc, 1096 struct ahc_initiator_tinfo *tinfo, 1097 struct ahc_syncrate *syncrate, 1098 u_int *offset, int wide, 1099 role_t role); 1100 void ahc_validate_width(struct ahc_softc *ahc, 1101 struct ahc_initiator_tinfo *tinfo, 1102 u_int *bus_width, 1103 role_t role); 1104 void ahc_set_width(struct ahc_softc *ahc, 1105 struct ahc_devinfo *devinfo, 1106 u_int width, u_int type, int paused); 1107 void ahc_set_syncrate(struct ahc_softc *ahc, 1108 struct ahc_devinfo *devinfo, 1109 struct ahc_syncrate *syncrate, 1110 u_int period, u_int offset, 1111 u_int ppr_options, 1112 u_int type, int paused); 1113 void ahc_set_tags(struct ahc_softc *ahc, 1114 struct ahc_devinfo *devinfo, int enable); 1115 1116 /**************************** Target Mode *************************************/ 1117 #ifdef AHC_TARGET_MODE 1118 void ahc_send_lstate_events(struct ahc_softc *, 1119 struct tmode_lstate *); 1120 void ahc_handle_en_lun(struct ahc_softc *ahc, 1121 struct cam_sim *sim, union ccb *ccb); 1122 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1123 struct cam_sim *sim, union ccb *ccb, 1124 struct tmode_tstate **tstate, 1125 struct tmode_lstate **lstate, 1126 int notfound_failure); 1127 void ahc_setup_target_msgin(struct ahc_softc *ahc, 1128 struct ahc_devinfo *devinfo); 1129 #ifndef AHC_TMODE_ENABLE 1130 #define AHC_TMODE_ENABLE 0 1131 #endif 1132 #endif 1133 /******************************* Debug ***************************************/ 1134 void ahc_print_scb(struct scb *scb); 1135 void ahc_dump_card_state(struct ahc_softc *ahc); 1136 #endif /* _AIC7XXX_H_ */ 1137