1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: aic7xxx.h,v 1.9 1999/05/17 21:53:51 gibbs Exp $ 38 */ 39 40 #ifndef _AIC7XXX_H_ 41 #define _AIC7XXX_H_ 42 43 #include "ahc.h" /* for NAHC from config */ 44 #include "opt_aic7xxx.h" /* for config options */ 45 46 #include <sys/bus.h> /* For device_t */ 47 48 #ifndef MAX 49 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 50 #endif 51 52 #ifndef MIN 53 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 54 #endif 55 56 /* 57 * The maximum transfer per S/G segment. 58 */ 59 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 60 61 /* 62 * The number of dma segments supported. The current implementation limits 63 * us to 255 S/G entries (this may change to be unlimited at some point). 64 * To reduce the driver's memory consumption, we further limit the number 65 * supported to be sufficient to handle the largest mapping supported by 66 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 67 * and unaligned, this turns out to be the number of paged sized transfers 68 * in MAXPHYS plus an extra element to handle any unaligned residual. 69 */ 70 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 71 72 #define AHC_SCB_MAX 255 /* 73 * Up to 255 SCBs on some types of aic7xxx 74 * based boards. The aic7870 have 16 internal 75 * SCBs, but external SRAM bumps this to 255. 76 * The aic7770 family have only 4, and the 77 * aic7850 has only 3. 78 */ 79 80 #define AHC_TMODE_CMDS 256 /* 81 * Ring Buffer of incoming target commands. 82 * We allocate 256 to simplify the logic 83 * in the sequencer by using the natural 84 * wrap point of an 8bit counter. 85 */ 86 87 struct ahc_dma_seg { 88 u_int32_t addr; 89 u_int32_t len; 90 }; 91 92 typedef enum { 93 AHC_NONE = 0x0000, 94 AHC_CHIPID_MASK = 0x00FF, 95 AHC_AIC7770 = 0x0001, 96 AHC_AIC7850 = 0x0002, 97 AHC_AIC7860 = 0x0003, 98 AHC_AIC7870 = 0x0004, 99 AHC_AIC7880 = 0x0005, 100 AHC_AIC7890 = 0x0006, 101 AHC_AIC7895 = 0x0007, 102 AHC_AIC7896 = 0x0008, 103 AHC_VL = 0x0100, /* Bus type VL */ 104 AHC_EISA = 0x0200, /* Bus type EISA */ 105 AHC_PCI = 0x0400, /* Bus type PCI */ 106 } ahc_chip; 107 108 typedef enum { 109 AHC_FENONE = 0x0000, 110 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 111 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 112 AHC_WIDE = 0x0004, /* Wide Channel */ 113 AHC_TWIN = 0x0008, /* Twin Channel */ 114 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 115 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 116 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 117 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 118 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 119 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 120 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 121 AHC_AIC7770_FE = AHC_FENONE, 122 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 123 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 124 AHC_AIC7870_FE = AHC_FENONE, 125 AHC_AIC7880_FE = AHC_ULTRA, 126 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 127 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX, 128 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 129 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 130 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX, 131 } ahc_feature; 132 133 typedef enum { 134 AHC_FNONE = 0x000, 135 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 136 AHC_CHANNEL_B_PRIMARY = 0x002,/* 137 * On twin channel adapters, probe 138 * channel B first since it is the 139 * primary bus. 140 */ 141 AHC_USEDEFAULTS = 0x004,/* 142 * For cards without an seeprom 143 * or a BIOS to initialize the chip's 144 * SRAM, we use the default target 145 * settings. 146 */ 147 AHC_SHARED_SRAM = 0x010, 148 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 149 AHC_RESET_BUS_A = 0x040, 150 AHC_RESET_BUS_B = 0x080, 151 AHC_EXTENDED_TRANS_A = 0x100, 152 AHC_EXTENDED_TRANS_B = 0x200, 153 AHC_TERM_ENB_A = 0x400, 154 AHC_TERM_ENB_B = 0x800, 155 AHC_INITIATORMODE = 0x1000,/* 156 * Allow initiator operations on 157 * this controller. 158 */ 159 AHC_TARGETMODE = 0x2000,/* 160 * Allow target operations on this 161 * controller. 162 */ 163 AHC_NEWEEPROM_FMT = 0x4000, 164 AHC_RESOURCE_SHORTAGE = 0x8000, 165 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 166 } ahc_flag; 167 168 typedef enum { 169 SCB_FREE = 0x0000, 170 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 171 * Another device was active 172 * during the first timeout for 173 * this SCB so we gave ourselves 174 * an additional timeout period 175 * in case it was hogging the 176 * bus. 177 */ 178 SCB_DEVICE_RESET = 0x0004, 179 SCB_SENSE = 0x0008, 180 SCB_RECOVERY_SCB = 0x0040, 181 SCB_ABORT = 0x1000, 182 SCB_QUEUED_MSG = 0x2000, 183 SCB_ACTIVE = 0x4000, 184 SCB_TARGET_IMMEDIATE = 0x8000 185 } scb_flag; 186 187 /* 188 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 189 * consists of a "hardware SCB" mirroring the fields availible on the card 190 * and additional information the kernel stores for each transaction. 191 */ 192 struct hardware_scb { 193 /*0*/ u_int8_t control; 194 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 195 /*2*/ u_int8_t status; 196 /*3*/ u_int8_t SG_count; 197 /*4*/ u_int32_t SG_pointer; 198 /*8*/ u_int8_t residual_SG_count; 199 /*9*/ u_int8_t residual_data_count[3]; 200 /*12*/ u_int32_t data; 201 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 202 * faster to treat it as a long on 203 * a quad boundary. 204 */ 205 /*20*/ u_int32_t cmdpointer; 206 /*24*/ u_int8_t cmdlen; 207 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 208 * Also used as the tag for tagged I/O 209 */ 210 /*26*/ u_int8_t next; /* Used for threading SCBs in the 211 * "Waiting for Selection" and 212 * "Disconnected SCB" lists down 213 * in the sequencer. 214 */ 215 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 216 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 217 /*29*/ u_int8_t spare[3]; /* 218 * Spare space available on 219 * all controller types. 220 */ 221 /*32*/ u_int8_t cmdstore[16]; /* 222 * CDB storage for controllers 223 * supporting 64 byte SCBs. 224 */ 225 /*48*/ u_int32_t cmdstore_busaddr; /* 226 * Address of command store for 227 * 32byte SCB adapters 228 */ 229 /*48*/ u_int8_t spare_64[12]; /* 230 * Pad to 64 bytes. 231 */ 232 }; 233 234 struct scb { 235 struct hardware_scb *hscb; 236 SLIST_ENTRY(scb) links; /* for chaining */ 237 union ccb *ccb; /* the ccb for this cmd */ 238 scb_flag flags; 239 bus_dmamap_t dmamap; 240 struct ahc_dma_seg *sg_list; 241 bus_addr_t sg_list_phys; 242 u_int sg_count;/* How full ahc_dma_seg is */ 243 }; 244 245 /* 246 * Connection desciptor for select-in requests in target mode. 247 * The first byte is the connecting target, followed by identify 248 * message and optional tag information, terminated by 0xFF. The 249 * remainder is the command to execute. The cmd_valid byte is on 250 * an 8 byte boundary to simplify setting it on aic7880 hardware 251 * which only has limited direct access to the DMA FIFO. 252 */ 253 struct target_cmd { 254 u_int8_t initiator_channel; 255 u_int8_t targ_id; /* Target ID we were selected at */ 256 u_int8_t identify; /* Identify message */ 257 u_int8_t bytes[21]; 258 u_int8_t cmd_valid; 259 u_int8_t pad[7]; 260 }; 261 262 /* 263 * Per lun target mode state including accept TIO CCB 264 * and immediate notify CCB pools. 265 */ 266 struct tmode_lstate { 267 struct ccb_hdr_slist accept_tios; 268 struct ccb_hdr_slist immed_notifies; 269 }; 270 271 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 272 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 273 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 274 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 275 276 struct ahc_transinfo { 277 u_int8_t width; 278 u_int8_t period; 279 u_int8_t offset; 280 }; 281 282 struct ahc_initiator_tinfo { 283 u_int8_t scsirate; 284 struct ahc_transinfo current; 285 struct ahc_transinfo goal; 286 struct ahc_transinfo user; 287 }; 288 289 /* 290 * Per target mode enabled target state. Esentially just an array of 291 * pointers to lun target state as well as sync/wide negotiation information 292 * for each initiator<->target mapping (including the mapping for when we 293 * are the initiator). 294 */ 295 struct tmode_tstate { 296 struct tmode_lstate* enabled_luns[8]; 297 struct ahc_initiator_tinfo transinfo[16]; 298 299 /* 300 * Per initiator state bitmasks. 301 */ 302 u_int16_t ultraenb; /* Using ultra sync rate */ 303 u_int16_t discenable; /* Disconnection allowed */ 304 u_int16_t tagenable; /* Tagged Queuing allowed */ 305 }; 306 307 /* 308 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 309 */ 310 311 struct seeprom_config { 312 /* 313 * SCSI ID Configuration Flags 314 */ 315 u_int16_t device_flags[16]; /* words 0-15 */ 316 #define CFXFER 0x0007 /* synchronous transfer rate */ 317 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 318 #define CFDISC 0x0010 /* enable disconnection */ 319 #define CFWIDEB 0x0020 /* wide bus device */ 320 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 321 /* UNUSED 0x0080 */ 322 #define CFSTART 0x0100 /* send start unit SCSI command */ 323 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 324 #define CFRNFOUND 0x0400 /* report even if not found */ 325 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 326 /* UNUSED 0xf000 */ 327 328 /* 329 * BIOS Control Bits 330 */ 331 u_int16_t bios_control; /* word 16 */ 332 #define CFSUPREM 0x0001 /* support all removeable drives */ 333 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 334 #define CFBIOSEN 0x0004 /* BIOS enabled */ 335 /* UNUSED 0x0008 */ 336 #define CFSM2DRV 0x0010 /* support more than two drives */ 337 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 338 /* UNUSED 0x0060 */ 339 #define CFEXTEND 0x0080 /* extended translation enabled */ 340 /* UNUSED 0xff00 */ 341 342 /* 343 * Host Adapter Control Bits 344 */ 345 u_int16_t adapter_control; /* word 17 */ 346 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 347 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 348 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 349 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 350 #define CFSTERM 0x0004 /* SCSI low byte termination */ 351 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 352 #define CFSPARITY 0x0010 /* SCSI parity */ 353 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 354 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 355 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 356 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 357 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 358 /* UNUSED 0xf080 */ 359 360 /* 361 * Bus Release, Host Adapter ID 362 */ 363 u_int16_t brtime_id; /* word 18 */ 364 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 365 /* UNUSED 0x00f0 */ 366 #define CFBRTIME 0xff00 /* bus release time */ 367 368 /* 369 * Maximum targets 370 */ 371 u_int16_t max_targets; /* word 19 */ 372 #define CFMAXTARG 0x00ff /* maximum targets */ 373 /* UNUSED 0xff00 */ 374 u_int16_t res_1[11]; /* words 20-30 */ 375 u_int16_t checksum; /* word 31 */ 376 }; 377 378 struct ahc_syncrate { 379 int sxfr_ultra2; 380 int sxfr; 381 /* Rates in Ultra mode have bit 8 of sxfr set */ 382 #define ULTRA_SXFR 0x100 383 u_int8_t period; /* Period to send to SCSI target */ 384 char *rate; 385 }; 386 387 typedef enum { 388 MSG_TYPE_NONE = 0x00, 389 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 390 MSG_TYPE_INITIATOR_MSGIN = 0x02, 391 MSG_TYPE_TARGET_MSGOUT = 0x03, 392 MSG_TYPE_TARGET_MSGIN = 0x04 393 } ahc_msg_type; 394 395 struct sg_map_node { 396 bus_dmamap_t sg_dmamap; 397 bus_addr_t sg_physaddr; 398 struct ahc_dma_seg* sg_vaddr; 399 SLIST_ENTRY(sg_map_node) links; 400 }; 401 402 struct scb_data { 403 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 404 struct scb *scbarray; /* Array of kernel SCBs */ 405 SLIST_HEAD(, scb) free_scbs; /* 406 * Pool of SCBs ready to be assigned 407 * commands to execute. 408 */ 409 struct scsi_sense_data *sense; /* Per SCB sense data */ 410 411 /* 412 * "Bus" addresses of our data structures. 413 */ 414 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 415 bus_dmamap_t hscb_dmamap; 416 bus_addr_t hscb_busaddr; 417 bus_dma_tag_t sense_dmat; 418 bus_dmamap_t sense_dmamap; 419 bus_addr_t sense_busaddr; 420 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 421 SLIST_HEAD(, sg_map_node) sg_maps; 422 u_int8_t numscbs; 423 u_int8_t maxhscbs; /* Number of SCBs on the card */ 424 u_int8_t init_level; /* 425 * How far we've initialized 426 * this structure. 427 */ 428 }; 429 430 struct ahc_softc { 431 bus_space_tag_t tag; 432 bus_space_handle_t bsh; 433 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 434 struct scb_data *scb_data; 435 436 /* 437 * CCBs that have been send to the controller 438 */ 439 LIST_HEAD(, ccb_hdr) pending_ccbs; 440 441 /* 442 * Target mode related state kept on a per enabled lun basis. 443 * Targets that are not enabled will have null entries. 444 * As an initiator, we keep one target entry for our initiator 445 * ID to store our sync/wide transfer settings. 446 */ 447 struct tmode_tstate* enabled_targets[16]; 448 449 /* 450 * The black hole device responsible for handling requests for 451 * disabled luns on enabled targets. 452 */ 453 struct tmode_lstate* black_hole; 454 455 /* 456 * Device instance currently on the bus awaiting a continue TIO 457 * for a command that was not given the disconnect priveledge. 458 */ 459 struct tmode_lstate* pending_device; 460 461 /* 462 * Card characteristics 463 */ 464 ahc_chip chip; 465 ahc_feature features; 466 ahc_flag flags; 467 468 /* Values to store in the SEQCTL register for pause and unpause */ 469 u_int8_t unpause; 470 u_int8_t pause; 471 472 /* Command Queues */ 473 u_int8_t qoutfifonext; 474 u_int8_t qinfifonext; 475 u_int8_t *qoutfifo; 476 u_int8_t *qinfifo; 477 478 /* 479 * 256 byte array storing the SCBID of outstanding 480 * untagged SCBs indexed by TCL. 481 */ 482 u_int8_t *untagged_scbs; 483 484 /* 485 * Hooks into the XPT. 486 */ 487 struct cam_sim *sim; 488 struct cam_sim *sim_b; 489 struct cam_path *path; 490 struct cam_path *path_b; 491 492 int unit; 493 494 /* Channel Names ('A', 'B', etc.) */ 495 char channel; 496 char channel_b; 497 498 /* Initiator Bus ID */ 499 u_int8_t our_id; 500 u_int8_t our_id_b; 501 502 /* Targets that need negotiation messages */ 503 u_int16_t targ_msg_req; 504 505 /* 506 * PCI error detection and data for running the 507 * PCI error interrupt handler. 508 */ 509 int unsolicited_ints; 510 device_t device; 511 512 /* 513 * Target incoming command FIFO. 514 */ 515 struct target_cmd *targetcmds; 516 u_int8_t tqinfifonext; 517 518 /* 519 * Incoming and outgoing message handling. 520 */ 521 u_int8_t send_msg_perror; 522 ahc_msg_type msg_type; 523 u_int8_t msgout_buf[8]; /* Message we are sending */ 524 u_int8_t msgin_buf[8]; /* Message we are receiving */ 525 u_int msgout_len; /* Length of message to send */ 526 u_int msgout_index; /* Current index in msgout */ 527 u_int msgin_index; /* Current index in msgin */ 528 529 int regs_res_type; 530 int regs_res_id; 531 int irq_res_type; 532 struct resource *regs; 533 struct resource *irq; 534 void *ih; 535 bus_dma_tag_t parent_dmat; 536 bus_dma_tag_t shared_data_dmat; 537 bus_dmamap_t shared_data_dmamap; 538 bus_addr_t shared_data_busaddr; 539 540 /* Number of enabled target mode device on this card */ 541 u_int enabled_luns; 542 543 /* Initialization level of this data structure */ 544 u_int init_level; 545 }; 546 547 struct full_ahc_softc { 548 struct ahc_softc softc; 549 struct scb_data scb_data_storage; 550 }; 551 552 /* #define AHC_DEBUG */ 553 #ifdef AHC_DEBUG 554 /* Different debugging levels used when AHC_DEBUG is defined */ 555 #define AHC_SHOWMISC 0x0001 556 #define AHC_SHOWCMDS 0x0002 557 #define AHC_SHOWSCBS 0x0004 558 #define AHC_SHOWABORTS 0x0008 559 #define AHC_SHOWSENSE 0x0010 560 #define AHC_SHOWSCBCNT 0x0020 561 562 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 563 #endif 564 565 char *ahc_name(struct ahc_softc *ahc); 566 567 struct ahc_softc* 568 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 569 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 570 ahc_feature features, ahc_flag flags, 571 struct scb_data *scb_data); 572 int ahc_reset(struct ahc_softc *ahc); 573 void ahc_free(struct ahc_softc *); 574 int ahc_probe_scbs(struct ahc_softc *); 575 int ahc_init(struct ahc_softc *); 576 int ahc_attach(struct ahc_softc *); 577 void ahc_intr(void *arg); 578 579 #define ahc_inb(ahc, port) \ 580 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 581 582 #define ahc_outb(ahc, port, value) \ 583 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 584 585 #define ahc_outsb(ahc, port, valp, count) \ 586 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 587 588 #endif /* _AIC7XXX_H_ */ 589