1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * the GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #include "ahc.h" /* for NAHC from config */ 40 #include "opt_aic7xxx.h" /* for config options */ 41 42 #include <sys/bus.h> /* For device_t */ 43 44 #ifndef MAX 45 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 46 #endif 47 48 #ifndef MIN 49 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 50 #endif 51 52 /* 53 * The maximum transfer per S/G segment. 54 */ 55 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 56 57 /* 58 * The number of dma segments supported. The current implementation limits 59 * us to 255 S/G entries (this may change to be unlimited at some point). 60 * To reduce the driver's memory consumption, we further limit the number 61 * supported to be sufficient to handle the largest mapping supported by 62 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 63 * and unaligned, this turns out to be the number of paged sized transfers 64 * in MAXPHYS plus an extra element to handle any unaligned residual. 65 */ 66 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 67 68 #define AHC_SCB_MAX 255 /* 69 * Up to 255 SCBs on some types of aic7xxx 70 * based boards. The aic7870 have 16 internal 71 * SCBs, but external SRAM bumps this to 255. 72 * The aic7770 family have only 4, and the 73 * aic7850 has only 3. 74 */ 75 76 #define AHC_TMODE_CMDS 256 /* 77 * Ring Buffer of incoming target commands. 78 * We allocate 256 to simplify the logic 79 * in the sequencer by using the natural 80 * wrap point of an 8bit counter. 81 */ 82 83 struct ahc_dma_seg { 84 u_int32_t addr; 85 u_int32_t len; 86 }; 87 88 typedef enum { 89 AHC_NONE = 0x0000, 90 AHC_CHIPID_MASK = 0x00FF, 91 AHC_AIC7770 = 0x0001, 92 AHC_AIC7850 = 0x0002, 93 AHC_AIC7855 = 0x0003, 94 AHC_AIC7859 = 0x0004, 95 AHC_AIC7860 = 0x0005, 96 AHC_AIC7870 = 0x0006, 97 AHC_AIC7880 = 0x0007, 98 AHC_AIC7890 = 0x0008, 99 AHC_AIC7895 = 0x0009, 100 AHC_AIC7896 = 0x000a, 101 AHC_VL = 0x0100, /* Bus type VL */ 102 AHC_EISA = 0x0200, /* Bus type EISA */ 103 AHC_PCI = 0x0400, /* Bus type PCI */ 104 AHC_BUS_MASK = 0x0F00 105 } ahc_chip; 106 107 typedef enum { 108 AHC_FENONE = 0x0000, 109 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 110 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 111 AHC_WIDE = 0x0004, /* Wide Channel */ 112 AHC_TWIN = 0x0008, /* Twin Channel */ 113 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 114 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 115 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 116 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 117 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 118 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 119 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 120 AHC_AIC7770_FE = AHC_FENONE, 121 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 122 AHC_AIC7855_FE = AHC_FENONE|AHC_SPIOCAP, 123 AHC_AIC7859_FE = AHC_ULTRA|AHC_SPIOCAP, 124 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 125 AHC_AIC7870_FE = AHC_FENONE, 126 AHC_AIC7880_FE = AHC_ULTRA, 127 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 128 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX, 129 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 130 AHC_AIC7895C_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA|AHC_MULTI_TID, 131 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 132 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 133 } ahc_feature; 134 135 typedef enum { 136 AHC_FNONE = 0x000, 137 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 138 AHC_CHANNEL_B_PRIMARY = 0x002,/* 139 * On twin channel adapters, probe 140 * channel B first since it is the 141 * primary bus. 142 */ 143 AHC_USEDEFAULTS = 0x004,/* 144 * For cards without an seeprom 145 * or a BIOS to initialize the chip's 146 * SRAM, we use the default target 147 * settings. 148 */ 149 AHC_SHARED_SRAM = 0x010, 150 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 151 AHC_RESET_BUS_A = 0x040, 152 AHC_RESET_BUS_B = 0x080, 153 AHC_EXTENDED_TRANS_A = 0x100, 154 AHC_EXTENDED_TRANS_B = 0x200, 155 AHC_TERM_ENB_A = 0x400, 156 AHC_TERM_ENB_B = 0x800, 157 AHC_INITIATORMODE = 0x1000,/* 158 * Allow initiator operations on 159 * this controller. 160 */ 161 AHC_TARGETMODE = 0x2000,/* 162 * Allow target operations on this 163 * controller. 164 */ 165 AHC_NEWEEPROM_FMT = 0x4000, 166 AHC_RESOURCE_SHORTAGE = 0x8000, 167 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 168 } ahc_flag; 169 170 typedef enum { 171 SCB_FREE = 0x0000, 172 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 173 * Another device was active 174 * during the first timeout for 175 * this SCB so we gave ourselves 176 * an additional timeout period 177 * in case it was hogging the 178 * bus. 179 */ 180 SCB_DEVICE_RESET = 0x0004, 181 SCB_SENSE = 0x0008, 182 SCB_RECOVERY_SCB = 0x0040, 183 SCB_ABORT = 0x1000, 184 SCB_QUEUED_MSG = 0x2000, 185 SCB_ACTIVE = 0x4000, 186 SCB_TARGET_IMMEDIATE = 0x8000 187 } scb_flag; 188 189 /* 190 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 191 * consists of a "hardware SCB" mirroring the fields availible on the card 192 * and additional information the kernel stores for each transaction. 193 */ 194 struct hardware_scb { 195 /*0*/ u_int8_t control; 196 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 197 /*2*/ u_int8_t status; 198 /*3*/ u_int8_t SG_count; 199 /*4*/ u_int32_t SG_pointer; 200 /*8*/ u_int8_t residual_SG_count; 201 /*9*/ u_int8_t residual_data_count[3]; 202 /*12*/ u_int32_t data; 203 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 204 * faster to treat it as a long on 205 * a quad boundary. 206 */ 207 /*20*/ u_int32_t cmdpointer; 208 /*24*/ u_int8_t cmdlen; 209 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 210 * Also used as the tag for tagged I/O 211 */ 212 /*26*/ u_int8_t next; /* Used for threading SCBs in the 213 * "Waiting for Selection" and 214 * "Disconnected SCB" lists down 215 * in the sequencer. 216 */ 217 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 218 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 219 /*29*/ u_int8_t spare[3]; /* 220 * Spare space available on 221 * all controller types. 222 */ 223 /*32*/ u_int8_t cmdstore[16]; /* 224 * CDB storage for controllers 225 * supporting 64 byte SCBs. 226 */ 227 /*48*/ u_int32_t cmdstore_busaddr; /* 228 * Address of command store for 229 * 32byte SCB adapters 230 */ 231 /*48*/ u_int8_t spare_64[12]; /* 232 * Pad to 64 bytes. 233 */ 234 }; 235 236 struct scb { 237 struct hardware_scb *hscb; 238 SLIST_ENTRY(scb) links; /* for chaining */ 239 union ccb *ccb; /* the ccb for this cmd */ 240 scb_flag flags; 241 bus_dmamap_t dmamap; 242 struct ahc_dma_seg *sg_list; 243 bus_addr_t sg_list_phys; 244 u_int sg_count;/* How full ahc_dma_seg is */ 245 }; 246 247 /* 248 * Connection desciptor for select-in requests in target mode. 249 * The first byte is the connecting target, followed by identify 250 * message and optional tag information, terminated by 0xFF. The 251 * remainder is the command to execute. The cmd_valid byte is on 252 * an 8 byte boundary to simplify setting it on aic7880 hardware 253 * which only has limited direct access to the DMA FIFO. 254 */ 255 struct target_cmd { 256 u_int8_t initiator_channel; 257 u_int8_t targ_id; /* Target ID we were selected at */ 258 u_int8_t identify; /* Identify message */ 259 u_int8_t bytes[21]; 260 u_int8_t cmd_valid; 261 u_int8_t pad[7]; 262 }; 263 264 /* 265 * Number of events we can buffer up if we run out 266 * of immediate notify ccbs. 267 */ 268 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 269 struct ahc_tmode_event { 270 u_int8_t initiator_id; 271 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 272 #define EVENT_TYPE_BUS_RESET 0xFF 273 u_int8_t event_arg; 274 }; 275 276 /* 277 * Per lun target mode state including accept TIO CCB 278 * and immediate notify CCB pools. 279 */ 280 struct tmode_lstate { 281 struct cam_path *path; 282 struct ccb_hdr_slist accept_tios; 283 struct ccb_hdr_slist immed_notifies; 284 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 285 u_int8_t event_r_idx; 286 u_int8_t event_w_idx; 287 }; 288 289 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 290 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 291 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 292 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 293 294 struct ahc_transinfo { 295 u_int8_t width; 296 u_int8_t period; 297 u_int8_t offset; 298 }; 299 300 struct ahc_initiator_tinfo { 301 u_int8_t scsirate; 302 struct ahc_transinfo current; 303 struct ahc_transinfo goal; 304 struct ahc_transinfo user; 305 }; 306 307 /* 308 * Per target mode enabled target state. Esentially just an array of 309 * pointers to lun target state as well as sync/wide negotiation information 310 * for each initiator<->target mapping (including the mapping for when we 311 * are the initiator). 312 */ 313 struct tmode_tstate { 314 struct tmode_lstate* enabled_luns[8]; 315 struct ahc_initiator_tinfo transinfo[16]; 316 317 /* 318 * Per initiator state bitmasks. 319 */ 320 u_int16_t ultraenb; /* Using ultra sync rate */ 321 u_int16_t discenable; /* Disconnection allowed */ 322 u_int16_t tagenable; /* Tagged Queuing allowed */ 323 }; 324 325 /* 326 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 327 */ 328 329 struct seeprom_config { 330 /* 331 * SCSI ID Configuration Flags 332 */ 333 u_int16_t device_flags[16]; /* words 0-15 */ 334 #define CFXFER 0x0007 /* synchronous transfer rate */ 335 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 336 #define CFDISC 0x0010 /* enable disconnection */ 337 #define CFWIDEB 0x0020 /* wide bus device */ 338 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 339 /* UNUSED 0x0080 */ 340 #define CFSTART 0x0100 /* send start unit SCSI command */ 341 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 342 #define CFRNFOUND 0x0400 /* report even if not found */ 343 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 344 /* UNUSED 0xf000 */ 345 346 /* 347 * BIOS Control Bits 348 */ 349 u_int16_t bios_control; /* word 16 */ 350 #define CFSUPREM 0x0001 /* support all removeable drives */ 351 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 352 #define CFBIOSEN 0x0004 /* BIOS enabled */ 353 /* UNUSED 0x0008 */ 354 #define CFSM2DRV 0x0010 /* support more than two drives */ 355 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 356 /* UNUSED 0x0060 */ 357 #define CFEXTEND 0x0080 /* extended translation enabled */ 358 /* UNUSED 0xff00 */ 359 360 /* 361 * Host Adapter Control Bits 362 */ 363 u_int16_t adapter_control; /* word 17 */ 364 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 365 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 366 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 367 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 368 #define CFSTERM 0x0004 /* SCSI low byte termination */ 369 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 370 #define CFSPARITY 0x0010 /* SCSI parity */ 371 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 372 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 373 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 374 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 375 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 376 /* UNUSED 0xf080 */ 377 378 /* 379 * Bus Release, Host Adapter ID 380 */ 381 u_int16_t brtime_id; /* word 18 */ 382 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 383 /* UNUSED 0x00f0 */ 384 #define CFBRTIME 0xff00 /* bus release time */ 385 386 /* 387 * Maximum targets 388 */ 389 u_int16_t max_targets; /* word 19 */ 390 #define CFMAXTARG 0x00ff /* maximum targets */ 391 /* UNUSED 0xff00 */ 392 u_int16_t res_1[11]; /* words 20-30 */ 393 u_int16_t checksum; /* word 31 */ 394 }; 395 396 struct ahc_syncrate { 397 int sxfr_ultra2; 398 int sxfr; 399 /* Rates in Ultra mode have bit 8 of sxfr set */ 400 #define ULTRA_SXFR 0x100 401 u_int8_t period; /* Period to send to SCSI target */ 402 char *rate; 403 }; 404 405 typedef enum { 406 MSG_TYPE_NONE = 0x00, 407 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 408 MSG_TYPE_INITIATOR_MSGIN = 0x02, 409 MSG_TYPE_TARGET_MSGOUT = 0x03, 410 MSG_TYPE_TARGET_MSGIN = 0x04 411 } ahc_msg_type; 412 413 struct sg_map_node { 414 bus_dmamap_t sg_dmamap; 415 bus_addr_t sg_physaddr; 416 struct ahc_dma_seg* sg_vaddr; 417 SLIST_ENTRY(sg_map_node) links; 418 }; 419 420 struct scb_data { 421 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 422 struct scb *scbarray; /* Array of kernel SCBs */ 423 SLIST_HEAD(, scb) free_scbs; /* 424 * Pool of SCBs ready to be assigned 425 * commands to execute. 426 */ 427 struct scsi_sense_data *sense; /* Per SCB sense data */ 428 429 /* 430 * "Bus" addresses of our data structures. 431 */ 432 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 433 bus_dmamap_t hscb_dmamap; 434 bus_addr_t hscb_busaddr; 435 bus_dma_tag_t sense_dmat; 436 bus_dmamap_t sense_dmamap; 437 bus_addr_t sense_busaddr; 438 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 439 SLIST_HEAD(, sg_map_node) sg_maps; 440 u_int8_t numscbs; 441 u_int8_t maxhscbs; /* Number of SCBs on the card */ 442 u_int8_t init_level; /* 443 * How far we've initialized 444 * this structure. 445 */ 446 }; 447 448 struct ahc_softc { 449 bus_space_tag_t tag; 450 bus_space_handle_t bsh; 451 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 452 struct scb_data *scb_data; 453 454 /* 455 * CCBs that have been send to the controller 456 */ 457 LIST_HEAD(, ccb_hdr) pending_ccbs; 458 459 /* 460 * Target mode related state kept on a per enabled lun basis. 461 * Targets that are not enabled will have null entries. 462 * As an initiator, we keep one target entry for our initiator 463 * ID to store our sync/wide transfer settings. 464 */ 465 struct tmode_tstate* enabled_targets[16]; 466 467 /* 468 * The black hole device responsible for handling requests for 469 * disabled luns on enabled targets. 470 */ 471 struct tmode_lstate* black_hole; 472 473 /* 474 * Device instance currently on the bus awaiting a continue TIO 475 * for a command that was not given the disconnect priveledge. 476 */ 477 struct tmode_lstate* pending_device; 478 479 /* 480 * Card characteristics 481 */ 482 ahc_chip chip; 483 ahc_feature features; 484 ahc_flag flags; 485 486 /* Values to store in the SEQCTL register for pause and unpause */ 487 u_int8_t unpause; 488 u_int8_t pause; 489 490 /* Command Queues */ 491 u_int8_t qoutfifonext; 492 u_int8_t qinfifonext; 493 u_int8_t *qoutfifo; 494 u_int8_t *qinfifo; 495 496 /* 497 * 256 byte array storing the SCBID of outstanding 498 * untagged SCBs indexed by TCL. 499 */ 500 u_int8_t *untagged_scbs; 501 502 /* 503 * Hooks into the XPT. 504 */ 505 struct cam_sim *sim; 506 struct cam_sim *sim_b; 507 struct cam_path *path; 508 struct cam_path *path_b; 509 510 int unit; 511 512 /* Channel Names ('A', 'B', etc.) */ 513 char channel; 514 char channel_b; 515 516 /* Initiator Bus ID */ 517 u_int8_t our_id; 518 u_int8_t our_id_b; 519 520 /* Targets that need negotiation messages */ 521 u_int16_t targ_msg_req; 522 523 /* 524 * PCI error detection and data for running the 525 * PCI error interrupt handler. 526 */ 527 int unsolicited_ints; 528 device_t device; 529 530 /* 531 * Target incoming command FIFO. 532 */ 533 struct target_cmd *targetcmds; 534 u_int8_t tqinfifonext; 535 536 /* 537 * Incoming and outgoing message handling. 538 */ 539 u_int8_t send_msg_perror; 540 ahc_msg_type msg_type; 541 u_int8_t msgout_buf[8]; /* Message we are sending */ 542 u_int8_t msgin_buf[8]; /* Message we are receiving */ 543 u_int msgout_len; /* Length of message to send */ 544 u_int msgout_index; /* Current index in msgout */ 545 u_int msgin_index; /* Current index in msgin */ 546 547 int regs_res_type; 548 int regs_res_id; 549 int irq_res_type; 550 struct resource *regs; 551 struct resource *irq; 552 void *ih; 553 bus_dma_tag_t parent_dmat; 554 bus_dma_tag_t shared_data_dmat; 555 bus_dmamap_t shared_data_dmamap; 556 bus_addr_t shared_data_busaddr; 557 558 /* Number of enabled target mode device on this card */ 559 u_int enabled_luns; 560 561 /* Initialization level of this data structure */ 562 u_int init_level; 563 564 u_int16_t user_discenable;/* Disconnection allowed */ 565 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 566 }; 567 568 struct full_ahc_softc { 569 struct ahc_softc softc; 570 struct scb_data scb_data_storage; 571 }; 572 573 /* #define AHC_DEBUG */ 574 #ifdef AHC_DEBUG 575 /* Different debugging levels used when AHC_DEBUG is defined */ 576 #define AHC_SHOWMISC 0x0001 577 #define AHC_SHOWCMDS 0x0002 578 #define AHC_SHOWSCBS 0x0004 579 #define AHC_SHOWABORTS 0x0008 580 #define AHC_SHOWSENSE 0x0010 581 #define AHC_SHOWSCBCNT 0x0020 582 583 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 584 #endif 585 586 char *ahc_name(struct ahc_softc *ahc); 587 588 struct ahc_softc* 589 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 590 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 591 ahc_feature features, ahc_flag flags, 592 struct scb_data *scb_data); 593 int ahc_reset(struct ahc_softc *ahc); 594 void ahc_free(struct ahc_softc *); 595 int ahc_probe_scbs(struct ahc_softc *); 596 int ahc_init(struct ahc_softc *); 597 int ahc_attach(struct ahc_softc *); 598 void ahc_intr(void *arg); 599 600 #define ahc_inb(ahc, port) \ 601 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 602 603 #define ahc_outb(ahc, port, value) \ 604 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 605 606 #define ahc_outsb(ahc, port, valp, count) \ 607 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 608 609 #define ahc_insb(ahc, port, valp, count) \ 610 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 611 612 #endif /* _AIC7XXX_H_ */ 613