1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40 #ifndef _AIC7XXX_H_ 41 #define _AIC7XXX_H_ 42 43 #include "ahc.h" /* for NAHC from config */ 44 #include "opt_aic7xxx.h" /* for config options */ 45 46 #include <sys/bus.h> /* For device_t */ 47 48 #ifndef MAX 49 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 50 #endif 51 52 #ifndef MIN 53 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 54 #endif 55 56 /* 57 * The maximum transfer per S/G segment. 58 */ 59 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 60 61 /* 62 * The number of dma segments supported. The current implementation limits 63 * us to 255 S/G entries (this may change to be unlimited at some point). 64 * To reduce the driver's memory consumption, we further limit the number 65 * supported to be sufficient to handle the largest mapping supported by 66 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 67 * and unaligned, this turns out to be the number of paged sized transfers 68 * in MAXPHYS plus an extra element to handle any unaligned residual. 69 */ 70 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 71 72 #define AHC_SCB_MAX 255 /* 73 * Up to 255 SCBs on some types of aic7xxx 74 * based boards. The aic7870 have 16 internal 75 * SCBs, but external SRAM bumps this to 255. 76 * The aic7770 family have only 4, and the 77 * aic7850 has only 3. 78 */ 79 80 #define AHC_TMODE_CMDS 256 /* 81 * Ring Buffer of incoming target commands. 82 * We allocate 256 to simplify the logic 83 * in the sequencer by using the natural 84 * wrap point of an 8bit counter. 85 */ 86 87 struct ahc_dma_seg { 88 u_int32_t addr; 89 u_int32_t len; 90 }; 91 92 typedef enum { 93 AHC_NONE = 0x0000, 94 AHC_CHIPID_MASK = 0x00FF, 95 AHC_AIC7770 = 0x0001, 96 AHC_AIC7850 = 0x0002, 97 AHC_AIC7855 = 0x0003, 98 AHC_AIC7859 = 0x0004, 99 AHC_AIC7860 = 0x0005, 100 AHC_AIC7870 = 0x0006, 101 AHC_AIC7880 = 0x0007, 102 AHC_AIC7890 = 0x0008, 103 AHC_AIC7895 = 0x0009, 104 AHC_AIC7896 = 0x000a, 105 AHC_VL = 0x0100, /* Bus type VL */ 106 AHC_EISA = 0x0200, /* Bus type EISA */ 107 AHC_PCI = 0x0400, /* Bus type PCI */ 108 } ahc_chip; 109 110 typedef enum { 111 AHC_FENONE = 0x0000, 112 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 113 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 114 AHC_WIDE = 0x0004, /* Wide Channel */ 115 AHC_TWIN = 0x0008, /* Twin Channel */ 116 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 117 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 118 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 119 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 120 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 121 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 122 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 123 AHC_AIC7770_FE = AHC_FENONE, 124 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 125 AHC_AIC7855_FE = AHC_FENONE|AHC_SPIOCAP, 126 AHC_AIC7859_FE = AHC_ULTRA|AHC_SPIOCAP, 127 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 128 AHC_AIC7870_FE = AHC_FENONE, 129 AHC_AIC7880_FE = AHC_ULTRA, 130 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 131 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX, 132 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 133 AHC_AIC7895C_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA|AHC_MULTI_TID, 134 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 135 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 136 } ahc_feature; 137 138 typedef enum { 139 AHC_FNONE = 0x000, 140 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 141 AHC_CHANNEL_B_PRIMARY = 0x002,/* 142 * On twin channel adapters, probe 143 * channel B first since it is the 144 * primary bus. 145 */ 146 AHC_USEDEFAULTS = 0x004,/* 147 * For cards without an seeprom 148 * or a BIOS to initialize the chip's 149 * SRAM, we use the default target 150 * settings. 151 */ 152 AHC_SHARED_SRAM = 0x010, 153 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 154 AHC_RESET_BUS_A = 0x040, 155 AHC_RESET_BUS_B = 0x080, 156 AHC_EXTENDED_TRANS_A = 0x100, 157 AHC_EXTENDED_TRANS_B = 0x200, 158 AHC_TERM_ENB_A = 0x400, 159 AHC_TERM_ENB_B = 0x800, 160 AHC_INITIATORMODE = 0x1000,/* 161 * Allow initiator operations on 162 * this controller. 163 */ 164 AHC_TARGETMODE = 0x2000,/* 165 * Allow target operations on this 166 * controller. 167 */ 168 AHC_NEWEEPROM_FMT = 0x4000, 169 AHC_RESOURCE_SHORTAGE = 0x8000, 170 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 171 } ahc_flag; 172 173 typedef enum { 174 SCB_FREE = 0x0000, 175 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 176 * Another device was active 177 * during the first timeout for 178 * this SCB so we gave ourselves 179 * an additional timeout period 180 * in case it was hogging the 181 * bus. 182 */ 183 SCB_DEVICE_RESET = 0x0004, 184 SCB_SENSE = 0x0008, 185 SCB_RECOVERY_SCB = 0x0040, 186 SCB_ABORT = 0x1000, 187 SCB_QUEUED_MSG = 0x2000, 188 SCB_ACTIVE = 0x4000, 189 SCB_TARGET_IMMEDIATE = 0x8000 190 } scb_flag; 191 192 /* 193 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 194 * consists of a "hardware SCB" mirroring the fields availible on the card 195 * and additional information the kernel stores for each transaction. 196 */ 197 struct hardware_scb { 198 /*0*/ u_int8_t control; 199 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 200 /*2*/ u_int8_t status; 201 /*3*/ u_int8_t SG_count; 202 /*4*/ u_int32_t SG_pointer; 203 /*8*/ u_int8_t residual_SG_count; 204 /*9*/ u_int8_t residual_data_count[3]; 205 /*12*/ u_int32_t data; 206 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 207 * faster to treat it as a long on 208 * a quad boundary. 209 */ 210 /*20*/ u_int32_t cmdpointer; 211 /*24*/ u_int8_t cmdlen; 212 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 213 * Also used as the tag for tagged I/O 214 */ 215 /*26*/ u_int8_t next; /* Used for threading SCBs in the 216 * "Waiting for Selection" and 217 * "Disconnected SCB" lists down 218 * in the sequencer. 219 */ 220 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 221 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 222 /*29*/ u_int8_t spare[3]; /* 223 * Spare space available on 224 * all controller types. 225 */ 226 /*32*/ u_int8_t cmdstore[16]; /* 227 * CDB storage for controllers 228 * supporting 64 byte SCBs. 229 */ 230 /*48*/ u_int32_t cmdstore_busaddr; /* 231 * Address of command store for 232 * 32byte SCB adapters 233 */ 234 /*48*/ u_int8_t spare_64[12]; /* 235 * Pad to 64 bytes. 236 */ 237 }; 238 239 struct scb { 240 struct hardware_scb *hscb; 241 SLIST_ENTRY(scb) links; /* for chaining */ 242 union ccb *ccb; /* the ccb for this cmd */ 243 scb_flag flags; 244 bus_dmamap_t dmamap; 245 struct ahc_dma_seg *sg_list; 246 bus_addr_t sg_list_phys; 247 u_int sg_count;/* How full ahc_dma_seg is */ 248 }; 249 250 /* 251 * Connection desciptor for select-in requests in target mode. 252 * The first byte is the connecting target, followed by identify 253 * message and optional tag information, terminated by 0xFF. The 254 * remainder is the command to execute. The cmd_valid byte is on 255 * an 8 byte boundary to simplify setting it on aic7880 hardware 256 * which only has limited direct access to the DMA FIFO. 257 */ 258 struct target_cmd { 259 u_int8_t initiator_channel; 260 u_int8_t targ_id; /* Target ID we were selected at */ 261 u_int8_t identify; /* Identify message */ 262 u_int8_t bytes[21]; 263 u_int8_t cmd_valid; 264 u_int8_t pad[7]; 265 }; 266 267 /* 268 * Number of events we can buffer up if we run out 269 * of immediate notify ccbs. 270 */ 271 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 272 struct ahc_tmode_event { 273 u_int8_t initiator_id; 274 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 275 #define EVENT_TYPE_BUS_RESET 0xFF 276 u_int8_t event_arg; 277 }; 278 279 /* 280 * Per lun target mode state including accept TIO CCB 281 * and immediate notify CCB pools. 282 */ 283 struct tmode_lstate { 284 struct cam_path *path; 285 struct ccb_hdr_slist accept_tios; 286 struct ccb_hdr_slist immed_notifies; 287 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 288 u_int8_t event_r_idx; 289 u_int8_t event_w_idx; 290 }; 291 292 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 293 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 294 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 295 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 296 297 struct ahc_transinfo { 298 u_int8_t width; 299 u_int8_t period; 300 u_int8_t offset; 301 }; 302 303 struct ahc_initiator_tinfo { 304 u_int8_t scsirate; 305 struct ahc_transinfo current; 306 struct ahc_transinfo goal; 307 struct ahc_transinfo user; 308 }; 309 310 /* 311 * Per target mode enabled target state. Esentially just an array of 312 * pointers to lun target state as well as sync/wide negotiation information 313 * for each initiator<->target mapping (including the mapping for when we 314 * are the initiator). 315 */ 316 struct tmode_tstate { 317 struct tmode_lstate* enabled_luns[8]; 318 struct ahc_initiator_tinfo transinfo[16]; 319 320 /* 321 * Per initiator state bitmasks. 322 */ 323 u_int16_t ultraenb; /* Using ultra sync rate */ 324 u_int16_t discenable; /* Disconnection allowed */ 325 u_int16_t tagenable; /* Tagged Queuing allowed */ 326 }; 327 328 /* 329 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 330 */ 331 332 struct seeprom_config { 333 /* 334 * SCSI ID Configuration Flags 335 */ 336 u_int16_t device_flags[16]; /* words 0-15 */ 337 #define CFXFER 0x0007 /* synchronous transfer rate */ 338 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 339 #define CFDISC 0x0010 /* enable disconnection */ 340 #define CFWIDEB 0x0020 /* wide bus device */ 341 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 342 /* UNUSED 0x0080 */ 343 #define CFSTART 0x0100 /* send start unit SCSI command */ 344 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 345 #define CFRNFOUND 0x0400 /* report even if not found */ 346 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 347 /* UNUSED 0xf000 */ 348 349 /* 350 * BIOS Control Bits 351 */ 352 u_int16_t bios_control; /* word 16 */ 353 #define CFSUPREM 0x0001 /* support all removeable drives */ 354 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 355 #define CFBIOSEN 0x0004 /* BIOS enabled */ 356 /* UNUSED 0x0008 */ 357 #define CFSM2DRV 0x0010 /* support more than two drives */ 358 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 359 /* UNUSED 0x0060 */ 360 #define CFEXTEND 0x0080 /* extended translation enabled */ 361 /* UNUSED 0xff00 */ 362 363 /* 364 * Host Adapter Control Bits 365 */ 366 u_int16_t adapter_control; /* word 17 */ 367 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 368 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 369 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 370 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 371 #define CFSTERM 0x0004 /* SCSI low byte termination */ 372 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 373 #define CFSPARITY 0x0010 /* SCSI parity */ 374 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 375 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 376 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 377 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 378 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 379 /* UNUSED 0xf080 */ 380 381 /* 382 * Bus Release, Host Adapter ID 383 */ 384 u_int16_t brtime_id; /* word 18 */ 385 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 386 /* UNUSED 0x00f0 */ 387 #define CFBRTIME 0xff00 /* bus release time */ 388 389 /* 390 * Maximum targets 391 */ 392 u_int16_t max_targets; /* word 19 */ 393 #define CFMAXTARG 0x00ff /* maximum targets */ 394 /* UNUSED 0xff00 */ 395 u_int16_t res_1[11]; /* words 20-30 */ 396 u_int16_t checksum; /* word 31 */ 397 }; 398 399 struct ahc_syncrate { 400 int sxfr_ultra2; 401 int sxfr; 402 /* Rates in Ultra mode have bit 8 of sxfr set */ 403 #define ULTRA_SXFR 0x100 404 u_int8_t period; /* Period to send to SCSI target */ 405 char *rate; 406 }; 407 408 typedef enum { 409 MSG_TYPE_NONE = 0x00, 410 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 411 MSG_TYPE_INITIATOR_MSGIN = 0x02, 412 MSG_TYPE_TARGET_MSGOUT = 0x03, 413 MSG_TYPE_TARGET_MSGIN = 0x04 414 } ahc_msg_type; 415 416 struct sg_map_node { 417 bus_dmamap_t sg_dmamap; 418 bus_addr_t sg_physaddr; 419 struct ahc_dma_seg* sg_vaddr; 420 SLIST_ENTRY(sg_map_node) links; 421 }; 422 423 struct scb_data { 424 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 425 struct scb *scbarray; /* Array of kernel SCBs */ 426 SLIST_HEAD(, scb) free_scbs; /* 427 * Pool of SCBs ready to be assigned 428 * commands to execute. 429 */ 430 struct scsi_sense_data *sense; /* Per SCB sense data */ 431 432 /* 433 * "Bus" addresses of our data structures. 434 */ 435 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 436 bus_dmamap_t hscb_dmamap; 437 bus_addr_t hscb_busaddr; 438 bus_dma_tag_t sense_dmat; 439 bus_dmamap_t sense_dmamap; 440 bus_addr_t sense_busaddr; 441 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 442 SLIST_HEAD(, sg_map_node) sg_maps; 443 u_int8_t numscbs; 444 u_int8_t maxhscbs; /* Number of SCBs on the card */ 445 u_int8_t init_level; /* 446 * How far we've initialized 447 * this structure. 448 */ 449 }; 450 451 struct ahc_softc { 452 bus_space_tag_t tag; 453 bus_space_handle_t bsh; 454 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 455 struct scb_data *scb_data; 456 457 /* 458 * CCBs that have been send to the controller 459 */ 460 LIST_HEAD(, ccb_hdr) pending_ccbs; 461 462 /* 463 * Target mode related state kept on a per enabled lun basis. 464 * Targets that are not enabled will have null entries. 465 * As an initiator, we keep one target entry for our initiator 466 * ID to store our sync/wide transfer settings. 467 */ 468 struct tmode_tstate* enabled_targets[16]; 469 470 /* 471 * The black hole device responsible for handling requests for 472 * disabled luns on enabled targets. 473 */ 474 struct tmode_lstate* black_hole; 475 476 /* 477 * Device instance currently on the bus awaiting a continue TIO 478 * for a command that was not given the disconnect priveledge. 479 */ 480 struct tmode_lstate* pending_device; 481 482 /* 483 * Card characteristics 484 */ 485 ahc_chip chip; 486 ahc_feature features; 487 ahc_flag flags; 488 489 /* Values to store in the SEQCTL register for pause and unpause */ 490 u_int8_t unpause; 491 u_int8_t pause; 492 493 /* Command Queues */ 494 u_int8_t qoutfifonext; 495 u_int8_t qinfifonext; 496 u_int8_t *qoutfifo; 497 u_int8_t *qinfifo; 498 499 /* 500 * 256 byte array storing the SCBID of outstanding 501 * untagged SCBs indexed by TCL. 502 */ 503 u_int8_t *untagged_scbs; 504 505 /* 506 * Hooks into the XPT. 507 */ 508 struct cam_sim *sim; 509 struct cam_sim *sim_b; 510 struct cam_path *path; 511 struct cam_path *path_b; 512 513 int unit; 514 515 /* Channel Names ('A', 'B', etc.) */ 516 char channel; 517 char channel_b; 518 519 /* Initiator Bus ID */ 520 u_int8_t our_id; 521 u_int8_t our_id_b; 522 523 /* Targets that need negotiation messages */ 524 u_int16_t targ_msg_req; 525 526 /* 527 * PCI error detection and data for running the 528 * PCI error interrupt handler. 529 */ 530 int unsolicited_ints; 531 device_t device; 532 533 /* 534 * Target incoming command FIFO. 535 */ 536 struct target_cmd *targetcmds; 537 u_int8_t tqinfifonext; 538 539 /* 540 * Incoming and outgoing message handling. 541 */ 542 u_int8_t send_msg_perror; 543 ahc_msg_type msg_type; 544 u_int8_t msgout_buf[8]; /* Message we are sending */ 545 u_int8_t msgin_buf[8]; /* Message we are receiving */ 546 u_int msgout_len; /* Length of message to send */ 547 u_int msgout_index; /* Current index in msgout */ 548 u_int msgin_index; /* Current index in msgin */ 549 550 int regs_res_type; 551 int regs_res_id; 552 int irq_res_type; 553 struct resource *regs; 554 struct resource *irq; 555 void *ih; 556 bus_dma_tag_t parent_dmat; 557 bus_dma_tag_t shared_data_dmat; 558 bus_dmamap_t shared_data_dmamap; 559 bus_addr_t shared_data_busaddr; 560 561 /* Number of enabled target mode device on this card */ 562 u_int enabled_luns; 563 564 /* Initialization level of this data structure */ 565 u_int init_level; 566 567 u_int16_t user_discenable;/* Disconnection allowed */ 568 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 569 }; 570 571 struct full_ahc_softc { 572 struct ahc_softc softc; 573 struct scb_data scb_data_storage; 574 }; 575 576 /* #define AHC_DEBUG */ 577 #ifdef AHC_DEBUG 578 /* Different debugging levels used when AHC_DEBUG is defined */ 579 #define AHC_SHOWMISC 0x0001 580 #define AHC_SHOWCMDS 0x0002 581 #define AHC_SHOWSCBS 0x0004 582 #define AHC_SHOWABORTS 0x0008 583 #define AHC_SHOWSENSE 0x0010 584 #define AHC_SHOWSCBCNT 0x0020 585 586 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 587 #endif 588 589 char *ahc_name(struct ahc_softc *ahc); 590 591 struct ahc_softc* 592 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 593 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 594 ahc_feature features, ahc_flag flags, 595 struct scb_data *scb_data); 596 int ahc_reset(struct ahc_softc *ahc); 597 void ahc_free(struct ahc_softc *); 598 int ahc_probe_scbs(struct ahc_softc *); 599 int ahc_init(struct ahc_softc *); 600 int ahc_attach(struct ahc_softc *); 601 void ahc_intr(void *arg); 602 603 #define ahc_inb(ahc, port) \ 604 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 605 606 #define ahc_outb(ahc, port, value) \ 607 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 608 609 #define ahc_outsb(ahc, port, valp, count) \ 610 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 611 612 #endif /* _AIC7XXX_H_ */ 613