1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: aic7xxx.h,v 1.3 1998/12/10 04:14:50 gibbs Exp $ 38 */ 39 40 #ifndef _AIC7XXX_H_ 41 #define _AIC7XXX_H_ 42 43 #include "ahc.h" /* for NAHC from config */ 44 #include "opt_aic7xxx.h" /* for config options */ 45 46 #include <pci/pcivar.h> /* for pcici_t */ 47 48 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 49 #define AHC_NSEG 32 /* The number of dma segments supported. 50 * AHC_NSEG can be maxed out at 256 entries, 51 * but the kernel will never need to transfer 52 * such a large (1MB) request. To reduce the 53 * driver's memory consumption, we reduce the 54 * max to 32. 16 would work if all transfers 55 * are paged alined since the kernel will only 56 * generate at most a 64k transfer, but to 57 * handle non-page aligned transfers, you need 58 * 17, so we round to the next power of two 59 * to make allocating SG space easy and 60 * efficient. 61 */ 62 63 #define AHC_SCB_MAX 255 /* 64 * Up to 255 SCBs on some types of aic7xxx 65 * based boards. The aic7870 have 16 internal 66 * SCBs, but external SRAM bumps this to 255. 67 * The aic7770 family have only 4, and the 68 * aic7850 has only 3. 69 */ 70 71 #define AHC_TMODE_CMDS 256 /* 72 * Ring Buffer of incoming target commands. 73 * We allocate 256 to simplify the logic 74 * in the sequencer by using the natural 75 * wrap point of an 8bit counter. 76 */ 77 78 #if defined(__FreeBSD__) 79 extern u_long ahc_unit; 80 #endif 81 82 struct ahc_dma_seg { 83 u_int32_t addr; 84 u_int32_t len; 85 }; 86 87 typedef enum { 88 AHC_NONE = 0x0000, 89 AHC_CHIPID_MASK = 0x00FF, 90 AHC_AIC7770 = 0x0001, 91 AHC_AIC7850 = 0x0002, 92 AHC_AIC7860 = 0x0003, 93 AHC_AIC7870 = 0x0004, 94 AHC_AIC7880 = 0x0005, 95 AHC_AIC7890 = 0x0006, 96 AHC_AIC7895 = 0x0007, 97 AHC_AIC7896 = 0x0008, 98 AHC_VL = 0x0100, /* Bus type VL */ 99 AHC_EISA = 0x0200, /* Bus type EISA */ 100 AHC_PCI = 0x0400, /* Bus type PCI */ 101 } ahc_chip; 102 103 typedef enum { 104 AHC_FENONE = 0x0000, 105 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 106 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 107 AHC_WIDE = 0x0004, /* Wide Channel */ 108 AHC_TWIN = 0x0008, /* Twin Channel */ 109 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 110 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 111 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 112 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 113 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 114 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 115 AHC_AIC7770_FE = AHC_FENONE, 116 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 117 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 118 AHC_AIC7870_FE = AHC_FENONE, 119 AHC_AIC7880_FE = AHC_ULTRA, 120 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 121 |AHC_SG_PRELOAD|AHC_MULTI_TID, 122 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 123 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 124 |AHC_SG_PRELOAD|AHC_MULTI_TID, 125 } ahc_feature; 126 127 typedef enum { 128 AHC_FNONE = 0x000, 129 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 130 AHC_CHANNEL_B_PRIMARY = 0x002,/* 131 * On twin channel adapters, probe 132 * channel B first since it is the 133 * primary bus. 134 */ 135 AHC_USEDEFAULTS = 0x004,/* 136 * For cards without an seeprom 137 * or a BIOS to initialize the chip's 138 * SRAM, we use the default target 139 * settings. 140 */ 141 AHC_INDIRECT_PAGING = 0x008, 142 AHC_SHARED_SRAM = 0x010, 143 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 144 AHC_RESET_BUS_A = 0x040, 145 AHC_RESET_BUS_B = 0x080, 146 AHC_EXTENDED_TRANS_A = 0x100, 147 AHC_EXTENDED_TRANS_B = 0x200, 148 AHC_TERM_ENB_A = 0x400, 149 AHC_TERM_ENB_B = 0x800, 150 AHC_INITIATORMODE = 0x1000,/* 151 * Allow initiator operations on 152 * this controller. 153 */ 154 AHC_TARGETMODE = 0x2000,/* 155 * Allow target operations on this 156 * controller. 157 */ 158 AHC_NEWEEPROM_FMT = 0x4000, 159 AHC_RESOURCE_SHORTAGE = 0x8000 160 } ahc_flag; 161 162 typedef enum { 163 SCB_FREE = 0x0000, 164 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 165 * Another device was active 166 * during the first timeout for 167 * this SCB so we gave ourselves 168 * an additional timeout period 169 * in case it was hogging the 170 * bus. 171 */ 172 SCB_DEVICE_RESET = 0x0004, 173 SCB_SENSE = 0x0008, 174 SCB_RECOVERY_SCB = 0x0040, 175 SCB_ABORT = 0x1000, 176 SCB_QUEUED_MSG = 0x2000, 177 SCB_ACTIVE = 0x4000, 178 SCB_TARGET_IMMEDIATE = 0x8000 179 } scb_flag; 180 181 /* 182 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 183 * consists of a "hardware SCB" mirroring the fields availible on the card 184 * and additional information the kernel stores for each transaction. 185 */ 186 struct hardware_scb { 187 /*0*/ u_int8_t control; 188 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 189 /*2*/ u_int8_t status; 190 /*3*/ u_int8_t SG_count; 191 /*4*/ u_int32_t SG_pointer; 192 /*8*/ u_int8_t residual_SG_count; 193 /*9*/ u_int8_t residual_data_count[3]; 194 /*12*/ u_int32_t data; 195 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 196 * faster to treat it as a long on 197 * a quad boundary. 198 */ 199 /*20*/ u_int32_t cmdpointer; 200 /*24*/ u_int8_t cmdlen; 201 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 202 * Also used as the tag for tagged I/O 203 */ 204 /*26*/ u_int8_t next; /* Used for threading SCBs in the 205 * "Waiting for Selection" and 206 * "Disconnected SCB" lists down 207 * in the sequencer. 208 */ 209 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 210 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 211 /*29*/ u_int8_t spare[3]; /* 212 * Spare space available on 213 * all controller types. 214 */ 215 /*32*/ u_int8_t cmdstore[16]; /* 216 * CDB storage for controllers 217 * supporting 64 byte SCBs. 218 */ 219 /*48*/ u_int32_t cmdstore_busaddr; /* 220 * Address of command store for 221 * 32byte SCB adapters 222 */ 223 /*48*/ u_int8_t spare_64[12]; /* 224 * Pad to 64 bytes. 225 */ 226 }; 227 228 struct scb { 229 struct hardware_scb *hscb; 230 STAILQ_ENTRY(scb) links; /* for chaining */ 231 union ccb *ccb; /* the ccb for this cmd */ 232 scb_flag flags; 233 bus_dmamap_t dmamap; 234 struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */ 235 u_int32_t ahc_dmaphys;/* Phsical address of SG list */ 236 u_int sg_count;/* How full ahc_dma_seg is */ 237 }; 238 239 struct scb_data { 240 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 241 struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */ 242 STAILQ_HEAD(, scb) free_scbs; /* 243 * Pool of SCBs ready to be assigned 244 * commands to execute. 245 */ 246 u_int8_t numscbs; 247 u_int8_t maxhscbs; /* Number of SCBs on the card */ 248 u_int8_t maxscbs; /* 249 * Max SCBs we allocate total including 250 * any that will force us to page SCBs 251 */ 252 }; 253 254 /* 255 * Connection desciptor for select-in requests in target mode. 256 * The first byte is the connecting target, followed by identify 257 * message and optional tag information, terminated by 0xFF. The 258 * remainder is the command to execute. The cmd_valid byte is on 259 * an 8 byte boundary to simplify setting it on aic7880 hardware 260 * which only has limited direct access to the DMA FIFO. 261 */ 262 struct target_cmd { 263 u_int8_t initiator_channel; 264 u_int8_t targ_id; /* Target ID we were selected at */ 265 u_int8_t identify; /* Identify message */ 266 u_int8_t bytes[21]; 267 u_int8_t cmd_valid; 268 u_int8_t pad[7]; 269 }; 270 271 /* 272 * Per lun target mode state including accept TIO CCB 273 * and immediate notify CCB pools. 274 */ 275 struct tmode_lstate { 276 struct ccb_hdr_slist accept_tios; 277 struct ccb_hdr_slist immed_notifies; 278 }; 279 280 /* 281 * Per target mode enabled target state. Esentially just an array of 282 * pointers to lun target state. 283 */ 284 struct tmode_tstate { 285 struct tmode_lstate* enabled_luns[8]; 286 }; 287 288 /* 289 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 290 */ 291 292 struct seeprom_config { 293 /* 294 * SCSI ID Configuration Flags 295 */ 296 u_int16_t device_flags[16]; /* words 0-15 */ 297 #define CFXFER 0x0007 /* synchronous transfer rate */ 298 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 299 #define CFDISC 0x0010 /* enable disconnection */ 300 #define CFWIDEB 0x0020 /* wide bus device */ 301 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 302 /* UNUSED 0x0080 */ 303 #define CFSTART 0x0100 /* send start unit SCSI command */ 304 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 305 #define CFRNFOUND 0x0400 /* report even if not found */ 306 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 307 /* UNUSED 0xf000 */ 308 309 /* 310 * BIOS Control Bits 311 */ 312 u_int16_t bios_control; /* word 16 */ 313 #define CFSUPREM 0x0001 /* support all removeable drives */ 314 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 315 #define CFBIOSEN 0x0004 /* BIOS enabled */ 316 /* UNUSED 0x0008 */ 317 #define CFSM2DRV 0x0010 /* support more than two drives */ 318 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 319 /* UNUSED 0x0060 */ 320 #define CFEXTEND 0x0080 /* extended translation enabled */ 321 /* UNUSED 0xff00 */ 322 323 /* 324 * Host Adapter Control Bits 325 */ 326 u_int16_t adapter_control; /* word 17 */ 327 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 328 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 329 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 330 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 331 #define CFSTERM 0x0004 /* SCSI low byte termination */ 332 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 333 #define CFSPARITY 0x0010 /* SCSI parity */ 334 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 335 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 336 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 337 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 338 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 339 /* UNUSED 0xf080 */ 340 341 /* 342 * Bus Release, Host Adapter ID 343 */ 344 u_int16_t brtime_id; /* word 18 */ 345 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 346 /* UNUSED 0x00f0 */ 347 #define CFBRTIME 0xff00 /* bus release time */ 348 349 /* 350 * Maximum targets 351 */ 352 u_int16_t max_targets; /* word 19 */ 353 #define CFMAXTARG 0x00ff /* maximum targets */ 354 /* UNUSED 0xff00 */ 355 u_int16_t res_1[11]; /* words 20-30 */ 356 u_int16_t checksum; /* word 31 */ 357 }; 358 359 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 360 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 361 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 362 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 363 364 struct ahc_transinfo { 365 u_int8_t width; 366 u_int8_t period; 367 u_int8_t offset; 368 }; 369 370 struct ahc_target_tinfo { 371 u_int8_t scsirate; 372 struct ahc_transinfo current; 373 struct ahc_transinfo goal; 374 struct ahc_transinfo user; 375 }; 376 377 struct ahc_syncrate { 378 int sxfr_ultra2; 379 int sxfr; 380 /* Rates in Ultra mode have bit 8 of sxfr set */ 381 #define ULTRA_SXFR 0x100 382 u_int8_t period; /* Period to send to SCSI target */ 383 char *rate; 384 }; 385 386 typedef enum { 387 MSG_TYPE_NONE = 0x00, 388 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 389 MSG_TYPE_INITIATOR_MSGIN = 0x02, 390 MSG_TYPE_TARGET_MSGOUT = 0x03, 391 MSG_TYPE_TARGET_MSGIN = 0x04 392 } ahc_msg_type; 393 394 struct ahc_softc { 395 bus_space_tag_t tag; 396 bus_space_handle_t bsh; 397 bus_dma_tag_t dmat; 398 struct scb_data *scb_data; 399 400 /* 401 * CCBs that have been send to the controller 402 */ 403 LIST_HEAD(, ccb_hdr) pending_ccbs; 404 405 /* 406 * Target mode related state kept on a per enabled lun basis. 407 * Targets that are not enabled will have null entries. 408 */ 409 struct tmode_tstate* enabled_targets[16]; 410 411 /* 412 * Device instance currently on the bus awaiting a continue TIO 413 * for a command that was not given the disconnect priveledge. 414 */ 415 struct tmode_lstate* pending_device; 416 417 /* 418 * Card characteristics 419 */ 420 ahc_chip chip; 421 ahc_feature features; 422 ahc_flag flags; 423 424 /* Values to store in the SEQCTL register for pause and unpause */ 425 u_int8_t unpause; 426 u_int8_t pause; 427 428 /* Command Queues */ 429 u_int8_t qoutfifonext; 430 u_int8_t qinfifonext; 431 u_int8_t qoutfifo[256]; 432 u_int8_t qinfifo[256]; 433 434 /* 435 * 256 byte array storing the SCBID of outstanding 436 * untagged SCBs indexed by TCL. 437 */ 438 u_int8_t untagged_scbs[256]; 439 440 /* 441 * User/Current/Active Negotiation settings 442 */ 443 struct ahc_target_tinfo transinfo[16]; 444 445 /* 446 * Per target state bitmasks. 447 */ 448 u_int16_t ultraenb; /* Using ultra sync rate */ 449 u_int16_t discenable; /* Disconnection allowed */ 450 u_int16_t tagenable; /* Tagged Queuing allowed */ 451 u_int16_t targ_msg_req; /* Need negotiation messages */ 452 453 /* 454 * Hooks into the XPT. 455 */ 456 struct cam_sim *sim; 457 struct cam_sim *sim_b; 458 struct cam_path *path; 459 struct cam_path *path_b; 460 461 int unit; 462 463 /* Channel Names ('A', 'B', etc.) */ 464 char channel; 465 char channel_b; 466 467 /* Initiator Bus ID */ 468 u_int8_t our_id; 469 u_int8_t our_id_b; 470 471 /* 472 * PCI error detection and data for running the 473 * PCI error interrupt handler. 474 */ 475 int unsolicited_ints; 476 pcici_t pci_config_id; 477 478 /* 479 * Target incoming command FIFO. 480 */ 481 struct target_cmd *targetcmds; 482 u_int8_t tqinfifonext; 483 484 /* 485 * Incoming and outgoing message handling. 486 */ 487 u_int8_t send_msg_perror; 488 ahc_msg_type msg_type; 489 u_int8_t msgout_buf[8]; /* Message we are sending */ 490 u_int8_t msgin_buf[8]; /* Message we are receiving */ 491 u_int msgout_len; /* Length of message to send */ 492 u_int msgout_index; /* Current index in msgout */ 493 u_int msgin_index; /* Current index in msgin */ 494 495 /* 496 * "Bus" addresses of our data structures. 497 */ 498 u_int32_t hscb_busaddr; 499 }; 500 501 struct full_ahc_softc { 502 struct ahc_softc softc; 503 struct scb_data scb_data_storage; 504 }; 505 506 /* #define AHC_DEBUG */ 507 #ifdef AHC_DEBUG 508 /* Different debugging levels used when AHC_DEBUG is defined */ 509 #define AHC_SHOWMISC 0x0001 510 #define AHC_SHOWCMDS 0x0002 511 #define AHC_SHOWSCBS 0x0004 512 #define AHC_SHOWABORTS 0x0008 513 #define AHC_SHOWSENSE 0x0010 514 #define AHC_SHOWSCBCNT 0x0020 515 516 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 517 #endif 518 519 char *ahc_name(struct ahc_softc *ahc); 520 521 struct ahc_softc *ahc_alloc(int unit, u_int32_t io_base, 522 vm_offset_t maddr, ahc_chip chip, 523 ahc_feature features, ahc_flag flags, 524 struct scb_data *scb_data); 525 int ahc_reset(struct ahc_softc *ahc); 526 void ahc_free(struct ahc_softc *); 527 int ahc_probe_scbs(struct ahc_softc *); 528 int ahc_init(struct ahc_softc *); 529 int ahc_attach(struct ahc_softc *); 530 void ahc_intr(void *arg); 531 532 #define ahc_inb(ahc, port) \ 533 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 534 535 #define ahc_outb(ahc, port, value) \ 536 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 537 538 #define ahc_outsb(ahc, port, valp, count) \ 539 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 540 541 #endif /* _AIC7XXX_H_ */ 542