1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * the GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #include "ahc.h" /* for NAHC from config */ 40 #include "opt_aic7xxx.h" /* for config options */ 41 42 #include <sys/bus.h> /* For device_t */ 43 44 #ifndef MAX 45 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 46 #endif 47 48 #ifndef MIN 49 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 50 #endif 51 52 /* 53 * The maximum transfer per S/G segment. 54 */ 55 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 56 57 /* 58 * The number of dma segments supported. The current implementation limits 59 * us to 255 S/G entries (this may change to be unlimited at some point). 60 * To reduce the driver's memory consumption, we further limit the number 61 * supported to be sufficient to handle the largest mapping supported by 62 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 63 * and unaligned, this turns out to be the number of paged sized transfers 64 * in MAXPHYS plus an extra element to handle any unaligned residual. 65 */ 66 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 67 68 #define AHC_SCB_MAX 255 /* 69 * Up to 255 SCBs on some types of aic7xxx 70 * based boards. The aic7870 have 16 internal 71 * SCBs, but external SRAM bumps this to 255. 72 * The aic7770 family have only 4, and the 73 * aic7850 has only 3. 74 */ 75 76 #define AHC_TMODE_CMDS 256 /* 77 * Ring Buffer of incoming target commands. 78 * We allocate 256 to simplify the logic 79 * in the sequencer by using the natural 80 * wrap point of an 8bit counter. 81 */ 82 83 struct ahc_dma_seg { 84 u_int32_t addr; 85 u_int32_t len; 86 }; 87 88 typedef enum { 89 AHC_NONE = 0x0000, 90 AHC_CHIPID_MASK = 0x00FF, 91 AHC_AIC7770 = 0x0001, 92 AHC_AIC7850 = 0x0002, 93 AHC_AIC7855 = 0x0003, 94 AHC_AIC7859 = 0x0004, 95 AHC_AIC7860 = 0x0005, 96 AHC_AIC7870 = 0x0006, 97 AHC_AIC7880 = 0x0007, 98 AHC_AIC7890 = 0x0008, 99 AHC_AIC7892 = 0x0009, 100 AHC_AIC7895 = 0x000a, 101 AHC_AIC7896 = 0x000b, 102 AHC_AIC7899 = 0x000c, 103 AHC_VL = 0x0100, /* Bus type VL */ 104 AHC_EISA = 0x0200, /* Bus type EISA */ 105 AHC_PCI = 0x0400, /* Bus type PCI */ 106 AHC_BUS_MASK = 0x0F00 107 } ahc_chip; 108 109 extern char *ahc_chip_names[]; 110 111 typedef enum { 112 AHC_FENONE = 0x0000, 113 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 114 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 115 AHC_WIDE = 0x0004, /* Wide Channel */ 116 AHC_TWIN = 0x0008, /* Twin Channel */ 117 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 118 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 119 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 120 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 121 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 122 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 123 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 124 AHC_DT = 0x0800, /* Double Transition transfers */ 125 AHC_NEW_TERMCTL = 0x1000, 126 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 127 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 128 AHC_AIC7770_FE = AHC_TARG_DMABUG, 129 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 130 AHC_AIC7855_FE = AHC_AIC7850_FE, 131 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 132 AHC_AIC7860_FE = AHC_AIC7859_FE, 133 AHC_AIC7870_FE = AHC_TARG_DMABUG, 134 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 135 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 136 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 137 |AHC_NEW_TERMCTL, 138 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 139 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 140 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 141 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 142 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 143 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 144 } ahc_feature; 145 146 typedef enum { 147 AHC_FNONE = 0x000, 148 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 149 AHC_CHANNEL_B_PRIMARY = 0x002,/* 150 * On twin channel adapters, probe 151 * channel B first since it is the 152 * primary bus. 153 */ 154 AHC_USEDEFAULTS = 0x004,/* 155 * For cards without an seeprom 156 * or a BIOS to initialize the chip's 157 * SRAM, we use the default target 158 * settings. 159 */ 160 AHC_SHARED_SRAM = 0x010, 161 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 162 AHC_RESET_BUS_A = 0x040, 163 AHC_RESET_BUS_B = 0x080, 164 AHC_EXTENDED_TRANS_A = 0x100, 165 AHC_EXTENDED_TRANS_B = 0x200, 166 AHC_TERM_ENB_A = 0x400, 167 AHC_TERM_ENB_B = 0x800, 168 AHC_INITIATORMODE = 0x1000,/* 169 * Allow initiator operations on 170 * this controller. 171 */ 172 AHC_TARGETMODE = 0x2000,/* 173 * Allow target operations on this 174 * controller. 175 */ 176 AHC_NEWEEPROM_FMT = 0x4000, 177 AHC_RESOURCE_SHORTAGE = 0x8000, 178 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 179 AHC_INT50_SPEEDFLEX = 0x20000,/* 180 * Internal 50pin connector 181 * sits behind an aic3860 182 */ 183 } ahc_flag; 184 185 typedef enum { 186 SCB_FREE = 0x0000, 187 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 188 * Another device was active 189 * during the first timeout for 190 * this SCB so we gave ourselves 191 * an additional timeout period 192 * in case it was hogging the 193 * bus. 194 */ 195 SCB_DEVICE_RESET = 0x0004, 196 SCB_SENSE = 0x0008, 197 SCB_RECOVERY_SCB = 0x0040, 198 SCB_ABORT = 0x1000, 199 SCB_QUEUED_MSG = 0x2000, 200 SCB_ACTIVE = 0x4000, 201 SCB_TARGET_IMMEDIATE = 0x8000 202 } scb_flag; 203 204 /* 205 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 206 * consists of a "hardware SCB" mirroring the fields availible on the card 207 * and additional information the kernel stores for each transaction. 208 */ 209 struct hardware_scb { 210 /*0*/ u_int8_t control; 211 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 212 /*2*/ u_int8_t status; 213 /*3*/ u_int8_t SG_count; 214 /*4*/ u_int32_t SG_pointer; 215 /*8*/ u_int8_t residual_SG_count; 216 /*9*/ u_int8_t residual_data_count[3]; 217 /*12*/ u_int32_t data; 218 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 219 * faster to treat it as a long on 220 * a quad boundary. 221 */ 222 /*20*/ u_int32_t cmdpointer; 223 /*24*/ u_int8_t cmdlen; 224 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 225 * Also used as the tag for tagged I/O 226 */ 227 /*26*/ u_int8_t next; /* Used for threading SCBs in the 228 * "Waiting for Selection" and 229 * "Disconnected SCB" lists down 230 * in the sequencer. 231 */ 232 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 233 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 234 /*29*/ u_int8_t spare[3]; /* 235 * Spare space available on 236 * all controller types. 237 */ 238 /*32*/ u_int8_t cmdstore[16]; /* 239 * CDB storage for controllers 240 * supporting 64 byte SCBs. 241 */ 242 /*48*/ u_int32_t cmdstore_busaddr; /* 243 * Address of command store for 244 * 32byte SCB adapters 245 */ 246 /*48*/ u_int8_t spare_64[12]; /* 247 * Pad to 64 bytes. 248 */ 249 }; 250 251 struct scb { 252 struct hardware_scb *hscb; 253 SLIST_ENTRY(scb) links; /* for chaining */ 254 union ccb *ccb; /* the ccb for this cmd */ 255 scb_flag flags; 256 bus_dmamap_t dmamap; 257 struct ahc_dma_seg *sg_list; 258 bus_addr_t sg_list_phys; 259 u_int sg_count;/* How full ahc_dma_seg is */ 260 }; 261 262 /* 263 * Connection desciptor for select-in requests in target mode. 264 * The first byte is the connecting target, followed by identify 265 * message and optional tag information, terminated by 0xFF. The 266 * remainder is the command to execute. The cmd_valid byte is on 267 * an 8 byte boundary to simplify setting it on aic7880 hardware 268 * which only has limited direct access to the DMA FIFO. 269 */ 270 struct target_cmd { 271 u_int8_t initiator_channel; 272 u_int8_t targ_id; /* Target ID we were selected at */ 273 u_int8_t identify; /* Identify message */ 274 u_int8_t bytes[21]; 275 u_int8_t cmd_valid; 276 u_int8_t pad[7]; 277 }; 278 279 /* 280 * Number of events we can buffer up if we run out 281 * of immediate notify ccbs. 282 */ 283 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 284 struct ahc_tmode_event { 285 u_int8_t initiator_id; 286 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 287 #define EVENT_TYPE_BUS_RESET 0xFF 288 u_int8_t event_arg; 289 }; 290 291 /* 292 * Per lun target mode state including accept TIO CCB 293 * and immediate notify CCB pools. 294 */ 295 struct tmode_lstate { 296 struct cam_path *path; 297 struct ccb_hdr_slist accept_tios; 298 struct ccb_hdr_slist immed_notifies; 299 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 300 u_int8_t event_r_idx; 301 u_int8_t event_w_idx; 302 }; 303 304 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 305 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 306 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 307 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 308 309 struct ahc_transinfo { 310 u_int8_t width; 311 u_int8_t period; 312 u_int8_t offset; 313 u_int8_t ppr_flags; 314 }; 315 316 struct ahc_initiator_tinfo { 317 u_int8_t scsirate; 318 struct ahc_transinfo current; 319 struct ahc_transinfo goal; 320 struct ahc_transinfo user; 321 }; 322 323 /* 324 * Per target mode enabled target state. Esentially just an array of 325 * pointers to lun target state as well as sync/wide negotiation information 326 * for each initiator<->target mapping (including the mapping for when we 327 * are the initiator). 328 */ 329 struct tmode_tstate { 330 struct tmode_lstate* enabled_luns[8]; 331 struct ahc_initiator_tinfo transinfo[16]; 332 333 /* 334 * Per initiator state bitmasks. 335 */ 336 u_int16_t ultraenb; /* Using ultra sync rate */ 337 u_int16_t discenable; /* Disconnection allowed */ 338 u_int16_t tagenable; /* Tagged Queuing allowed */ 339 }; 340 341 /* 342 * Define the format of the aic7XXX SEEPROM registers (16 bits). 343 */ 344 345 struct seeprom_config { 346 /* 347 * SCSI ID Configuration Flags 348 */ 349 u_int16_t device_flags[16]; /* words 0-15 */ 350 #define CFXFER 0x0007 /* synchronous transfer rate */ 351 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 352 #define CFDISC 0x0010 /* enable disconnection */ 353 #define CFWIDEB 0x0020 /* wide bus device */ 354 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 355 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 356 #define CFSTART 0x0100 /* send start unit SCSI command */ 357 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 358 #define CFRNFOUND 0x0400 /* report even if not found */ 359 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 360 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 361 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 362 363 /* 364 * BIOS Control Bits 365 */ 366 u_int16_t bios_control; /* word 16 */ 367 #define CFSUPREM 0x0001 /* support all removeable drives */ 368 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 369 #define CFBIOSEN 0x0004 /* BIOS enabled */ 370 /* UNUSED 0x0008 */ 371 #define CFSM2DRV 0x0010 /* support more than two drives */ 372 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 373 /* UNUSED 0x0040 */ 374 #define CFEXTEND 0x0080 /* extended translation enabled */ 375 /* UNUSED 0xff00 */ 376 377 /* 378 * Host Adapter Control Bits 379 */ 380 u_int16_t adapter_control; /* word 17 */ 381 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 382 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 383 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 384 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 385 #define CFSTERM 0x0004 /* SCSI low byte termination */ 386 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 387 #define CFSPARITY 0x0010 /* SCSI parity */ 388 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 389 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 390 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 391 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 392 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 393 /* UNUSED 0xf280 */ 394 395 /* 396 * Bus Release, Host Adapter ID 397 */ 398 u_int16_t brtime_id; /* word 18 */ 399 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 400 /* UNUSED 0x00f0 */ 401 #define CFBRTIME 0xff00 /* bus release time */ 402 403 /* 404 * Maximum targets 405 */ 406 u_int16_t max_targets; /* word 19 */ 407 #define CFMAXTARG 0x00ff /* maximum targets */ 408 /* UNUSED 0xff00 */ 409 u_int16_t res_1[11]; /* words 20-30 */ 410 u_int16_t checksum; /* word 31 */ 411 }; 412 413 struct ahc_syncrate { 414 int sxfr_u2; 415 int sxfr; 416 /* Rates in Ultra mode have bit 8 of sxfr set */ 417 #define ULTRA_SXFR 0x100 418 #define ST_SXFR 0x010 419 u_int8_t period; /* Period to send to SCSI target */ 420 char *rate; 421 }; 422 423 typedef enum { 424 MSG_TYPE_NONE = 0x00, 425 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 426 MSG_TYPE_INITIATOR_MSGIN = 0x02, 427 MSG_TYPE_TARGET_MSGOUT = 0x03, 428 MSG_TYPE_TARGET_MSGIN = 0x04 429 } ahc_msg_type; 430 431 struct sg_map_node { 432 bus_dmamap_t sg_dmamap; 433 bus_addr_t sg_physaddr; 434 struct ahc_dma_seg* sg_vaddr; 435 SLIST_ENTRY(sg_map_node) links; 436 }; 437 438 struct scb_data { 439 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 440 struct scb *scbarray; /* Array of kernel SCBs */ 441 SLIST_HEAD(, scb) free_scbs; /* 442 * Pool of SCBs ready to be assigned 443 * commands to execute. 444 */ 445 struct scsi_sense_data *sense; /* Per SCB sense data */ 446 447 /* 448 * "Bus" addresses of our data structures. 449 */ 450 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 451 bus_dmamap_t hscb_dmamap; 452 bus_addr_t hscb_busaddr; 453 bus_dma_tag_t sense_dmat; 454 bus_dmamap_t sense_dmamap; 455 bus_addr_t sense_busaddr; 456 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 457 SLIST_HEAD(, sg_map_node) sg_maps; 458 u_int8_t numscbs; 459 u_int8_t maxhscbs; /* Number of SCBs on the card */ 460 u_int8_t init_level; /* 461 * How far we've initialized 462 * this structure. 463 */ 464 }; 465 466 struct ahc_softc { 467 bus_space_tag_t tag; 468 bus_space_handle_t bsh; 469 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 470 struct scb_data *scb_data; 471 472 /* 473 * CCBs that have been send to the controller 474 */ 475 LIST_HEAD(, ccb_hdr) pending_ccbs; 476 477 /* 478 * Target mode related state kept on a per enabled lun basis. 479 * Targets that are not enabled will have null entries. 480 * As an initiator, we keep one target entry for our initiator 481 * ID to store our sync/wide transfer settings. 482 */ 483 struct tmode_tstate* enabled_targets[16]; 484 485 /* 486 * The black hole device responsible for handling requests for 487 * disabled luns on enabled targets. 488 */ 489 struct tmode_lstate* black_hole; 490 491 /* 492 * Device instance currently on the bus awaiting a continue TIO 493 * for a command that was not given the disconnect priveledge. 494 */ 495 struct tmode_lstate* pending_device; 496 497 /* 498 * Card characteristics 499 */ 500 ahc_chip chip; 501 ahc_feature features; 502 ahc_flag flags; 503 504 /* Values to store in the SEQCTL register for pause and unpause */ 505 u_int8_t unpause; 506 u_int8_t pause; 507 508 /* Command Queues */ 509 u_int8_t qoutfifonext; 510 u_int8_t qinfifonext; 511 u_int8_t *qoutfifo; 512 u_int8_t *qinfifo; 513 514 /* 515 * 256 byte array storing the SCBID of outstanding 516 * untagged SCBs indexed by TCL. 517 */ 518 u_int8_t *untagged_scbs; 519 520 /* 521 * Hooks into the XPT. 522 */ 523 struct cam_sim *sim; 524 struct cam_sim *sim_b; 525 struct cam_path *path; 526 struct cam_path *path_b; 527 528 int unit; 529 530 /* Channel Names ('A', 'B', etc.) */ 531 char channel; 532 char channel_b; 533 534 /* Initiator Bus ID */ 535 u_int8_t our_id; 536 u_int8_t our_id_b; 537 538 /* Targets that need negotiation messages */ 539 u_int16_t targ_msg_req; 540 541 /* 542 * PCI error detection and data for running the 543 * PCI error interrupt handler. 544 */ 545 int unsolicited_ints; 546 device_t device; 547 548 /* 549 * Target incoming command FIFO. 550 */ 551 struct target_cmd *targetcmds; 552 u_int8_t tqinfifonext; 553 554 /* 555 * Incoming and outgoing message handling. 556 */ 557 u_int8_t send_msg_perror; 558 ahc_msg_type msg_type; 559 u_int8_t msgout_buf[8]; /* Message we are sending */ 560 u_int8_t msgin_buf[8]; /* Message we are receiving */ 561 u_int msgout_len; /* Length of message to send */ 562 u_int msgout_index; /* Current index in msgout */ 563 u_int msgin_index; /* Current index in msgin */ 564 565 int regs_res_type; 566 int regs_res_id; 567 int irq_res_type; 568 struct resource *regs; 569 struct resource *irq; 570 void *ih; 571 bus_dma_tag_t parent_dmat; 572 bus_dma_tag_t shared_data_dmat; 573 bus_dmamap_t shared_data_dmamap; 574 bus_addr_t shared_data_busaddr; 575 bus_addr_t dma_bug_buf; 576 577 /* Number of enabled target mode device on this card */ 578 u_int enabled_luns; 579 580 /* Initialization level of this data structure */ 581 u_int init_level; 582 583 u_int16_t user_discenable;/* Disconnection allowed */ 584 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 585 }; 586 587 struct full_ahc_softc { 588 struct ahc_softc softc; 589 struct scb_data scb_data_storage; 590 }; 591 592 /* #define AHC_DEBUG */ 593 #ifdef AHC_DEBUG 594 /* Different debugging levels used when AHC_DEBUG is defined */ 595 #define AHC_SHOWMISC 0x0001 596 #define AHC_SHOWCMDS 0x0002 597 #define AHC_SHOWSCBS 0x0004 598 #define AHC_SHOWABORTS 0x0008 599 #define AHC_SHOWSENSE 0x0010 600 #define AHC_SHOWSCBCNT 0x0020 601 602 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 603 #endif 604 605 char *ahc_name(struct ahc_softc *ahc); 606 607 struct ahc_softc* 608 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 609 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 610 ahc_feature features, ahc_flag flags, 611 struct scb_data *scb_data); 612 int ahc_reset(struct ahc_softc *ahc); 613 void ahc_free(struct ahc_softc *); 614 int ahc_probe_scbs(struct ahc_softc *); 615 int ahc_init(struct ahc_softc *); 616 int ahc_attach(struct ahc_softc *); 617 void ahc_intr(void *arg); 618 619 #define ahc_inb(ahc, port) \ 620 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 621 622 #define ahc_outb(ahc, port, value) \ 623 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 624 625 #define ahc_outsb(ahc, port, valp, count) \ 626 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 627 628 #define ahc_insb(ahc, port, valp, count) \ 629 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 630 631 #endif /* _AIC7XXX_H_ */ 632