1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#29 $ 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 /* Register Definitions */ 40 #include "aic7xxx_reg.h" 41 42 /************************* Forward Declarations *******************************/ 43 struct ahc_platform_data; 44 struct scb_platform_data; 45 46 /****************************** Useful Macros *********************************/ 47 #ifndef MAX 48 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 49 #endif 50 51 #ifndef MIN 52 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 53 #endif 54 55 #ifndef TRUE 56 #define TRUE 1 57 #endif 58 #ifndef FALSE 59 #define FALSE 0 60 #endif 61 62 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 63 64 #define ALL_CHANNELS '\0' 65 #define ALL_TARGETS_MASK 0xFFFF 66 #define INITIATOR_WILDCARD (~0) 67 68 #define SCSIID_TARGET(ahc, scsiid) \ 69 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 70 >> TID_SHIFT) 71 #define SCSIID_OUR_ID(scsiid) \ 72 ((scsiid) & OID) 73 #define SCSIID_CHANNEL(ahc, scsiid) \ 74 ((((ahc)->features & AHC_TWIN) != 0) \ 75 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 76 : 'A') 77 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 78 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 79 #define SCB_GET_OUR_ID(scb) \ 80 SCSIID_OUR_ID((scb)->hscb->scsiid) 81 #define SCB_GET_TARGET(ahc, scb) \ 82 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 83 #define SCB_GET_CHANNEL(ahc, scb) \ 84 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 85 #define SCB_GET_LUN(scb) \ 86 ((scb)->hscb->lun) 87 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 88 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 89 #define SCB_GET_TARGET_MASK(ahc, scb) \ 90 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 91 #define TCL_TARGET_OFFSET(tcl) \ 92 ((((tcl) >> 4) & TID) >> 4) 93 #define TCL_LUN(tcl) \ 94 (tcl & (AHC_NUM_LUNS - 1)) 95 #define BUILD_TCL(scsiid, lun) \ 96 ((lun) | (((scsiid) & TID) << 4)) 97 98 #ifndef AHC_TARGET_MODE 99 #undef AHC_TMODE_ENABLE 100 #define AHC_TMODE_ENABLE 0 101 #endif 102 103 /**************************** Driver Constants ********************************/ 104 /* 105 * The maximum number of supported targets. 106 */ 107 #define AHC_NUM_TARGETS 16 108 109 /* 110 * The maximum number of supported luns. 111 * The identify message only supports 64 luns in SPI3. 112 * You can have 2^64 luns when information unit transfers are enabled, 113 * but it is doubtful this driver will ever support IUTs. 114 */ 115 #define AHC_NUM_LUNS 64 116 117 /* 118 * The maximum transfer per S/G segment. 119 */ 120 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 121 122 /* 123 * The maximum amount of SCB storage in hardware on a controller. 124 * This value represents an upper bound. Controllers vary in the number 125 * they actually support. 126 */ 127 #define AHC_SCB_MAX 255 128 129 /* 130 * The maximum number of concurrent transactions supported per driver instance. 131 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 132 * the space for SCBs on the host adapter varies by model, the driver will 133 * page the SCBs between host and controller memory as needed. We are limited 134 * to 253 because: 135 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 136 * 2) We reserve one value, 255, to represent the invalid element. 137 * 3) Our input queue scheme requires one SCB to always be reserved 138 * in advance of queuing any SCBs. This takes us down to 254. 139 * 4) To handle our output queue correctly on machines that only 140 * support 32bit stores, we must clear the array 4 bytes at a 141 * time. To avoid colliding with a DMA write from the sequencer, 142 * we must be sure that 4 slots are empty when we write to clear 143 * the queue. This reduces us to 253 SCBs: 1 that just completed 144 * and the known three additional empty slots in the queue that 145 * precede it. 146 */ 147 #define AHC_MAX_QUEUE 253 148 149 /* 150 * Ring Buffer of incoming target commands. 151 * We allocate 256 to simplify the logic in the sequencer 152 * by using the natural wrap point of an 8bit counter. 153 */ 154 #define AHC_TMODE_CMDS 256 155 156 /* Reset line assertion time in us */ 157 #define AHC_BUSRESET_DELAY 250 158 159 /******************* Chip Characteristics/Operating Settings *****************/ 160 /* 161 * Chip Type 162 * The chip order is from least sophisticated to most sophisticated. 163 */ 164 typedef enum { 165 AHC_NONE = 0x0000, 166 AHC_CHIPID_MASK = 0x00FF, 167 AHC_AIC7770 = 0x0001, 168 AHC_AIC7850 = 0x0002, 169 AHC_AIC7855 = 0x0003, 170 AHC_AIC7859 = 0x0004, 171 AHC_AIC7860 = 0x0005, 172 AHC_AIC7870 = 0x0006, 173 AHC_AIC7880 = 0x0007, 174 AHC_AIC7895 = 0x0008, 175 AHC_AIC7895C = 0x0009, 176 AHC_AIC7890 = 0x000a, 177 AHC_AIC7896 = 0x000b, 178 AHC_AIC7892 = 0x000c, 179 AHC_AIC7899 = 0x000d, 180 AHC_VL = 0x0100, /* Bus type VL */ 181 AHC_EISA = 0x0200, /* Bus type EISA */ 182 AHC_PCI = 0x0400, /* Bus type PCI */ 183 AHC_BUS_MASK = 0x0F00 184 } ahc_chip; 185 186 /* 187 * Features available in each chip type. 188 */ 189 typedef enum { 190 AHC_FENONE = 0x00000, 191 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 192 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 193 AHC_WIDE = 0x00004, /* Wide Channel */ 194 AHC_TWIN = 0x00008, /* Twin Channel */ 195 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 196 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 197 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 198 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 199 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 200 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 201 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 202 AHC_DT = 0x00800, /* Double Transition transfers */ 203 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 204 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 205 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 206 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 207 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 208 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 209 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 210 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 211 AHC_AIC7770_FE = AHC_FENONE, 212 /* 213 * The real 7850 does not support Ultra modes, but there are 214 * several cards that use the generic 7850 PCI ID even though 215 * they are using an Ultra capable chip (7859/7860). We start 216 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 217 * register to determine if the capability is really present. 218 */ 219 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 220 AHC_AIC7860_FE = AHC_AIC7850_FE, 221 AHC_AIC7870_FE = AHC_TARGETMODE, 222 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 223 /* 224 * Although we have space for both the initiator and 225 * target roles on ULTRA2 chips, we currently disable 226 * the initiator role to allow multi-scsi-id target mode 227 * configurations. We can only respond on the same SCSI 228 * ID as our initiator role if we allow initiator operation. 229 * At some point, we should add a configuration knob to 230 * allow both roles to be loaded. 231 */ 232 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 233 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 234 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 235 |AHC_TARGETMODE, 236 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 237 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 238 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 239 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 240 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 241 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 242 } ahc_feature; 243 244 /* 245 * Bugs in the silicon that we work around in software. 246 */ 247 typedef enum { 248 AHC_BUGNONE = 0x00, 249 /* 250 * On all chips prior to the U2 product line, 251 * the WIDEODD S/G segment feature does not 252 * work during scsi->HostBus transfers. 253 */ 254 AHC_TMODE_WIDEODD_BUG = 0x01, 255 /* 256 * On the aic7890/91 Rev 0 chips, the autoflush 257 * feature does not work. A manual flush of 258 * the DMA FIFO is required. 259 */ 260 AHC_AUTOFLUSH_BUG = 0x02, 261 /* 262 * On many chips, cacheline streaming does not work. 263 */ 264 AHC_CACHETHEN_BUG = 0x04, 265 /* 266 * On the aic7896/97 chips, cacheline 267 * streaming must be enabled. 268 */ 269 AHC_CACHETHEN_DIS_BUG = 0x08, 270 /* 271 * PCI 2.1 Retry failure on non-empty data fifo. 272 */ 273 AHC_PCI_2_1_RETRY_BUG = 0x10, 274 /* 275 * Controller does not handle cacheline residuals 276 * properly on S/G segments if PCI MWI instructions 277 * are allowed. 278 */ 279 AHC_PCI_MWI_BUG = 0x20, 280 /* 281 * An SCB upload using the SCB channel's 282 * auto array entry copy feature may 283 * corrupt data. This appears to only 284 * occur on 66MHz systems. 285 */ 286 AHC_SCBCHAN_UPLOAD_BUG = 0x40 287 } ahc_bug; 288 289 /* 290 * Configuration specific settings. 291 * The driver determines these settings by probing the 292 * chip/controller's configuration. 293 */ 294 typedef enum { 295 AHC_FNONE = 0x000, 296 AHC_PRIMARY_CHANNEL = 0x003,/* 297 * The channel that should 298 * be probed first. 299 */ 300 AHC_USEDEFAULTS = 0x004,/* 301 * For cards without an seeprom 302 * or a BIOS to initialize the chip's 303 * SRAM, we use the default target 304 * settings. 305 */ 306 AHC_SEQUENCER_DEBUG = 0x008, 307 AHC_SHARED_SRAM = 0x010, 308 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 309 AHC_RESET_BUS_A = 0x040, 310 AHC_RESET_BUS_B = 0x080, 311 AHC_EXTENDED_TRANS_A = 0x100, 312 AHC_EXTENDED_TRANS_B = 0x200, 313 AHC_TERM_ENB_A = 0x400, 314 AHC_TERM_ENB_B = 0x800, 315 AHC_INITIATORROLE = 0x1000,/* 316 * Allow initiator operations on 317 * this controller. 318 */ 319 AHC_TARGETROLE = 0x2000,/* 320 * Allow target operations on this 321 * controller. 322 */ 323 AHC_NEWEEPROM_FMT = 0x4000, 324 AHC_RESOURCE_SHORTAGE = 0x8000, 325 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 326 AHC_INT50_SPEEDFLEX = 0x20000,/* 327 * Internal 50pin connector 328 * sits behind an aic3860 329 */ 330 AHC_SCB_BTT = 0x40000,/* 331 * The busy targets table is 332 * stored in SCB space rather 333 * than SRAM. 334 */ 335 AHC_BIOS_ENABLED = 0x80000, 336 AHC_ALL_INTERRUPTS = 0x100000, 337 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 338 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 339 AHC_39BIT_ADDRESSING = 0x1000000 /* Use 39 bit addressing scheme. */ 340 } ahc_flag; 341 342 /************************* Hardware SCB Definition ***************************/ 343 344 /* 345 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 346 * consists of a "hardware SCB" mirroring the fields availible on the card 347 * and additional information the kernel stores for each transaction. 348 * 349 * To minimize space utilization, a portion of the hardware scb stores 350 * different data during different portions of a SCSI transaction. 351 * As initialized by the host driver for the initiator role, this area 352 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 353 * the cdb has been presented to the target, this area serves to store 354 * residual transfer information and the SCSI status byte. 355 * For the target role, the contents of this area do not change, but 356 * still serve a different purpose than for the initiator role. See 357 * struct target_data for details. 358 */ 359 360 /* 361 * Status information embedded in the shared poriton of 362 * an SCB after passing the cdb to the target. The kernel 363 * driver will only read this data for transactions that 364 * complete abnormally (non-zero status byte). 365 */ 366 struct status_pkt { 367 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 368 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 369 uint8_t scsi_status; /* Standard SCSI status byte */ 370 }; 371 372 /* 373 * Target mode version of the shared data SCB segment. 374 */ 375 struct target_data { 376 uint8_t target_phases; /* Bitmap of phases to execute */ 377 uint8_t data_phase; /* Data-In or Data-Out */ 378 uint8_t scsi_status; /* SCSI status to give to initiator */ 379 uint8_t initiator_tag; /* Initiator's transaction tag */ 380 }; 381 382 struct hardware_scb { 383 /*0*/ union { 384 /* 385 * If the cdb is 12 bytes or less, we embed it directly 386 * in the SCB. For longer cdbs, we embed the address 387 * of the cdb payload as seen by the chip and a DMA 388 * is used to pull it in. 389 */ 390 uint8_t cdb[12]; 391 uint32_t cdb_ptr; 392 struct status_pkt status; 393 struct target_data tdata; 394 } shared_data; 395 /* 396 * A word about residuals. 397 * The scb is presented to the sequencer with the dataptr and datacnt 398 * fields initialized to the contents of the first S/G element to 399 * transfer. The sgptr field is initialized to the bus address for 400 * the S/G element that follows the first in the in core S/G array 401 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 402 * S/G entry for this transfer (single S/G element transfer with the 403 * first elements address and length preloaded in the dataptr/datacnt 404 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 405 * The SG_FULL_RESID flag ensures that the residual will be correctly 406 * noted even if no data transfers occur. Once the data phase is entered, 407 * the residual sgptr and datacnt are loaded from the sgptr and the 408 * datacnt fields. After each S/G element's dataptr and length are 409 * loaded into the hardware, the residual sgptr is advanced. After 410 * each S/G element is expired, its datacnt field is checked to see 411 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 412 * residual sg ptr and the transfer is considered complete. If the 413 * sequencer determines that there is a residual in the tranfer, it 414 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 415 * host memory. To sumarize: 416 * 417 * Sequencer: 418 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 419 * or residual_sgptr does not have SG_LIST_NULL set. 420 * 421 * o We are transfering the last segment if residual_datacnt has 422 * the SG_LAST_SEG flag set. 423 * 424 * Host: 425 * o A residual has occurred if a completed scb has the 426 * SG_RESID_VALID flag set. 427 * 428 * o residual_sgptr and sgptr refer to the "next" sg entry 429 * and so may point beyond the last valid sg entry for the 430 * transfer. 431 */ 432 /*12*/ uint32_t dataptr; 433 /*16*/ uint32_t datacnt; /* 434 * Byte 3 (numbered from 0) of 435 * the datacnt is really the 436 * 4th byte in that data address. 437 */ 438 /*20*/ uint32_t sgptr; 439 #define SG_PTR_MASK 0xFFFFFFF8 440 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 441 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 442 /*26*/ uint8_t lun; 443 /*27*/ uint8_t tag; /* 444 * Index into our kernel SCB array. 445 * Also used as the tag for tagged I/O 446 */ 447 /*28*/ uint8_t cdb_len; 448 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 449 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 450 /*31*/ uint8_t next; /* 451 * Used for threading SCBs in the 452 * "Waiting for Selection" and 453 * "Disconnected SCB" lists down 454 * in the sequencer. 455 */ 456 /*32*/ uint8_t cdb32[32]; /* 457 * CDB storage for cdbs of size 458 * 13->32. We store them here 459 * because hardware scbs are 460 * allocated from DMA safe 461 * memory so we are guaranteed 462 * the controller can access 463 * this data. 464 */ 465 }; 466 467 /************************ Kernel SCB Definitions ******************************/ 468 /* 469 * Some fields of the SCB are OS dependent. Here we collect the 470 * definitions for elements that all OS platforms need to include 471 * in there SCB definition. 472 */ 473 474 /* 475 * Definition of a scatter/gather element as transfered to the controller. 476 * The aic7xxx chips only support a 24bit length. We use the top byte of 477 * the length to store additional address bits and a flag to indicate 478 * that a given segment terminates the transfer. This gives us an 479 * addressable range of 512GB on machines with 64bit PCI or with chips 480 * that can support dual address cycles on 32bit PCI busses. 481 */ 482 struct ahc_dma_seg { 483 uint32_t addr; 484 uint32_t len; 485 #define AHC_DMA_LAST_SEG 0x80000000 486 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 487 #define AHC_SG_LEN_MASK 0x00FFFFFF 488 }; 489 490 struct sg_map_node { 491 bus_dmamap_t sg_dmamap; 492 bus_addr_t sg_physaddr; 493 struct ahc_dma_seg* sg_vaddr; 494 SLIST_ENTRY(sg_map_node) links; 495 }; 496 497 /* 498 * The current state of this SCB. 499 */ 500 typedef enum { 501 SCB_FREE = 0x0000, 502 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 503 * Another device was active 504 * during the first timeout for 505 * this SCB so we gave ourselves 506 * an additional timeout period 507 * in case it was hogging the 508 * bus. 509 */ 510 SCB_DEVICE_RESET = 0x0004, 511 SCB_SENSE = 0x0008, 512 SCB_CDB32_PTR = 0x0010, 513 SCB_RECOVERY_SCB = 0x0020, 514 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 515 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 516 SCB_ABORT = 0x1000, 517 SCB_UNTAGGEDQ = 0x2000, 518 SCB_ACTIVE = 0x4000, 519 SCB_TARGET_IMMEDIATE = 0x8000 520 } scb_flag; 521 522 struct scb { 523 struct hardware_scb *hscb; 524 union { 525 SLIST_ENTRY(scb) sle; 526 TAILQ_ENTRY(scb) tqe; 527 } links; 528 LIST_ENTRY(scb) pending_links; 529 ahc_io_ctx_t io_ctx; 530 struct ahc_softc *ahc_softc; 531 scb_flag flags; 532 #ifndef __linux__ 533 bus_dmamap_t dmamap; 534 #endif 535 struct scb_platform_data *platform_data; 536 struct sg_map_node *sg_map; 537 struct ahc_dma_seg *sg_list; 538 bus_addr_t sg_list_phys; 539 u_int sg_count;/* How full ahc_dma_seg is */ 540 }; 541 542 struct scb_data { 543 SLIST_HEAD(, scb) free_scbs; /* 544 * Pool of SCBs ready to be assigned 545 * commands to execute. 546 */ 547 struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */ 548 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 549 struct scb *scbarray; /* Array of kernel SCBs */ 550 struct scsi_sense_data *sense; /* Per SCB sense data */ 551 552 /* 553 * "Bus" addresses of our data structures. 554 */ 555 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 556 bus_dmamap_t hscb_dmamap; 557 bus_addr_t hscb_busaddr; 558 bus_dma_tag_t sense_dmat; 559 bus_dmamap_t sense_dmamap; 560 bus_addr_t sense_busaddr; 561 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 562 SLIST_HEAD(, sg_map_node) sg_maps; 563 uint8_t numscbs; 564 uint8_t maxhscbs; /* Number of SCBs on the card */ 565 uint8_t init_level; /* 566 * How far we've initialized 567 * this structure. 568 */ 569 }; 570 571 /************************ Target Mode Definitions *****************************/ 572 573 /* 574 * Connection desciptor for select-in requests in target mode. 575 */ 576 struct target_cmd { 577 uint8_t scsiid; /* Our ID and the initiator's ID */ 578 uint8_t identify; /* Identify message */ 579 uint8_t bytes[22]; /* 580 * Bytes contains any additional message 581 * bytes terminated by 0xFF. The remainder 582 * is the cdb to execute. 583 */ 584 uint8_t cmd_valid; /* 585 * When a command is complete, the firmware 586 * will set cmd_valid to all bits set. 587 * After the host has seen the command, 588 * the bits are cleared. This allows us 589 * to just peek at host memory to determine 590 * if more work is complete. cmd_valid is on 591 * an 8 byte boundary to simplify setting 592 * it on aic7880 hardware which only has 593 * limited direct access to the DMA FIFO. 594 */ 595 uint8_t pad[7]; 596 }; 597 598 /* 599 * Number of events we can buffer up if we run out 600 * of immediate notify ccbs. 601 */ 602 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 603 struct ahc_tmode_event { 604 uint8_t initiator_id; 605 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 606 #define EVENT_TYPE_BUS_RESET 0xFF 607 uint8_t event_arg; 608 }; 609 610 /* 611 * Per enabled lun target mode state. 612 * As this state is directly influenced by the host OS'es target mode 613 * environment, we let the OS module define it. Forward declare the 614 * structure here so we can store arrays of them, etc. in OS neutral 615 * data structures. 616 */ 617 #ifdef AHC_TARGET_MODE 618 struct ahc_tmode_lstate { 619 struct cam_path *path; 620 struct ccb_hdr_slist accept_tios; 621 struct ccb_hdr_slist immed_notifies; 622 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 623 uint8_t event_r_idx; 624 uint8_t event_w_idx; 625 }; 626 #else 627 struct ahc_tmode_lstate; 628 #endif 629 630 /******************** Transfer Negotiation Datastructures *********************/ 631 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 632 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 633 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 634 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 635 636 /* 637 * Transfer Negotiation Information. 638 */ 639 struct ahc_transinfo { 640 uint8_t protocol_version; /* SCSI Revision level */ 641 uint8_t transport_version; /* SPI Revision level */ 642 uint8_t width; /* Bus width */ 643 uint8_t period; /* Sync rate factor */ 644 uint8_t offset; /* Sync offset */ 645 uint8_t ppr_options; /* Parallel Protocol Request options */ 646 }; 647 648 /* 649 * Per-initiator current, goal and user transfer negotiation information. */ 650 struct ahc_initiator_tinfo { 651 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 652 struct ahc_transinfo curr; 653 struct ahc_transinfo goal; 654 struct ahc_transinfo user; 655 }; 656 657 /* 658 * Per enabled target ID state. 659 * Pointers to lun target state as well as sync/wide negotiation information 660 * for each initiator<->target mapping. For the initiator role we pretend 661 * that we are the target and the targets are the initiators since the 662 * negotiation is the same regardless of role. 663 */ 664 struct ahc_tmode_tstate { 665 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 666 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 667 668 /* 669 * Per initiator state bitmasks. 670 */ 671 uint16_t auto_negotiate;/* Auto Negotiation Required */ 672 uint16_t ultraenb; /* Using ultra sync rate */ 673 uint16_t discenable; /* Disconnection allowed */ 674 uint16_t tagenable; /* Tagged Queuing allowed */ 675 }; 676 677 /* 678 * Data structure for our table of allowed synchronous transfer rates. 679 */ 680 struct ahc_syncrate { 681 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 682 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 683 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 684 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 685 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 686 uint8_t period; /* Period to send to SCSI target */ 687 char *rate; 688 }; 689 690 /* 691 * The synchronouse transfer rate table. 692 */ 693 extern struct ahc_syncrate ahc_syncrates[]; 694 695 /* 696 * Indexes into our table of syncronous transfer rates. 697 */ 698 #define AHC_SYNCRATE_DT 0 699 #define AHC_SYNCRATE_ULTRA2 1 700 #define AHC_SYNCRATE_ULTRA 3 701 #define AHC_SYNCRATE_FAST 6 702 703 /***************************** Lookup Tables **********************************/ 704 /* 705 * Phase -> name and message out response 706 * to parity errors in each phase table. 707 */ 708 struct ahc_phase_table_entry { 709 uint8_t phase; 710 uint8_t mesg_out; /* Message response to parity errors */ 711 char *phasemsg; 712 }; 713 714 /************************** Serial EEPROM Format ******************************/ 715 716 struct seeprom_config { 717 /* 718 * Per SCSI ID Configuration Flags 719 */ 720 uint16_t device_flags[16]; /* words 0-15 */ 721 #define CFXFER 0x0007 /* synchronous transfer rate */ 722 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 723 #define CFDISC 0x0010 /* enable disconnection */ 724 #define CFWIDEB 0x0020 /* wide bus device */ 725 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 726 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 727 #define CFSTART 0x0100 /* send start unit SCSI command */ 728 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 729 #define CFRNFOUND 0x0400 /* report even if not found */ 730 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 731 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 732 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 733 734 /* 735 * BIOS Control Bits 736 */ 737 uint16_t bios_control; /* word 16 */ 738 #define CFSUPREM 0x0001 /* support all removeable drives */ 739 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 740 #define CFBIOSEN 0x0004 /* BIOS enabled */ 741 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 742 #define CFSM2DRV 0x0010 /* support more than two drives */ 743 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 744 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 745 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 746 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 747 #define CFEXTEND 0x0080 /* extended translation enabled */ 748 #define CFSCAMEN 0x0100 /* SCAM enable */ 749 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 750 #define CFMSG_VERBOSE 0x0000 751 #define CFMSG_SILENT 0x0200 752 #define CFMSG_DIAG 0x0400 753 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 754 /* UNUSED 0xff00 */ 755 756 /* 757 * Host Adapter Control Bits 758 */ 759 uint16_t adapter_control; /* word 17 */ 760 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 761 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 762 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 763 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 764 #define CFSTERM 0x0004 /* SCSI low byte termination */ 765 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 766 #define CFSPARITY 0x0010 /* SCSI parity */ 767 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 768 #define CFMULTILUN 0x0020 769 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 770 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 771 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 772 #define CFBOOTCHANSHIFT 8 773 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 774 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 775 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 776 #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 777 778 /* 779 * Bus Release Time, Host Adapter ID 780 */ 781 uint16_t brtime_id; /* word 18 */ 782 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 783 /* UNUSED 0x00f0 */ 784 #define CFBRTIME 0xff00 /* bus release time */ 785 786 /* 787 * Maximum targets 788 */ 789 uint16_t max_targets; /* word 19 */ 790 #define CFMAXTARG 0x00ff /* maximum targets */ 791 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 792 #define CFBOOTID 0xf000 /* Target to boot from */ 793 uint16_t res_1[10]; /* words 20-29 */ 794 uint16_t signature; /* Signature == 0x250 */ 795 #define CFSIGNATURE 0x250 796 #define CFSIGNATURE2 0x300 797 uint16_t checksum; /* word 31 */ 798 }; 799 800 /**************************** Message Buffer *********************************/ 801 typedef enum { 802 MSG_TYPE_NONE = 0x00, 803 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 804 MSG_TYPE_INITIATOR_MSGIN = 0x02, 805 MSG_TYPE_TARGET_MSGOUT = 0x03, 806 MSG_TYPE_TARGET_MSGIN = 0x04 807 } ahc_msg_type; 808 809 typedef enum { 810 MSGLOOP_IN_PROG, 811 MSGLOOP_MSGCOMPLETE, 812 MSGLOOP_TERMINATED 813 } msg_loop_stat; 814 815 /*********************** Software Configuration Structure *********************/ 816 TAILQ_HEAD(scb_tailq, scb); 817 818 struct ahc_suspend_channel_state { 819 uint8_t scsiseq; 820 uint8_t sxfrctl0; 821 uint8_t sxfrctl1; 822 uint8_t simode0; 823 uint8_t simode1; 824 uint8_t seltimer; 825 uint8_t seqctl; 826 }; 827 828 struct ahc_suspend_state { 829 struct ahc_suspend_channel_state channel[2]; 830 uint8_t optionmode; 831 uint8_t dscommand0; 832 uint8_t dspcistatus; 833 /* hsmailbox */ 834 uint8_t crccontrol1; 835 uint8_t scbbaddr; 836 /* Host and sequencer SCB counts */ 837 uint8_t dff_thrsh; 838 uint8_t *scratch_ram; 839 uint8_t *btt; 840 }; 841 842 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 843 844 struct ahc_softc { 845 bus_space_tag_t tag; 846 bus_space_handle_t bsh; 847 #ifndef __linux__ 848 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 849 #endif 850 struct scb_data *scb_data; 851 852 struct scb *next_queued_scb; 853 854 /* 855 * SCBs that have been sent to the controller 856 */ 857 LIST_HEAD(, scb) pending_scbs; 858 859 /* 860 * Counting lock for deferring the release of additional 861 * untagged transactions from the untagged_queues. When 862 * the lock is decremented to 0, all queues in the 863 * untagged_queues array are run. 864 */ 865 u_int untagged_queue_lock; 866 867 /* 868 * Per-target queue of untagged-transactions. The 869 * transaction at the head of the queue is the 870 * currently pending untagged transaction for the 871 * target. The driver only allows a single untagged 872 * transaction per target. 873 */ 874 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 875 876 /* 877 * Platform specific data. 878 */ 879 struct ahc_platform_data *platform_data; 880 881 /* 882 * Platform specific device information. 883 */ 884 ahc_dev_softc_t dev_softc; 885 886 /* 887 * Bus specific device information. 888 */ 889 ahc_bus_intr_t bus_intr; 890 891 /* 892 * Target mode related state kept on a per enabled lun basis. 893 * Targets that are not enabled will have null entries. 894 * As an initiator, we keep one target entry for our initiator 895 * ID to store our sync/wide transfer settings. 896 */ 897 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 898 899 /* 900 * The black hole device responsible for handling requests for 901 * disabled luns on enabled targets. 902 */ 903 struct ahc_tmode_lstate *black_hole; 904 905 /* 906 * Device instance currently on the bus awaiting a continue TIO 907 * for a command that was not given the disconnect priveledge. 908 */ 909 struct ahc_tmode_lstate *pending_device; 910 911 /* 912 * Card characteristics 913 */ 914 ahc_chip chip; 915 ahc_feature features; 916 ahc_bug bugs; 917 ahc_flag flags; 918 919 /* Values to store in the SEQCTL register for pause and unpause */ 920 uint8_t unpause; 921 uint8_t pause; 922 923 /* Command Queues */ 924 uint8_t qoutfifonext; 925 uint8_t qinfifonext; 926 uint8_t *qoutfifo; 927 uint8_t *qinfifo; 928 929 /* Critical Section Data */ 930 struct cs *critical_sections; 931 u_int num_critical_sections; 932 933 /* Links for chaining softcs */ 934 TAILQ_ENTRY(ahc_softc) links; 935 936 /* Channel Names ('A', 'B', etc.) */ 937 char channel; 938 char channel_b; 939 940 /* Initiator Bus ID */ 941 uint8_t our_id; 942 uint8_t our_id_b; 943 944 /* 945 * PCI error detection. 946 */ 947 int unsolicited_ints; 948 949 /* 950 * Target incoming command FIFO. 951 */ 952 struct target_cmd *targetcmds; 953 uint8_t tqinfifonext; 954 955 /* 956 * Incoming and outgoing message handling. 957 */ 958 uint8_t send_msg_perror; 959 ahc_msg_type msg_type; 960 uint8_t msgout_buf[12];/* Message we are sending */ 961 uint8_t msgin_buf[12];/* Message we are receiving */ 962 u_int msgout_len; /* Length of message to send */ 963 u_int msgout_index; /* Current index in msgout */ 964 u_int msgin_index; /* Current index in msgin */ 965 966 /* 967 * Mapping information for data structures shared 968 * between the sequencer and kernel. 969 */ 970 bus_dma_tag_t parent_dmat; 971 bus_dma_tag_t shared_data_dmat; 972 bus_dmamap_t shared_data_dmamap; 973 bus_addr_t shared_data_busaddr; 974 975 /* 976 * Bus address of the one byte buffer used to 977 * work-around a DMA bug for chips <= aic7880 978 * in target mode. 979 */ 980 bus_addr_t dma_bug_buf; 981 982 /* Information saved through suspend/resume cycles */ 983 struct ahc_suspend_state suspend_state; 984 985 /* Number of enabled target mode device on this card */ 986 u_int enabled_luns; 987 988 /* Initialization level of this data structure */ 989 u_int init_level; 990 991 /* PCI cacheline size. */ 992 u_int pci_cachesize; 993 994 /* Per-Unit descriptive information */ 995 const char *description; 996 char *name; 997 int unit; 998 999 /* Selection Timer settings */ 1000 int seltime; 1001 int seltime_b; 1002 1003 uint16_t user_discenable;/* Disconnection allowed */ 1004 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1005 }; 1006 1007 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1008 extern struct ahc_softc_tailq ahc_tailq; 1009 1010 /************************ Active Device Information ***************************/ 1011 typedef enum { 1012 ROLE_UNKNOWN, 1013 ROLE_INITIATOR, 1014 ROLE_TARGET 1015 } role_t; 1016 1017 struct ahc_devinfo { 1018 int our_scsiid; 1019 int target_offset; 1020 uint16_t target_mask; 1021 u_int target; 1022 u_int lun; 1023 char channel; 1024 role_t role; /* 1025 * Only guaranteed to be correct if not 1026 * in the busfree state. 1027 */ 1028 }; 1029 1030 /****************************** PCI Structures ********************************/ 1031 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1032 1033 struct ahc_pci_identity { 1034 uint64_t full_id; 1035 uint64_t id_mask; 1036 char *name; 1037 ahc_device_setup_t *setup; 1038 }; 1039 extern struct ahc_pci_identity ahc_pci_ident_table []; 1040 extern const u_int ahc_num_pci_devs; 1041 1042 /***************************** VL/EISA Declarations ***************************/ 1043 struct aic7770_identity { 1044 uint32_t full_id; 1045 uint32_t id_mask; 1046 char *name; 1047 ahc_device_setup_t *setup; 1048 }; 1049 extern struct aic7770_identity aic7770_ident_table []; 1050 extern const int ahc_num_aic7770_devs; 1051 1052 #define AHC_EISA_SLOT_OFFSET 0xc00 1053 #define AHC_EISA_IOSIZE 0x100 1054 1055 /*************************** Function Declarations ****************************/ 1056 /******************************************************************************/ 1057 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1058 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1059 void ahc_busy_tcl(struct ahc_softc *ahc, 1060 u_int tcl, u_int busyid); 1061 1062 /***************************** PCI Front End *********************************/ 1063 struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1064 int ahc_pci_config(struct ahc_softc *, 1065 struct ahc_pci_identity *); 1066 1067 /*************************** EISA/VL Front End ********************************/ 1068 struct aic7770_identity *aic7770_find_device(uint32_t); 1069 int aic7770_config(struct ahc_softc *ahc, 1070 struct aic7770_identity *); 1071 1072 /************************** SCB and SCB queue management **********************/ 1073 int ahc_probe_scbs(struct ahc_softc *); 1074 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1075 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1076 struct scb_tailq *queue); 1077 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1078 struct scb *scb); 1079 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1080 int target, char channel, int lun, 1081 u_int tag, role_t role); 1082 1083 /****************************** Initialization ********************************/ 1084 struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1085 int ahc_softc_init(struct ahc_softc *); 1086 void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1087 int ahc_init(struct ahc_softc *ahc); 1088 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1089 void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1090 int ahc_suspend(struct ahc_softc *ahc); 1091 int ahc_resume(struct ahc_softc *ahc); 1092 void ahc_softc_insert(struct ahc_softc *); 1093 void ahc_set_unit(struct ahc_softc *, int); 1094 void ahc_set_name(struct ahc_softc *, char *); 1095 void ahc_alloc_scbs(struct ahc_softc *ahc); 1096 void ahc_free(struct ahc_softc *ahc); 1097 int ahc_reset(struct ahc_softc *ahc); 1098 void ahc_shutdown(void *arg); 1099 1100 /*************************** Interrupt Services *******************************/ 1101 void ahc_pci_intr(struct ahc_softc *ahc); 1102 void ahc_clear_intstat(struct ahc_softc *ahc); 1103 void ahc_run_qoutfifo(struct ahc_softc *ahc); 1104 #ifdef AHC_TARGET_MODE 1105 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1106 #endif 1107 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1108 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1109 void ahc_handle_scsiint(struct ahc_softc *ahc, 1110 u_int intstat); 1111 void ahc_clear_critical_section(struct ahc_softc *ahc); 1112 1113 /***************************** Error Recovery *********************************/ 1114 typedef enum { 1115 SEARCH_COMPLETE, 1116 SEARCH_COUNT, 1117 SEARCH_REMOVE 1118 } ahc_search_action; 1119 int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1120 char channel, int lun, u_int tag, 1121 role_t role, uint32_t status, 1122 ahc_search_action action); 1123 int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1124 char channel, int lun, u_int tag, 1125 int stop_on_first, int remove, 1126 int save_state); 1127 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1128 int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1129 int initiate_reset); 1130 void ahc_restart(struct ahc_softc *ahc); 1131 void ahc_calc_residual(struct scb *scb); 1132 /*************************** Utility Functions ********************************/ 1133 struct ahc_phase_table_entry* 1134 ahc_lookup_phase_entry(int phase); 1135 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1136 u_int our_id, u_int target, 1137 u_int lun, char channel, 1138 role_t role); 1139 /************************** Transfer Negotiation ******************************/ 1140 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1141 u_int *ppr_options, u_int maxsync); 1142 u_int ahc_find_period(struct ahc_softc *ahc, 1143 u_int scsirate, u_int maxsync); 1144 void ahc_validate_offset(struct ahc_softc *ahc, 1145 struct ahc_initiator_tinfo *tinfo, 1146 struct ahc_syncrate *syncrate, 1147 u_int *offset, int wide, 1148 role_t role); 1149 void ahc_validate_width(struct ahc_softc *ahc, 1150 struct ahc_initiator_tinfo *tinfo, 1151 u_int *bus_width, 1152 role_t role); 1153 int ahc_update_neg_request(struct ahc_softc*, 1154 struct ahc_devinfo*, 1155 struct ahc_tmode_tstate*, 1156 struct ahc_initiator_tinfo*, 1157 int /*force*/); 1158 void ahc_set_width(struct ahc_softc *ahc, 1159 struct ahc_devinfo *devinfo, 1160 u_int width, u_int type, int paused); 1161 void ahc_set_syncrate(struct ahc_softc *ahc, 1162 struct ahc_devinfo *devinfo, 1163 struct ahc_syncrate *syncrate, 1164 u_int period, u_int offset, 1165 u_int ppr_options, 1166 u_int type, int paused); 1167 typedef enum { 1168 AHC_QUEUE_NONE, 1169 AHC_QUEUE_BASIC, 1170 AHC_QUEUE_TAGGED 1171 } ahc_queue_alg; 1172 1173 void ahc_set_tags(struct ahc_softc *ahc, 1174 struct ahc_devinfo *devinfo, 1175 ahc_queue_alg alg); 1176 1177 /**************************** Target Mode *************************************/ 1178 #ifdef AHC_TARGET_MODE 1179 void ahc_send_lstate_events(struct ahc_softc *, 1180 struct ahc_tmode_lstate *); 1181 void ahc_handle_en_lun(struct ahc_softc *ahc, 1182 struct cam_sim *sim, union ccb *ccb); 1183 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1184 struct cam_sim *sim, union ccb *ccb, 1185 struct ahc_tmode_tstate **tstate, 1186 struct ahc_tmode_lstate **lstate, 1187 int notfound_failure); 1188 #ifndef AHC_TMODE_ENABLE 1189 #define AHC_TMODE_ENABLE 0 1190 #endif 1191 #endif 1192 /******************************* Debug ***************************************/ 1193 void ahc_print_scb(struct scb *scb); 1194 void ahc_dump_card_state(struct ahc_softc *ahc); 1195 #endif /* _AIC7XXX_H_ */ 1196